Semiconductor device manufacturing method

Abstract

To sufficiently activate impurities to form a collector layer and a cathode layer.SOLUTION: A method includes preparing a semiconductor substrate 10, ion-implanting a second impurity I2 of a second conductivity type that constitutes a collector layer 21 from the other surface 10b side, ion-implanting a third impurity I3 of a first conductivity type that constitutes a cathode layer 22 from the other surface 10b side, irradiating with a Gr laser to activate the second impurity I2 and the third impurity I3 located on the other surface 10b side to form a first collector layer 21a and a first cathode layer 22a that are portions of the collector layer 21 and the cathode layer 22 on the other surface 10b side, and after irradiating with the Gr laser, irradiating with an Ir laser to activate the second impurity I2 located between the first collector layer 21a and the FS layer 20 and the third impurity I3 located between the first cathode layer 22a and the FS layer 20 to form a second collector layer 21b and a second cathode layer 22b.SELECTED DRAWING: Figure 3F

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device in which an insulated gate bipolar transistor (hereinafter referred to as an IGBT) element and a freewheel diode (hereinafter referred to as an FWD) element are formed on a common semiconductor substrate.

Background Art

[0002] Conventionally, for example, as a switching element used in an inverter or the like, a semiconductor device in which an IGBT element and an FWD element are formed on a common semiconductor substrate has been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, a base layer is formed on one surface side of a semiconductor substrate constituting an N - type drift layer, and a plurality of trenches are formed so as to penetrate the base layer. Each trench is extended such that one direction in the plane direction of the semiconductor substrate is the longitudinal direction. And a gate insulating film and a gate electrode are formed in each trench in this order.

[0003] An N + type emitter region is formed on the surface layer portion of the base layer so as to be in contact with the trench. On the other surface side of the semiconductor substrate, a P + type collector layer and an N + type cathode layer are formed. Further, an N-type field stop layer (hereinafter also simply referred to as an FS layer) is formed between the drift layer and the collector layer and the cathode layer.

[0004] And an upper electrode electrically connected to the emitter region and the base layer is formed on one surface side of the semiconductor substrate. A lower electrode electrically connected to the collector layer and the cathode layer is formed on the other surface side of the semiconductor substrate.

[0005] In such a semiconductor device, the region where the collector layer is formed is defined as the IGBT region, and the region where the cathode layer is formed is defined as the FWD region. In the FWD region, with the above-described configuration, an FWD element having a PN junction is formed by an N-type cathode layer and drift layer and a P-type base layer.

[0006] Then, the FS layer, collector layer, and cathode layer in such a semiconductor device are formed as follows.

[0007] First, after ion-implanting impurities that form the FS layer from the other surface side of the semiconductor substrate, impurities that form the collector layer are ion-implanted, and impurities that form the cathode layer are also ion-implanted. Next, a green laser (hereinafter also simply referred to as a Gr laser) is irradiated to activate impurities in the shallow portion from the other surface side of the semiconductor substrate, forming the collector layer and the cathode layer. Thereafter, an infrared laser (hereinafter also simply referred to as an IR laser) is irradiated to activate impurities in the deep portion from the other surface side of the semiconductor substrate, forming the FS layer.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] However, according to the study by the present inventors, it has been confirmed that in the above manufacturing method, depending on the depths of the collector layer and cathode layer to be formed, impurities located at a slightly deeper position from the other surface side of the semiconductor substrate may not be sufficiently activated. Note that the slightly deeper position refers to the portion on the FS layer side among the impurities that form the collector layer and the impurities that form the cathode layer.

[0010] An object of the present disclosure is to provide a method for manufacturing a semiconductor device capable of sufficiently activating impurities to form a collector layer and a cathode layer.

Means for Solving the Problems

[0011] According to one aspect of the present disclosure, there is provided a semiconductor device having an IGBT region (1a) where an IGBT element is formed and an FWD region (1b) where an FWD element is formed, including a drift layer (11) of a first conductivity type, a base layer (12) of a second conductivity type formed on the drift layer, an FS layer (20) of the first conductivity type formed on the opposite side of the base layer with the drift layer interposed therebetween, in the IGBT region, a collector layer (21) of the second conductivity type formed on the opposite side of the drift layer with the FS layer interposed therebetween, and in the FWD region, a cathode layer (22) of the first conductivity type formed on the opposite side of the drift layer with the FS layer interposed therebetween. The semiconductor substrate (10) has a surface on the base layer side as one surface (10a) and a surface on the collector layer and cathode layer sides as the other surface (10b). In the IGBT region, an emitter region (16) of the first conductivity type is formed on the surface layer portion of the base layer, a gate insulating film (14) is formed between the drift layer and the emitter region in the base layer, and a gate electrode (15) is formed on the gate insulating film. A method for manufacturing the semiconductor device includes preparing a semiconductor substrate having one surface and the other surface opposite to the one surface, ion-implanting a first impurity (I1) of the first conductivity type that constitutes the FS layer on the other surface side, irradiating an Ir laser from the other surface side to activate the first impurity and form the FS layer, ion-implanting a second impurity (I2) of the second conductivity type that constitutes the collector layer from the other surface side, ion-implanting a third impurity (I3) of the first conductivity type that constitutes the cathode layer from the other surface side, irradiating a Gr laser from the other surface side to activate the second impurity and the third impurity located on the other surface side, and forming a first collector layer (21a) and a first cathode layer (22a) that are portions on the other surface side of the collector layer and the cathode layer. After irradiating the Gr laser, irradiating an Ir laser from the other surface side to activate the second impurity located between the first collector layer and the FS layer and the third impurity located between the first cathode layer and the FS layer, and forming a second collector layer (21b) between the first collector layer and the FS layer to constitute a collector layer including the first collector layer and the second collector layer, and forming a second cathode layer (22b) between the first cathode layer and the FS layer to form a cathode layer including the first cathode layer and the second cathode layer.

[0012] According to this, after irradiating with a Gr laser to form the first collector layer and the first cathode layer, an IR laser is irradiated to form the second collector layer and the second cathode layer. For this reason, a semiconductor device is manufactured in which impurities are sufficiently activated also in a portion located between the first collector layer and the first cathode layer and the FS layer.

[0013] Note that the reference numerals in parentheses attached to each component etc. show an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2A

Figure 2B

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 3E

Figure 3F

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 7A

Figure 7B

Figure 7C

Figure 7D

Figure 7E

Figure 8

Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In each of the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

[0016] (First Embodiment) The first embodiment will be described with reference to the drawings. Note that the semiconductor device manufactured by the manufacturing method of this embodiment is preferably used as a power switching element used in a power circuit such as an inverter or a DC / DC converter. First, the configuration of the semiconductor device manufactured by the manufacturing method of this embodiment will be described with reference to FIG. 1.

[0017] As shown in FIG. 1, the semiconductor device is an RC (abbreviation for Reverse Conducting)-IGBT in which an IGBT region 1a where an IGBT element is formed and an FWD region 1b where an FWD element is formed are formed on a common semiconductor substrate 10. Specifically, although it will be described later, in this embodiment, as will be described later, the portion on the collector layer 21 located on the other surface 10b of the semiconductor substrate 10 is the IGBT region 1a, and the portion on the cathode layer 22 located on the other surface 10b of the semiconductor substrate 10 is the FWD region 1b.

[0018] The semiconductor device has a semiconductor substrate 10 that constitutes an N - -type drift layer 11. The semiconductor substrate 10 of this embodiment is composed of a silicon substrate. A base layer 12 is formed on the drift layer 11. That is, the base layer 12 is formed on one surface 10a side of the semiconductor substrate 10.

[0019] A plurality of trenches 13 are formed in the semiconductor substrate 10 so as to penetrate the base layer 12 from the one surface 10a side and reach the drift layer 11. As a result, the base layer 12 is separated into a plurality of parts by the trenches 13. In this embodiment, the plurality of trenches 13 are formed in the IGBT region 1a and the FWD region 1b, respectively. Also, in this embodiment, the plurality of trenches 13 are formed in a stripe shape with one direction intersecting the arrangement direction of the IGBT region 1a and the FWD region 1b as the longitudinal direction (that is, the depth direction in the drawing of FIG. 1).

[0020] Each trench 13 is filled with a gate insulating film 14 formed to cover the wall surface of each trench 13 and a gate electrode 15 composed of polysilicon or the like formed on the gate insulating film 14. As a result, a trench gate structure is configured.

[0021] Although not particularly shown, the gate electrode 15 formed in the IGBT region 1a is connected to a gate driver or the like via a gate pad or the like (not shown) so that a predetermined voltage is applied thereto. The gate electrode 15 formed in the FWD region 1b is connected to the upper electrode 19 described later and is set to the same potential as the upper electrode 19.

[0022] In the surface layer portion of the base layer 12, in the IGBT region 1a, an N + type emitter region 16 having a higher concentration than the drift layer 11 is formed. That is, on the one surface 10a side of the semiconductor substrate 10, in the IGBT region 1a, the emitter region 16 is formed. Further, in the surface layer portion of the base layer 12, in the IGBT region 1a, a P + type contact region 17 having a higher concentration than the base layer 12 is formed. Specifically, the emitter region 16 is formed to terminate within the base layer 12 and to contact the side surface of the trench 13. Further, the contact region 17 is formed to terminate within the base layer 12 and to be sandwiched between two emitter regions 16.

[0023] More specifically, the emitter region 16 is formed in a rod shape so as to contact the side surface of the trench 13 along the longitudinal direction of the trench 13 in the region between adjacent trenches 13 and to terminate inside the tip of the trench 13. Further, the contact region 17 is formed in a rod shape along the longitudinal direction of the trench 13 so as to contact the emitter region 16.

[0024] In the present embodiment, the portion of the wall surface of the trench 13 that is located between the emitter region 16 and the drift layer 11 corresponds to the surface of the base layer that is located between the emitter region and the drift layer. Further, in the present embodiment, the contact region 17 is formed deeper than the emitter region 16.

[0025] On one surface 10a of the semiconductor substrate 10, an interlayer insulating film 18 made of BPSG (abbreviation for Borophosphosilicate Glass) or the like is formed. In the interlayer insulating film 18, in the IGBT region 1a on the one surface 10a of the semiconductor substrate 10, contact holes 18a are formed to expose the emitter region 16 and the contact region 17 located between adjacent trenches 13. Further, in the interlayer insulating film 18, in the FWD region 1b on the one surface 10a of the semiconductor substrate 10, contact holes 18b for exposing the base layer 12 are formed, and contact holes 18c for exposing the gate electrode 15 are formed.

[0026] An upper electrode 19 is formed on the interlayer insulating film 18. In the IGBT region 1a, the upper electrode 19 is electrically connected to the emitter region 16 and the contact region 17 through the contact holes 18a formed in the interlayer insulating film 18. Further, in the FWD region 1b, the upper electrode 19 is electrically connected to the base layer 12 through the contact holes 18b formed in the interlayer insulating film 18 and is electrically connected to the gate electrode 15 through the contact holes 18c.

[0027] That is, an upper electrode 19 that functions as an emitter electrode in the IGBT region 1a and functions as an anode electrode in the FWD region 1b is formed on the interlayer insulating film 18. In the present embodiment, the upper electrode 19 constitutes the first electrode.

[0028] On the side of the drift layer 11 opposite to the base layer 12 side, an N-type FS layer 20 having a higher concentration than the drift layer 11 is formed. That is, the FS layer 20 is formed on the other surface 10b side of the semiconductor substrate 10.

[0029] And in the IGBT region 1a, a P + -type collector layer 21 is formed on the side opposite to the drift layer 11 with the FS layer 20 interposed therebetween, and in the FWD region 1b, an N +A cathode layer 22 of a certain type is formed. In the present embodiment, the IGBT region 1a and the FWD region 1b are partitioned in this way depending on whether the layer located on the other surface 10b of the semiconductor substrate 10 is the collector layer 21 or the cathode layer 22. That is, in the present embodiment, the portion on the collector layer 21 located on the other surface 10b of the semiconductor substrate 10 is the IGBT region 1a, and the portion on the cathode layer 22 located on the other surface 10b of the semiconductor substrate 10 is the FWD region 1b.

[0030] Here, the FS layer 20, the collector layer 21, and the cathode layer 22 of the present embodiment are specifically formed by laser irradiation after ion implantation of impurities, although it will be described later. Also, the cathode layer 22 of the present embodiment is formed by ion implanting P-type impurities constituting the collector layer 21 over the entire surface on the other surface 10b side of the semiconductor substrate 10, and then ion implanting N-type impurities into the region constituting the cathode layer 22 to turn the P-type region into an N-type region. For this reason, the cathode layer 22 of the present embodiment also contains P-type impurities and is made N-type by having more N-type impurities than P-type impurities.

[0031] And, in order to improve the short-circuit withstand capacity, the semiconductor device of the present embodiment forms the collector layer 21 and the cathode layer 22 deeply (that is, thickly). For example, the collector layer 21 and the cathode layer 22 of the present embodiment have a depth (that is, thickness) of about 1 μm when the direction from the other surface 10b side of the semiconductor substrate 10 toward the one surface 10a side is the depth direction.

[0032] Hereinafter, in the present embodiment, the regions located on the other surface side of the semiconductor substrate 10 of the collector layer 21 and the cathode layer 22 are the first collector layer 21a and the first cathode layer 22a. Also, the region located between the first collector layer 21a of the collector layer 21 and the FS layer 20 is the second collector layer 21b, and the region located between the first cathode layer 22a of the cathode layer 22 and the FS layer 20 is the second cathode layer 22b.

[0033] Note that the first collector layer 21a and the first cathode layer 22a are parts formed in the first formation process described later, and are constituted by parts with a depth of about 0 to 0.2 μm from the other surface 10b of the semiconductor substrate 10. The second collector layer 21b and the second cathode layer 22b are parts formed in the second formation process described later, and are constituted by parts with a depth of about 0.2 to 1.0 μm from the other surface 10b of the semiconductor substrate 10. However, the depths of the first collector layer 21a and the first cathode layer 22a, and the depths of the second collector layer 21b and the second cathode layer 22b also depend on the actual impurity concentration and may be different from each other. For example, the cathode layer 22 may be formed deeper than the collector layer 21.

[0034] And as shown in FIG. 2A, the collector layer 21 of the present embodiment is configured to have a first collector peak CP1 where the impurity concentration is maximized in the first collector layer 21a in terms of the impurity concentration in the depth direction. Further, the collector layer 21 is configured to have a second collector peak CP2 where the impurity concentration is maximized in the second collector layer 21b. Similarly, the cathode layer 22 is configured to have a first cathode peak KP1 where the impurity concentration is maximized in the first cathode layer 22a in terms of the impurity concentration in the depth direction. Further, the cathode layer 22 is configured to have a second cathode peak KP2 where the impurity concentration is maximized in the second cathode layer 22b.

[0035] As shown in FIG. 1, a lower electrode 23 electrically connected to the collector layer 21 and the cathode layer 22 is formed on the side opposite to the drift layer 11 with the collector layer 21 and the cathode layer 22 interposed therebetween. In other words, the lower electrode 23 is formed on the other surface 10b of the semiconductor substrate 10. That is, the lower electrode 23 that functions as a collector electrode in the IGBT region 1a and functions as a cathode electrode in the FWD region 1b is formed. In the present embodiment, the lower electrode 23 corresponds to the second electrode.

[0036] By being configured in this manner, the semiconductor device of this embodiment forms an IGBT element in the IGBT region 1a, with the base layer 12 as the base, the emitter region 16 as the emitter, and the collector layer 21 as the collector. Further, in the FWD region 1b, a FWD element is formed by PN junction with the base layer as the anode and the drift layer 11, FS layer 20, and cathode layer 22 as the cathode.

[0037] The above is the configuration of the semiconductor device in this embodiment. In this embodiment, N-type, N + -type, and N - -type correspond to the first conductivity type, and P-type, P + -type correspond to the second conductivity type. Also, in this embodiment, by being configured as described above, the semiconductor substrate 10 has a configuration including the collector layer 21, cathode layer 22, FS layer 20, drift layer 11, base layer 12, emitter region 16, and contact region 17.

[0038] Next, the basic operation of the above semiconductor device will be described.

[0039] When a voltage higher than the upper electrode 19 is applied to the lower electrode 23 in the semiconductor device of this embodiment, the PN junction formed between the base layer 12 and the drift layer 11 becomes in a reverse conduction state and a depletion layer is formed. Then, when a voltage at a low level (e.g., 0V) lower than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 15, no current flows between the upper electrode 19 and the lower electrode 23.

[0040] To turn on the IGBT element, a high-level voltage equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 15 of the IGBT region 1a while a voltage higher than the upper electrode 19 is applied to the lower electrode 23. As a result, in the IGBT region 1a, an inversion layer is formed in a portion of the base layer 12 that is in contact with the trench 13 where the gate electrode 15 is disposed. Then, in the IGBT element, electrons are supplied from the emitter region 16 to the drift layer 11 through the inversion layer, holes are supplied from the collector layer 21 to the drift layer 11, and the resistance value of the drift layer 11 decreases due to conductivity modulation, thereby turning on the element.

[0041] Also, when turning off the IGBT element and turning on the FWD element (i.e., operating the FWD element as a diode), the voltages applied to the upper electrode 19 and the lower electrode 23 are switched, and a forward voltage application is performed in which a voltage higher than the lower electrode 23 is applied to the upper electrode 19. As a result, holes are supplied to the base layer 12 and electrons are supplied to the cathode layer 22, causing the FWD element to operate as a diode.

[0042] Next, a method for manufacturing a semiconductor device including a method for forming the above-described FS layer 20, collector layer 21, and cathode layer 22 will be described with reference to FIGS. 3A to 3F. Note that in FIGS. 3A to 3F, the configuration on the one surface 10a side of the semiconductor substrate 10 is shown with omission.

[0043] First, as shown in FIG. 3A, although not shown, a semiconductor substrate 10 having a base layer 12, an emitter region 16, a gate electrode 15, etc. formed on the one surface 10a side is prepared. Here, the semiconductor substrate 10 is a wafer-shaped semiconductor substrate 10 as will be described later, and is configured by dividing the semiconductor substrate 10 into chip units. However, the semiconductor substrate 10 may not be in a wafer shape but may be previously divided into chip units.

[0044] Then, N-type first impurity I1 that constitutes the FS layer 20 is ion-implanted from the other surface 10b side of the semiconductor substrate 10. For example, when ion-implanting the first impurity I1, the acceleration energy is 3 MeV and the dose amount is 2×10 12 cm -2 This is done. Note that the first impurity I1 is, for example, boron.

[0045] Next, as shown in FIG. 3B, a laser is irradiated from the other surface 10b side of the semiconductor substrate 10, and a FS layer forming step of activating the first impurity I1 to form the FS layer 20 is performed. In the present embodiment, when performing the FS layer forming step, an IR laser having a wavelength of 780 to 1700 nm is irradiated with an irradiation energy of 5.0 to 10 J / cm 2 . At this time, since the impurities that constitute the collector layer 21 and the cathode layer 22 have not yet been implanted on the other surface 10b side of the semiconductor substrate 10, the IR laser is less likely to be scattered or the like at the portion on the other surface 10b side of the semiconductor substrate 10. For this reason, the IR laser is irradiated to a deep position for forming the FS layer 20.

[0046] Subsequently, as shown in FIG. 3C, P-type second impurity I2 that constitutes the collector layer 21 is ion-implanted. In the present embodiment, without arranging a mask, the second impurity I2 is ion-implanted over the entire surface from the other surface 10b side of the semiconductor substrate 10. That is, the second impurity I2 is also ion-implanted into the portion that constitutes the cathode layer 22. In the present embodiment, when ion-implanting the second impurity I2, multi-stage implantation is performed in which the second impurity I2 is ion-implanted a plurality of times while changing the acceleration voltage and the dose amount. As a result, when the second impurity I2 is activated to form the collector layer 21, as shown in FIG. 2A, the collector layer 21 having a plurality of collector peaks CP1 and CP2 is formed.

[0047] In the present embodiment, when ion-implanting the second impurity, ion-implantation is performed three times. For example, the first ion-implantation is performed with an acceleration energy of 200 keV and a dose amount of 1×10 13 cm -2 The second ion-implantation is performed with an acceleration energy of 100 keV and a dose amount of 1×10 12 cm-2 performed with an acceleration energy of 10 keV and a dose of 3×10 12 cm -2 The second impurity I2 is implanted at a deeper position as the acceleration voltage is higher. Also, the second impurity I2 is, for example, phosphorus.

[0048] Subsequently, as shown in FIG. 3D, a mask (not shown) with an opening in the region where the cathode layer 22 is to be formed is disposed on the other surface 10b of the semiconductor substrate 10, and an N-type third impurity I3 is ion-implanted into the portion constituting the cathode layer 22 from the other surface 10b side of the semiconductor substrate 10. In this embodiment, when ion-implanting the third impurity, multi-step implantation is performed in which the third impurity I3 is ion-implanted a plurality of times while changing the acceleration voltage and the dose. In this case, more of the third impurity I3 than the second impurity I2 is ion-implanted so that the region where the third impurity I3 is implanted becomes N-type as a whole when activated. As a result, when the third impurity I3 is activated to form the cathode layer 22, a cathode layer 22 having a plurality of cathode peaks KP1, KP2 is formed as shown in FIG. 2B.

[0049] In this embodiment, when ion-implanting the third impurity, two ion-implantations are performed. For example, the first ion-implantation is performed with an acceleration energy of 450 keV and a dose of 3×10 13 cm -2 The second ion-implantation is performed with an acceleration energy of 20 keV and a dose of 2×10 15 cm -2

[0050] Next, as shown in FIGS. 3E and 3F, a laser is irradiated to activate the second impurity I2 to form the collector layer 21 and to activate the third impurity I3 to form the cathode layer 22.

[0051] ​First, in this embodiment, as shown in FIG. 3E, as a laser, a Gr laser having a wavelength of about 532 nm is irradiated with an irradiation energy of 1.5 to 3.0 J to perform a first forming step of forming the first collector layer 21a and the first cathode layer 22a. Here, according to the study by the present inventors, when irradiated with the Gr laser, although it also depends on the dose amounts of the second and third impurities I2 and I3, it was confirmed that the second and third impurities I2 and I3 up to a depth of about 0.2 μm from the other surface 10b side of the semiconductor substrate 10 are easily activated. Therefore, in this first forming step, the first collector layer 21a and the first cathode layer 22a among the collector layer 21 and the cathode layer 22 are configured. In other words, it can be said that the first collector layer 21a and the first cathode layer 22a are portions formed by irradiating the Gr laser. Note that the second and third impurities I2 and I3 located between the first collector layer 21a and the first cathode layer 22a and the FS layer 20 are still in an inactive state.

[0052] Subsequently, as shown in FIG. 3F, an IR laser is irradiated with an irradiation energy of 5.0 to 10 J to perform a second forming step of forming the second collector layer 21b and the second cathode layer 22b. Specifically, by irradiating the IR laser, the second impurity I2 and the third impurity I3 in an inactive state between the first collector layer 21a and the first cathode layer 22a and the FS layer 20 are activated, and the second collector layer 21b and the second cathode layer 22b among the collector layer 21 and the cathode layer 22 are configured. Therefore, it can be said that the second collector layer 21b and the second cathode layer 22b are portions formed by irradiating the IR laser.

[0053] As described above, a collector layer including the first collector layer 21a and the second collector layer 21b is configured, and a cathode layer 22 including the first cathode layer 22a and the second cathode layer 22b is configured.

[0054] FIG. 4 is a diagram showing the actual phosphorus (P) and boron (B) impurity concentrations along the depth direction of the collector layer 21 and the cathode layer 22 configured under the above conditions. Note that phosphorus is an impurity constituting the cathode layer 22, and boron is an impurity constituting the collector layer 21.

[0055] As shown in FIG. 4, in the present embodiment, since the second and third impurities I2 and I3 are ion-implanted by multi-step implantation, it is confirmed that the first collector peak CP1 exists in the first collector layer 21a and the second collector peak CP2 exists in the second collector layer 21b. Similarly, it is confirmed that the first cathode peak KP1 exists in the first cathode layer 22a and the second cathode peak KP2 exists in the second cathode layer 22b. Then, when the carrier concentration of phosphorus constituting the cathode layer 22 is investigated using SMM (abbreviation for scanning microwave microscopy), it is confirmed that phosphorus is sufficiently activated.

[0056] In the present embodiment, in the first forming step and the second forming step, although not particularly shown, a laser device having a laser light source that oscillates a laser, a dichroic mirror arranged to change the optical axis of the laser light, a condenser lens for condensing the laser light, and a displaceable stage, etc. is used. When irradiating each laser, as shown in FIG. 5, the position of the stage or the like is adjusted so that the region irradiated with the laser is relatively scanned along the plane direction of the other surface 10b of the semiconductor substrate 10. In the present embodiment, in the plane direction of the other surface 10b of the semiconductor substrate 10, when one direction is the X-axis direction and the direction orthogonal to the X-axis direction is the Y-axis direction, after being scanned along the X-axis direction, it is folded back in the Y-axis direction and scanned again along the X-axis direction so that the entire surface of the other surface 10b of the semiconductor substrate 10 is sequentially irradiated with the laser.

[0057] Then, in this embodiment, each laser is irradiated so that the overlap ratio becomes -50%. In this case, by performing laser irradiation three times on the other surface 10b of the semiconductor substrate 10, as shown in FIGS. 6A and 6B, each region is laser-irradiated twice. By performing laser irradiation in this way, while suppressing the temperature of the other surface 10b of the semiconductor substrate 10 from becoming so high as to melt, the energy per shot can be increased, making it easier to transfer heat to a deep position.

[0058] Note that FIG. 6A is a diagram when laser irradiation is performed along the X-axis direction. In FIG. 6A, for ease of understanding, for example, a diagram is shown in which the shot positions of the second and third rounds in the first to third rounds are shifted in the Y-axis direction of the paper surface, but actually, the positions in the Y-axis direction are the same. Similarly, FIG. 6B is a diagram when laser irradiation is performed along the Y-axis direction. In FIG. 6B, for ease of understanding, for example, a diagram is shown in which the shot positions of the second and third rounds in the first to third rounds are shifted in the X-axis direction of the paper surface, but actually, the positions in the X-axis direction are the same. Also, although not particularly limited, a similar laser treatment is performed in the FS layer formation step in FIG. 3B.

[0059] Thereafter, although not particularly shown, a lower electrode 23 is formed on the other surface 10b side of the semiconductor substrate 10, and the semiconductor device shown in FIG. 1 is manufactured by dividing the semiconductor substrate 10 into chip units.

[0060] According to the present embodiment described above, after irradiating the Gr laser to form the first collector layer 21a and the first cathode layer 22a, the IR laser is irradiated to form the second collector layer 21b and the second cathode layer 22b. Therefore, a semiconductor device is manufactured in which impurities are sufficiently activated even in the portion located between the first collector layer 21a and the first cathode layer 22a and the FS layer 20.

[0061] (Second Embodiment) The second embodiment will be described. This embodiment is different from the first embodiment in that the manufacturing process is changed. Since other aspects are the same as those of the first embodiment, the description thereof will be omitted here.

[0062] In this embodiment, after forming the FS layer 20 up to the process of FIG. 3B, as shown in FIG. 7A, the second impurity I2 is ion-implanted to the depth of the portion where the first collector layer 21a is formed by adjusting the acceleration energy. In this embodiment, this process corresponds to the first ion implantation.

[0063] Next, as shown in FIG. 7B, a mask (not shown) with an opening in the region where the cathode layer 22 is to be formed is disposed on the other surface 10b of the semiconductor substrate 10, and the third impurity I3 is ion-implanted to the depth of the portion where the first cathode layer 22a is formed by adjusting the acceleration energy. When ion-implanting the third impurity, more of the third impurity I3 than the second impurity I2 is ion-implanted so that the region where the third impurity I3 is implanted becomes N-type as a whole when activated. In this embodiment, this process corresponds to the third ion implantation.

[0064] Subsequently, as shown in FIG. 7C, the same process as in FIG. 3E is performed to carry out the first forming process of forming the first collector layer 21a and the first cathode layer 22a by irradiating with a Gr laser.

[0065] Thereafter, as shown in FIG. 7D, the second impurity I2 is ion-implanted into the portion where the second collector layer 21b is formed and the third impurity I3 is ion-implanted into the portion where the second cathode layer 22b is formed by adjusting the acceleration energy.

[0066] In the present embodiment, the first collector layer 21a and the first cathode layer 22a have already been formed. Therefore, when implanting the second impurity I2 by ion implantation, a mask that covers the first cathode layer 22a is disposed and the second impurity I2 is implanted by ion implantation. Similarly, when implanting the third impurity I3 by ion implantation, a mask that covers the first collector layer 21a is disposed and the third impurity I3 is implanted by ion implantation. Further, in the present embodiment, this step corresponds to the second ion implantation and the fourth ion implantation.

[0067] Thereafter, as shown in FIG. 7E, a second forming step is performed in which the same steps as in FIG. 3F are carried out and an IR laser is irradiated to form the second collector layer 21b and the second cathode layer 22b. Thereby, a collector layer 21 including the first collector layer 21a and the second collector layer 21b is configured, and a cathode layer 22 including the first cathode layer 22a and the second cathode layer 22b is configured.

[0068] In the present embodiment described above, after irradiating the Gr laser to form the first collector layer 21a and the first cathode layer 22a, the IR laser is irradiated to form the second collector layer 21b and the second cathode layer 22b. Therefore, the same effects as those of the first embodiment can be obtained. Further, as in the present embodiment, even if the second impurity I2 constituting the second collector layer 21b and the third impurity I3 constituting the second cathode layer 22b are implanted by ion implantation after forming the first collector layer 21a and the first cathode layer 22a, the same effects as those of the first embodiment can be obtained.

[0069] (Third Embodiment) The third embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the collector layer 21 is changed. Since the other aspects are the same as those of the first embodiment, the description thereof is omitted here.

[0070] As shown in FIG. 8, in the semiconductor device of this embodiment, the collector layer 21 has an extended portion 210 included in the second collector layer 21b that extends up to the cathode layer 22. That is, the cathode layer 22 has a configuration in which the portion on the collector layer 21 side is covered by the extended portion 210.

[0071] In such a semiconductor device, when the IGBT element is turned on, the electrons supplied to the drift layer 11 reach the portion located in the IGBT region 1a of the FS layer 20 and then move along the plane direction of the semiconductor substrate 10 toward the FWD region 1b side and are more likely to be discharged from the cathode layer 22. Then, holes supplied from the collector layer 21 to the drift layer 11 are also supplied to the drift layer 11 from the extended portion 210. Therefore, when the extended portion 210 is arranged on the cathode layer 22, it is easier to increase the hole concentration at the boundary between the IGBT region 1a and the FWD region 1b compared to the case where the extended portion 210 is not arranged on the cathode layer 22. For this reason, the occurrence of snapback can be suppressed.

[0072] Note that for such a semiconductor device, when ion-implanting the third impurity I3 in FIG. 3D above, a mask for ion-implanting the third impurity I3 in a state where the acceleration voltage is high and a mask for ion-implanting the third impurity in a state where the acceleration voltage is low may be prepared separately.

[0073] According to the present embodiment described above, after forming the first collector layer 21a and the first cathode layer 22a by irradiating with a Gr laser, the second collector layer 21b and the second cathode layer 22b are formed by irradiating with an IR laser. Therefore, the same effects as those of the first embodiment can be obtained.

[0074] (Other Embodiments) Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to such embodiments and structures. The present disclosure also includes various modifications and variations within the equivalent scope. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, are within the scope and spirit of the present disclosure.

[0075] For example, in each of the above embodiments, an example has been described in which the first conductivity type is N-type and the second conductivity type is P-type. However, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0076] Also, in each of the above embodiments, the semiconductor device may be of a planar type in which the gate electrode 15 is disposed on one surface 10a of the semiconductor substrate 10 instead of the trench gate type.

[0077] Furthermore, in each of the above embodiments, the configuration on the one surface 10a side of the semiconductor substrate 10 in the FWD region 1b can be appropriately changed. For example, an N-type region corresponding to the emitter region 16 or the like may be formed on the one surface 10a side of the semiconductor substrate 10 in the FWD region 1b.

[0078] Also, in each of the above embodiments, when performing laser irradiation, the overlap rate may be set to +50%, and each region may be irradiated twice by performing one round of laser irradiation.

[0079] And in the first embodiment, when ion-implanting the second impurity I2 and the third impurity I3, only one ion implantation with a constant acceleration voltage may be performed. In this case, the collector layer 21 has an impurity peak formed in one of the first collector layer 21a and the second collector layer 21b. Similarly, the cathode layer 22 has an impurity peak formed in one of the first cathode layer 22a and the second cathode layer 22b.

Description of Reference Numerals

[0080] 1a IGBT region 1b FWD region 10 Semiconductor substrate 10a One surface 10b The other surface 11 Drift layer 12 Base layer 14 Gate insulating film 15 Gate electrode 20 FS layer 21 Collector layer 21a First collector layer 21b Second collector layer 22 Cathode layer 22a First cathode layer 22b Second cathode layer I1 First impurity I2 Second impurity I3 Third impurity

Claims

1. It has an IGBT region (1a) where an IGBT element is formed and an FWD region (1b) where an FWD element is formed, a drift layer (11) of a first conductivity type, a base layer (12) of a second conductivity type formed on the drift layer, a field stop layer (20) of the first conductivity type formed on the opposite side of the base layer with the drift layer interposed therebetween, in the IGBT region, a collector layer (21) of the second conductivity type formed on the opposite side of the drift layer with the field stop layer interposed therebetween, and in the FWD region, a cathode layer (22) of the first conductivity type formed on the opposite side of the drift layer with the field stop layer interposed therebetween, with the surface on the base layer side as one surface (10a) and the surface on the collector layer and cathode layer sides as the other surface (10b), a semiconductor substrate (10); in the IGBT region, an emitter region (16) of the first conductivity type formed in the surface layer portion of the base layer; in the IGBT region, a gate insulating film (14) formed between the drift layer and the emitter region in the base layer; a gate electrode (15) formed on the gate insulating film, and a method for manufacturing a semiconductor device, comprising: preparing the semiconductor substrate having the one surface and the other surface opposite to the one surface; ion-implanting a first impurity (I1) of the first conductivity type that constitutes the field stop layer on the other surface side; irradiating an infrared laser from the other surface side to activate the first impurity and form the field stop layer; ion-implanting a second impurity (I2) of the second conductivity type that constitutes the collector layer from the other surface side; ion-implanting a third impurity (I3) of the first conductivity type that constitutes the cathode layer from the other surface side; irradiating a green laser from the other surface side to activate the second impurity and the third impurity located on the other surface side, and form a first collector layer (21a) and a first cathode layer (22a) that are portions on the other surface side of the collector layer and the cathode layer; After irradiating the green laser, irradiate an infrared laser from the other surface side to activate the second impurity located between the first collector layer and the field stop layer and the third impurity located between the first cathode layer and the field stop layer, and form a second collector layer (21b) between the first collector layer and the field stop layer to constitute the collector layer including the first collector layer and the second collector layer, and form a second cathode layer (22b) between the first cathode layer and the field stop layer to form the cathode layer including the first cathode layer and the second cathode layer. A method for manufacturing a semiconductor device.

2. By ion-implanting the second impurity and ion-implanting the third impurity, perform multiple ion-implantations while changing the acceleration energy. By forming the first collector layer and the first cathode layer, form the first collector layer and the first cathode layer including peaks (CP1, KP1) where the impurity concentration is maximized within the first collector layer and the first cathode layer. The method for manufacturing a semiconductor device according to claim 1, wherein by forming the second collector layer and the second cathode layer, form the second collector layer and the second cathode layer including peaks (CP2, KP2) where the impurity concentration is maximized within the second collector layer and the second cathode layer.

3. By ion-implanting the second impurity and ion-implanting the third impurity, ion-implant the second impurity and the third impurity across the space from the other surface of the semiconductor substrate to the field stop layer. Forming the first collector layer and the first cathode layer is performed after ion-implanting the second impurity and ion-implanting the third impurity. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein forming the second collector layer and the second cathode layer is performed after forming the first collector layer and the first cathode layer.

4. By ion-implanting the second impurity, perform a first ion-implantation for ion-implanting the second impurity on the other surface side, and a second ion-implantation for ion-implanting the second impurity at a position deeper than the first ion-implantation from the other surface side. By ion-implanting the third impurity, a third ion-implantation for ion-implanting the third impurity on the other surface side and a fourth ion-implantation for ion-implanting the third impurity at a position deeper than the third ion-implantation from the other surface side are performed. Forming the first collector layer and the first cathode layer is performed after the first ion-implantation and the third ion-implantation. The second ion-implantation and the fourth ion-implantation are performed after forming the first collector layer and the first cathode layer. A method of manufacturing a semiconductor device according to claim 1 or 2, wherein forming the second collector layer and the second cathode layer is performed after the second ion-implantation and the fourth ion-implantation.

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