Array substrate whose opening ratio can be improved while suppressing decrease in moisture resistance and display device

Abstract

To improve the opening ratio while suppressing the decrease in moisture resistance.SOLUTION: An array substrate 30 includes a first inorganic insulating film 45 disposed on an upper layer side of an insulating substrate 30A with a light-transmitting property, and a second inorganic insulating film 46 disposed on the first inorganic insulating film 45, having a higher refractive index than the first inorganic insulating film 45, and formed of a material with a high moisture-proof property. In a TFT area AA1 where a thin film transistor 37 is provided in a display area AA, inorganic insulating films 45 and 46 are provided and the second inorganic insulating film 46 covers a side surface 45A of the first inorganic insulating film 45. In an opening area AA2 in which a pixel electrode 38 is provided in the display area AA and which does not overlap with the thin film transistor 37 in a plan view, at least the first inorganic insulating film 45 is not provided.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present technology relates to an array substrate and a display device that can improve an aperture ratio while suppressing a decrease in moisture resistance. [Background technology]

[0002] It is known that TFTs (thin film transistors) are used as switching elements in display panels such as liquid crystal panels and organic EL (electroluminescence) panels. TFTs are known to be formed by stacking various thin films using a photolithography method on an array substrate (active matrix substrate, TFT substrate) that constitutes the display panel, and an example of this is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-242803

[0004] The array substrate described in Patent Document 1 does not extend the laminated film structure in the non-aperture region where the TFT is formed to the aperture region as it is, but rather has a difference in film configuration between the non-aperture region and the aperture region. More specifically, among the multiple transparent films included in the film configuration of the non-aperture region, a layer (specifically, silicon nitride (SiN x ) film) has been removed from the film structure of the aperture area, which is said to suppress unnecessary reflection of light passing through the aperture area and improve the transmittance and color temperature of the aperture area. Summary of the Invention [Problem to be solved by the invention]

[0005] However, according to the film configuration described in Patent Document 1, SiN xThere is a concern that the moisture resistance may be reduced by removing the film. x There is a concern that moisture may penetrate from the side of the laminated film at the boundary between the removed and remaining film sections, reducing moisture resistance. If moisture penetrates the semiconductor film of the TFT, the TFT's characteristics will change.

[0006] The technology described in this specification has been made in consideration of the above-described circumstances, and aims to improve the aperture ratio while suppressing a decrease in moisture resistance. [Means for solving the problem]

[0007] (1) An array substrate related to the technology described in the present specification comprises a light-transmitting insulating substrate, a first inorganic insulating film arranged on the upper layer side of the insulating substrate, and a second inorganic insulating film arranged on the first inorganic insulating film and made of a material having a higher refractive index and higher moisture resistance than the first inorganic insulating film, wherein the first inorganic insulating film and the second inorganic insulating film are arranged in a TFT region of the display region where thin film transistors are arranged, and the second inorganic insulating film covers the side surfaces of the first inorganic insulating film, and at least the first inorganic insulating film is not arranged in an opening region of the display region where pixel electrodes are arranged and which does not overlap the thin film transistors in a planar view.

[0008] (2) In addition to the above (1), the array substrate may be configured such that the first inorganic insulating film is made of silicon oxide and the second inorganic insulating film is made of silicon nitride.

[0009] (3) In addition to the above (1) or (2), the array substrate may be such that the first inorganic insulating film is a first interlayer insulating film arranged on the source electrode of the thin film transistor, and the second inorganic insulating film is a second interlayer insulating film arranged on the first interlayer insulating film.

[0010] (4) In addition to the above (3), the array substrate may have a gate insulating film interposed between the gate electrode of the thin film transistor and the semiconductor film in the TFT region, the gate insulating film is not provided in the opening region, and the second interlayer insulating film, which is the second inorganic insulating film, covers a side surface of the gate insulating film in the TFT region.

[0011] (5) In addition to any one of (1) to (4), the array substrate may be such that the second inorganic insulating film is not provided in the opening region.

[0012] (6) A display device related to the technology described in this specification includes an array substrate of any one of (1) to (5) above, a counter substrate arranged opposite the array substrate, and a liquid crystal layer sealed between the array substrate and the counter substrate. [Effects of the Invention]

[0013] According to the technology described in the present specification, it is possible to improve the aperture ratio while suppressing a decrease in moisture resistance. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a perspective view of a liquid crystal display device according to a first embodiment; [Figure 2] Cross section of a liquid crystal panel [Figure 3] Schematic diagram showing the planar layout of the display area of ​​the array substrate [Figure 4] Cross-sectional view of the array substrate [Figure 5] 1 is a cross-sectional view of an array substrate according to a first comparative example; [Figure 6] 10 is a cross-sectional view of an array substrate according to a second embodiment. [Figure 7] 10 is a cross-sectional view of an array substrate according to a third embodiment. [Figure 8] 10 is a cross-sectional view of an array substrate according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] <Embodiment 1> A liquid crystal display device 100 (an example of a display device) according to embodiment 1 will be described with reference to Figures 1 to 4. The drawings show X, Y, and Z axes, and each axis is drawn so that it is a common direction in each drawing. The +Z direction is the front side (display surface side), and the -Z direction is the back side.

[0016] As shown in FIG. 1, the liquid crystal display device 100 includes a liquid crystal panel 10 (an example of a display panel) that displays an image, a driver 12 that drives the liquid crystal panel 10, a control board 16 that supplies various signals to the driver 12, a flexible board 14 that electrically connects the liquid crystal panel 10 and the control board 16, and a backlight device 80 (an example of a lighting device) that is an external light source arranged on the back side of the liquid crystal panel 10 and irradiates the liquid crystal panel 10 with light for display.

[0017] 1 and 2, the surface of the liquid crystal panel 10 is divided into a display area (active area) AA that is capable of displaying an image and is located in the center, and a non-display area (non-active area) NAA that is located on the outer periphery of the display area AA and has a frame-like (picture frame-like) shape in a plan view. The planar shape of the liquid crystal panel 10 is not limited, but in this embodiment, it has an overall vertically elongated rectangular shape with its short side aligned with the X direction, its long side aligned with the Y direction, and its thickness aligned with the Z direction.

[0018] 2, the liquid crystal panel 10 comprises a pair of substrates 20, 30 and a liquid crystal layer 18 (an example of a medium layer) containing liquid crystal molecules whose optical properties change when an electric field is applied. The substrates 20, 30 are bonded together with a sealant 11 while maintaining a cell gap equal to the thickness of the liquid crystal layer 18, and the liquid crystal layer 18 is sealed in the internal space. In addition, polarizing plates 19 are attached to the outer surfaces of the substrates 20, 30, respectively.

[0019] Of the pair of substrates 20, 30, the one disposed on the front side (display surface side) is the counter substrate 20, and the one disposed on the back side is the array substrate (active matrix substrate, TFT substrate) 30. The counter substrate 20 and the array substrate 30 each have a configuration in which various films 20B, 30B are laminated on the inner surface (liquid crystal layer 18 side) of a light-transmitting glass substrate 20A, 30A (an example of an insulating substrate). The counter substrate 20 and the array substrate 30 are manufactured by laminating various films on the glass substrates 20A, 30A while patterning them using a known photolithography method. An alignment film is applied to the top layer of the counter substrate 20 and the array substrate 30 (the layer closest to the liquid crystal layer 18) so as to cover the laminated film formed by the photolithography method.

[0020] 3, a large number of gate wirings (scanning lines) 33 extending in the X direction and source wirings (data lines, signal lines) 34 extending in the Y direction intersecting the gate wirings 33 are formed in a grid pattern in the display area AA of the array substrate 30. TFTs 37, which are switching elements, and pixel electrodes 38 are formed in each area surrounded by the gate wirings 33 and the source wirings 34. A large number of TFTs 37 and pixel electrodes 38 are arranged in a matrix pattern throughout the entire display area AA.

[0021] The pixel electrode 38 is disposed in a region surrounded by two source lines 34 spaced apart in the X direction and two gate lines 33 spaced apart in the Y direction. The pixel electrode 38 has, for example, a vertically elongated rectangular shape in a plan view to match the planar shape of this region. The region of the display region AA where the TFT 37 is provided is referred to as the TFT region AA1, and the region of the display region AA where the pixel electrode 38 is provided and does not overlap the TFT 37 in a plan view is referred to as the aperture region AA2. That is, the display region AA includes the TFT region AA1 and the aperture region AA2.

[0022] The source wiring 34 is connected to the driver 12 via lead-out wiring, and a data signal (image signal) is supplied to the source wiring 34 from a source drive circuit in the driver 12. The gate wiring 33 is connected to a GDM (Gate Driver Monolithic circuit) section monolithically formed in the non-display area NAA, and a scanning signal is supplied to the gate wiring 33 from the GDM section. The GDM section is connected to the flexible substrate 14 via lead-out wiring, and a signal is supplied from the control substrate 16 through the flexible substrate 14.

[0023] When a signal is input to the TFT 37 from the source line 34 and the gate line 33, the pixel electrode 38 connected to the TFT 37 is charged, changing the potential difference between the pixel electrode 38 and the common electrode. A reference potential is supplied to the common electrode. By controlling the electric field applied to the liquid crystal layer 18 using this potential difference, the orientation state of the liquid crystal molecules is appropriately switched, thereby driving the liquid crystal panel 10. The common electrode may be formed on either the array substrate 30 or the counter substrate 20, but in this embodiment it is formed on the counter substrate 20.

[0024] On the opposing substrate 20, color filters (red color filter, blue color filter, green color filter) are formed at positions overlapping with the pixel electrodes 38, and a light-shielding film (so-called black matrix) is formed at least at positions overlapping with the source wiring 34.

[0025] Next, the layer structure of the array substrate 30 will be described. As shown in FIG. 4, the array substrate 30 includes, in order from the glass substrate 30A side, a light-shielding portion 41, a base coat film 42, a gate electrode 37G and gate wiring 33 made of a gate metal film, a first gate insulating film 43, a second gate insulating film 44, a semiconductor film 37C (which serves as the channel region of the TFT 37), a source electrode 37S made of a source metal film, a source wiring 34 and drain electrode 37D, a first interlayer insulating film 45 (an example of a first inorganic insulating film), a second interlayer insulating film 46 (an example of a second inorganic insulating film), a planarizing film 47, and a pixel electrode 38 made of a first transparent conductive film. The pixel electrode 38 penetrates the first interlayer insulating film 45, the second interlayer insulating film 46, and the planarizing film 47 and is interlayer-connected to the drain electrode 37D. If a common electrode is provided on the array substrate 30, the common electrode is formed below or above the pixel electrode 38 via another interlayer insulating film.

[0026] The light-shielding portion 41, the gate metal film, and the source metal film are each a single layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials, and have electrical conductivity and light-shielding properties.

[0027] The base coat film 42, the second gate insulating film 44, and the first interlayer insulating film 45 are made of an inorganic insulating material, for example, an SiO2 (silicon oxide) film.

[0028] The first gate insulating film 43 and the second interlayer insulating film 46 are made of an inorganic insulating material that has a higher refractive index and is more moisture-proof than the base coat film 42 and the first interlayer insulating film 45 disposed below them. For example, when the base coat film 42 and the first interlayer insulating film 45 are made of SiO2, the first gate insulating film 43 and the second interlayer insulating film 46 are made of SiN x It is said that.

[0029] The semiconductor film 37C has one end connected to the source electrode 37S and the other end connected to the drain electrode 37D. The semiconductor film 37C is disposed above the gate electrode 37G, and the TFT 37 has a so-called bottom-gate structure. The semiconductor film 37C is made of an oxide semiconductor material containing at least one metal element selected from the group consisting of In, Ga, and Zn.

[0030] The planarization film 47 is made of an organic resin material, for example, PMMA (acrylic resin), and is usually thicker than other insulating films made of inorganic materials.

[0031] The first transparent conductive film is made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0032] In the TFT region AA1, a light-shielding portion 41 is provided at a position overlapping at least the entire area of ​​the gate electrode 37G. The light-shielding portion 41 blocks light irradiated from the backlight device 80 onto the semiconductor film 37C from below. This makes it possible to suppress fluctuations in the characteristics of the TFT 37 that may occur when light is irradiated onto the channel region of the TFT 37.

[0033] In the TFT region AA1, a base coat film 42 is interposed between the light-shielding portion 41 and the gate electrode 37G, gate insulating films 43 and 44 are interposed between the gate electrode 37G and the semiconductor film 37C, and interlayer insulating films 45 and 46 are interposed between the source electrode 37S and the drain electrode 37D and the planarizing film 47. On the other hand, in the opening region AA2 where the TFT 37 is not provided, the base coat film 42, the gate insulating films 43 and 44, and the interlayer insulating films 45 and 46 are not provided.

[0034] In the TFT region AA1, a side surface 42A of the base coat film 42, a side surface 44A of the second gate insulating film 44, and a side surface 45A of the first interlayer insulating film 45 are covered with the second interlayer insulating film 46. An emission-side main surface 45B (the main surface opposite to the glass substrate 30A) of the first interlayer insulating film 45 is covered with the second interlayer insulating film 46. An incidence-side main surface 44B (the main surface on the glass substrate 30A side) of the second gate insulating film 44 is covered with the first gate insulating film 43.

[0035] The array substrate 30 having the above-described configuration is manufactured by laminating various films in the above-described order on the glass substrate 30A while patterning them using a known photolithography method. Each film may be subjected to a heat treatment at any timing.

[0036] Here, "patterning" refers to film processing based on a general photolithography method, specifically, forming a photoresist film on the film to be processed, exposing the photoresist film to light using an exposure device through a photomask with a predetermined pattern, developing the photoresist film, and then etching the film to be processed through the developed photoresist film.

[0037] Next, the effects of the array substrate 30 having the above-described configuration will be described in comparison with Comparative Example 1. If, as shown in an array substrate 930 according to Comparative Example 1 in Fig. 5, the base coat film 142, gate insulating films 943 and 944, and first interlayer insulating film 945 are formed in the opening region AA2 as in the TFT region AA1, light from the backlight device 80 is transmitted between the base coat film 142 (for example, an SiO2 film) and the first gate insulating film 943 (for example, an SiN x and the interface between the first interlayer insulating film 945 (for example, an SiO2 film) and the second interlayer insulating film 46 (for example, an SiN x As a result, the aperture ratio (transmittance) of the aperture region AA2 decreases.

[0038] In contrast, in this embodiment, as shown in FIG. 4 , the base coat film 42, gate insulating films 43 and 44, and interlayer insulating films 45 and 46 are not provided in the opening region AA2. This eliminates the interface where the refractive index difference occurs in the opening region AA2, thereby suppressing reflection caused by the interface. Even with this layer configuration, the highly moisture-resistant second interlayer insulating film 46 covers the side surface 44A of the second gate insulating film 44 and the side surface 45A of the first interlayer insulating film 45, thereby preventing a decrease in the moisture resistance of the TFT 37. More specifically, this prevents moisture from penetrating into the semiconductor film 37C located inside these side surfaces 44A and 45A, thereby preventing fluctuations in the characteristics of the TFT 37. Moisture may penetrate from the outside through the planarization film 47, which is made of an organic insulating material, for example.

[0039] Furthermore, the emission-side main surface 45B of the first interlayer insulating film 45 is covered with the highly moisture-resistant second interlayer insulating film 46, and the incidence-side main surface 44B of the second gate insulating film 44 is covered with the highly moisture-resistant first gate insulating film 43. This prevents moisture from penetrating into the semiconductor film 37C through the emission-side main surface 45B and the incidence-side main surface 44B. As described above, the array substrate 30 according to this embodiment can improve the aperture ratio while preventing a decrease in moisture resistance.

[0040] <Embodiment 2> An array substrate 130 according to embodiment 2 will be described with reference to Fig. 6. This embodiment differs from embodiment 1 in that a base coat film 142 is provided in the opening area AA2. Duplicate descriptions of the structure, action, and effects similar to those of embodiment 1 will be omitted.

[0041] The base coat film 142 is also provided in the opening region AA2, extending from the TFT region AA1. Even in this case, the interfaces where refractive index differences occur in the opening region AA2, as in Comparative Example 1 (the interface between the base coat film 142 and the first gate insulating film 943, and the interface between the first interlayer insulating film 945 and the second interlayer insulating film 46 in FIG. 5 ) are eliminated, thereby suppressing reflection caused by these interfaces. Furthermore, the side surface 44A of the second gate insulating film 44 and the side surface 45A of the first interlayer insulating film 45 are covered by the second interlayer insulating film 46, which has high moisture resistance. As a result, it is possible to prevent moisture from penetrating the semiconductor film 37C located inside these layers, which would cause fluctuations in the characteristics of the TFT 37, and to suppress a decrease in moisture resistance.

[0042] <Embodiment 3> An array substrate 230 according to embodiment 3 will be described with reference to Fig. 7. This embodiment differs from embodiment 1 in that a second interlayer insulating film 146 is provided in the opening area AA2. Duplicate descriptions of the structure, action, and effects similar to those of embodiments 1 and 2 will be omitted.

[0043] The second interlayer insulating film 146 is also provided in the aperture region AA2, and extends from the TFT region AA1. This eliminates the need for a process for patterning the second interlayer insulating film 146 in the manufacturing process, thereby reducing the number of steps. However, since light from the backlight device 80 is reflected at the interface between the glass substrate 30A and the second interlayer insulating film 146, the effect of improving the aperture ratio (transmittance) is lower than in the first and second embodiments.

[0044] <Embodiment 4> An array substrate 330 according to embodiment 4 will be described with reference to Fig. 8. This embodiment differs from embodiment 3 in that a base coat film 142 is provided in the opening area AA2. Duplicate descriptions of the structure, action, and effect similar to those of embodiments 1 to 3 will be omitted.

[0045] The base coat film 142 and the second interlayer insulating film 146 are also provided in the aperture region AA2, and extend from the TFT region AA1. That is, this embodiment can be said to have a layer structure that combines the second and third embodiments. This eliminates the need for a step of patterning the second interlayer insulating film 146 in the manufacturing process, thereby suppressing an increase in the number of steps. However, since light from the backlight device 80 is reflected at the interface between the base coat film 142 and the second interlayer insulating film 146, the effect of improving the aperture ratio (transmittance) is lower than in the first and second embodiments.

[0046] <Other embodiments> The technology described in this specification is not limited to the embodiments described above with reference to the drawings, and the following embodiments, for example, are also included within the technical scope of the present invention.

[0047] (1) The layer structure and planar layout of each layer of the liquid crystal panel 10 are not limited to those shown in the drawings. For example, the TFT 37 may have a top gate structure or a double gate structure.

[0048] (2) The technology described in this specification can also be applied to display panels (for example, organic EL panels) other than the liquid crystal panel 10 that uses TFTs as switching elements in the display area AA. [Explanation of symbols]

[0049] 10...liquid crystal panel (display panel), 18...liquid crystal layer, 20...counter substrate, 30, 130, 230, 330...array substrate, 37...thin film transistor, 37C...semiconductor film, 37G...gate electrode, 37S...source electrode, 38...pixel electrode, 44...second gate insulating film (gate insulating film), 44A...side surface, 45...first interlayer insulating film (first inorganic insulating film), 45A...side surface, 46...second interlayer insulating film (second inorganic insulating film), 100...liquid crystal display device (display device), AA...display area, AA1...TFT area, AA2...aperture area

Claims

1. a light-transmitting insulating substrate; a first inorganic insulating film disposed on an upper layer side of the insulating substrate; a second inorganic insulating film disposed on the first inorganic insulating film and made of a material having a higher refractive index and higher moisture resistance than the first inorganic insulating film; In the TFT region of the display region where thin film transistors are provided, the first inorganic insulating film and the second inorganic insulating film are provided; the second inorganic insulating film covers a side surface of the first inorganic insulating film, an array substrate in which at least the first inorganic insulating film is not provided in an opening region of the display region where a pixel electrode is provided and which does not overlap the thin film transistor in a plan view;

2. 2. The array substrate according to claim 1, wherein the first inorganic insulating film is made of silicon oxide, and the second inorganic insulating film is made of silicon nitride.

3. the first inorganic insulating film is a first interlayer insulating film disposed on a source electrode of the thin film transistor, 3. The array substrate according to claim 1, wherein the second inorganic insulating film is a second interlayer insulating film disposed on the first interlayer insulating film.

4. a gate insulating film interposed between a gate electrode of the thin film transistor and a semiconductor film is provided in the TFT region; The gate insulating film is not provided in the opening region, 4. The array substrate according to claim 3, wherein in the TFT region, the second interlayer insulating film, which is the second inorganic insulating film, covers a side surface of the gate insulating film.

5. 3. The array substrate according to claim 1, wherein the second inorganic insulating film is not provided in the opening region.

6. The array substrate according to claim 1 or 2; an opposing substrate disposed opposite the array substrate; a liquid crystal layer sealed between the array substrate and the counter substrate.

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