Clock doubler with correction for output clock cycle and clock duty cycle

Abstract

A synthesizable clock doubler is disclosed. The clock doubler is implemented using a unique combination of logic cells from a standard cell library. At the core of the clock doubler is a high-frequency ring oscillator that generates timing information for clock measurements. A replica ring oscillator is used to generate programmable delays to compensate for output clock imperfections, such as cycle-to-cycle variations and double the clock duty cycle.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 412,915, filed October 4, 2022, entitled "CLOCK DOUBLER WITH CORRECTION FOR OUTPUT CLOCK CYCLE AND CLOCK DUTY CYCLE," which is expressly incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to electronic devices and systems, and more particularly to circuits for generating clock signals for electronic components. [Background technology]

[0003] In electronic instrumentation and signal processing, a clock is a circuit that generates a clock signal for timing the operation of electronic components, e.g., analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc. Clocks are used in many different applications, e.g., automotive, communications, aerospace, and defense.

[0004] Various factors can affect the cost, quality, and robustness of a clock. Physical constraints such as space / surface area can further constrain the requirements or specifications of a clock, thus necessitating trade-offs and ingenuity when designing an optimal clock for a given application. Summary of the Invention [Means for solving the problem]

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all possible aspects, and it is not intended to identify key or critical elements of all aspects or to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006] According to one embodiment, a clock doubler may include a calibration circuit including a ring oscillator and a first counter. The ring oscillator may be configured to identify timing information for a clock measurement associated with an output clock frequency. The first counter may be configured to output timing information for calibration of a clock providing the input clock frequency. The clock doubler may further include a delay circuit including a replica ring oscillator and a second counter. The replica ring oscillator may be configured to determine a delay value for correction of the input clock frequency based on the defined delay value. The second counter may be configured to output a delay value for correction of an output clock frequency having a clock frequency that is a multiple of the input clock frequency.

[0007] According to another embodiment, a method for clock cycle correction may include identifying, via a ring oscillator, timing information for a clock measurement associated with an output clock frequency. The method may further include outputting, via a first counter, timing information for calibration of a clock providing the input clock frequency. The method may further include determining, via a replica ring oscillator, a delay value for correction of the input clock frequency based on the defined delay value. The method may further include outputting, via a second counter, a delay value for correction of an output clock frequency having a clock frequency that is a multiple of the input clock frequency.

[0008] According to additional embodiments, the clock doubler may include means for identifying timing information for a clock measurement associated with the output clock frequency. The clock doubler may further include means for outputting timing information for calibration of a clock providing the input clock frequency. The clock doubler may further include means for determining a delay value for correction of the input clock frequency based on the defined delay value. The clock doubler may additionally include means for outputting a delay value for correction of an output clock frequency having a clock frequency that is a multiple of the input clock frequency.

[0009] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts and in which: [Brief explanation of the drawings]

[0010] [Figure 1] 1 provides a block diagram of a clock doubler according to some embodiments of the present disclosure; [Figure 2] 1 provides an illustration of an exemplary clock doubler, according to some embodiments of the present disclosure. [Figure 3] 1 provides a diagram of an example calibration circuit for a clock doubler, according to some embodiments of the present disclosure. [Figure 4] 1 provides a diagram of an example programmable delay circuit for a clock doubler, in accordance with some embodiments of the present disclosure. [Figure 5] 1 is a flowchart of an exemplary method for clock cycle correction, according to some embodiments of the present disclosure. [Figure 6] 1 provides a schematic diagram of an example system in which one or more clock doublers may be implemented, according to some embodiments of the present disclosure. [Figure 7] FIG. 1 is a block diagram of an example electrical device that may include one or more clock doublers, in accordance with some embodiments of the present disclosure. [Figure 8]1 provides a block diagram illustrating an example data processing system that may be configured to control the operation of one or more clock doublers, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this disclosure are set forth in the following description and accompanying drawings.

[0012] A synthesizable clock doubler is disclosed. The clock doubler is implemented using a unique combination of logic cells from a standard cell library. At the core of the clock doubler is a high-frequency ring oscillator that generates timing information for clock measurements. A replica ring oscillator is used to generate programmable delays to compensate for output clock imperfections, such as cycle-to-cycle variations and double the clock duty cycle.

[0013] As will be appreciated by those skilled in the art, aspects of the present disclosure, particularly aspects of the clock doubler proposed herein, may be embodied in various ways, such as a method, a system, a computer program product, or a computer-readable storage medium. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a “circuit,” “module,” or “system.” Functionality described in the present disclosure may be implemented as an algorithm executed by one or more hardware processing units, e.g., one or more microprocessors of one or more computers. In various embodiments, each different step and some steps of the methods described herein may be performed by different processing units. Furthermore, aspects of the present disclosure may take the form of a computer program product having computer-readable program code embodied therein, e.g., stored thereon, preferably non-transitory, in one or more computer-readable media. In various embodiments, such computer programs may, for example, be downloaded (updated) into existing devices and systems (e.g., existing ADCs, DACs, other electronic components, digital signal processing (DSP) cores, and / or their controllers, etc.) or may be stored in these devices and systems at the time of manufacture.

[0014] The following detailed description presents various descriptions of certain specific embodiments, however, the innovations described herein can be embodied in many different ways, as defined and encompassed by, for example, selected examples.

[0015] In the following description, reference is made to the drawings, in which like reference numbers may indicate identical or functionally similar elements. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. Moreover, some embodiments may incorporate any suitable combination of features from two or more drawings. It should also be understood that an embodiment may include more elements than shown in the drawings and / or a subset of the elements shown in the drawings. Generally, the several drawings provided herein illustrate various aspects of clock doublers and systems in which such circuits may be implemented, although the details of these systems may vary in different embodiments. For example, various components of the clock doublers presented herein may have additional components included therein or coupled thereto, such as logic, memory, passive elements (e.g., resistors), or other elements not specifically shown in the drawings. In another example, details shown in some of the drawings, such as the specific arrangements and example implementation details of various components (e.g., duty cycle correction circuits, delay circuits, etc.) of the clock doublers presented herein, the specific arrangements of coupling connections between the outputs of various stages of the clock doubler and the clock doubler's logic elements, may vary in different embodiments, and the drawing figures provide only some examples of how these components may be used together to implement a clock doubler with relatively low area and power consumption. In yet another example, while some embodiments shown in the drawings depict a certain number of components (e.g., a certain number of delay circuits), it is understood that these embodiments may be implemented in a clock doubler or any other device or system having any number of these components in accordance with the description provided herein. Furthermore, while certain elements, such as various elements of a clock doubler, may be depicted in the drawings as communicatively coupled using a single depicted line, in some embodiments, any of these elements may be coupled by multiple conductive lines, such as those that may be present in a bus, or when differential signals are involved.

[0016] The detailed description may use the phrases "in one embodiment" or "in an embodiment," each of which may refer to one or more of the same or different embodiments. Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe a common object merely indicates that various instances of the same object are being referred to and is not intended to imply that the objects so described must be in a given order, temporally, spatially, ranked, or in any other manner. Furthermore, for purposes of this disclosure, the phrase "A and / or B" or the designation "A / B" means (A), (B), or (A and B), and the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the designation "A / B / C" means (A, B, and / or C). The term "between" when used in reference to a measurement range includes the ends of the measurement range.

[0017] Various aspects of the illustrative embodiments are described using terms commonly used by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term “connected” means a direct electrical connection between the things connected, with no intermediate devices / components, while the term “coupled” means either a direct electrical connection between the things connected, or an indirect electrical connection via one or more passive or active intermediate devices / components. In another example, the terms “circuit” or “circuitry” (which may be used interchangeably) refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired functionality. Sometimes, in this description, the term “circuit” may be omitted (e.g., a clock doubler circuit may simply be referred to as a “clock doubler,” etc.). When used, terms such as “substantially,” “approximately,” and “about” may be used to refer to being within + / −10% of a target value, e.g., within + / −5% of a target value, or within + / −2% of a target value, generally, as described herein or known in the art, in light of a particular value.

[0018] FIG. 1 provides a block diagram of a clock doubler 100 according to some embodiments of the present disclosure. As shown, clock doubler 100 may be configured to receive an input clock signal 102 (or simply “input clock”) and output an output clock signal 104 (or simply “output clock”) that is a clock signal doubled compared to input clock signal 102 (i.e., output clock signal 104 is a clock signal having a frequency substantially doubled compared to the frequency of input clock signal 102). As further shown in FIG. 1 , clock doubler 100 may include a ring oscillator 110 and one or more replica ring oscillators 120. Ring oscillator 110 may be configured to generate timing information for clock measurements. In some embodiments, ring oscillator 110 may be a high-frequency ring oscillator. Replica ring oscillator 120 may be configured to generate a programmable delay to compensate for imperfections in the output clock, such as cycle-to-cycle variations and duty cycles of the doubled clock generated by clock doubler 100. FIG. 1 further indicates that in some embodiments, clock doubler 100 may further include a calibration circuit 130 and / or a programmable delay circuit 140.

[0019] Clock doubler 100 may be a relatively simple clock to implement without analog components such as resistors and capacitors, and without analog blocks such as comparators. Clock doubler 100 may be implemented using logic cells solely from standard cell libraries and therefore may be fully synthesizable and easily reusable in various technologies. For example, in some implementations, output clock signal 104 of clock doubler 100 may be used directly to clock the operation of one or more ADCs and / or one or more DACs.

[0020] Typically, the phase noise, clock cycle-to-clock variation, and clock duty cycle of the doubled clock are major areas of concern. In the clock doubler 100, the ring oscillator 110 may be a high-frequency free-running ring oscillator used to generate timing information for clock measurement and correction. The absolute error after clock calibration and correction may be limited by the clock period of the ring oscillator 110. When the ratio of the ring oscillator frequency to the doubled clock frequency is large, the relative error may be small. The clock period and duty cycle may be characterized by counting the number of ring oscillator clock cycles. The clock characterization engine may have six operating modes: input clock period measurement, input clock duty cycle measurement, double clock period and duty cycle measurement using a clock aligned with the input clock's logic high region, and double clock period and duty cycle measurement using a clock aligned with the input clock's logic low region. The input clock duty cycle measurement and double clock period measurement may be used for input clock duty cycle correction. Input clock duty cycle correction can be performed with a single delay chain that can operate on either the rising or falling edge of the clock to correct for duty cycle errors above or below a target (e.g., a 50% target). The replica ring oscillator 120 and counter can be used to generate timing information that ensures the doubled clock has an approximately 50% duty cycle. Together, the ring oscillator 110 and counter can be viewed as a programmable wraparound delay line with the potential to generate long delays with just a few logic gates.

[0021] FIG. 2 provides a diagram of an exemplary clock doubler 200 in accordance with some embodiments of the present disclosure. Clock doubler 200 may be an implementation of clock doubler 100 of FIG. 1. To that end, several components of clock doubler 100 are shown in clock doubler 200. Specifically, as shown in FIG. 2, clock doubler 200 may include a calibration circuit 130 that includes ring oscillator 110, and may further include two programmable delay circuits 140 (labeled in FIG. 2 as first delay circuit 140-1 and second delay circuit 140-2), each of which may include a respective replica ring oscillator 120. Although not specifically shown in FIG. 2, calibration circuit 130 and programmable delay circuit 140 each include a respective counter.

[0022] There are many ways to implement a clock doubler, including XORing an input clock with a delayed version of the input clock, using a delay-locked loop, or using resistor-capacitor (RC) time constants to generate the necessary timing information. Clock doubler 200 is a novel extension to XOR-based clock doublers with a built-in time base and clock measurement and correction circuitry to generate a near-perfect clock at twice the input clock frequency. The resulting clock doubler consumes relatively low power, has good phase noise characteristics, is fully synthesizable in newer technologies, and may be easily reusable. A free-running ring oscillator with synchronous start control and counters is an efficient way to generate long, programmable delays. A ring oscillator can also provide a time base independent of the input clock used for clock measurement and correction. Overall, clock doubler 200 is a simpler, all-digital design suitable for software-defined radios.

[0023] The clock doubler 200 may have a wide input range for the frequency of the input clock signal 102, for example, from approximately 10 megahertz (MHz) to approximately 80 MHz. The clock doubler 200 may be synthesizable and may be an all-standard-cell implementation with calibration for double the clock cycle-to-cycle variation and duty cycle. The clock doubler 200 may use a free-running ring oscillator as a time reference for calibration and two replica ring oscillators 120 for long clock delay generation. The clock doubler 200 may implement process voltage temperature (PVT) tracking of the multiple ring oscillators. Calibration of the clock doubler 200 may occur in the background without affecting the clock path. The clock doubler 200 may implement substantially glitch-free clock non-ideality correction.

[0024] 3 provides a diagram of an example calibration circuit 300 for a clock doubler (i.e., clock doublers 100 and 200) according to some embodiments of the present disclosure. Calibration circuit 300 may be one implementation of calibration circuit 130 of FIG.

[0025] The calibration circuit 300 may include a pulse generator 302 configured to receive a clock and a count start signal and output pulses to a ring oscillator 304 and a counter 306. The ring oscillator 304 and the counter 306 may be configured to provide clock period and clock pulse width measurements. The clock period and clock pulse width may be measured as a number of ring oscillator clock cycles. The reference ring oscillator-based measurements may be applied to generate a programmable delay using a replica ring oscillator-based delay circuit.

[0026] 4 provides a diagram of an example programmable delay circuit 400 for a clock doubler (i.e., clock doublers 100 and 200) according to some embodiments of the present disclosure. Delay circuit 400 may be one implementation of delay circuit 140 of FIG.

[0027] Delay circuit 400 may include a programmable delay circuit based on a ring oscillator 402 and a counter 404. When oscillator 402 starts, counter 404 may start with a value set by P[M-1:0], and when counter 404 counts down to 0, a delay pulse may be generated.

[0028] 5 is a flowchart of an example method 500 of clock cycle correction. Example method 500 may be performed by clock doublers 100 and / or 200, which may include one or more components as discussed in FIGS. 1-4 and may operate according to additional electrical or electronic components as discussed in FIGS. 6-8.

[0029] At block 502, method 500 may identify timing information for a clock measurement associated with the output clock frequency. For example, calibration circuit 130 of clock doubler 100 or 200, via ring oscillator 110 or 304, may identify or otherwise determine timing information such as a clock period and clock pulse width for a clock measurement associated with the output clock frequency (i.e., of output clock signal 104).

[0030] At block 504, method 500 may output timing information for calibration of the clock that provides the input clock frequency. For example, calibration circuit 130 of clock doubler 100 or 200 may output timing information for calibration of the clock that provides the input clock frequency via a first counter (i.e., counter 306).

[0031] At block 506, method 500 may determine a delay value for correction of the input clock frequency based on the defined delay value. For example, programmable delay circuit 140 of clock doubler 100 or 200 may determine or otherwise receive, via replica ring oscillator 120 or 402, a delay value for correction of the input clock frequency (i.e., of input clock signal 102) based on the defined delay value (i.e., Delay[M-1:0]).

[0032] At block 508, method 500 may output a delay value for correcting an output clock frequency having a clock frequency that is a multiple of the input clock frequency. For example, programmable delay circuit 140 of clock doubler 100 or 200 may output, via a second counter (i.e., counter 404), a delay value for correcting an output clock frequency (i.e., output clock signal 104) having a clock frequency that is a multiple (i.e., twice) of the input clock frequency.

[0033] In some embodiments, the clock period and clock pulse width may be identified based on the number of ring oscillator clock cycles (ie, of ring oscillator 110).

[0034] In some embodiments, the delay value may be further based on timing information (ie, clock period and clock pulse width).

[0035] In some embodiments, the correction of the output clock frequency (ie, of the output clock signal 104) may include at least one of correcting a double clock cycle-to-cycle variation or a double clock duty cycle.

[0036] In some embodiments, the replica ring oscillator may be configured to determine the delay value based on a counter value corresponding to zero.

[0037] In some embodiments, the delay circuit includes two replica ring oscillators.

[0038] In various embodiments, a controller may be used to control various aspects of operating clock doubler 100 as described herein. Such a controller may be implemented, for example, as a data processing system as shown in FIG.

[0039] The clock doubler 100 can be implemented in a variety of electronic devices and systems, some examples of which are shown in FIGS.

[0040] 6 provides a schematic diagram of an example system 600 in which one or more clock doublers 100 and 200 may be implemented, according to some embodiments of the present disclosure. Specifically, FIG. 6 illustrates that clock doublers 100 and 200 may be included as part of or communicatively coupled to a DSP core or circuitry 610. System 600 may further include a controller 620 configured to control various aspects of operating clock doublers 100 and 200, as described herein.

[0041] FIG. 7 is a block diagram of an example electrical device 600 that may include one or more clock doublers 100 according to any of the embodiments disclosed herein. For example, any suitable ones of the components of electrical device 700 may include one or more of the clock doublers 200 disclosed herein. Although several components are shown in FIG. 7 as being included in electrical device 700, any one or more of these components may be omitted or duplicated as suitable for the application. In some embodiments, some or all of the components included in electrical device 700 may be mounted on one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SoC).

[0042] 7, electrical device 700 may not include one or more of the components shown in FIG. 7, but electrical device 700 may include interface circuitry for coupling to one or more of the components. For example, electrical device 700 may not include display device 706, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 706 may be coupled. In another set of examples, electrical device 700 may not include audio input device 718 or audio output device 708, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 718 or audio output device 708 may be coupled.

[0043] The electrical device 700 may include a processing device 702 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. The processing device 702 may include one or more DSPs, application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 700 may include memory 704, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 704 may include memory that shares a die with the processing device 702. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic RAM (STT-MRAM).

[0044] In some embodiments, electrical device 700 may include a communications chip 712 (e.g., one or more communications chips). For example, communications chip 712 may be configured to manage wireless communications for data transfer to and from electrical device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through a non-solid medium through the use of modulated electromagnetic radiation. The term does not imply that the associated device does not include any wiring, although in some embodiments it may not.

[0045] The communications chip 712 may implement any of several wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), the Long Term Evolution (LTE) project along with any amendments, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, a certification mark for products that pass conformance and interoperability testing for the IEEE 802.16 standard. The communications chip 712 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications chip 712 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications chip 712 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols specified for 3G, 4G, 5G, and beyond. In other embodiments, the communications chip 712 may operate according to other wireless protocols. Electrical device 700 may include an antenna 722 for facilitating wireless communications and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0046] In some embodiments, the communications chip 712 may manage wired communications, such as electrical communications protocols, optical communications protocols, or any other suitable communications protocol (e.g., Ethernet). As described above, the communications chip 712 may include multiple communications chips. For example, a first communications chip 712 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications chip 712 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications chip 712 may be dedicated to wireless communications, and the second communications chip 712 may be dedicated to wired communications.

[0047] Electrical device 700 may include battery / power circuitry 714. Battery / power circuitry 714 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 700 to an energy source separate from electrical device 700 (e.g., AC line power).

[0048] The electrical device 700 may include a display device 706 (or corresponding interface circuitry as discussed above), which may include any visual indicator such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0049] The electrical device 700 may include an audio output device 708 (or corresponding interface circuitry as discussed above), which may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0050] The electrical device 700 may include an audio input device 718 (or corresponding interface circuitry as discussed above), which may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0051] The electrical device 2100 may include a GPS device 716 (or corresponding interface circuitry as discussed above), which may communicate with a satellite-based system, as known in the art, and receive the location of the electrical device 700.

[0052] The electrical device 700 may include another output device 710 (or corresponding interface circuitry as discussed above). Examples of other output devices 710 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0053] The electrical device 700 may include other input devices 720 (or corresponding interface circuitry as discussed above). Examples of other input devices 720 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a mouse, a stylus, a cursor control device such as a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0054] Electrical device 700 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server device or other network computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, electrical device 700 may be any other electronic device that processes data.

[0055] 8 provides a block diagram illustrating an exemplary data processing system 800 that may be configured to control the operation of one or more clock doublers 100, according to some embodiments of the present disclosure. For example, data processing system 800 may be configured to implement or control portions of clock doubler 100, clock doubler 200, or any further embodiments of a clock doubler described herein. In another example, data processing system 800 may be configured to implement at least a portion of controller 520 or any other controller configured to control various aspects of operating a clock doubler as described herein.

[0056] 8, data processing system 800 may include at least one processor 802, e.g., a hardware processor 802, coupled to memory elements 804 via a system bus 806. As such, the data processing system may store program code in memory elements 804. The processor 802 may also execute program code accessed from memory elements 804 via the system bus 806. In one aspect, the data processing system may be implemented as a computer suitable for storing and / or executing program code. However, it should be understood that data processing system 800 may be implemented in the form of any system including a processor and memory capable of performing the functions described within this disclosure.

[0057] In some embodiments, processor 802 can execute software or algorithms to perform activities as discussed in this disclosure, particularly activities related to a clock doubler as described herein. Processor 802 may include any combination of hardware, software, or firmware providing programmable logic, including, by way of non-limiting example, a microprocessor, a DSP, a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific integrated circuit (ASIC), or a virtual machine processor. Processor 802 may be communicatively coupled to memory element 804, for example, in a direct memory access (DMA) configuration, such that processor 802 can read from or write to memory element 804.

[0058] In general, memory elements 804 may include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash, read-only memory (ROM), optical media, virtual memory area, magnetic or tape memory, or any other suitable technology. Unless otherwise specified, any of the memory elements discussed herein should be construed as being encompassed within the broad term “memory.” Information measured, processed, tracked, or transmitted to or from any of the components of data processing system 2200 may be provided in any database, register, control list, cache, or storage structure, all of which may be referenced in any suitable time frame. Any of such storage options may be included within the broad term “memory” as used herein. Similarly, any of the potential processing elements, modules, and machines described herein should be construed as being encompassed within the broad term “processor.” Each of the elements shown in this figure, for example, any element of the clock doubler 100 shown in Figures 1-4, may also include an interface suitable for receiving, transmitting, and / or otherwise communicating data or information in a network environment so that they can communicate with, for example, data processing system 800.

[0059] In certain example implementations, mechanisms for implementing one or more clock doublers as outlined herein may be implemented by logic encoded on one or more tangible media, which may include non-transitory media, such as embedded logic provided in an ASIC or DSP instructions, software (potentially including object code and source code) executed by a processor, or other similar machine. In some of these embodiments, a memory element, such as memory element 804 shown in FIG. 8, may store data or information used in the operations described herein. This includes memory elements that can store software, logic, code, or processor instructions that are executed to perform the activities described herein. A processor may execute any type of instruction associated with data or information to achieve the operations detailed herein. In one embodiment, a processor, such as processor 802 shown in FIG. 8, may transform an element or item (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein may be implemented in fixed or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein may be any type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or ASIC, including digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0060] The memory elements 804 may include one or more physical memory devices, such as, for example, a local memory 808 and one or more bulk storage devices 810. Local memory may refer to RAM or other non-persistent memory devices typically used during the actual execution of the program code. The bulk storage devices may be implemented as hard drives or other persistent data storage devices. The processing system 800 may also include one or more cache memories (not shown) that provide temporary storage of at least some program code to reduce the number of times the program code must be retrieved from the bulk storage devices 810 during execution.

[0061] 8, memory element 804 may store application 818. In various embodiments, application 818 may be stored in local memory 808, in one or more bulk storage devices 810, or remotely from local memory and bulk storage devices. It should be understood that data processing system 800 may further execute an operating system (not shown in FIG. 8), which may facilitate the execution of application 818. Application 818, implemented in the form of executable program code, may be executed by data processing system 800, for example, by processor 802. In response to executing the application, data processing system 800 may be configured to perform one or more operations or method steps described herein.

[0062] Input / output (I / O) devices, depicted as input device(s) 812 and output device(s) 814, may optionally be coupled to the data processing system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, and the like. Examples of output devices may include, but are not limited to, a monitor or display, a speaker, and the like. In some embodiments, the output device(s) 814 may be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some implementations, the system may include a driver (not shown) for the output device(s) 814. The input and / or output devices 812, 814 may be coupled to the data processing system directly or through intervening I / O controllers.

[0063] In one embodiment, the input and output devices may be implemented as a combined input / output device (shown in FIG. 8 by the dashed lines surrounding input device 812 and output device 814). One example of such a combined device is a touch-sensitive display, sometimes referred to as a "touchscreen display" or simply a "touchscreen." In such an embodiment, input to the device may be provided by the movement of a physical object, such as a stylus or a user's finger, on or near the touchscreen display.

[0064] A network adapter 816 may also be optionally coupled to the data processing system to enable the data processing system to be coupled to other systems, computer systems, remote network devices, and / or remote storage devices through intervening private or public networks. A network adapter may comprise a data receiver for receiving data transmitted to data processing system 800 by the systems, devices, and / or networks, and a data transmitter for transmitting data from data processing system 800 to the systems, devices, and / or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that may be used with data processing system 800.

[0065] The following paragraphs provide various examples of the embodiments disclosed herein.

[0066] Example 1 provides a clock doubler configured to use a synchronously triggered free-running ring oscillator as a time base with a counter for clock measurement.

[0067] Example 2 provides a clock doubler configured to use a synchronously triggered free-running replica ring oscillator with a counter for long programmable delay generation.

[0068] Example 3 provides a clock doubler configured to use background clock calibration and a substantially glitch-free clock correction technique.

[0069] Example 4 provides an electronic device including a clock doubler according to any of the previous examples and / or any embodiment of the present disclosure.

[0070] Example 5 provides the electronic device of example 4, wherein the electronic device is a digital signal processing core or a digital signal processing circuit.

[0071] Example 6 provides the electronic device according to example 4 or 5, wherein the clock doubler is for clocking the operation of one or more ADCs and / or one or more DACs.

[0072] Example 7 provides a method for operating a clock doubler according to any embodiment described herein.

[0073] Example 8 provides a non-transitory computer-readable storage medium comprising instructions for execution operable, when executed by a processor, to perform the operations of the method described in Example 7.

[0074] Although embodiments of the present disclosure have been described above with reference to exemplary implementations such as those illustrated in FIGS. 1-8, those skilled in the art will recognize that the various teachings described above are applicable to a wide variety of other implementations.

[0075] In the discussion of the above embodiments, system components such as counters, logic elements (e.g., XOR gates), and / or other components can be readily exchanged, substituted, or otherwise modified to accommodate the needs of a particular circuit. Moreover, it should be noted that the use of complementary electronic devices, hardware, software, etc., provides equally viable options for implementing the teachings of the present disclosure related to implementing one or more clock doublers.

[0076] Components of various systems for implementing one or more clock doublers as proposed herein may include electronic circuitry for performing the functions described herein. In some cases, one or more components of a system may be provided by a processor specially configured to perform the functions described herein. For example, the processor may include one or more application-specific components or may include programmable logic gates configured to perform the functions described herein. The circuitry may operate in the analog domain, the digital domain, or the mixed-signal domain. In some examples, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

[0077] In some embodiments, any number of the electrical circuits depicted herein may be implemented on a board of an associated electronic device. The board may be a general circuit board that can hold various components of the electronic device's internal electronic system and may further provide connectors for other peripheral devices. More specifically, the board may provide electrical connections by which other components of the system can communicate electrically. Any suitable processor (including DSPs, microprocessors, supporting chipsets, etc.), computer-readable, non-transitory memory elements, etc. may be suitably coupled to the board based on particular configuration needs, processing requirements, computer design, etc. Other components, such as external storage devices, additional sensors, controllers for audio / video displays, and peripheral devices, may be attached to the board as plug-in cards via cables or integrated into the board itself. In various embodiments, the functionality described herein may be implemented in an emulation form as software or firmware operating within one or more configurable (e.g., programmable) elements arranged in a structure that supports these functions. The software or firmware providing the emulation may be provided on a non-transitory computer-readable storage medium that includes instructions for causing a processor to perform those functionality.

[0078] In some embodiments, the electrical circuits in this diagram may be implemented as stand-alone modules (e.g., devices with associated components and circuitry configured to perform a particular application or function) or as plug-in modules into application-specific hardware in an electronic device. It should be noted that certain embodiments of the present disclosure may be readily included, in part or in whole, in a system-on-chip (SOC) package. SOC refers to an IC that combines components of a computer or other electronic system into a single chip. This may include digital, analog, mixed-signal, and often RF functions, all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM) with multiple separate ICs arranged within a single electronic package and configured to closely interact with each other through the electronic package.

[0079] All specifications, dimensions, and relationships outlined herein (e.g., the number of components of a clock doubler shown in the drawings, or portions thereof) are provided solely for illustrative and instructional purposes. Such information may vary considerably without departing from the spirit of the present disclosure or the scope of the appended claims. The specifications apply to one non-limiting example only, and accordingly, they should be construed as such. In the foregoing description, example embodiments have been described with reference to particular processor and / or component arrangements. Various modifications and changes can be made to such embodiments without departing from the scope of the appended claims. Accordingly, the description and drawings should be regarded in an illustrative sense, and not a restrictive sense.

[0080] It should be noted that in many of the examples provided herein, interactions may be described in terms of two, three, four, or more electrical components. However, this is done merely for purposes of clarity and illustration. It should be understood that systems may be integrated in any suitable manner. Along similar design alternatives, any of the components, modules, and elements shown in the figures may be combined in a variety of possible configurations, all of which are clearly within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more of the functionality of a given set of flows by only referencing a limited number of electrical elements. It should be understood that the electrical circuits of the figures and their teachings are readily expandable to accommodate numerous components and more complex or sophisticated arrangements and configurations. Thus, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to countless other architectures.

[0081] Furthermore, the functionality associated with implementing one or more clock doublers as proposed herein represents only a portion of the possible functions that may be performed by or within the system depicted in this figure. Some of these operations may be omitted or eliminated as desired, or these operations may be significantly modified or changed without departing from the scope of the present disclosure. Additionally, the timing of these operations may be significantly changed. The foregoing operational flows are provided for example and discussion purposes. Substantial flexibility is provided by the embodiments described herein in that any suitable arrangement, order, configuration, and timing mechanism may be provided without departing from the teachings of the present disclosure.

[0082] It should be noted that any and all optional features of the apparatus described above may also be implemented in relation to the methods or processes described herein, and the example details may be used anywhere in one or more embodiments.

[0083] Numerous other changes, substitutions, variations, changes, and modifications may be ascertainable by those skilled in the art, and the present disclosure is intended to encompass all such changes, substitutions, variations, changes, and modifications as fall within the scope of the appended claims. [Explanation of symbols]

[0084] 100 Clock Doubler 102 Input Clock Signal 104 Output Clock Signal 110 Ring Oscillator 120 Replica Ring Oscillator 130 Calibration Circuit 140 Delay Circuit 200 Clock Doubler 300 Calibration Circuit 302 Pulse Generator 304 Ring Oscillator 306 Counter 400 Delay Circuit 402 Replica Ring Oscillator 404 Counter 520 Controller 600 System 600 Electrical Devices 610 DSP circuit 620 Controller 700 Electrical Devices 702 Processing Device 704 memory 706 Display Devices 708 Audio Output Device 710 output device 712 Communication Chip 714 Power circuit 716 GPS devices 718 Audio Input Device 720 input devices 722 Antenna 800 Data Processing Systems 802 hardware processor 804 memory elements 806 system bus 808 Local Memory 810 Bulk Storage Devices 812 input devices 814 output devices 816 Network Adapter 818 Applications 2100 Electrical Devices 2200 Data Processing System

Claims

1. A clock doubler that outputs an output clock having twice the frequency of an input clock, A calibration circuit including a ring oscillator and a first counter, The ring oscillator is configured to output pulses for measuring the pulse width of the output clock, The first counter is configured to output the number of pulses of the ring oscillator corresponding to the pulse width of the output clock, and the calibration circuit is configured to output the number of pulses of the ring oscillator corresponding to the pulse width of the output clock. A delay circuit including a replica ring oscillator and a second counter, The replica ring oscillator is configured to output a predetermined pulse, A clock doubler comprising: a second counter configured to count down a count value from a predetermined delay value supplied to the delay circuit based on pulses from the replica ring oscillator, and output a delay pulse of the output clock when the count value becomes zero, and the duty cycle of the output clock pulse is corrected as the predetermined delay value is determined based on the count.

2. The clock doubler according to claim 1, wherein the delay circuit includes two replica ring oscillators.

3. A method for correcting clock cycles, The ring oscillator outputs pulses to measure the pulse width of an output clock having twice the frequency of the input clock, The first counter outputs the number of pulses of the ring oscillator corresponding to the pulse width of the output clock, Outputting a predetermined pulse via a replica ring oscillator, A method comprising counting down a count value from a predetermined delay value based on pulses from the replica ring oscillator via a second counter, and outputting a delay pulse of the output clock as the count value becomes zero, wherein the duty cycle of the output clock pulse is corrected by determining the predetermined delay value based on the count.

4. The method according to claim 3, comprising two replica ring oscillators.

5. A clock doubler that outputs an output clock having twice the frequency of an input clock, A means for outputting a pulse to measure the pulse width of the output clock, Means for outputting the number of pulses of a ring oscillator corresponding to the pulse width of the output clock, Means for outputting a predetermined pulse, A clock doubler comprising: means for counting down a count value from a predetermined delay value based on pulses from a replica ring oscillator, and outputting a delayed pulse of the output clock in response to the count value becoming zero, wherein the duty cycle of the output clock pulse is corrected by determining the predetermined delay value based on the count.

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