Electronic device with improved reliability

Abstract

To provide an electronic device which effectively solves the problem of delamination of a passivation layer from silicon carbide (SiC) starting from the edge of the device, and to provide a manufacturing process of the electronic device.SOLUTION: The electronic device 50 includes a silicon carbide semiconductor body 50 having a surface 50 a with a first portion of the surface defining an active region 54 of the electronic device, a second portion of the surface external to the active region, metallization 55 extending over the first portion of the surface of the semiconductor body, a passivation layer 56 extending over the metallization, and an adhesive layer 57 based on one or more carbon allotropes extending over the passivation layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to Italian Patent Application No. 102024000017716, filed July 30, 2024, entitled "DISPOSITIVO ELETTRONICO CON AFFIDABILITA' MIGLIORATA," which is incorporated herein by reference to the fullest extent permitted by law.

[0002] FIELD OF THE INVENTION The present disclosure relates to electronic devices, particularly silicon carbide based devices, with improved reliability. In particular, the present disclosure relates to electronic devices and processes for manufacturing electronic devices. [Background technology]

[0003] Silicon carbide (SiC) is of great interest in the semiconductor industry, especially for the manufacture of electronic components such as diodes or transistors, especially for power applications.

[0004] Electronic devices fabricated in substrates of silicon carbide of various polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC) offer many advantages, including low output resistance when conducting, low leakage current, high operating temperature tolerance, and high operating frequency.

[0005] However, the development and manufacture of SiC-based electronic devices is limited by factors such as the electrical and mechanical properties of the passivation layer (included in such electronic devices, e.g., extending over the SiC semiconductor body of the electronic device). Specifically, it is known to form the passivation layer using a polymeric material (e.g., polyimide) that can withstand the high operating temperatures of the electronic device and has a high dielectric strength (e.g., greater than 400 kV / mm). Specifically, the high dielectric strength of the polymeric material ensures that the passivation layer can withstand high electric fields, and thus high potential differences, without experiencing electrical breakdown and thus becoming conductive.

[0006] However, polymeric materials have high coefficients of thermal expansion (CTE) (e.g., for polybenzobisoxazole material, or "PIX," CTE=43e-6 1 / K), which makes adhesion of the passivation layer to SiC, which instead has a much lower coefficient of thermal expansion (CTE=3.8e-6 1 / K), problematic.

[0007] Specifically, such adhesion problems between the passivation layer and SiC can occur during thermal cycling tests (e.g., performed from about −50° C. to about +150° C.) or when the electronic device is subjected to high temperature fluctuations (e.g., operating temperature differences of about 200° C. or more) during use of the electronic device. Due to the large difference in CTE between the passivation layer and SiC, such large thermal fluctuations can generate mechanical stresses at the interface between the passivation layer and SiC, which can lead to (at least partial) delamination of the passivation layer relative to the SiC semiconductor body.

[0008] If this delamination becomes too large (for example, if two metallizations of an electronic device are set to different potentials and no part of the passivation layer is present between them, separating them only by air), discharges can occur at this interface, potentially damaging the same electronic device. Specifically, if the latter is used under reverse bias conditions, the voltage difference it must withstand is large (for example, more than 1000 V), increasing the risk of damage to the electronic device.

[0009] In current devices, the risk of delamination is even more pronounced due to the presence of an additional protective layer on top of the passivation layer. This protective layer is used to protect the electronic device during insertion into the package and is generally made of a carbon-based resin, such as Bakelite. This resin has a thermal expansion coefficient that is not significantly different from that of the passivation material (e.g., approximately 7 ppm / °C for the resin and approximately 67 ppm / °C for the passivation material), and its thickness is generally greater than that of the passivation layer. As a result, during thermal cycling tests or during use of electronic devices subjected to high thermal fluctuations, the protective layer deforms in the same way as the passivation layer. This deformation of the protective layer is transferred to the passivation layer, inducing additional mechanical stress at the interface between the passivation layer and SiC, which exacerbates the aforementioned delamination phenomenon.

[0010] For example, delamination can manifest itself with bending of the passivation layer relative to the SiC, peeling of the passivation layer from the SiC starting at the edge of the device, and cracks or openings in the passivation layer.

[0011] Known solutions to this problem have been proposed, including the use of anchor elements for the passivation layer on the SiC, the use of alternative composite structures for the passivation and protective layers, or the use of alternative materials. However, none of these known solutions effectively solves the delamination problem, rendering known devices unreliable in operation. Furthermore, these known solutions generally significantly complicate the final structure of the device and its manufacturing process, thereby increasing manufacturing costs and increasing susceptibility to failure.

[0012] It is an object of the present disclosure to provide an electronic device and a process for manufacturing an electronic device that overcomes the shortcomings of the prior art. Summary of the Invention

[0013] In accordance with the present disclosure, there is provided an electronic device and a process for manufacturing an electronic device, as defined in the appended claims, which form an integral part of this specification. [Brief explanation of the drawings]

[0014] For a better understanding of the present disclosure, preferred embodiments will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Figure 1] 1 illustrates a cross-sectional view of an electronic device according to one embodiment of the present disclosure. [Figure 2] 2 illustrates a plan view of the electronic device of FIG. 1 according to one embodiment of the present disclosure. [Figure 3A] 2A-2C illustrate, in cross-sectional views, a process for fabricating the electronic device of FIG. 1, limited to fabrication of an adhesive layer, according to one embodiment of the present disclosure. [Figure 3B] 2A-2C illustrate, in cross-sectional views, a process for fabricating the electronic device of FIG. 1, limited to fabrication of an adhesive layer, according to one embodiment of the present disclosure. [Figure 3C] 2A-2C illustrate, in cross-sectional views, a process for fabricating the electronic device of FIG. 1, limited to fabrication of an adhesive layer, according to one embodiment of the present disclosure. [Figure 3D]2A-2C illustrate, in cross-sectional views, a process for fabricating the electronic device of FIG. 1, limited to fabrication of an adhesive layer, according to one embodiment of the present disclosure.

[0015] Specifically, these figures are shown with reference to a three-axis Cartesian coordinate system defined by mutually orthogonal X-, Y-, and Z-axes.

[0016] In the following description, elements that are common to different embodiments are designated using the same reference numerals. DETAILED DESCRIPTION OF THE INVENTION

[0017] FIG. 1 shows a cross-sectional side view of an electronic device 50 according to one embodiment of the present disclosure taken along section line II shown in FIG.

[0018] Specifically, the electronic device 50 is a high power device, ie, configured to operate at an electrical voltage equal to about 650-2200V and a current equal to about 1-5A.

[0019] In particular, device 50 is a JBS ("Junction Barrier Schottky") diode. However, the present disclosure is not limited to such devices and may also find application in other types of electronic devices, particularly power devices such as, for example, MOSFETs, IGBTs, MPSs, Schottky diodes, PN diodes, PiN diodes, etc.

[0020] Electronic device 50 includes the elements described below with reference to FIG.

[0021] A semiconductor body 53 (e.g., including a substrate 53′ and, optionally, one or more epitaxial layers 53″ grown thereon) of N-type or P-type SiC (hereinafter, non-limitingly, referring only to N-type) has an upper surface 53a opposite a back surface 53b along the Z-axis.

[0022] In the example illustrated in FIG. 1 , semiconductor body 53 includes substrate 53′ on which epitaxial layer 53″ acting as a drift layer of electronic device 50 is grown, both of which are N-type SiC (specifically, 4H—SiC, although other polytypes such as, but not limited to, 2H—SiC, 3C—SiC, and 6H—SiC may also be used). For example, substrate 53′ has an N-type dopant concentration of 1 to 10 at / cm to 1 to 10 at / cm and a thickness measured along the Z-axis between surfaces 53 a and 53 b of 300 μm to 450 μm, specifically equal to about 360 μm. Drift layer 53″ has a respective dopant concentration lower than that of the substrate and a thickness of, for example, 5 to 15 μm.

[0023] An ohmic contact layer 56 (eg of nickel silicide) extends over the back surface 53b, and a metallization 57, in this example a cathode metallization of, for example, Ti / NiV / Ag or Ti / NiV / Au, extends over the ohmic contact region 56.

[0024] One or more doped regions 59' of P type extend in the semiconductor body 53 (particularly in the drift layer) facing the upper surface 53°.

[0025] Each doped region 59' receives a respective ohmic contact (not shown, of a known type) such that each doped region 59' forms a respective junction barrier (JB) element 59. An edge termination region, or guard ring 60, specifically a further P-type doped region, extends within the drift layer, faces upper surface 53a, and completely surrounds JB element 59 (in plan view, in the XY plane defined by axes X and Y). Edge termination region 60 may be omitted.

[0026] An insulating layer 61 (an insulating or dielectric material, e.g., silicon oxide, TEOS) extends over the upper surface 53a so as to completely surround the JB element 59 (as viewed in the XY plane) and to partially overlap the guard ring 60 (if present).

[0027] Metallization 58, in this example an anode metallization, e.g., Ti / AlSiCu or Ni / AlSiCu metallization, extends over a portion of upper surface 53a externally bounded by insulating layer 61 (i.e., in JB element 59 / active region 54) and partially over insulating layer 61.

[0028] A passivation layer 69 of polymeric material such as polyamide (eg, PIX) extends over the anode metallization 58 and insulating layer 61 .

[0029] Here, an interfacial layer 63 of silicon nitride (SiN) extends above the anode metallization 58 and the insulating layer 61, and below the passivation layer 69. In other words, the interfacial layer 63 acts as an interface between the passivation layer 69 and the layer below it, here the metallization 58 and the insulating layer 61, and promotes adhesion of the passivation layer 69 thereover.

[0030] One or more Schottky diodes 62 are formed laterally to the doped region 59′ at the interface between the semiconductor body 53 and the anode metallization 58. Specifically, (semiconductor-metal) Schottky junctions are formed by portions of the semiconductor layer 53 that are in direct electrical contact with respective portions of the anode metallization 58.

[0031] Furthermore, each ohmic contact extending within a respective doped region 59' forms an electrical connection having a lower electrical resistance than the electrical resistance of the doped region 59' that contains it. Thus, JB element 59 is a PiN diode.

[0032] The region of the electronic device 50 that includes the JB element 59 and the Schottky diode 62 (ie, the region bounded by the guard ring 60) is the active region (or area) 54 of the electronic device 50.

[0033] Outside the active region 54, i.e., beyond the edge termination region 60, there are lateral surfaces 53c of the semiconductor body 53, which extend, for example, substantially perpendicular to the top surface 53a. The lateral surfaces 53c are formed after a dicing process of the SiC wafer, in which a plurality of electronic devices 50 are formed. The dicing process serves to separate the electronic devices 50 from one another on the same wafer. The dicing is performed along a scribe line (not shown) in the SiC wafer from which the electronic devices 50 are obtained. The scribe line surrounds the active region 54, the guard ring 60, and the insulating layer 61 at a distance in the XY plane.

[0034] Hereinafter, the portion (or region) of the upper surface 53a that extends inside the guard ring 60 and thus defines the active region 54 will also be referred to as a first portion of the upper surface 53a (indicated by reference numeral 55' in FIG. 1), while the portion (or region) of the upper surface 53a that extends outside the guard ring 60 and thus is outside the active region 54 will also be referred to as a second portion of the upper surface 53a (indicated by reference numeral 55'' in FIG. 1).

[0035] Additionally, adhesion layer (or region) 76 extends above passivation layer 69 .

[0036] Adhesion layer 76 may also extend above upper surface 53a outside of active region 54 where upper surface 53a is exposed by passivation layer 69. In this case, adhesion layer 76 contacts second portion 55" of upper surface 53a.

[0037] Adhesion layer 76 extends a distance from anode metallization 58 so as to be electrically isolated from (ie, not in electrical contact with) the anode metallization 58 .

[0038] Adhesion layer 76 is made from one or more carbon allotropes (eg, graphene, graphite, carbon nanotubes, diamond), and in particular is one such carbon allotrope.

[0039] In the exemplary embodiment discussed below, adhesion layer 76 is made from graphene.

[0040] Specifically, in the embodiments discussed herein, adhesion layer 76 includes a single graphene layer or a graphene multilayer (or stack) formed by stacking multiple graphene layers on top of each other (e.g., about 2-10 stacked graphene layers).

[0041] More specifically, one or more graphene layers are arranged to extend substantially parallel to the XY plane, and thus substantially parallel to the upper surface 53a (i.e., the planar plane of each graphene layer is substantially parallel to the XY plane).

[0042] For example, the adhesive layer 76 has a thickness along the Z-axis direction of about 0.3 nm to about 5 nm.

[0043] A protective layer 74, made of a resin such as Bakelite, extends over the adhesive layer 76 and the anode metallization 58 (where the passivation layer 69 is exposed) to protect the electronic device 50 when inserted into a package (not shown).

[0044] As a result, along the Z-axis, the adhesion layer 76 is interposed between (and in particular in direct physical contact with) the passivation layer 69 and the protective layer 74, acting as an interface layer between these two layers, etc.

[0045] More specifically, it has been determined that adhesion layer 76 reduces the mechanical bond between passivation layer 69 and protective layer 74, thereby reducing the transfer of stress and strain from one layer to the other. Specifically, this is due to the fact that adhesion layer 76 bonds to passivation layer 69 and protective layer 74 via van der Waals forces, thereby reducing stresses applied at the interface between passivation layer 69 and the underlying semiconductor body 53 that result from overall thermal deformation of passivation layer 69 and protective layer 74.

[0046] Furthermore, the adhesive layer 76, particularly when made of graphene, has been found to reduce heating of the active region 54 during use. Indeed, graphene has a high "in-plane" type thermal conductivity, i.e., a thermal conductivity with heat exchange occurring planarly with respect to the flat planes of the carbon atoms (e.g., approximately 2-60 W / mK), and a low "inter-plane" type thermal conductivity, i.e., a thermal conductivity with heat exchange occurring perpendicular to the flat planes of the carbon atoms (e.g., approximately 0.1-0.3 W / mK). This suggests that the graphene of the electronic device 50 has optimal thermal conductivity for heat exchange occurring parallel to the XY plane and poor thermal conductivity for heat exchange occurring parallel to the Z axis. Thus, the adhesive layer 76 collects heat generated in the active region 54 during use of the electronic device 50 and transports it outside the active region 54, where it can be dispersed without affecting the operation of the electronic device 50. This prevents heat generated in the active region 54 from being transferred to the protective layer 74 or from being built up in the passivation layer 69. Consequently, the mechanical strain caused by heating of these layers is reduced.

[0047] FIG. 2 shows a schematic top view (on the XY plane) of an electronic device 50 according to an embodiment.

[0048] Referring to FIG. 2, the adhesion layer 76 extends in the XY plane to completely surround and cover the passivation layer 69 .

[0049] When viewed in the XY plane of FIG. 2, the inner edge of adhesive layer 76 defines a closed polygonal shape, more particularly a square shape with rounded corners (although different shapes are possible, such as a circular shape, a rectangular shape, or a generally polygonal or irregular shape).

[0050] 1 will be described below with reference to Figures 3A to 3D, focusing on the manufacturing process of the adhesive layer 76. Figures 3A to 3D are expressed in the same three-axis system as Figure 1.

[0051] Referring to FIG. 3A, a wafer including a semiconductor body 53 of SiC, an insulating layer 61, an anode metallization 58, an interface layer 63, and a passivation layer 69 is arranged according to a manufacturing process previously described (and known and therefore not further described herein) to form elements of an electronic device 50 identified by the same reference numerals.

[0052] In FIG. 3A, an adhesion layer 90 is uniformly formed over the passivation layer 69, the areas of the anode metallization 58 where the passivation layer 69 is exposed, and the areas of the top surface 53a of the semiconductor body 53 where the passivation layer 69 is exposed outside the active region 54.

[0053] Adhesion layer 90 is made from one or more carbon allotropes (eg, graphene, graphite, carbon nanotubes, diamond), and in particular is one of such carbon allotropes.

[0054] In the exemplary embodiments discussed below, the adhesion layer 76 is made from graphene. Specifically, the adhesion layer 76 includes a single graphene layer or multiple graphene layers (or stacks).

[0055] Adhesive layer 90 has a thickness along the Z axis equal to the thickness of adhesive layer 76 described above.

[0056] The adhesive layer 90 forms the adhesive layer 76 by the procedure described below.

[0057] Specifically, adhesion layer 90 is formed by vapor deposition, for example, chemical vapor deposition (CVD).

[0058] Referring to FIG. 3B, a lithography mask 91 is formed on the adhesion layer 90 .

[0059] The lithography mask 91 has an opening 92 that is substantially vertically aligned (i.e., overlapped along the Z-axis) with the active region 54. More specifically, the opening 92 is vertically aligned with the inner edge of the passivation layer 69 such that the lithography mask 91 vertically overlaps the passivation layer 69 and the regions of the upper surface 53a of the semiconductor body 53 where the passivation layer 69 is exposed outside the active region 54, but does not vertically overlap the regions of the anode metallization 58 where the passivation layer 69 is exposed.

[0060] The lithographic mask 91 is made, for example, from photoresist and is formed according to lithographic and chemical etching techniques known per se.

[0061] Next, in FIG. 3C, etching of adhesion layer 90 is performed through previously formed openings 92 to expose areas of anode metallization 58 not covered by passivation layer 69 .

[0062] This etching causes the adhesive layer 76 to be patterned, starting from the adhesive processing layer 90. Specifically, this etching patterning forms a closed polygonal shape at the inner edge of the adhesive layer 76 when viewed from the XY plane.

[0063] The etching is, for example, dry and uses an etching chemistry that is selective to the material of the adhesion layer 90 (e.g., in O2, N2), thereby removing the exposed portions of the adhesion layer 90 without removing the underlying anode metallization 58 and lithography mask 91.

[0064] Specifically, etching will proceed as long as the top surface of the anode metallization 58 is exposed.

[0065] Next, in FIG. 3D, the lithographic mask 91 is removed in a manner known per se.

[0066] Subsequently, in a manner not shown, a protective layer 74 is formed over the adhesion layer 76 and the anode metallization 58, also according to techniques of known type.

[0067] For example, a liquid or semi-liquid resin is applied by "molding" onto the wafer so as to pass through the openings 92 and contact the anode metallization 58. A thermal process is then performed (curing process or in-heater process) to harden the resin and form the protective layer 74. The resin is, for example, Bakelite.

[0068] The manufacturing process then continues with subsequent steps for forming further elements of the electronic device 50 (e.g., ohmic contact layer 56 and cathode metallization 57), which are known per se and therefore not described in detail here.

[0069] The advantages gained from the features of the embodiments of the present disclosure are clear when considered.

[0070] In particular, the adhesion layer 76 ensures adhesion between the passivation layer 69 and the underlying semiconductor body 53, preventing delamination phenomena for the reasons mentioned above. In particular, this is ensured by the fact that the adhesion layer 76 acts as a heat sink towards the outside of the electronic device 50, preventing an excessive rise in the local temperature of the active region 54, which would lead to excessive expansion of the passivation layer 69 and thus to mechanical stresses at its interface with the semiconductor body 53. These advantages are achieved with any carbon allotrope, but in an optimal manner with graphene in particular, due to its excellent thermal conductivity properties.

[0071] This avoids the risk of damage to the electronic device 50 due to discharges between metallizations set at different potentials (e.g., between the EQR metallization and the anode metallization 58), thereby improving the reliability of the electronic device 50, especially when subjected to high thermal fluctuations and operating under reverse bias conditions.

[0072] In conclusion, it will be clearly seen that modifications and variations may be made to the present disclosure as described and illustrated herein without departing from the scope of the present disclosure.

[0073] For example, the different embodiments described may be combined with each other to provide further solutions.

Claims

1. 1. An electronic device comprising: a semiconductor body of silicon carbide having a surface, the surface having a first portion of the surface defining an active area of ​​the electronic device and a second portion of the surface outside the active area; a metallization extending over the first portion of the surface of the semiconductor body; a passivation layer extending over a portion of the metallization; an adhesion layer made from one or more carbon allotropes extending over the passivation layer; , an electronic device.

2. further comprising a protective layer extending over the adhesion layer and the metallization; 2. The electronic device of claim 1, wherein the passivation layer is exposed such that the adhesion layer is interposed between the passivation layer and the protective layer perpendicular to the surface of the semiconductor body.

3. 2. The electronic device of claim 1, wherein the adhesion layer further extends over the second portion of the surface outside the active area and where the metallization and the passivation layer are exposed.

4. The electronic device of claim 3 , wherein the adhesive layer contacts the second portion of the surface.

5. The electronic device of claim 1 , wherein the adhesion layer extends a distance from the metallization.

6. The electronic device of claim 1 , wherein the adhesion layer is one of graphene, graphite, diamond, or carbon nanotubes.

7. The electronic device of claim 6 , wherein the adhesion layer is formed by a single graphene layer or a multi-layer of graphene formed by stacking a plurality of single graphene layers on top of each other.

8. 8. The electronic device of claim 7, wherein the single graphene layer or the plurality of single graphene layers are at least partially aligned parallel to the surface of the semiconductor body.

9. 10. The electronic device of claim 1, wherein the adhesion layer completely surrounds the passivation layer parallel to the surface of the semiconductor body and further covers the passivation layer perpendicular to the surface of the semiconductor body.

10. 10. The electronic device of claim 1, wherein the electronic device is selected from the group consisting of a Schottky diode, a PiN diode, a PN diode, an MPS device, a JBS diode, a MOSFET, an IGBT, and a power device.

11. 1. A process for manufacturing an electronic device, comprising: - forming a semiconductor body of silicon carbide having a surface, the surface having a first portion of the surface defining an active area of ​​the electronic device and a second portion of the surface outside the active area; forming a metallization on the first portion of the surface of the semiconductor body; - forming a passivation layer on parts of said metallization; - forming on said passivation layer an adhesion layer made from one or more carbon allotropes; The process includes:

12. Forming the adhesive layer forming an adhesion layer made from one or more carbon allotropes on the passivation layer, on the portion of the metallization exposed by the passivation layer, and on the second portion of the surface outside the active area; - forming a lithography mask from the adhesion layer, the lithography mask being superimposed on the passivation layer and on the second portion of the surface and having openings superimposed on the portions of the metallization where the passivation layer is exposed; - selectively etching the adhesion layer through the openings to expose the portions of the metallization where the passivation layer is exposed; - removing said lithographic mask; 12. The process for manufacturing the electronic device of claim 11, comprising:

13. 13. The process for manufacturing the electronic device of claim 12, wherein forming the adhesion layer comprises performing vapor deposition.

14. 14. The process for manufacturing the electronic device of claim 13, wherein the deposition is chemical vapor deposition.

15. 13. The process for manufacturing the electronic device of claim 12, wherein performing the selective etching comprises performing a dry etch using an etching chemistry selective to the material of the adhesion layer.

16. 12. The process for manufacturing the electronic device of claim 11, further comprising forming a protective layer on the adhesion layer and the metallization, wherein the passivation layer is exposed such that the adhesion layer is interposed between the passivation layer and the protective layer perpendicular to the surface of the semiconductor body.

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