Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can suppress crosstalk between adjacent communication channels. [Solution] The semiconductor device comprises a semiconductor substrate having an upper surface and a lower surface located opposite the upper surface; a first insulating layer formed on the upper surface; a first coil formed on the first insulating layer; a second coil formed on the first insulating layer and located next to the first coil in a plan view; a first conductor pattern formed on the first insulating layer, extending in a second direction perpendicular to the first direction in a plan view, and formed between the first coil and the second coil in the first direction which is the arrangement direction of the first coil and the second coil; a second insulating layer formed on the first insulating layer so as to cover the first coil, the second coil and the first conductor pattern; a third coil formed on the second insulating layer and overlapping with the first coil in a plan view; and a fourth coil formed on the second insulating layer and overlapping with the second coil in a plan view. The first conductor pattern is electrically connected to the semiconductor substrate.

Claims

1. A semiconductor substrate having an upper surface and a lower surface located opposite the upper surface, The first insulating layer formed on the upper surface, A first coil formed on the first insulating layer, A second coil is formed on the first insulating layer and is located next to the first coil in a plan view, A first conductor pattern is formed on the first insulating layer, extends in a second direction perpendicular to the first direction which is the arrangement direction of the first coil and the second coil in a plan view, and is formed between the first coil and the second coil in the first direction, A second insulating layer formed on the first insulating layer so as to cover the first coil, the second coil, and the first conductor pattern, A third coil formed on the second insulating layer and overlapping the first coil in a plan view, The device comprises a fourth coil formed on the second insulating layer and overlapping the second coil in a plan view, The first conductor pattern is electrically connected to the semiconductor substrate, and the semiconductor device is a semiconductor device.

2. The semiconductor substrate has an impurity diffusion layer formed within the semiconductor substrate at a position closer to the upper surface than to the lower surface. The semiconductor device according to claim 1, wherein the first conductor pattern is electrically connected to the impurity diffusion layer.

3. The second conductor pattern and Multiple via plugs, It also includes multiple contact plugs, The first insulating layer comprises a first interlayer insulating film formed on the upper surface of the semiconductor substrate and a second interlayer insulating film formed on the first interlayer insulating film. The second conductor pattern is formed on the first interlayer insulating film, is covered by the second interlayer insulating film, and extends in the second direction so as to overlap the first conductor pattern in a plan view. The plurality of via plugs are formed within the second interlayer insulating film so as to overlap the first conductor pattern in a plan view. The plurality of contact plugs are formed within the first interlayer insulating film so as to overlap the second conductor pattern in a plan view. The semiconductor device according to claim 2, wherein the first conductor pattern is electrically connected to the semiconductor substrate via the plurality of via plugs, the second conductor pattern, and the plurality of contact plugs.

4. The semiconductor device according to claim 3, wherein the first conductor pattern is electrically connected to the impurity diffusion layer via the plurality of via plugs, the second conductor pattern, and the plurality of contact plugs.

5. In a plan view, the device further comprises guard rings surrounding the third coil and the fourth coil, The semiconductor device according to claim 4, wherein the guard ring is electrically connected to the first conductor pattern and the impurity diffusion layer.

6. Third conductor pattern and A fourth conductor pattern is further provided, The first insulating layer has a first interlayer insulating film formed on the upper surface and a second interlayer insulating film formed on the first interlayer insulating film. The third conductor pattern and the fourth conductor pattern are formed on the first interlayer insulating film and covered by the second interlayer insulating film. The third conductor pattern overlaps the first coil in a plan view. The semiconductor device according to claim 1, wherein the fourth conductor pattern overlaps the second coil in a plan view.

7. The third conductor pattern has a first portion and a second portion formed at a distance from the first portion. The semiconductor device according to claim 6, wherein the fourth conductor pattern has a third portion and a fourth portion formed at a distance from the third portion.

8. In a plan view, the device further comprises guard rings surrounding the third coil and the fourth coil, The semiconductor device according to claim 7, wherein the guard ring is electrically connected to the third conductor pattern and the fourth conductor pattern.

9. The semiconductor device according to claim 1, wherein the minimum distance between the first coil and the second coil in the first direction is less than 100 μm.

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