Scalable thermalization and signal attenuation of quantum device interconnects in quantum computing systems

Abstract

The present disclosure is directed to a quantum processor system. The system includes a first cryogenic chamber, a signal reflecting element disposed within the first cryogenic chamber, a second cryogenic chamber, and a quantum device disposed in the second chamber. The signal reflecting element is configured to split an input signal into a first signal component and a second signal component. The system further includes a first signal line and a second signal line. The first signal line is configured to supply the input signal from an external environment to the signal reflecting element and to supply the reflected first signal component from the signal reflecting element to the external environment. The second signal line is configured to supply the transmitted second signal component from the signal reflecting element to the quantum device. The signal reflecting element electrically couples the first signal line to the second signal line.

Description

[Technical Field]

[0001] This application claims priority to U.S. Application No. 18 / 073,224, filed December 1, 2022, and is incorporated herein by reference.

[0002] The present disclosure relates generally to quantum computing and information processing systems, and more particularly to thermalizing control wiring of quantum devices (e.g., qubits) within quantum computing and information processing systems. [Background technology]

[0003] Quantum computing is a computing method that utilizes quantum effects such as basis state superposition and quantum entanglement to perform certain calculations more efficiently than classical digital computers. In contrast to digital computers, which store and manipulate information in the form of bits, e.g., "1" or "0," quantum computing systems can manipulate information using quantum bits ("qubits"). A qubit can refer to a quantum device that allows for the superposition of data in multiple states, e.g., both "0" and "1," and / or the superposition of data in multiple states itself. In conventional terminology, the superposition of "0" and "1" states in a quantum system may be expressed, for example, as a|0>+b|1>. The "0" and "1" states of a digital computer are analogous to the |0> and |1> basis states of a qubit, respectively. Summary of the Invention

[0004] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the description that follows, or may be learned from the description, or may be learned by practice of the embodiments.

[0005] One exemplary aspect of the present disclosure is directed to a quantum processor system (e.g., a quantum computing system and / or a quantum information processing system). The system may include a first cryogenic chamber, a signal reflecting element disposed within the first cryogenic chamber, a second cryogenic chamber, and a quantum device disposed in the second chamber. The signal reflecting element is configured to split the input signal into a first signal component and a second signal component by partial reflection of the input signal. The partial reflection of the input signal causes the first signal component of the input signal to be reflected by the signal reflecting element and the second signal component of the input signal to be transmitted by the signal reflecting element. The system further includes a first signal line and a second signal line. The first signal line is configured to supply the input signal from an external environment to the signal reflecting element. The first signal line is further configured to supply the reflected first signal component from the signal reflecting element to the external environment. The external environment is external to each of the first cryogenic chamber and the second cryogenic chamber. The second signal line is configured to provide the transmitted second signal component from the signal reflecting element to a quantum device disposed in the second cryogenic chamber, and the signal reflecting element electrically couples the first signal line to the second signal line such that the transmitted second signal component is transmitted through the signal reflecting element to the second signal line.

[0006] Other aspects of the present disclosure are directed to various systems, methods, apparatus, non-transitory computer-readable media, computer-readable instructions, and computing devices.

[0007] These and other features, aspects, and advantages of various embodiments of the present disclosure will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and, together with the description, explain associated principles.

[0008] Detailed descriptions of embodiments directed to those skilled in the art are set forth herein with reference to the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 provides a schematic diagram of a conventional multi-stage cryogenic system and conventional architectures typically employed to thermalize signal lines and attenuate signals in quantum computing systems. [Figure 1B] 1 illustrates an exemplary quantum computing system according to an exemplary embodiment of the present disclosure. [Figure 2] A schematic diagram of an enhanced multi-stage cryogenic system and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in quantum computing systems is provided. [Figure 3] A schematic diagram of an enhanced multi-stage cryogenic system and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in quantum computing systems is provided. [Figure 4] A schematic diagram of an enhanced multi-stage cryogenic system and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in quantum computing systems is provided. [Figure 5] A schematic diagram of an enhanced multi-stage cryogenic system and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in quantum computing systems is provided. [Figure 6] A schematic diagram of an enhanced multi-stage cryogenic system and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in quantum computing systems is provided. DETAILED DESCRIPTION OF THE INVENTION

[0010] Exemplary aspects of the present disclosure are directed to methods, architectures, and hardware configurations that enable thermalization of control wiring of quantum devices (e.g., qubits, qubit couplers, and / or quantum gates) in quantum computing and / or quantum information processing systems. Embodiments enable thermalization of control wiring as the number of quantum devices scales to large numbers (e.g., embodiments enable such systems to scale to at least millions of quantum devices cooled via a single cryogenic system). Traditional thermalization of control wiring typically involves attenuating the control signal (by absorbing a significant portion of the signal) in the "middle" stages of the cryogenic system that maintain the coherence of the quantum devices. Such signal absorption is typically achieved via resistive elements in the middle stages of the cryogenic system. However, absorbing the signal in the middle stages of the cryogenic system generates a significant amount of heat. Furthermore, these absorbers radiate highly emissive electromagnetic blackbody radiation to the final stages of the cryogenic system that house the quantum devices via blackbody radiation. In such conventional absorption-based architectures, as the number of quantum devices scales, the amount of heat load on the cryogenic system and the amount of heat radiated to the quantum devices also scales, resulting in a loss of coherence.

[0011] Rather than absorbing the signal in an intermediate stage of a cryogenic system, as conventional systems do, various embodiments place a “reflective” element within the intermediate stage. Such a reflective element need not be an ideal reflector, but rather a “partial reflector” such that a portion of the signal is transmitted through the reflective element. Such a partially reflective element can function as a signal “splitter,” where a significant portion of the signal is reflected to a “heat sink” element (e.g., located outside the cryogenic system), and the “unreflected” portion of the control signal is provided to a quantum device in a final stage of the cryogenic system. Through partial reflection of the control signal, signal attenuation (and at least partial signal thermalization) is achieved such that excessive heat is not radiated to the quantum device due to the filter's lower blackbody emissivity, and thus coherence can be maintained by the cryogenic system. If necessary, the attenuated signal (e.g., the unreflected portion of the control signal) may be further thermalized in the final stage of the cryogenic system. Due to the significant reflective attenuation (rather than absorption-based attenuation) of the control signal in the intermediate stage, such further thermalization in the final stage may not generate a sufficient amount of heat to induce decoherence in the quantum device. Such "signal splitting" (or partial signal reflection) As discussed throughout, the reflecting element may be achieved through a variety of architectures depending on the frequency of the control signal, the amplitude of the control signal, the amount of reflection or transmission required, the number of quantum devices included in the final stage, or various other factors.

[0012] In various embodiments, a cryogenic system (of a quantum computing system) may include at least three stages: an initial stage, one or more intermediate stages, and a final stage housing a quantum device. The initial stage may be a room temperature (RT) stage maintained at approximately 300 Kelvin. Accordingly, the initial stage may be referred to as an RT stage. At least one of the one or more intermediate stages may house one or more reflective (e.g., partially reflective) elements that perform non-absorptive (e.g., reflective) signal attenuation. These one or more intermediate stages housing the reflective elements may be maintained at a temperature of approximately 3 Kelvin. Accordingly, these one or more intermediate stages housing the reflective elements may be collectively referred to as a "low temperature" stage or a "3K" stage. The final stage housing the quantum device may be maintained at a temperature on the order of millikelvin (e.g., 20 millikelvin), and therefore, the final stage may be referred to as a "ultra-low temperature" stage or a "millikelvin" stage.

[0013] The control signal may simply be referred to as the signal. In some embodiments, the control signal may be a direct current (DC) signal. In other embodiments, the control signal may be an alternating current (AC) signal, e.g., a microwave signal. A control signal (e.g., directed to one or more quantum devices in the cryogenic stage) may originate at (or at least pass through) the RT stage. During signal propagation along the control line, before reaching the cryogenic stage, the signal may pass through a cryogenic stage containing one or more reflective elements. The one or more reflective elements may attenuate the signal by partial reflection of the signal. The “reflected” portion of the signal may be reflected back to the RT stage (e.g., along either the control line or another signal line that provided the signal to the reflective element). The “transmitted” portion of the signal may continue its propagation toward the cryogenic stage (e.g., along the same control line or another signal line). Because the RT stage is held at approximately 300 Kelvin, the RT stage may act as a heat sink and absorb the heat associated with the reflected signal without significant adverse effects. In some embodiments, the signal attenuation achieved via the reflecting element is approximately 20 decibels (dB), although this attenuation factor may vary depending on the embodiment. Thus, the reflected signal may return approximately 99% of the original signal's power to the RT stage, and the transmitted signal may carry approximately 1% of the original signal's power to the cryogenic stage. Due to the strong non-absorptive attenuation of the signal in the cryogenic stage (e.g., approximately 20 dB), the transmitted signal (e.g., the non-reflected portion of the signal) and / or its control lines may be effectively thermalized in the cryogenic stage without significantly heating the cryogenic stage. The transmitted portion of the signal may be referred to interchangeably as the attenuated signal and / or the transmitted signal.

[0014] FIG. 1A provides a schematic diagram of a conventional multi-stage cryogenic system 10 and conventional architecture typically employed to thermalize signal lines and attenuate signals in quantum computing systems (QCS). The conventional cryogenic system 10 includes at least three stages: a room temperature (RT) stage 20, a low temperature stage 40, and an ultra-low temperature stage 60. As noted above, the RT stage 20 can operate at approximately 300 Kelvin and may be interchangeably referred to as an initial stage. The low temperature stage 40 can operate at approximately 3 Kelvin and may be interchangeably referred to as an intermediate stage. The ultra-low temperature stage 60 can operate at approximately 20 milliKelvin and may be interchangeably referred to as a final stage. The ultra-low temperature stage 60 can house a set of quantum devices 62. The set of quantum devices 62 can include a set of qubits, a set of quantum logic gates, a set of qubit couplers (e.g., employable as quantum gates), etc.

[0015] The conventional cryogenic system 10 may further include a signal line 14 (e.g., a control signal line) and a ground line 16. The signal line 14 and the ground line 16 may be electrically coupled via an absorptive attenuation element 42 housed in the cryogenic stage 40. As shown in FIG. 2 , the absorptive attenuation element 42 may be implemented via one or more resistors. That is, the signal attenuation provided by the absorptive attenuation element 42 is achieved via a heat-generating resistive means that effectively “absorbs” (and radiates) energy associated with at least a portion of the input signal 12. Thus, the absorptive attenuation element 42 may be a resistive attenuation element. The signal line may carry the input signal 12 toward one or more qubit devices in the set of qubit devices 62. The absorptive attenuation element 42 in the cryogenic stage 40 may attenuate the input signal 12 such that an attenuated output signal 18 is provided to one or more quantum devices in the set of quantum devices. In some scenarios, the attenuation from the input signal 12 to the output signal 14 is substantial (e.g., approximately 20 dB) to filter out much of the signal noise generated in the RT stage 20.

[0016] The absorbing attenuation element may include at least a first resistor 44, a second resistor 46, and a third resistor 48. The resistance of the third resistor 48 may be significantly greater than the resistance of the first resistor 44 and the second resistor 46 combined in series. Thus, the third resistor 48 may effectively "reroute" a significant portion of the energy of the input signal 12 through the first and second resistors 44 / 46. With a significant portion of the input signal 12 rerouted through the first resistor 44, the first resistor may function to significantly attenuate the input signal 12 and absorb a significant amount of the energy of the input signal 12. Thus, the first resistor 44 may function as a heat sink and may act as a heat dissipation resistor (e.g., R heat )). The first resistor 44 may emit radiant heat 50 toward the cryogenic stage 60. The second resistor 46 acts as a "bridge" back to the signal line 14, redirecting the remaining portion of the attenuated input signal 12 (e.g., output signal 18) back toward the cryogenic stage 60. That is, the second resistor 46 may "blow" the output signal (and its temperature and resulting noise) into the cryogenic environment. Thus, the second resistor 46 may function as a signal and / or heat emitting resistor (e.g., R emit ) and the second resistor 45 therefore emits 3k noise into the cryogenic stage 60. The first resistor 44 (i.e., R heat ), a second resistor 46 (i.e., R emit ), and third resistor 46 operate at the same temperature (eg, about 3 Kelvin).

[0017] Resistive damping by the absorptive damping element 42 can generate a significant amount of heat that dissipates from the cold stage 40. Such radiant heat 45 is indicated by dashed arrows pointing away from the absorptive damping element 42. As shown in FIG. 1A, at least a portion of the radiant heat 50 (e.g., via the first resistor 44) accumulates in the cryogenic stage 60. The radiant heat 50 warms the cryogenic stage 60 and can result in decoherence within the set of quantum devices 62. Decoherence in the set of quantum devices 62 can reduce the computational and information processing capabilities of the QCS. Note that as the density of the set of quantum devices 62 scales, the number of signal lines 14 also scales. Thus, as the number of quantum devices used by the QCS increases, the ability to control the temperature of the cryogenic stage 60 and / or the coherence of the set of quantum devices 62 becomes increasingly difficult to maintain with conventional absorptive damping architectures and methods.

[0018] Various embodiments disclosed herein replace the absorptive attenuation element 42 with a reflective element that operates as a signal splitter. The signal splitter functions to provide a similar level of attenuation of the input signal 12. However, in contrast to the absorptive attenuation element 42, the attenuation provided by the reflective element does not generate a significant amount of heat. Rather, the components of the input signal 12 that are not provided to the cryogenic stage 60 are redirected toward the RT stage 20, which can function as an effective heat sink without affecting the cryogenic stage 60. The components of the input signal 12 provided to the cryogenic stage 60 (e.g., the output signal 18) are transmitted through the reflective element. Because significant signal attenuation is achieved by splitting the signal through a reflective element (rather than an absorptive attenuation element), the signal line 14 and / or the significantly attenuated output signal 18 can be thermalized in the cryogenic stage 60 without significantly heating the cryogenic stage 60 and / or affecting the coherence of the set of quantum devices 62.

[0019] It should be noted that application of the embodiments is not limited to quantum computing systems and quantum information processing systems. Rather, the embodiments may be employed in any application using a multi-stage cryogenic system in which a signal originates in a hotter environment (e.g., an RT environment) and is transmitted to a colder environment (e.g., a cryogenic environment). The embodiments may be employed in any application in which a signal from an environment (e.g., an RT environment) needs to be thermalized and / or attenuated before being provided to the cryogenic environment without radiating significant heat to the cryogenic environment. It should be noted that such non-absorbing attenuation may be useful for filtering out a large portion of the signal noise generated in the RT environment, so that the filtered-out portion of the noise is not transmitted to the cryogenic environment where the noise may have a greater impact.

[0020] Aspects of the present disclosure provide several technical effects and advantages. For example, by partially reflecting, rather than resistively absorbing, control signals in the intermediate stages of a cryogenic system, it becomes possible to scale the number of quantum devices in the final stage of a cryogenic system by at least several orders of magnitude without radiating significant amounts of heat to the final stage. Thus, maintaining coherence among millions of qubits and / or logic gates may be achieved. Thus, scalable quantum computing and quantum information processing may be achieved by various embodiments.

[0021] 1B illustrates an exemplary quantum computing system 100. System 100 is one example of a system of one or more classical computers and / or quantum computing devices at one or more locations, which may implement the systems, components, and techniques described below. Using the disclosure provided herein, one skilled in the art will understand that other quantum computing devices or systems may be used without departing from the scope of the present disclosure.

[0022] System 100 includes quantum hardware 102 in data communication with one or more classical processors 104. Classical processor 104 can be configured to execute computer-readable instructions stored in one or more memory devices to perform operations, such as any of the operations described herein. Quantum hardware 102 includes components for performing quantum computations. For example, quantum hardware 102 includes quantum system 110, control device(s) 112, and readout device(s) 114 (e.g., readout resonator(s)). Quantum system 110 can include one or more multi-level quantum subsystems, such as a register of qubits (e.g., qubit 120). In some implementations, the multi-level quantum subsystem can include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, gmon qubits, and spin-based qubits.

[0023] The type of multi-level quantum subsystem utilized by system 100 may vary. For example, in some cases it may be advantageous to include one or more readout device(s) 114 attached to one or more superconducting qubits, e.g., transmon, fluxon, gmon, xmon, or other qubits. In other cases, ion traps, photonic devices, or superconducting cavities (which may prepare states without the need for qubits) may be used. Further examples of multi-level quantum subsystem implementations include fluxon qubits, silicon quantum dots, or phosphorus impurity qubits.

[0024] Quantum circuits may be constructed and applied to a register of qubits included in quantum system 110 via multiple control lines coupled to one or more control devices 112. Exemplary control devices 112 operating on a register of qubits may be used to implement quantum gates or quantum circuits having multiple quantum gates, such as, for example, Pauli gates, Hadamard gates, controlled-NOT (CNOT) gates, controlled phase gates, T-gates, multi-qubit quantum gates, coupler quantum gates, etc. One or more control devices 112 may be configured to operate on quantum system 110 through one or more respective control parameters (e.g., one or more physical control parameters). For example, in some implementations, the multi-level quantum subsystem may be a superconducting qubit, and control device 112 may be configured to provide control pulses to the control lines to generate magnetic fields that tune the frequency of the qubits.

[0025] The quantum hardware 102 may further include a readout device 114 (e.g., a readout resonator). Measurements 108 obtained via the measurement device may be provided to a classical processor 104 for processing and analysis. In some implementations, the quantum hardware 102 may include quantum circuits, and the control device(s) 112 and readout device(s) 114 may implement one or more quantum logic gates that operate on the quantum system 102 via physical control parameters (e.g., microwave pulses) transmitted through wires included in the quantum hardware 102. Further examples of control devices include arbitrary waveform generators in which a DAC (digital-to-analog converter) creates a signal.

[0026] The readout device(s) 114 may be configured to perform quantum measurements on the quantum system 110 and send the measurement results 108 to the classical processor 104. Additionally, the quantum hardware 102 may be configured to receive data from the classical processor 104 specifying the physical control qubit parameter values ​​106. The quantum hardware 102 may use the received physical control qubit parameter values ​​106 to update the action of the control device(s) 112 and readout device(s) 114 on the quantum system 110. For example, the quantum hardware 102 may receive data specifying new values ​​representing the voltage magnitudes of one or more DACs included in the control device 112 and may update the action of the DACs on the quantum system 110 accordingly. The classical processor 104 may be configured to initialize the quantum system 110 to an initial quantum state, for example, by sending data specifying an initial set of parameters 106 to the quantum hardware 102.

[0027] In some implementations, the readout device(s) 114 can measure the state of an element (e.g., a qubit) of a quantum system, such as a qubit, by utilizing the difference in impedance for the |0> and |1> states of the element. For example, the resonant frequency of the readout resonator can be different when the qubit is in the |0> or |1> state due to the nonlinearity of the qubit. Thus, microwave pulses reflected from the readout device 114 convey amplitude and phase shifts that depend on the qubit state. In some implementations, a Purcell filter can be used in conjunction with the readout device(s) 114 to prevent microwave propagation at the qubit frequency.

[0028] In some embodiments, quantum system 110 may include multiple qubits 120 arranged, for example, in a two-dimensional grid 122. For clarity, two-dimensional grid 122 depicted in FIG. 1B includes 4x4 qubits, although in some implementations, system 110 may include a fewer or greater number of qubits. In some embodiments, multiple qubits 120 may interact through a multi-qubit coupler, such as qubit coupler 124. The qubit coupler may define nearest-neighbor interactions between multiple qubits 120. In some implementations, the strength of the multi-qubit coupler is a tunable parameter. In some cases, the multi-qubit couplers included in quantum computing system 100 may be couplers with fixed coupling strengths.

[0029] In some implementations, the plurality of qubits 120 may include data qubits, such as qubit 126, and measurement qubits, such as qubit t. A data qubit is a qubit that participates in a computation being performed by system 100. A measurement qubit is a qubit that can be used to determine the result of a computation performed by a data qubit. That is, during a computation, the unknown state of a data qubit is conveyed to a measurement qubit using an appropriate physical operation and measured by an appropriate measurement operation performed on the measurement qubit.

[0030] In some implementations, each qubit of plurality of qubits 120 may operate using a respective operating frequency, such as an idle frequency, an interaction frequency, a readout frequency, and / or a reset frequency. The operating frequency may vary from qubit to qubit. For example, each qubit may idle at a different operating frequency. The operating frequency of qubit 120 may be selected before a computation is performed.

[0031] 1B illustrates one exemplary quantum computing system that may be used to implement methods and operations according to exemplary aspects of the present disclosure. Other quantum computing systems may be used without departing from the scope of the present disclosure.

[0032] FIG. 2 provides a schematic diagram of an enhanced multi-stage cryogenic system 210 and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in a quantum computing system (QCS). The embodiment shown in FIG. 2 is intended for an AC (e.g., radio frequency (RF)) input signal 212 and may therefore be an alternating current (AC) embodiment. The enhanced cryogenic system 210 includes at least three stages: a room temperature (RT) stage 220, a low temperature stage 240, and an ultra-low temperature stage 260. The RT stage 220 can operate at approximately 300 Kelvin and may interchangeably be referred to as the initial stage of the cryogenic system 210. The low temperature stage 240 can operate at approximately 3 Kelvin and may interchangeably be referred to as the middle stage of the cryogenic system 210. The ultra-low temperature stage 260 can operate at approximately 220 milliKelvin and may interchangeably be referred to as the final stage of the cryogenic system 210. The ultra-low temperature stage 260 can house a set of quantum devices 262. The set of quantum devices 262 may include a set of qubits, a set of quantum logic gates, a set of qubit couplers (e.g., employable as quantum gates), etc. For example, the set of quantum devices may include the plurality of qubits 120, the two-dimensional grid 122, and / or the qubit couplers 124 of FIG.

[0033] The enhanced cryogenic system 210 may further include a first signal line 214 (e.g., a control signal line), a second signal line 224, and a ground line 216. As shown in FIG. 2, the first signal line 214 may extend from the RT stage 220 into the cold stage 240 and back to the RT stage 220. Also shown in FIG. 2, the second signal line 224 may extend from the cryogenic stage 260 into the cold stage 240 and back to the cryogenic stage 260. The first signal line 214 and the ground line 216 may be electrically coupled (at the RT stage 220) through a first resistive element 226 disposed in the RT stage 220. The second signal line 224 may be electrically coupled to ground (e.g., which may be, but is not required to be, the ground line 216) through a second resistive element 264 disposed in the cryogenic stage 260. The first signal line 214 and the second signal line 224 may be electrically coupled at the cold stage 240 via a directional coupler 242. The ground line 216 and the second resistive element 264 may be electrically coupled to electrical ground.

[0034] The directional coupler 242 may function as a signal reflecting element of the cold stage 240 and to electrically couple the first signal line 214 with the second signal line 224. That is, the directional coupler 242 may reflect a portion of the input signal 212 (e.g., the return signal 222) and transmit the remaining portion of the input signal (e.g., the output signal 218) to the second signal line 224. The directional coupler 242 may function as a signal “splitter” element that splits the input signal 212 into the return signal 222 and the output signal 218 through partial reflection of the input signal 212. The return signal 222 may be referred to as a reflected signal component (e.g., a first signal component), and the output signal 218 may be referred to as a transmitted signal component (e.g., a second signal component). Thus, by partial reflection, the directional coupler 242 (e.g., a signal reflecting element) is configured to split the input signal 212 into a reflected signal component (e.g., reflected by the signal reflecting element) and a transmitted signal component (e.g., transmitted by the signal reflecting element).

[0035] By splitting input signal 212 into return signal 222 and output signal 218, directional coupler 242 may function to attenuate input signal 212. In some embodiments, directional coupler 242 attenuates input signal 212 by approximately 20 dB. The attenuation achieved via directional coupler 242 is “reflective” attenuation, rather than absorptive attenuation, as shown in FIG. 1A . Thus, the signal attenuation achieved in cryostage 240 does not generate heat in cryostage 240, as opposed to heat generation in cryostage 40 of FIG. 1A . Return signal 222 is returned to RT stage 220 via first signal line 214, and output signal 218 is provided via second signal line 224 to ultra-low temperature stage 260 and one or more quantum devices in set of quantum devices 262.

[0036] The first resistive element 226 can function as a heat absorber and can be a heat absorbing resistor (e.g., R heat ) in some embodiments. The resistance of the first resistive element 226 may be approximately 50 ohms. The second resistive element 264 may "absorb" and "emit" at very low temperatures. Thus, the second resistive element 264 acts as a low-temperature blackbody emitter and absorber (e.g., R emit ) The second resistive element 264 may function to thermalize the portion of the second signal line 224 at the output signal 218 and / or the ultra-low temperature stage 260. Because the output signal 218 is significantly attenuated, the amount of heat stored at the ultra-low temperature stage 260 is significantly attenuated. In some embodiments, the resistance of the second resistive element 264 may be approximately 50 ohms.

[0037] Referring to FIG. 2 , cold stage 240 may include a first cryogenic chamber, and cryogenic stage 260 may include a second cryogenic chamber. Accordingly, one or more quantum devices (e.g., qubits, qubit couplers, quantum logic gates, etc.) of set of quantum devices 262 may be disposed within the second cryogenic chamber. In at least one embodiment, the second cryogenic chamber may be nested within the first cryogenic chamber. RT stage 220 may or may not include a third cryogenic chamber. That is, RT stage 220 may be outside any cryogenic chamber. The RT stage may include an external environment that is external to each of the first and second cryogenic chambers. A signal reflection element (e.g., directional coupler 242) is disposed within the first cryogenic chamber. The signal reflecting element is configured to split the input signal 212 into a first signal component (e.g., return signal 222) and a second signal component (e.g., output signal 218) by partial reflection of the input signal 212. Due to partial reflection of the input signal 212, the first signal component of the input signal 212 is reflected by the signal reflecting element and the second signal component of the input signal 212 is transmitted by the signal reflecting element. The partial reflection of the input signal 212 attenuates the input signal 212, and the second signal component (e.g., output signal 218) is an attenuated version of the input signal 212. The attenuation of the input signal 212 may be approximately 20 decibels (dB). If the signal reflecting element is a directional coupler, the input signal 212 may be an alternating current (AC) signal. The input signal 212 may be a radio frequency (RF) signal.

[0038] As shown in Figure 2, input signal 212 may originate in an external environment. First signal line 214 is further configured to provide the reflected first signal component from the signal reflecting element to the external environment. Second signal line 224 is configured to provide the transmitted second signal component from the signal reflecting element to a quantum device disposed within a second cryogenic chamber. The signal reflecting element electrically couples input signal 212 to the second signal line such that the second signal component transmitted by the signal reflecting element is transmitted through the signal reflecting element to the second signal line.

[0039] The ground line 216 may pass through the external environment, the first cryogenic chamber, and the second cryogenic chamber. As shown in FIG. 2 , the ground line 216 may be electrically coupled to electrical ground. A resistive element (e.g., a first resistive element 226) may be disposed in the external environment. The first resistive element 226 couples the first signal line 214 to electrical ground so that heat associated with the energy of the first signal component (e.g., the return signal 222) is dissipated to the external environment. Another resistive element (e.g., a second resistive element 264) may be disposed in the second cryogenic chamber. The second resistive element 264 couples the second signal line 224 to electrical ground so that the second signal component (e.g., the output signal 218) is at least partially thermalized in the second cryogenic chamber.

[0040] Input signal line 212 may include a first portion that carries input signal 212 from the external environment to the signal reflecting element. First signal line 214 may include a second portion that carries a first signal component (e.g., return signal 222) from the signal reflecting element to the external environment. The first and second portions of first signal line 214 may be non-contiguous portions such that input signal 212 and the first signal component are carried by non-contiguous portions of first signal line 214.

[0041] FIG. 3 provides a schematic diagram of another enhanced multi-stage cryogenic system 310 and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in a quantum computing system (QCS). The embodiment shown in FIG. 3 is intended for an AC (e.g., radio frequency (RF)) input signal 312 and may be an alternating current (AC) embodiment. However, the embodiment shown in FIG. 3 is not limited thereto and may be a direct current (DC) embodiment as it can transmit a DC input signal 312. The enhanced cryogenic system 310 includes at least three stages: a room temperature (RT) stage 220 of FIG. 2, a low temperature stage 40 of FIG. 2, and an ultra-low temperature stage 260 of FIG. 2. As discussed with respect to FIG. 2, the RT stage 220 can operate at approximately 300 Kelvin and may interchangeably be referred to as the initial stage of the cryogenic system 210. The low temperature stage 240 can operate at approximately 3 Kelvin and may interchangeably be referred to as the middle stage of the cryogenic system 210. Cryogenic stage 260 can operate at approximately 220 millikelvin and may interchangeably be referred to as the final stage of cryogenic system 210. Cryogenic stage 260 can house set of quantum devices 262 of FIG. 2. Set of quantum devices 262 can include a set of qubits, a set of quantum logic gates, a set of qubit couplers (e.g., employable as quantum gates), etc. For example, set of quantum devices can include plurality of qubits 120, two-dimensional grid 122, and / or qubit coupler 124 of FIG. 1B.

[0042] The enhanced cryogenic system 310 may further include a first signal line 314 (e.g., a control signal line), a second signal line 324, and a ground line 216 of Figure 2. As shown in Figure 3, the first signal line 314 may extend between the RT stage 220 and the cold stage 240. As shown in Figure 3, the second signal line 324 may extend between the ultra-low temperature stage 260 and the cold stage 240. The first signal line 314 and the second signal line 324 may be electrically coupled at the cold stage 240 via a resistive element 342.

[0043] The resistance of the resistive element 342 may be large enough that the resistive element 342 can function as a signal reflecting element of the cold stage 240 and electrically couple the first signal line 314 with the second signal line 324. That is, the resistive element 342 may reflect a portion of the input signal 312 (e.g., a return signal 322) and transmit the remaining portion of the input signal (e.g., an output signal 318) to the second signal line 324. The resistive element 342 may function as a signal “splitter” element that splits the input signal 312 into the return signal 322 and the output signal 318 by partial reflection of the input signal 312. The return signal 322 may be referred to as a reflected signal component (e.g., a first signal component), and the output signal 318 may be referred to as a transmitted signal component (e.g., a second signal component). Thus, by partial reflection, the resistive element 342 (e.g., a signal reflecting element) is configured to split the input signal 312 into a reflected signal component (e.g., reflected by the signal reflecting element) and a transmitted signal component (e.g., transmitted by the signal reflecting element).

[0044] By splitting the input signal 312 into the return signal 322 and the output signal 318, the resistive element 342 may function to attenuate the input signal 312. In some embodiments, the resistive element 342 attenuates the input signal 312 by approximately 20 dB. The attenuation achieved via the resistive element 342 is “reflective” attenuation, rather than absorptive attenuation, as shown in FIG. 1A . As described above, the resistance of the resistive element 342 may be sufficiently large so that the resistive element 342 (e.g., >>50 ohms) can function as a signal reflecting element in the cold-stage 240. Selecting the resistance may be based on the current and / or voltage amplitude of the input signal 312 and / or the desired value of reflectance, e.g., 20 dB. Reflective attenuation, unlike absorptive attenuation, may be achieved by selecting the resistance of the resistive element 342 to be sufficiently larger than the absorptive attenuation element 42 of FIG. 1A . Thus, the signal attenuation achieved in the cold-stage 240 does not generate heat in the cold-stage 240, as opposed to heat generation in the cold-stage 40 of FIG. 1A . Return signal 322 is returned to RT stage 220 via first signal line 314, and output signal 318 is provided to cryogenic stage 260 and one or more quantum devices of set of quantum devices 262 via second signal line 324. In embodiments where the input signal is an alternating current (AC) signal, resistive element 342 may be replaced and / or augmented with a circulator element. Employing a circulator element may help to mitigate some unwanted aspects of reflections of input signal 312.

[0045] As shown in FIG. 3 , low-temperature stage 240 may include a first cryogenic chamber, and cryogenic stage 260 may include a second cryogenic chamber. Accordingly, one or more quantum devices (e.g., qubits, qubit couplers, quantum logic gates, etc.) of set of quantum devices 262 may be disposed within the second cryogenic chamber. In at least one embodiment, the second cryogenic chamber may be nested within the first cryogenic chamber. RT stage 220 may or may not include a third cryogenic chamber. That is, RT stage 220 may be external to any cryogenic chambers. The RT stage may include an external environment that is external to each of the first and second cryogenic chambers. A signal reflecting element (e.g., resistive element 342) is disposed within the first cryogenic chamber. The signal reflecting element is configured to split the input signal 312 into a first signal component (e.g., return signal 322) and a second signal component (e.g., output signal 318) by partial reflection of the input signal 312. Due to partial reflection of the input signal 312, the first signal component of the input signal 312 is reflected by the signal reflecting element and the second signal component of the input signal 312 is transmitted by the signal reflecting element. The partial reflection of the input signal 312 attenuates the input signal 312, and the second signal component (e.g., output signal 318) becomes an attenuated version of the input signal 312. The attenuation of the input signal 312 may be approximately 20 decibels (dB). If the signal reflecting element is a circulator element, the input signal 312 may be an alternating current (AC) signal. If the signal reflecting element is a resistive element 342, the input signal 312 may be a direct current (DC) signal.

[0046] The first signal line 314 may be configured to provide the input signal 312 from an external environment (e.g., the RT stage 220) to the signal reflecting element. As shown in FIG. 3, the input signal 312 may originate in the external environment. The first signal line 314 is further configured to provide the reflected first signal component from the signal reflecting element to the external environment. The second signal line 324 is configured to provide the transmitted second signal component from the signal reflecting element to a quantum device disposed in a second cryogenic chamber. The signal reflecting element (e.g., the reflecting element 342) electrically couples the first signal line 314 to the second signal line 324 such that the second signal component transmitted by the signal reflecting element is transmitted through the signal reflecting element to the second signal line.

[0047] The ground wire 216 may pass through the external environment, the first cryogenic chamber, and the second cryogenic chamber. As shown in FIG. 3 , the ground wire 216 may be electrically coupled to electrical ground. The first signal wire 314 may include a common portion configured to transmit the input signal 312 from the external environment (e.g., the RT stage 220) to the signal reflecting element (e.g., the resistive element 342). The common portion of the first signal wire 314 may be further configured to transmit a first signal component (e.g., a return signal 322) from the signal reflecting element to the external environment such that both the input signal 312 and the first signal component are transmitted by the common portion of the first signal wire 314.

[0048] 4 provides a schematic diagram of another enhanced multi-stage cryogenic system 410 and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in a quantum computing system (QCS). The enhanced cryogenic system 410 of FIG. 4 may be similar to the enhanced cryogenic system 310 of FIG. 3, but includes a second resistive element 464 disposed in the cryogenic stage 260 and connected to electrical ground. The inclusion of the second resistive element 464 in the cryogenic stage 260 may provide and / or enable functionality similar to the inclusion of the second resistive element 264 in the enhanced cryogenic system 210 of FIG. 2.

[0049] Similar to the enhanced cryogenic system 310 of FIG. 3 , the enhanced cryogenic system 410 of FIG. 4 may be an alternating current (AC) embodiment, as it is subject to an AC (e.g., radio frequency (RF)) input signal 412. However, the embodiment shown in FIG. 4 is not so limited and may alternatively be a direct current (DC) embodiment, as it is subject to a DC input signal 412. The enhanced cryogenic system 410 includes at least three stages: the room temperature (RT) stage 220 of FIG. 2 , the low temperature stage 40 of FIG. 2 , and the ultra-low temperature stage 260 of FIG. 2 . As discussed with respect to FIG. 2 , the RT stage 220 may operate at approximately 300 Kelvin and may interchangeably be referred to as the initial stage of the cryogenic system 210. The low temperature stage 240 may operate at approximately 3 Kelvin and may interchangeably be referred to as the middle stage of the cryogenic system 210. The ultra-low temperature stage 260 may operate at approximately 220 milliKelvin and may interchangeably be referred to as the final stage of the cryogenic system 210. Ultra-low temperature stage 260 may house set of quantum devices 262 of Figure 2. Set of quantum devices 262 may include a set of qubits, a set of quantum logic gates, a set of qubit couplers (e.g., employable as quantum gates), etc. For example, set of quantum devices may include a plurality of qubits 120, two-dimensional grid 122, and / or qubit coupler 124 of Figure 1B.

[0050] The enhanced cryogenic system 410 may further include a first signal line 414 (e.g., a control signal line), a second signal line 424, and a ground line 216 of Figure 2. As shown in Figure 4, the first signal line 414 may extend between the RT stage 220 and the cold stage 240. As also shown in Figure 4, the second signal line 424 may extend between the ultra-low temperature stage 260 and the cold stage 240. The first signal line 414 and the second signal line 324 may be electrically coupled at the cold stage 240 via a first resistive element 442.

[0051] The resistance of the first resistive element 442 may be large enough that the first resistive element 442 can function as a signal reflecting element of the cold stage 240 and electrically couple the first signal line 414 with the second signal line 424. That is, the first resistive element 442 may reflect a portion of the input signal 412 (e.g., a return signal 422) and transmit the remaining portion of the input signal (e.g., an output signal 418) to the second signal line 424. The first resistive element 442 may function as a signal “splitter” element that splits the input signal 412 into the return signal 422 and the output signal 418 by partial reflection of the input signal 412. The return signal 422 may be referred to as a reflected signal component (e.g., a first signal component), and the output signal 418 may be referred to as a transmitted signal component (e.g., a second signal component). Thus, by partial reflection, the first resistive element 442 (e.g., a signal reflecting element) is configured to split the input signal 412 into a reflected signal component (e.g., reflected by the signal reflecting element) and a transmitted signal component (e.g., transmitted by the signal reflecting element).

[0052] By splitting the input signal 412 into a return signal 422 and an output signal 418, the first resistive element 442 may function to attenuate the input signal 412. In some embodiments, the first resistive element 442 attenuates the input signal 412 by approximately 20 dB. The attenuation achieved via the resistive element 442 is a “reflective” attenuation rather than an absorptive attenuation, as shown in FIG. 1A . Thus, the signal attenuation achieved in the low-temperature stage 240 does not generate heat in the low-temperature stage 240, as opposed to heat generation in the low-temperature stage 40 of FIG. 1A . The return signal 422 is returned to the RT stage 220 via the first signal line 414, and the output signal 418 is provided to the ultra-low temperature stage 460 and one or more quantum devices in the set of quantum devices 262 via the second signal line 424. In embodiments in which the input signal is an alternating current (AC) signal, the first resistive element 442 may be replaced with a circulator element.

[0053] The second resistive element 464 can "dump" the output signal 418 into the cryogenic environment. Therefore, the second resistive element 464 can be a signal and / or heat dumping resistor (e.g., R emit ) The second resistive element 464 may function to thermalize the portion of the output signal 418 and / or the second signal line 424 that is at the cryogenic stage 260. Because the output signal 418 is significantly attenuated, the amount of heat stored in the cryogenic stage 260 is also significantly attenuated. In some embodiments, the resistance of the second resistive element 264 may be approximately 50 ohms. For AC embodiments, the "short to ground" achieved via the second resistive element 464 may function to significantly reduce reflections of the output signal 418 along the second signal line 424.

[0054] Referring to FIG. 4 , low-temperature stage 240 may include a first cryogenic chamber, and cryogenic stage 260 may include a second cryogenic chamber. Accordingly, one or more quantum devices (e.g., qubits, qubit couplers, quantum logic gates, etc.) of set of quantum devices 262 may be disposed within the second cryogenic chamber. In at least one embodiment, the second cryogenic chamber may be nested within the first cryogenic chamber. RT stage 220 may or may not include a third cryogenic chamber. That is, RT stage 220 may be outside any cryogenic chamber. The RT stage may include an external environment that is external to each of the first and second cryogenic chambers. A signal reflecting element (e.g., first resistive element 442) is disposed within the first cryogenic chamber. The signal reflecting element is configured to split the input signal 412 into a first signal component (e.g., return signal 422) and a second signal component (e.g., output signal 418) by partial reflection of the input signal 412. Due to partial reflection of the input signal 412, the first signal component of the input signal 412 is reflected by the signal reflecting element and the second signal component of the input signal 412 is transmitted by the signal reflecting element. The partial reflection of the input signal 412 attenuates the input signal 412, and the second signal component (e.g., output signal 418) is an attenuated version of the input signal 412. The attenuation of the input signal 412 may be approximately 20 decibels (dB). If the signal reflecting element is a circulator element, the input signal 412 may be an alternating current (AC) signal. If the signal reflecting element is the first resistive element 442, the input signal 412 may be a direct current (DC) signal or an AC signal.

[0055] The first signal line 414 may be configured to provide an input signal 412 from an external environment (e.g., the RT stage 220) to the signal reflecting element. As shown in FIG. 4, the input signal 412 may originate in the external environment. The first signal line 414 is further configured to provide a reflected first signal component from the signal reflecting element to the external environment. The second signal line 424 is configured to provide a transmitted second signal component from the signal reflecting element to a quantum device disposed in a second cryogenic chamber. The signal reflecting element (e.g., the first reflecting element 442) electrically couples the first signal line 414 to the second signal line 424 such that the second signal component transmitted by the signal reflecting element is transmitted through the signal reflecting element to the second signal line.

[0056] The ground wire 416 may pass through the external environment, the first cryogenic chamber, and the second cryogenic chamber. As shown in FIG. 4 , the ground wire 216 may be electrically coupled to electrical ground. The first signal wire 414 may include a common portion configured to transmit the input signal 412 from the external environment (e.g., the RT stage 220) to the signal reflecting element (e.g., the first resistive element 442). The common portion of the first signal wire 414 may be further configured to transmit a first signal component (e.g., the return signal 422) from the signal reflecting element to the external environment such that both the input signal 412 and the first signal component are transmitted by the common portion of the first signal wire 414. Another resistive element (e.g., the second resistive element 464) may be disposed in the second cryogenic chamber. The second resistive element 464 couples the second signal wire 424 to electrical ground such that the second signal component (e.g., the output signal 418) is at least partially thermalized in the second cryogenic chamber.

[0057] FIG. 5 provides a schematic diagram of another enhanced multi-stage cryogenic system 510 and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in a quantum computing system (QCS). Like the enhanced cryogenic system 410 of FIG. 4, the enhanced cryogenic system 510 of FIG. 5 may be an alternating current (AC) embodiment, as it is intended for an AC (e.g., radio frequency (RF)) input signal 412. However, the embodiment of FIG. 5 is not so limited and may alternatively be a direct current (DC) embodiment, as it is intended for a DC input signal 512. The enhanced cryogenic system 510 of FIG. 5 may be viewed as a combination of the enhanced cryogenic system 210 of FIG. 2 and the enhanced cryogenic system 310 of FIG. 3, with the signal reflecting element of the cryogenic system 210 (i.e., directional coupler 242) replaced with the signal reflecting element of the cryogenic system 310 (i.e., resistive element 342).

[0058] Similar to cryogenic system 210 and cryogenic system 310, enhanced cryogenic system 510 includes at least three stages: room temperature (RT) stage 220, low temperature stage 240, and ultra-low temperature stage 260. RT stage 220 can operate at approximately 300 Kelvin and may be interchangeably referred to as the initial stage of cryogenic system 210. Low temperature stage 240 can operate at approximately 3 Kelvin and may be interchangeably referred to as the middle stage of cryogenic system 210. Ultra-low temperature stage 260 can operate at approximately 220 milliKelvin and may be interchangeably referred to as the final stage of cryogenic system 210. Ultra-low temperature stage 260 can house a set of quantum devices 262. The set of quantum devices 262 can include a set of qubits, a set of quantum logic gates, a set of qubit couplers (e.g., employable as quantum gates), etc. For example, the set of quantum devices may include multiple qubits 120, two-dimensional grid 122, and / or qubit coupler 124 of FIG. 1B.

[0059] The enhanced cryogenic system 510 may further include a first signal line 514 (e.g., a control signal line), a second signal line 524, and a ground line 216 of FIG. 2. As shown in FIG. 5, the first signal line 514 may extend from the RT stage 220 into the cold stage 240 and back to the RT stage 220. Also shown in FIG. 5, the second signal line 524 may extend from the cryogenic stage 260 into the cold stage 240 and back to the cryogenic stage 260. The first signal line 514 and the ground line 216 may be electrically coupled (at the RT stage 220) through a first resistive element 526 disposed in the RT stage 220. The second signal line 524 may be electrically coupled to ground (e.g., which may be, but is not required to be, the ground line 216) through a second resistive element 564 disposed in the cryogenic stage 260. The first signal line 514 and the second signal line 524 may be electrically coupled at the cold stage 240 through a third resistive element 542. The ground line 216 and the second resistive element 564 may be electrically coupled to an electrical ground.

[0060] The resistance of the third resistive element 542 may be large enough that the third resistive element 542 can function as a signal reflecting element in the cold stage 240 and electrically couple the first signal line 514 with the second signal line 524. That is, the third resistive element 542 can reflect a portion of the input signal 512 (e.g., a return signal 522) and transmit the remaining portion of the input signal (e.g., an output signal 518) to the second signal line 524. The third resistive element 542 may function as a signal “splitter” element that splits the input signal 512 into the return signal 522 and the output signal 518 by partial reflection of the input signal 512. The return signal 522 may be referred to as a reflected signal component (e.g., a first signal component), and the output signal 518 may be referred to as a transmitted signal component (e.g., a second signal component). Thus, by partial reflection, the third resistive element 542 (e.g., a signal reflecting element) is configured to split the input signal 512 into a reflected signal component (e.g., reflected by the signal reflecting element) and a transmitted signal component (e.g., transmitted by the signal reflecting element).

[0061] By splitting the input signal 512 into a return signal 522 and an output signal 518, the third resistive element 542 may function to attenuate the input signal 512. In some embodiments, the third resistive element 542 attenuates the input signal 512 by approximately 20 dB. The attenuation achieved via the third resistive element 542 is a “reflective” attenuation rather than an absorptive attenuation, as shown in FIG. 1A . Thus, the signal attenuation achieved in the low-temperature stage 240 does not generate heat in the low-temperature stage 240, as opposed to the heat generation in the low-temperature stage 40 of FIG. 1A . The return signal 522 is returned to the RT stage 220 via a first signal line 514, and the output signal 518 is provided to the ultra-low temperature stage 260 and one or more quantum devices in the set of quantum devices 262 via a second signal line 524.

[0062] The first resistive element 526 acts as a heat sink and is a heat sink resistor (e.g., R heat ) The heat radiated by the first resistive element 526 is radiated to the RT stage 220. Because the RT stage 220 is at approximately 300 Kelvin, the RT stage 220 can act as a heat sink for the heat radiated by the first resistive element 526. In some embodiments, the resistance of the first resistive element 526 can be approximately 50 ohms. The second resistive element 564 can "radiate" the output signal 518 to the ultra-cold environment. Therefore, the second resistive element 564 can act as a signal and / or heat radiating resistor (e.g., R emit ) The second resistive element 564 may function to thermalize the portion of the second signal line 524 at the output signal 518 and / or the ultra-low temperature stage 260. Because the output signal 518 is significantly attenuated, the amount of heat stored at the ultra-low temperature stage 260 is significantly attenuated. In some embodiments, the resistance of the second resistive element 564 may be approximately 50 ohms.

[0063] As shown in FIG. 5 , the low-temperature stage 240 may include a first cryogenic chamber, and the cryogenic stage 260 may include a second cryogenic chamber. Accordingly, one or more quantum devices (e.g., qubits, qubit couplers, quantum logic gates, etc.) of the set of quantum devices 262 may be disposed within the second cryogenic chamber. In at least one embodiment, the second cryogenic chamber may be nested within the first cryogenic chamber. The RT stage 220 may or may not include a third cryogenic chamber. That is, the RT stage 220 may be outside any cryogenic chamber. The RT stage may include an external environment that is external to each of the first and second cryogenic chambers. A signal reflecting element (e.g., the third resistive element 542) is disposed within the first cryogenic chamber. The signal reflecting element is configured to split the input signal 512 into a first signal component (e.g., return signal 522) and a second signal component (e.g., output signal 518) due to partial reflection of the input signal 512. Due to partial reflection of the input signal 512, the first signal component of the input signal 512 is reflected by the signal reflecting element and the second signal component of the input signal 512 is transmitted by the signal reflecting element. The partial reflection of the input signal 512 attenuates the input signal 512, and the second signal component (e.g., output signal 518) is an attenuated version of the input signal 512. The attenuation of the input signal 512 may be approximately 20 decibels (dB).

[0064] The first signal line 514 may be configured to provide an input signal 512 from an external environment (e.g., the RT stage 220) to the signal reflecting element. As shown in FIG. 5, the input signal 512 may originate in the external environment. The first signal line 514 is further configured to provide a reflected first signal component from the signal reflecting element to the external environment. The second signal line 524 is configured to provide a transmitted second signal component from the signal reflecting element to a quantum device disposed in a second cryogenic chamber. The signal reflecting element electrically couples the first signal line 514 to the second signal line 524 such that the second signal component transmitted by the signal reflecting element is transmitted to the second signal line 524 via the signal reflecting element.

[0065] The ground line 216 may pass through the external environment, the first cryogenic chamber, and the second cryogenic chamber. As shown in FIG. 5 , the ground line 216 may be electrically coupled to electrical ground. A resistive element (e.g., a first resistive element 526) may be disposed in the external environment. The first resistive element 526 couples the first signal line 214 to electrical ground so that heat associated with the energy of the first signal component (e.g., the return signal 522) is dissipated to the external environment. Another resistive element (e.g., a second resistive element 564) may be disposed in the second cryogenic chamber. The second resistive element 564 couples the second signal line 524 to electrical ground so that the second signal component (e.g., the output signal 518) is at least partially thermalized in the second cryogenic chamber.

[0066] The first signal line 514 may include a first portion that carries the input signal 512 from the external environment to the signal reflecting element. The first signal line 514 may further include a second portion that carries a first signal component (e.g., return signal 522) from the signal reflecting element to the external environment. The first and second portions of the first signal line 514 may be non-contiguous portions such that the input signal 512 and the first signal component are carried by non-contiguous portions of the first signal line 514.

[0067] 6 provides a schematic diagram of another enhanced multi-stage cryogenic system 610 and enhanced architecture that can be employed to thermalize signal lines and attenuate signals in a quantum computing system (QCS). The embodiment shown in FIG. 2 is intended for an AC (e.g., radio frequency (RF)) input signal 212 and may therefore be an alternating current (AC) embodiment. The enhanced cryogenic system 610 of FIG. 6 may be similar to the enhanced cryogenic system 210 of FIG. 2, but with the addition of shunt inductors to the signal reflecting elements of the cryogenic system 210.

[0068] The enhanced cryogenic system 610 includes at least three stages: a room temperature (RT) stage 220, a low temperature stage 240, and an ultra-low temperature stage 260. The RT stage 220 can operate at approximately 300 Kelvin and may be interchangeably referred to as the initial stage of the cryogenic system 210. The low temperature stage 240 can operate at approximately 3 Kelvin and may be interchangeably referred to as the middle stage of the cryogenic system 210. The ultra-low temperature stage 260 can operate at approximately 220 milliKelvin and may be interchangeably referred to as the final stage of the cryogenic system 210. The ultra-low temperature stage 260 can house a set of quantum devices 262. The set of quantum devices 262 can include a set of qubits, a set of quantum logic gates, a set of qubit couplers (e.g., employable as quantum gates), etc. For example, the set of quantum devices can include the plurality of qubits 120, the two-dimensional grid 122, and / or the qubit coupler 124 of FIG. 1B.

[0069] The enhanced cryogenic system 610 may further include a first signal line 614 (e.g., a control signal line), a second signal line 624, and a ground line 216 of FIG. 2. As shown in FIG. 2, the first signal line 214 may extend from the RT stage 220 into the cold stage 240 and back to the RT stage 220. As also shown in FIG. 6, the second signal line 624 may extend from the cryogenic stage 260 into the cold stage 240 and back to the cryogenic stage 260. The first signal line 614 and the ground line 616 may be electrically coupled (at the RT stage 220) through a first resistive element 626 disposed in the RT stage 220. The second signal line 624 may be electrically coupled to ground (e.g., which may be, but is not required to be, the ground line 216) through a second resistive element 664 disposed in the cryogenic stage 260. The first signal line 614 and the second signal line 624 may be electrically coupled at the cold stage 240 via a directional coupler 642 and a shunt inductor 646. The ground line 216 and the second resistive element 264 may be electrically coupled to electrical ground.

[0070] The combination of directional coupler 642 and shunt inductor 644 may function as a signal reflecting element of cold stage 240 and to electrically couple first signal line 214 with second signal line 224. That is, the combination of directional coupler 642 and shunt inductor 644 may reflect a portion of input signal 612 (e.g., return signal 622) and transmit the remaining portion of the input signal (e.g., output signal 618) to second signal line 624. The combination of directional coupler 642 and shunt inductor 644 may function as a signal “splitter” element that splits input signal 612 into return signal 622 and output signal 618 through partial reflection of input signal 612. Return signal 622 may be referred to as a reflected signal component (e.g., a first signal component), and output signal 618 may be referred to as a transmitted signal component (e.g., a second signal component). Thus, through partial reflection, the directional coupler 642 and the shunt inductor 644 (e.g., a signal reflecting element) are configured to split the input signal 612 into a reflected signal component (e.g., reflected by the signal reflecting element) and a transmitted signal component (e.g., transmitted by the signal reflecting element). The shunt inductor 646 can act as a low-pass filter for the transmitted output signal 618.

[0071] By splitting the input signal 612 into a return signal 622 and an output signal 618, the combination of the directional coupler 642 and the shunt inductor 644 may function to attenuate the input signal 612. In some embodiments, the combination of the directional coupler 642 and the shunt inductor 644 attenuates the input signal 612 by approximately 20 dB. The attenuation achieved via the combination of the directional coupler 642 and the shunt inductor 644 is “reflective” attenuation, rather than absorptive attenuation, as shown in FIG. 1A . Thus, the signal attenuation achieved in the cold stage 240 does not generate heat in the cold stage 240, as opposed to heat generation in the cold stage 40 of FIG. 1A . The return signal 622 is returned to the RT stage 220 via the first signal line 614, and the output signal 618 is provided via the second signal line 224 to the ultra-low temperature stage 260 and one or more quantum devices in the set of quantum devices 262.

[0072] The first resistive element 626 can function as a heat sink and can be a heat sink resistor (e.g., R heat ) The heat radiated by the first resistive element 626 is radiated to the RT stage 220. Because the RT stage 620 is at approximately 300 Kelvin, the RT stage 220 can act as a heat sink for the heat radiated by the first resistive element 626. In some embodiments, the resistance of the first resistive element 626 can be approximately 50 ohms. The second resistive element 664 can "bleed" the output signal 618 to the cryogenic environment. Thus, the second resistive element 664 can act as a signal and / or heat radiating resistor (e.g., R emit ) The second resistive element 664 may function to thermalize the portion of the second signal line 624 at the output signal 618 and / or the ultra-low temperature stage 260. Because the output signal 618 is significantly attenuated, the amount of heat stored at the ultra-low temperature stage 260 is significantly attenuated. In some embodiments, the resistance of the second resistive element 664 may be approximately 50 ohms.

[0073] Referring to FIG. 6 , the low-temperature stage 240 may include a first cryogenic chamber, and the cryogenic stage 260 may include a second cryogenic chamber. Accordingly, one or more quantum devices (e.g., qubits, qubit couplers, quantum logic gates, etc.) of the set of quantum devices 262 may be disposed within the second cryogenic chamber. In at least one embodiment, the second cryogenic chamber may be nested within the first cryogenic chamber. The RT stage 220 may or may not include a third cryogenic chamber. That is, the RT stage 220 may be outside any cryogenic chamber. The RT stage may include an external environment that is external to each of the first and second cryogenic chambers. A signal reflection element (e.g., a combination of a directional coupler 642 and a shunt inductor 644) is disposed within the first cryogenic chamber. The signal reflecting element is configured to split the input signal 612 into a first signal component (e.g., return signal 622) and a second signal component (e.g., output signal 618) due to partial reflection of the input signal 612. Due to partial reflection of the input signal 612, the first signal component of the input signal 612 is reflected by the signal reflecting element and the second signal component of the input signal 612 is transmitted by the signal reflecting element. The partial reflection of the input signal 612 attenuates the input signal 612, and the second signal component (e.g., output signal 618) is an attenuated version of the input signal 612. The attenuation of the input signal 612 may be approximately 20 decibels (dB). The input signal 212 may be a radio frequency (RF) signal.

[0074] The first signal line 614 may be configured to provide an input signal 612 from an external environment (e.g., the RT stage 220) to the signal reflecting element. As shown in FIG. 6, the input signal 612 may originate in the external environment. The first signal line 614 is further configured to provide a reflected first signal component from the signal reflecting element to the external environment. The second signal line 624 is configured to provide a transmitted second signal component from the signal reflecting element to a quantum device disposed in a second cryogenic chamber. The signal reflecting element electrically couples the first signal line 614 to the second signal line 624 such that the second signal component transmitted by the signal reflecting element is transmitted to the second signal line 624 via the signal reflecting element.

[0075] A ground line 616 may pass through the external environment, the first cryogenic chamber, and the second cryogenic chamber. As shown in FIG. 6 , the ground line 216 may be electrically coupled to electrical ground. A resistive element (e.g., a first resistive element 626) may be disposed in the external environment. The first resistive element 226 couples the first signal line 614 to electrical ground so that heat associated with the energy of the first signal component (e.g., the return signal 622) is dissipated to the external environment. Another resistive element (e.g., a second resistive element 664) may be disposed in the second cryogenic chamber. The second resistive element 664 couples the second signal line 624 to electrical ground so that the second signal component (e.g., the output signal 618) is at least partially thermalized in the second cryogenic chamber.

[0076] The first signal line 614 may include a first portion that carries the input signal 612 from the external environment to the signal reflecting element. The first signal line 614 may further include a second portion that carries a first signal component (e.g., return signal 622) from the signal reflecting element to the external environment. The first and second portions of the first signal line 614 may be non-contiguous portions such that the input signal 612 and the first signal component are carried by non-contiguous portions of the first signal line 614.

[0077] Implementations of the digital, classical, and / or quantum subject matter, and digital functional operations and quantum operations described herein may be implemented in digital electronic circuitry, suitable quantum circuitry, or more generally, in a quantum computing system, in tangibly embodied digital and / or quantum computer software or firmware, in digital and / or quantum computing hardware including the structures disclosed herein and their equivalents, or in one or more combinations thereof. The term "quantum computing system" may include, but is not limited to, a quantum computer / computing system, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0078] Implementations of the digital, classical, and / or quantum subject matter, and digital functional operations and quantum operations described herein may be implemented in digital electronic circuitry, suitable quantum circuitry, or more generally, in a quantum computing system, in tangibly embodied digital and / or quantum computer software or firmware, in digital and / or quantum computing hardware including the structures disclosed herein and their equivalents, or in one or more combinations thereof. The term "quantum computing system" may include, but is not limited to, a quantum computer / computing system, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0079] Embodiments of the digital and / or quantum subject matter described herein can be implemented as one or more digital and / or quantum computer programs, i.e., as one or more modules of digital and / or quantum computer program instructions encoded on a tangible, non-transitory storage medium for execution by or to control the operation of a data processing apparatus. The digital and / or quantum computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubit structures, or a combination of one or more thereof. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) capable of encoding digital and / or quantum information, generated to encode the digital and / or quantum information for transmission to a suitable receiver device for execution by a data processing apparatus.

[0080] The terms quantum information and quantum data refer to information or data conveyed by, held by, or stored within a quantum system, with the smallest nontrivial system being a qubit, i.e., a system defining a unit of quantum information. The term "qubit" is understood to encompass all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems may include, for example, multi-level systems having two or more levels. By way of example, such systems may include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis state is identified with a ground state and a first excited state, although it is understood that other setups are possible in which the computational state is identified with a higher-level excited state (e.g., a qubit).

[0081] The term "data processing apparatus" refers to digital and / or quantum data processing hardware and encompasses all types of apparatus, devices, and machines for processing digital and / or quantum data, including, by way of example, a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, or multiple digital and quantum processors or computers, as well as combinations thereof. An apparatus may also be or include special-purpose logic circuits, such as FPGAs (field-programmable gate arrays), ASICs (application-specific integrated circuits), or quantum simulators, i.e., quantum data processing apparatuses designed to simulate or generate information about specific quantum systems. In particular, quantum simulators are special-purpose quantum computers that do not have the ability to perform universal quantum computations. In addition to hardware, an apparatus may optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or one or more combinations thereof.

[0082] A digital or classical computer program may be referred to as or described as a program, software, software application, module, software module, script, or code, and may be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program may be referred to as a program, software, software application, module, software module, script, or code, and may be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and may be converted to or written in a suitable quantum programming language, such as QCL, Quipper, Cirq, etc.

[0083] A digital and / or quantum computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file holding other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program, or in multiple linked files, e.g., files storing one or more modules, subprograms, or portions of code. A digital and / or quantum computer program can be deployed to run on one digital or quantum computer, or on multiple digital and / or quantum computers located at one location, or on multiple digital and / or quantum computers distributed at multiple locations and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network that can transmit quantum data using quantum systems, e.g., qubits. While digital data communication networks generally cannot transmit quantum data, quantum data communication networks can transmit both quantum data and digital data.

[0084] The processes and logic flows described herein may be implemented by one or more programmable digital and / or quantum computers operating on one or more digital and / or quantum processors, as appropriate, executing one or more digital and / or quantum computer programs that perform functions by performing operations on input digital and quantum data to generate output. The processes and logic flows may also be implemented as special purpose logic circuitry, e.g., FPGAs or ASICs, or as quantum simulators, or by a combination of special purpose logic circuitry or quantum simulators with one or more programmed digital and / or quantum computers.

[0085] One or more digital and / or quantum computers or processors are "configured" or "operable" to perform a particular operation or action means that the system has installed thereon software, firmware, hardware, or a combination thereof that, during operation, causes the system to perform the operation or action. One or more digital and / or quantum computer programs are configured to perform a particular operation or action means that the one or more programs contain instructions that, when executed by a digital and / or quantum data processing device, cause the device to perform the operation or action. A quantum computer may receive instructions from a digital computer that, when executed by a quantum computing device, cause the device to perform an operation or action.

[0086] A digital and / or quantum computer suitable for executing a digital and / or quantum computer program may be based on a general-purpose or a dedicated digital and / or quantum microprocessor, or both, or any other kind of central digital and / or quantum processing unit. Typically, the central digital and / or quantum processing unit receives instructions and digital and / or quantum data from a read-only memory, a random access memory, or a quantum system suitable for transmitting quantum data, e.g., photons, or a combination thereof.

[0087] Some exemplary elements of a digital and / or quantum computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and memory may be supplemented by or incorporated into special-purpose logic circuitry or a quantum simulator. Generally, a digital and / or quantum computer includes one or more mass storage devices for storing digital and / or quantum data, such as, for example, magnetic, magneto-optical, optical disks, or quantum systems suitable for storing quantum information, or is operably coupled to receive digital and / or quantum data therefrom, transfer digital and / or quantum data thereto, or both. However, a digital and / or quantum computer need not have such devices.

[0088] Digital and / or quantum computer-readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include, by way of example, all forms of non-volatile digital and / or quantum memories, media, and memory devices, including semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices, magnetic disks, e.g., internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks, and quantum systems, e.g., trapped atoms or electrons. Quantum memory is understood to be a device capable of long-term storage of quantum data with high fidelity and efficiency, such as, for example, a light-matter interface where light is used for transmission and matter is used for storage and preservation of quantum properties of the quantum data, such as superposition or quantum coherence.

[0089] Control of the various systems described herein, or portions thereof, may be implemented in a digital and / or quantum computer program product stored on one or more tangible, non-transitory, machine-readable storage media and including instructions executable on one or more digital and / or quantum processing devices. The systems described herein, or portions thereof, may each be implemented as an apparatus, method, or electronic system, which may include one or more digital and / or quantum processing devices and memory for storing executable instructions for performing the operations described herein.

[0090] While this specification contains many details of specific embodiments, these should not be construed as limiting the scope of what may be claimed, but rather as descriptions of features that may be inherent in particular embodiments. Certain features described herein in the context of individual embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, while features may be described above as functioning in a particular combination and may initially be claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0091] Similarly, while operations are shown in the figures in a particular order, this should not be understood as requiring such operations to be performed in the particular order or sequence shown, or that all of the illustrated operations be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the program components and systems described above may generally be integrated together in a single software product or packaged in multiple software products.

[0092] Specific implementations of the present subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still produce desirable results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. 1. A quantum computing system, comprising: a first cryogenic chamber; a signal reflecting element disposed within the first cryogenic chamber, the signal reflecting element configured to split the input signal into the first signal component and the second signal component by partial reflection of the input signal, causing a first signal component of the input signal to be reflected by the signal reflecting element and a second signal component of the input signal to be transmitted by the signal reflecting element; and a second cryogenic chamber; a quantum device disposed within the second cryogenic chamber; a first signal line configured to provide the input signal from an external environment to the signal reflecting element and to provide the reflected first signal component from the signal reflecting element to the external environment, the external environment being external to each of the first and second cryogenic chambers; a second signal line configured to provide the transmitted second signal component from the signal reflecting element to the quantum device disposed in the second cryogenic chamber, the signal reflecting element electrically coupling the first signal line to the second signal line such that the second signal component transmitted by the signal reflecting element is transmitted to the second signal line via the signal reflecting element; and A quantum computing system comprising:

2. 10. The quantum computing system of claim 1, wherein the signal reflecting element comprises a directional coupler and the input signal is an alternating current (AC) signal.

3. 10. The quantum computing system of claim 1, wherein the first cryogenic chamber is included in an intermediate stage of a cryogenic system of the quantum computing system and operates at a temperature of about 3 Kelvin.

4. 10. The quantum computing system of claim 1, wherein the second cryogenic chamber is included in an ultra-low temperature stage of a cryogenic system of the quantum computing system and operates at a temperature of about 20 millikelvin or less.

5. 10. The quantum computing system of claim 1, wherein the input signal originates in the external environment, and the external environment is greater than or equal to about 300 Kelvin.

6. 10. The quantum computing system of claim 1, further comprising a ground wire passing through the external environment, the first cryogenic chamber, and the second cryogenic chamber, the ground wire electrically coupled to an electrical ground.

7. 10. The quantum computing system of claim 1, further comprising a resistive element disposed in the external environment coupling the first signal line to an electrical ground such that heat associated with the energy of the first signal component is dissipated into the external environment.

8. 10. The quantum computing system of claim 1, further comprising a resistive element disposed in the second cryogenic chamber coupling the second signal line to an electrical ground such that the second signal component is at least partially thermalized in the second cryogenic chamber.

9. 10. The quantum computing system of claim 1, wherein the partial reflection of the input signal attenuates the input signal, and the second signal component is an attenuated version of the input signal.

10. 10. The quantum computing system of claim 1, wherein the attenuated signal is attenuated relative to the input signal by about 20 decibels (dB) or more.

11. 10. The quantum computing system of claim 1, wherein the signal reflecting element comprises a resistive element and the input signal is a direct current (DC) signal.

12. 10. The quantum computing system of claim 1, wherein the signal reflecting element comprises a circulator element and the input signal is an alternating current (AC) signal.

13. 2. The quantum computing system of claim 1, wherein the first signal line includes a first portion configured to transmit the input signal from the external environment to the signal reflecting element and a second portion, non-contiguous with the first portion, configured to transmit the first signal component from the signal reflecting element to the external environment, the input signal and the first signal component being transmitted by the non-contiguous portions of the first signal line.

14. The quantum computing system of claim 13 , wherein the signal reflecting element comprises a resistive element.

15. 14. The quantum computing system of claim 13, wherein the signal reflecting element comprises a directional coupler and the input signal is a radio frequency (RF) signal.

16. 16. The quantum computing system of claim 15, wherein the signal reflecting element further comprises a shunt inductor that acts as a low pass filter for the RF signal.

17. 2. The quantum computing system of claim 1, wherein the first signal line includes a common portion configured to transmit the input signal from the external environment to the signal reflecting element and to transmit the first signal component from the signal reflecting element to the external environment, such that both the input signal and the first signal component are transmitted by the common portion of the first signal line.

18. The quantum computing system of claim 1 , wherein the quantum device is a qubit.

19. a first cryogenic chamber; a signal reflecting element disposed within the first cryogenic chamber, the signal reflecting element configured to split the input signal into the first signal component and the second signal component by partial reflection of the input signal, causing a first signal component of the input signal to be reflected by the signal reflecting element and a second signal component of the input signal to be transmitted by the signal reflecting element; and a second cryogenic chamber; a first signal line configured to provide the input signal from an external environment to the signal reflecting element and to provide the reflected first signal component from the signal reflecting element to the external environment, the external environment being external to each of the first and second cryogenic chambers; a second signal line configured to provide the transmitted second signal component from the signal reflecting element to the second cryogenic chamber, the signal reflecting element electrically coupling the first signal line to the second signal line such that the second signal component transmitted by the signal reflecting element is transmitted to the second signal line via the signal reflecting element; and A cryogenic system comprising:

20. 1. A computing system comprising: a signal reflecting element configured to split an input signal into the first signal component and the second signal component by partial reflection of the input signal, the first signal component being reflected by the signal reflecting element and the second signal component being transmitted by the signal reflecting element; an information encoding device; a first signal line configured to provide the input signal to the signal reflecting element and to provide the reflected first signal component from the signal reflecting element to a room temperature (RT) environment; a second signal line configured to supply the transmitted second signal component from the signal reflecting element to the information encoding device; A computing system comprising:

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