Nonlinear Channel

Abstract

A finFET is presented that includes a nonlinear channel. The nonlinear channel includes one or more arcuate, curved, segmented, or the like sidewalls that define a channel width and a channel length. The nonlinear channel provides a relatively increased channel length compared to a linear fin oriented perpendicular to the gate width. Thus, the channel length of the nonlinear channel can be relatively increased within the boundaries of the gate. In other words, the relatively increased channel or fin length within the footprint of the gate can limit short-channel effects by suppressing the electric field along the nonlinear channel.

Description

[Background technology]

[0001] The present disclosure relates to fabrication methods and resulting structures for semiconductor devices. More particularly, the present disclosure relates to fabrication methods and resulting structures for integrated circuit (IC) devices, such as wafers, dies, processors, etc., that include transistors, such as finFETs, having nonlinear channels.

[0002] Semiconductor devices and IC devices are becoming more prevalent in many products, especially as their cost and size continue to decrease. There is a continuing desire to reduce the size of structural features and / or provide a greater quantity of structural features for a given device size. Miniaturization generally enables increased performance at lower power levels and lower cost. Current technology is at or approaching atomic-level scaling of several microdevices, such as logic gates, field-effect transistors (FETs), capacitors, and the like.

[0003] For example, when the fin width of a finFET is scaled down to or reaches 5 nanometers (nm) (approximately the 3 nm node), the contacted poly pitch (CPP) reaches a CPP limit of approximately 45 nm when the metal pitch is 22 nm. CPP is the distance separating the centers of adjacent gate contacts. The CPP limit may be driven by the desire to minimize or eliminate short channel effects, by the desire to minimize the increase in parasitic capacitance caused by smaller gate spacer widths, and / or by shrinking the space for source and / or drain contacts.

[0004] To achieve the expected finFET function, typically, the electric field of the gate should control the channel, and the electric field of the drain should have a smaller effect on the channel. If this is not the case, the finFET will exhibit a set of unwanted effects called short-channel effects. One way to reduce the tendency for short-channel effects is to increase the gate length (Lg). Summary of the Invention

[0005] In one embodiment of the present disclosure, a finFET is presented. The finFET includes a nonlinear channel beneath a gate. The nonlinear channel has a first nonlinear sidewall. The first nonlinear sidewall is nonlinear (i.e., not linear), and the nonlinear sidewall causes a relative increase in channel length within the boundaries of the gate footprint. This increased channel length is longer than an associated linear fin that is linear across the gate length. In other words, the relative increase in channel length can limit short-channel effects by suppressing the electric field along the nonlinear channel.

[0006] In one example, the nonlinear channel may further include a second nonlinear sidewall opposing the first nonlinear sidewall. In one example, the first nonlinear sidewall is a first curved nonlinear sidewall and / or the second nonlinear sidewall is a second curved nonlinear sidewall. In one example, the first curved nonlinear sidewall and the second curved nonlinear sidewall are parallel. In one example, the first curved nonlinear sidewall and the second curved nonlinear sidewall share the same central axis of curvature.

[0007] In one example, the finFET further comprises a source in physical contact with a first end face of the nonlinear channel and a drain in physical contact with an opposing second end face of the nonlinear channel. In one example, the finFET further comprises a gate spacer around the gate. In one example, the channel length of the nonlinear channel is longer than the gate length of the gate.

[0008] In one example, the first nonlinear channel has a first nonlinear sidewall and a second nonlinear sidewall opposite the first nonlinear sidewall, hi one example, the first nonlinear sidewall is a first curved sidewall and the second nonlinear sidewall is a second curved sidewall.

[0009] In one example, the second nonlinear channel has a third nonlinear sidewall and a fourth nonlinear sidewall opposite the first nonlinear sidewall, hi one example, the third nonlinear sidewall is a third curved sidewall and the fourth nonlinear sidewall is a fourth curved sidewall.

[0010] In one example, the first curved sidewall and the second curved sidewall are parallel, and the third curved sidewall and the fourth curved sidewall are parallel. In one example, the first curved sidewall, the second curved sidewall, the third curved sidewall, and the fourth curved sidewall share the same central axis of curvature.

[0011] In one example, the finFET further comprises a gate spacer around the gate. In one example, the channel length of the first nonlinear channel is longer than the gate length of the gate. In another example, the channel length of the second nonlinear channel is longer than the gate length.

[0012] In another embodiment of the present disclosure, a finFET fabrication method is presented, comprising: forming a nonlinear fin on a semiconductor substrate; forming a sacrificial gate on the nonlinear fin; forming gate spacers on each sidewall of the sacrificial gate; forming a source in physical contact with a first end face of the nonlinear fin; forming a drain in physical contact with a second end face of the nonlinear fin; removing the sacrificial gate between the gate spacers; and forming a replacement gate between the gate spacers. The nonlinear fin is a nonlinear channel for the finFET, and the channel length of the nonlinear channel is longer than the replacement gate length.

[0013] This nonlinear channel length is relatively long compared to the linear fin. Therefore, the nonlinear channel length can be relatively increased within the boundaries of the footprint of the replacement gate (e.g., gate length (Lg) x gate width). In other words, by relatively increasing the channel or fin length within the footprint of the replacement gate, the electric field along the nonlinear channel can be suppressed, thereby limiting short channel effects.

[0014] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure. [Brief explanation of the drawings]

[0015] The drawings included in this application are incorporated into and form a part of this specification. They illustrate embodiments of the present disclosure and, together with the description, explain the principles of the disclosure. The drawings are merely illustrative of particular embodiments and do not limit the disclosure.

[0016] [Figure 1] 1A-1D are cross-sectional and top views of a semiconductor device including a nonlinear channel according to an embodiment of the present disclosure.

[0017] [Figure 2] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure. [Figure 3] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure. [Figure 4] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure. [Figure 5] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure. [Figure 6] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure. [Figure 7] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure. [Figure 8] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure. [Figure 9] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure.

[0018] [Figure 10] 1A-1C illustrate a method of fabricating a semiconductor device including a nonlinear channel according to an embodiment of the present disclosure.

[0019] [Figure 11] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure. [Figure 12] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure. [Figure 13] 1A-1C are cross-sectional views of a semiconductor device including a nonlinear channel at different fabrication stages in a fabrication process according to an embodiment of the present disclosure.

[0020] [Figure 14] 1A-1C illustrate a method of fabricating a semiconductor device including a nonlinear channel according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0021] To reduce the tendency for short channel effects, the gate length (Lg) has typically been increased, but as CPPs scale down, there is less space to increase the gate dimensions.

[0022] Aspects of the present disclosure can limit short-channel effects in finFETs and may enable further scaling of finFETs. More specifically, a finFET is provided that includes a nonlinear fin. The nonlinear fin has a longer channel length compared to an associated linear fin (e.g., a conventional finFET having a vertically straight fin or channel across the gate length (Lg)). The channel length of the nonlinear fin can be obtained without scaling up the geometry of other finFET features, such as the gate length (Lg), gate spacer width, or the like. Thus, the geometry of a finFET that includes a nonlinear fin can be further scaled while taking advantage of the relatively increased channel length of the nonlinear fin. Because the electric field is suppressed along the longer channel length, increasing the channel length suppresses short-channel effects.

[0023] The flowcharts and cross-sectional views in the figures illustrate methods of fabricating IC devices including nonlinear fins according to various embodiments of the present disclosure. In some alternative implementations, the fabrication steps may occur in a different order than those depicted in the figures, and additional fabrication steps may be implemented between the steps depicted in the figures. Also, any of the layered structures depicted in the figures may include multiple sub-layers.

[0024] Various embodiments of the present disclosure are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of the present disclosure. Note that in the following description and drawings, various connections and relationships (e.g., above, below, adjacent, etc.) between elements are described. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present disclosure is not intended to be limiting in this respect. Thus, coupling of entities may refer to either direct or indirect coupling, and relationships between entities may be direct or indirect relationships. As an example of an indirect relationship, a reference herein to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") exist between layer "A" and layer "B," so long as the relevant properties and functions of layer "A" and layer "B" are not substantially altered by the intermediate layers.

[0025] The following definitions and abbreviations will be used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to include a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements but may include other elements that are not expressly listed or that are inherent to such composition, mixture, process, method, article, or device.

[0026] Hereinafter, for purposes of description, the terms “above,” “below,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives refer to the described structures and methods as oriented within the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is on a second element, such as a second structure, and an intervening element, such as an interface structure, may be present between the first and second elements. The term “directly contacting” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements. Note that the term “selective,” for example, as in “a first element selective to a second element,” means that the first element can be etched and the second element can act as an etch stop.

[0027] For the sake of brevity, conventional techniques associated with semiconductor device and / or IC fabrication may or may not be described in detail herein. Also, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. The various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will be mentioned only briefly herein or omitted entirely without providing details of the well-known processes.

[0028] Generally, the various processes used to form semiconductor devices, such as microchips that will be packaged into ICs, fall into four general categories: material deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from the wafer. Examples include etching processes (either wet or dry) and chemical-mechanical planarization (CMP), and the like. Materials, both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.), are used to connect and separate other wiring or device components. Semiconductor lithography is the formation of a three-dimensional relief image or pattern in an underlying material for later transfer of the pattern into the material. In semiconductor lithography, the pattern is formed by a light-sensitive polymer called a photoresist.

[0029] Referring now to the drawings, in which like numerals represent the same or similar elements, and initially to FIG. 1 , which illustrates a cross-sectional view and a top view of a semiconductor device 100 including a nonlinear channel 110 according to an embodiment of the present disclosure. The term “nonlinear channel” is defined herein to be a channel including opposing sidewalls (i.e., oppositely facing sidewalls) that define a nonlinear fin length that is not parallel to an X cross-section generally orthogonal to an associated gate width, as shown. The term “nonlinear” is defined herein to be non-linear. Thus, a nonlinear fin length will include at least one non-linear sidewall among the opposing sidewalls that define the fin length. For example, the nonlinear fin length may include one or more curved sidewalls that define the fin length. For example, the nonlinear channel may include one or more curved sidewalls that define the fin length, and the nonlinear channel may include a first set of straight, segmented sidewalls and a second set of straight, segmented sidewalls that are angled relative to the first set of segmented sidewalls (e.g., a V-shaped nonlinear channel, or the like).

[0030] The semiconductor device 100 may further include a semiconductor substrate 102, one or more isolation regions 112, one or more source / drains 150, one or more replacement gates 190, one or more gate spacers 180, and one or more interlayer dielectrics 195.

[0031] The nonlinear channel 110 may include arcuate, curved, segmented, or the like sidewalls that define a fin or channel width 181 and / or a fin or channel length 185. Specifically, as shown, the nonlinear channel 110 may include arcuate or curved sidewalls that define a channel or fin length 185. The nonlinear channel 110 generally has a longer channel or fin length 185 compared to a conventional linear fin (i.e., a fin that is parallel to the X-plane as shown). Thus, the channel or fin length 185 of the nonlinear channel 110 can be relatively increased within the boundaries of the footprint or replacement gate structure (e.g., the gate length (Lg) x gate width of the replacement gate 190). In other words, the fin or channel length 185 of the nonlinear channel 110 can be relatively increased without also increasing the gate length (Lg) 183 of the replacement gate 190. Although shown with arcuate or curved sidewalls, the nonlinear channel 110 may include V-shaped sidewalls, hexagonal sidewalls, or other segmented sidewalls that define the fin length.

[0032] 2 illustrates a top view of a semiconductor device 100 that will include a nonlinear channel 110 at another stage of the fabrication process, in which a hard mask (not shown) and one or more fin mandrels 104 are formed on a semiconductor substrate 102, according to an embodiment of the present disclosure.

[0033] The semiconductor substrate 102 comprises a semiconductor material, including, but not limited to, silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon germanium carbide (SiGeC), carbon-doped silicon germanium (SiGe:C), III-V, II-V compound semiconductors, or other similar semiconductors. Additionally, multiple layers of semiconductor material may be used as the semiconductor material of the substrate. The semiconductor substrate 102 may be a bulk substrate, as shown in this example, or may be a semiconductor-on-insulator substrate, such as, but not limited to, a silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), or III-V-on-insulator substrate, including a buried insulating layer, for example, a buried oxide or nitride layer.

[0034] A hard mask (not shown) including a nitride material, such as, but not necessarily limited to, silicon nitride (SiN) or titanium nitride (TiN), may be formed on the substrate 102. The hard mask may be deposited using deposition techniques including, but not necessarily limited to, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), radio-frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular layer deposition (MLD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), and / or sputtering. In some embodiments, a planarization process, such as chemical mechanical planarization (CMP), may be used to remove excess hard mask material. The height of the hard mask may be in the range of 20 nm to 100 nm, but is not necessarily limited to this.

[0035] The one or more fin mandrels 104, including but not limited to amorphous silicon (a-Si), amorphous carbon, polycrystalline silicon, polycrystalline silicon germanium, amorphous silicon germanium, polycrystalline germanium, and / or amorphous germanium, are formed on the hard mask and spaced apart from one another. Formation of the mandrels 104 can be performed by various patterning techniques, including but not limited to, for example, lithographic patterning followed by directional etching and / or a sidewall image transfer (SIT) process. In some embodiments, the process includes forming the one or more fin mandrels 104 using lithography followed by directional etching (e.g., reactive ion etching (ME)).

[0036] In one example, the fin mandrel 104 may be a circular cylinder and may have circular sidewalls with one central axis positioned in and out of the page. In this example, the nonlinear channels 110 fabricated associated therewith may also have circular sidewalls that define the fin width. The sidewalls associated with the nonlinear channels may have the same central axis as the fin mandrel. In another example, as shown, each mandrel 104 may be an oblong cylinder and may have arc-shaped sidewalls with two focal axes positioned in and out of the page. In this example, the nonlinear channels 110 fabricated associated therewith may also have elliptical arc-shaped sidewalls that define the fin length. In another example, each mandrel 104 may be a diamond-shaped cylinder and may have segmented sidewalls. In this example, the nonlinear channels 110 fabricated associated therewith may also have V-shaped segmented sidewalls that define the fin width. In another example, each mandrel 104 may be a diamond-shaped cylinder and may have segmented sidewalls. In this example, the nonlinear channel 110 fabricated associated therewith may also have V-shaped segmented sidewalls that define the fin width. In another example, each mandrel 104 may be a polygonal prism (such as a hexagonal prism) with one central bisector axis leading into and out of the page and may have associated segmented sidewalls. In this example, the nonlinear channel 110 fabricated associated therewith may also have polygonal segmented sidewalls that define the fin width.

[0037] 3 illustrates a top view of a semiconductor device 100 that will include a nonlinear channel 110 at another stage of the fabrication process, in which sidewall image transfer (SIT) spacers 106 are formed on the nonlinear sidewalls of the fin mandrels 104 and on the top surface of the hard mask, according to an embodiment of the present disclosure.

[0038] The SIT spacers 106 may be a conformal film and may be deposited followed by an etch-back process (e.g., ME). The deposition of material onto the mandrels 104 may also be referred to as spacer formation around the vertical sides of each mandrel 104. The material of the SIT spacers 106 may include, but is not limited to, silicon oxide (SiO ) formed by low-pressure chemical vapor deposition (LPCVD), PECVD, sub-atmospheric chemical vapor deposition (SACVD), rapid thermal chemical vapor deposition (RTCVD), in-situ radical-assisted deposition, high temperature oxide (HTO) deposition, low temperature oxide (LTO) deposition, ozone / TEOS deposition, limited reaction processing CVD (LRPCVD), and the like. x ) (where x is, for example, 2 for silicon dioxide (SiO2), or 1.99 or 2.01). Alternatively, some other dielectric material may be used as the material for the SIT spacers 106, such as SiOCN, SiCN, SiOC, etc. The height of the mandrels 104 and the corresponding SIT spacers 106 may be in the range of 30 nm to 100 nm, but is not necessarily limited thereto.

[0039] 4 shows top and cross-sectional views of a semiconductor device 100 including a nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure, in which one or more mandrels 104 have been removed, one or more nonlinear channels 110 have been formed, and one or more isolation regions 112 have been formed.

[0040] The nonlinear channel 110 may be formed by patterning a portion of the semiconductor substrate 102 into the nonlinear channel 110. The nonlinear channel 110 may be formed by removing the mandrels 104 to form an opening. The opening exposes a portion of the top surface of the hard mask and is formed using an etching process, such as, for example, plasma dry etching.

[0041] The nonlinear channel 110 is formed by patterning a portion of the semiconductor substrate 102 into the nonlinear channel 110. Selective removal of the mandrels 104 leaves SIT spacers 106 on the hard mask. The hard mask is patterned into a plurality of patterned hard mask portions 107 corresponding to the locations of the overlying SIT spacers 106, such that the underlying patterned hard mask portions 107 have the same shape as the overlying SIT spacers 106. More specifically, exposed portions of the hard mask not under the SIT spacers 106 (e.g., not masked by the SIT spacers 106) are removed using a directional etching process, including, for example, RIE, using CF, CHF, or other chemistries known to etch, for example, silicon nitride selectively with respect to other materials. Patterning the hard mask into a plurality of spaced-apart patterned hard mask portions 107 can be performed using, for example, SAMP techniques, including, but not limited to, SADP, SAQP, and SAOP.

[0042] Following removal of the SIT spacers 106, the patterned hard mask portions 107 are used as a mask to remove exposed portions of the semiconductor substrate 102 not covered by the hard mask portions 107 to a depth d1 (depending on the design) using a substrate etch. The substrate etch transfers the pattern of the hard mask portions 107 into the semiconductor substrate 102 to form the nonlinear channel 110, which has the same shape as the overlying hard mask portions 107. According to one embodiment, the semiconductor substrate 102, which comprises a semiconductor material such as Si, SiGe, SiC, Si:C, SiGeC, SiGe:C, III-V, II-V compound semiconductors, or other similar semiconductors, can be selectively etched relative to the hard mask portions 107 using, for example, a silicon RIE process.

[0043] Although embodiments of the present disclosure describe the channels as fins, embodiments are not necessarily limited to fin channels, but may include nanowire channels, or the like. Additionally, for ease of explanation, a finite number of nonlinear channels 110 are shown in the figures, although more or fewer nonlinear channels 110 may be formed.

[0044] After forming the nonlinear channel 110, the hard mask portions 107 may be removed and / or isolation regions 112 (e.g., shallow trench isolation (STI) regions) may be formed. After selectively removing portions of the semiconductor substrate 102 to a depth d1, a plurality of trenches or patterns may be formed in the semiconductor substrate 102, for example, by a wet or dry etching process. xA dielectric material including LTO, HTO, flowable oxide (FOX), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or some other dielectric is deposited within the trench or pattern. To define the isolation region 112, the dielectric material may be deposited using a deposition technique including, but not necessarily limited to, CVD, plasma-enhanced CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering. As shown, the upper surface of the isolation region 112 is below the upper surface of the one or more nonlinear channels 110.

[0045] 5 shows top and cross-sectional views of a semiconductor device 100 including a nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure, in which one or more sacrificial gate structures are formed.

[0046] One or more sacrificial gate structures may be formed over and around one or more nonlinear channels 110 and over the isolation region 112. The sacrificial gate structures may include a gate liner (not shown), a sacrificial gate 113, and a sacrificial gate cap 114.

[0047] The sacrificial gate structure may be formed by first forming a gate liner layer (e.g., a dielectric, an oxide, or the like) over the isolation region 112 and over and around the one or more nonlinear channels 110. For example, the gate liner layer may be deposited on the upper surface of the isolation region 112, the sidewalls of the one or more nonlinear channels 110, the upper surface of the one or more nonlinear channels 110, or the like. The sacrificial gate structure may be further formed by subsequently forming a sacrificial gate layer (e.g., a dielectric, amorphous silicon, or the like) over the gate liner. The thickness of the sacrificial gate layer may be greater than the height of the one or more nonlinear channels 110.

[0048] The sacrificial gate structure 160 may be further formed by subsequently forming a gate cap layer on the sacrificial gate layer. The gate cap layer may be formed by depositing a mask material, such as a hard mask material. The gate cap layer may be composed of one or more layers of masking material to protect the sacrificial gate layer and / or other underlying materials during subsequent processing of the device 100. The gate cap layer may be formed of a gate mask material, such as silicon nitride, silicon oxide, a combination thereof, or the like.

[0049] The gate cap layer, the sacrificial gate layer, and the gate liner may each be patterned using lithography and etching processes to remove unwanted portions and retain desired portions, and the retained desired portions of the gate cap layer, the sacrificial gate layer, and the gate liner layer may form the gate liner, the sacrificial gate 113, and the sacrificial gate cap 114, respectively, of each of the one or more sacrificial gate structures.

[0050] Each sacrificial gate structure may be formed over a targeted region or area of ​​semiconductor device 100 to define the length of one or more transistors and to provide sacrificial material for subsequent processing to yield the targeted transistor structure. According to one example, each sacrificial gate structure may have a height between about 50 nm and about 200 nm, and a length between about 15 nm and about 200 nm.

[0051] 6 illustrates top and cross-sectional views of a semiconductor device 100 including a nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure, in which one or more gate spacers 180 are formed.

[0052] One or more gate spacers 180 may be formed on at least each lateral surface of the sacrificial gate structure, on and around the exposed portion of the nonlinear channel 110, and on the isolation region 112. Gate spacers 180 may further be formed on the end faces of the associated sacrificial gate structure. The gate spacers 180 may be formed by conformal deposition of a dielectric material such as silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or combinations thereof, or the like. Unwanted portions of the dielectric material may be removed by an anisotropic etching process. Desired portions of the dielectric material may be retained on the sidewalls of the sacrificial gate structure.

[0053] 7 illustrates top and cross-sectional views of semiconductor device 100 including nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure, where the portion of nonlinear channel 110 not covered by gate spacer 180 may be recessed or otherwise removed.

[0054] The nonlinear channels 110 may be recessed by a directional etch or the like to remove portions of the nonlinear channels 110 that are not covered by the gate spacers 180. The top surfaces of the isolation regions 112 may be used as an etch stop, and the gate spacers 180 may be retained. Subsequently, each end face 125 of the nonlinear channels 110 may be flush with the lateral surfaces 123 of the gate spacers 180. By trimming or removing portions of the nonlinear channels 110, one or more source / drain (S / D) openings 111 may be formed. One or more of the S / D openings 111 may be defined or bounded by the top surfaces of the isolation regions 112 and at least one or more opposing and facing end faces 125 of adjacent nonlinear channels 110. One or more of the S / D openings 111 may be further defined or bounded by opposing and facing respective sections of the lateral surfaces 123 of the gate spacers 180.

[0055] To clarify, there may be two separate patterned nonlinear channels 310 fabricated from one fin structure around one common mandrel. For example, as shown in the top view, the upper FET includes a first channel and a second channel that share the same central axis of curvature.

[0056] 8 illustrates top and cross-sectional views of semiconductor device 100 including nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure, in which S / D regions 150 are formed in one or more S / D openings 111, respectively.

[0057] S / D regions 150 may be formed by epitaxially growing source / drain epitaxial regions in S / D openings 111, for example, from exposed end surfaces 125 of one or more nonlinear channels 110. In some embodiments, S / D regions 150 are formed by in-situ doped epitaxial growth. In some embodiments, the epitaxial growth and / or deposition process may be selective to formation on semiconductor surfaces and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0058] Suitable n-type dopants include, but are not limited to, phosphorus (P), and suitable p-type dopants include, but are not limited to, boron (B). The use of an in-situ doping process is merely an example. For example, an ex-situ process may alternatively be employed to introduce dopants into the source and drain. Other doping techniques may be used to incorporate dopants into the lower source / drain regions. Dopant techniques include, but are not limited to, ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid-phase doping, solid-phase doping, in-situ epitaxy growth, or any suitable combination of these techniques. In a preferred embodiment, the S / D epitaxial growth conditions promote in-situ boron-doped SiGe for p-type transistors and phosphorus- or arsenic-doped silicon or Si:C for n-type transistors. The doping concentration in the S / D regions 150 may range from 1×10 19 cm −3 to 2×10 21 cm −3 , or preferably between 2×10 20 cm −3 and 7×10 20 cm −3 .

[0059] In particular implementations, S / D regions 150 may be grown such that their bottom surfaces contact isolation region 112 and their top surfaces are above the top surface of nonlinear channel 110. For clarity, as shown in the X-sectional view, a first S / D region 150 may be a source region for nonlinear channel 110, and a second S / D region 150 may be a drain region for nonlinear channel 110. Furthermore, as shown in the top view, two different S / D regions 150 grown from separate nonlinear channels 110 may effectively merge to form a single S / D region 150 that can function as a source or drain for the separate nonlinear channels 110.

[0060] 9 shows top and cross-sectional views of semiconductor device 100 including nonlinear channel 110 at another stage of the fabrication process according to an embodiment of the present disclosure, in which interlayer dielectric 195 is formed over isolation regions 112 and S / D regions 150, and sacrificial gate 113 is removed and replaced with replacement gate 190.

[0061] An interlayer dielectric 195 may be formed over one or more S / D regions 150 and over the top surface of isolation region 112. Interlayer dielectric 195 may be formed by depositing a dielectric material, such as silicon oxide, silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof, or the like, as a blanket layer over isolation region 112, S / D regions 150, and gate spacer 180. In one embodiment, interlayer dielectric 195 may be formed to a thickness over the top surface of semiconductor device 100, after which the top surface of sacrificial gate 113 may be exposed (e.g., sacrificial gate cap 114 has been removed by CMP) and planarized by chemical mechanical polishing (CMP) or etching so that the top surface of sacrificial interlayer dielectric 195 is coplanar with the top surfaces of gate spacers 180.

[0062] Once a portion of the sacrificial gate 113 is exposed, the sacrificial gate 113 is removed by etching. Removal of the sacrificial gate 113 may expose the nonlinear channel 110 between the gate spacers 180 previously associated with it, may expose the gate dielectric underneath, and / or the like.

[0063] A replacement gate structure is then formed in place of the removed sacrificial gate 113 between the gate spacers 180 and over and around the nonlinear channel 110. The replacement gate structure may include a gate dielectric (not shown) and a replacement gate 190. The gate dielectric is the gate dielectric associated with the replacement gate structure, or the subsequent gate dielectric if removed, which may include any suitable dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, high-k material, or any combination of these materials. The gate dielectric may be formed by any suitable deposition process or the like. In some embodiments, the gate dielectric has a thickness in the range of 1 nm to 5 nm, although smaller and larger thicknesses are also contemplated.

[0064] The replacement gate 190 may be made of doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), carbide), or the like. The conductive material may comprise any suitable conductive material, including, but not limited to, tantalum (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO), cobalt silicide (CoSi), nickel silicide (NiSi), transition metal aluminides (e.g., TiAl, ZrAl), TaC, TaMgC, carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0065] The replacement gate 190 may further include a dopant incorporated during or after deposition. In some embodiments, the replacement gate 190 may further include a work function setting layer (not shown) between the gate dielectric and the replacement gate 190. The work function setting layer may be a work function metal (WFM). The replacement gate 190 and the WFM may be formed by any suitable process, or any suitable combination of processes, including, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser-assisted deposition, chemical solution deposition, etc.

[0066] The replacement gate structure may be formed by first forming a gate dielectric layer between the gate spacers around the nonlinear channel 110 and on the top surface of the isolation region. The replacement gate structure may be further formed by subsequently forming a gate conductor layer on the gate dielectric layer. The gate conductor layer and the gate dielectric layer may be patterned using lithography and etching processes to remove unwanted portions and retain desired portions, respectively. The retained desired portions of the gate conductor layer and the gate dielectric layer may form the replacement gate dielectric layer and the replacement gate 190, respectively. CMP, an etching process, or another subtractive removal technique may remove the unwanted portions of the replacement gate structure such that the top surface of the replacement gate structure is coplanar with the top surface of the gate spacer 180, the interlayer dielectric 195, or the like. In some implementations, the replacement gate 190 may be recessed below the top surface of the semiconductor device 100, and a dielectric gate cap (not shown) may be formed on the recessed replacement gate 190.

[0067] To clarify, to achieve expected finFET functionality, the electric field of the replacement gate 190 of the semiconductor device 100 generally controls the nonlinear channel 110, while the electric field of the drain (e.g., one of the S / D regions 150) has a smaller effect on the nonlinear channel 110. The nonlinear channel 110 includes arcuate, curved, segmented, or the like sidewalls that define a nonlinear channel or fin width 181. As shown, the nonlinear channel or fin width 181 can be constant over a channel or fin length 185 below the replacement gate 190. The nonlinearity of the nonlinear channel 110 results in a relative increase in the channel or fin length 185 compared to a linear fin with the same fin width. Thus, the channel or fin length 185 of the nonlinear channel 110 can be relatively increased within the boundaries of the footprint of the replacement gate 190 (e.g., gate length (Lg) 183 × gate width). In other words, the relative increase in channel or fin length 185 within the footprint of replacement gate 190 may limit short channel effects by suppressing the electric field along nonlinear channel 110.

[0068] 10 illustrates a method 200 for fabricating a semiconductor device 100 including a nonlinear channel 110 according to an embodiment of the present disclosure. The method 200 begins at block 202 by forming one or more fin mandrels 104 and one or more SIT spacers 106 on a substrate 102. The method 200 continues at block 204 by removing the one or more fin mandrels 104 and patterning a fin including nonlinear sidewalls to effectively form the nonlinear channel 110 and to form an isolation region 112. The method 200 continues at block 206 by removing the one or more SIT spacers 106, forming one or more sacrificial gate structures, and forming gate spacers 108 on the sidewalls of each of the one or more sacrificial gate structures.

[0069] The method 200 continues at block 208 by recessing one or more portions of the fin that are not protected by a sacrificial gate structure and / or that are not protected by gate spacers 108. The method 200 continues at block 210 by forming respective S / D regions 150 on opposing end faces of or in physical contact with one or more nonlinear channels 110. The method 200 may continue at block 210 by removing the sacrificial gate structure between the gate spacers 108 and instead forming replacement gate structures around the nonlinear channels 110 and between the gate spacers 108, and forming an interlayer dielectric 195.

[0070] 11 , which illustrates a cross-sectional view and a top view of a semiconductor device 300 including a nonlinear channel 310, according to an embodiment of the present disclosure. The semiconductor device 300 may further include a semiconductor substrate 302, one or more isolation regions 312, one or more source / drains (S / D) 350 (e.g., as shown in FIG. 12 ), one or more replacement gates 390 (e.g., as shown in FIGS. 12 and 13 ), one or more gate spacers 380 (e.g., as shown in FIG. 12 ), and one or more interlayer dielectrics 395 (e.g., as shown in FIG. 12 ).

[0071] The nonlinear channel 310 may include generally arcuate, curved, segmented, or the like sidewalls that form the nonlinear channel and define a fin width 181 and a channel length 185, illustratively shown in FIG. 14 . Specifically, as shown, the nonlinear channel 310 may include arcuate or curved sidewalls that define the fin or channel width 181. In general, the nonlinear channel has a longer fin or channel length 185 than a channel that includes the linear sidewalls of a conventional fin (i.e., sidewalls that are parallel to the X-plane as shown). Thus, the channel length 185 of the nonlinear channel 310 can be relatively increased within the boundaries of the footprint of the replacement gate (e.g., within the gate length (Lg) 183 of the replacement gate 390, illustratively shown in FIG. 14 ). In other words, the channel length 185 of the nonlinear channel 310 can be relatively increased without also increasing the gate length (Lg) 183 of the replacement gate 390. Although shown with arcuate or curved sidewalls, the nonlinear channel 310 may include V-shaped sidewalls, hexagonal sidewalls, or the like that define the fin or channel width 181 and fin or channel length 185.

[0072] 11 illustrates a top view and a cross-sectional view of a semiconductor device 300 that will include a nonlinear channel 310 after a fabrication process according to an embodiment of the present disclosure. At this fabrication stage, one or more fin mandrels 304 may be formed on a semiconductor substrate 302, a nonlinear channel 310 may be formed on the sidewalls of the one or more fin mandrels 304, the one or more nonlinear channels 310 may be patterned, and one or more isolation regions 320 may be formed.

[0073] Semiconductor substrate 302 includes the same or similar semiconductor material and / or structure as semiconductor substrate 102. One or more fin mandrels 304, including but not necessarily limited to amorphous silicon (a-Si), amorphous carbon, polycrystalline silicon, polycrystalline silicon germanium, amorphous silicon germanium, polycrystalline germanium, and / or amorphous germanium, are formed on substrate 302. In one embodiment, one or more fin mandrels 304 are formed by depositing or epitaxially growing a suitable material on substrate 302 as a blanket mandrel layer, depositing a mandrel mask layer (not shown) on the blanket mandrel layer, and patterning the mandrel mask layer and underlying blanket mandrel layer using lithography and etching techniques. Portions of the blanket mandrel layer and mandrel hard mask layer are removed, while desired portions of the blanket mandrel layer and mandrel hard mask layer are retained, thereby forming one or more fin mandrels 304 having hard mask portions 307 thereon, as shown.

[0074] One or more fin mandrels 304 may be spaced apart from one another. In one example, the fin mandrel 304 may be a circular cylinder and may have circular sidewalls with one central axis positioned in and out of the page of the top view of FIG. 11 . In this example, the nonlinear channel 310 fabricated associated therewith may also have circular sidewalls that define the fin width 181. In another example, as shown, each mandrel 304 may be an oblong cylinder and may have arc-shaped sidewalls with two focal axes positioned in and out of the page of the top view of FIG. 11 . In this example, the nonlinear channel 310 fabricated associated therewith may also have elliptical arc-shaped sidewalls that define the fin width 181. In another example, each mandrel 304 may be a diamond-shaped cylinder and may have segmented sidewalls with respect to the top view of FIG. 11 . In this example, the nonlinear channel 310 fabricated associated therewith may also have V-shaped segmented sidewalls that define the fin width 181. In another example, each mandrel 304 may be a polygonal prism (such as a hexagonal prism) with one central bisecting axis going into and out of the page in the top view of Figure 11 and with associated segmented sidewalls. In this example, the nonlinear channel 310 fabricated associated therewith may also have polygonal segmented sidewalls that define the fin width 181.

[0075] After forming the mandrels 304, the exposed portions of the semiconductor substrate 302 not covered by the mandrels 304 and hard mask portions 307 are removed to a depth d1 (depending on the design) using a substrate etch, using the mandrels 304 and / or hard mask portions 307 as a mask. The substrate etch transfers the pattern of the mandrels 304 and hard mask portions 307 into the semiconductor substrate 302. According to one embodiment, the semiconductor substrate 302, which comprises a semiconductor material such as Si, SiGe, SiC, Si:C, SiGeC, SiGe:C, III-V, II-V compound semiconductors, or other similar semiconductors, can be selectively etched relative to the hard mask portions 307 and fin mandrels 304, for example, using a silicon RIE process.

[0076] After forming the hard mask portions 307 and the fin mandrels 304, isolation regions 312 (e.g., shallow trench isolation (STI) regions) can be formed. After selectively removing portions of the semiconductor substrate 302 to a depth d1, a plurality of trenches or patterns are formed in the semiconductor substrate 302, for example, by a wet or dry etching process. x A dielectric material including LTO, HTO, flowable oxide (FOX), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or some other dielectric is deposited within the trench or pattern. To define the isolation region 312, the dielectric material may be deposited using a deposition technique including, but not necessarily limited to, CVD, plasma-enhanced CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering. As shown, the top surface of the isolation region 312 may be coplanar with the top surface of the substrate 302.

[0077] The one or more nonlinear channels 310 may be formed by epitaxially growing a semiconductor material, such as silicon, silicon germanium, or the like, from the sidewalls of one or more fin mandrels 304. In some embodiments, the epitaxial growth and / or deposition process may be selective to formation on semiconductor surfaces and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces. For example, the epitaxially grown semiconductor material may be grown from the exposed sidewalls of the fin mandrels 104, but not from the exposed surfaces of the isolation regions 312, the exposed surfaces of the hard mask portions 307, or the like.

[0078] Although embodiments of the present disclosure describe the nonlinear channels 310 as fins, embodiments are not necessarily limited to fin channels and may include nanowire channels, or the like. Additionally, for ease of explanation, a finite number of nonlinear channels 310 are shown in the figures, although more or fewer nonlinear channels 310 may be formed.

[0079] In an example, one or more fin mandrels 304 and the respective nonlinear channels 310 formed therearound may be patterned. For example, as shown in a top view, a first portion of the fin mandrel 304 and the respective nonlinear channels 310 formed therearound may be removed, while a second portion of the fin mandrel 304 and the respective nonlinear channels 310 formed therearound may be retained. The fin mandrels 304 and the respective nonlinear channels 310 formed therearound may each be patterned using lithography and etching processes to remove unwanted portions and retain desired portions. Subsequently, one or more fin mandrels 304 and the respective hard mask portions 307 may be removed, while the nonlinear channels 310 formed therearound may be retained on the upper surface of the isolation region 312.

[0080] In a subsequent fabrication stage, one or more sacrificial gate structures may be formed. The one or more sacrificial gate structures may be formed on and around the one or more nonlinear channels 310, on the substrate 302, and on the isolation region 312. The sacrificial gate structure may include a gate liner (not shown), a sacrificial gate (not shown), and a sacrificial gate cap (not shown). The sacrificial gate structure may be formed by first forming a gate liner layer (e.g., a dielectric, an oxide, or the like) on the isolation region 312, on the semiconductor substrate 302, and on and around the one or more nonlinear channels 310. For example, the gate liner layer may be deposited on the upper surface of the isolation region 312, the upper surface of the semiconductor substrate 302, the sidewalls of the one or more nonlinear channels 310, the upper surface of the one or more nonlinear channels 310, or the like. The sacrificial gate structure may be further formed by subsequently forming a sacrificial gate layer (e.g., a dielectric, amorphous silicon, or the like) on the gate liner. The thickness of the sacrificial gate layer may be greater than the height of the one or more nonlinear channels 310 .

[0081] The sacrificial gate structure may be further formed by subsequently forming a gate cap layer on the sacrificial gate layer. The gate cap layer may be formed by depositing a mask material, such as a hard mask material. The gate cap layer may be composed of one or more layers of masking material to protect the sacrificial gate layer and / or other underlying materials during subsequent processing of the device 300. The gate cap layer may be formed of a gate mask material, such as silicon nitride, silicon oxide, a combination thereof, or the like.

[0082] The gate cap layer, the sacrificial gate layer, and the gate liner may each be patterned using lithography and etching processes to remove unwanted portions and retain desired portions, and the retained desired portions of the gate cap layer, the sacrificial gate layer, and the gate liner layer may form the gate liner, the sacrificial gate, and the sacrificial gate cap, respectively, of each of the one or more sacrificial gate structures.

[0083] Each sacrificial gate structure may be formed over a targeted region or area of ​​semiconductor device 300 to define the length of one or more transistors and to provide sacrificial material for subsequent processing to yield the targeted transistor structure. According to one example, each sacrificial gate structure may have a height between about 50 nm and about 200 nm, and a length between about 15 nm and about 200 nm.

[0084] In another stage, one or more gate spacers 380 are formed, as exemplarily shown in FIG. 12 . One or more gate spacers 380 may be formed on at least each lateral surface of the sacrificial gate structure, on and around the exposed portion of the nonlinear channel 310, on the semiconductor substrate 302, and on the isolation region 312. Gate spacers 380 may further be formed on the end surfaces of the associated sacrificial gate structure. The gate spacers 380 may be formed by conformal deposition of a dielectric material such as silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or combinations thereof, or the like. Unwanted portions of the dielectric material may be removed by an anisotropic etching process. Desired portions of the dielectric material may be retained on the sidewalls of the sacrificial gate structure.

[0085] In another fabrication stage, portions of the nonlinear channel 310 not covered by the gate spacers 380 may be recessed or otherwise removed. These portions of the nonlinear channel 310 may be recessed by a directional etch or the like to remove the portions of the nonlinear channel 310 not covered by the gate spacers 380. The top surfaces of the isolation regions 312 may be used as an etch stop, and the gate spacers 380 may be retained. Subsequently, each end face of the nonlinear channel 310 may be flush with the outer lateral surfaces of the gate spacers 380. One or more source / drain (S / D) openings may be formed by trimming or removing portions of the nonlinear channel 310. One or more of the S / D openings may be defined or bounded by the top surfaces of the isolation regions 312 and at least one or more opposing and facing end faces of adjacent nonlinear channels 310. One or more of the S / D openings may be further defined or bounded by opposing and facing respective sections of the lateral surfaces of the gate spacer 380 .

[0086] 12 shows a top view and a cross-sectional view of a semiconductor device 300 including a nonlinear channel 310 after a fabrication process according to an embodiment of the present disclosure. FIG. 13 shows a top view and a cross-sectional view of a semiconductor device 300 including a nonlinear channel 310 after a fabrication process according to an embodiment of the present disclosure. At this stage of fabrication, S / D regions 350 are formed in one or more S / D openings, respectively, an interlayer dielectric 395 is formed over the isolation regions 312 and the S / D regions 350, and the sacrificial gate is removed and a replacement gate 390 is formed in its place.

[0087] The S / D regions 350 may be formed by epitaxially growing source / drain epitaxial regions within the S / D openings, for example, from the exposed end faces of one or more nonlinear channels 310. In some embodiments, the S / D regions 350 are formed by in-situ doped epitaxial growth. In some embodiments, the epitaxial growth and / or deposition process may be selective to formation on semiconductor surfaces and may not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0088] Suitable n-type dopants include, but are not limited to, phosphorus (P), and suitable p-type dopants include, but are not limited to, boron (B). The use of an in-situ doping process is merely an example. For example, an ex-situ process may alternatively be employed to introduce dopants into the source and drain. Other doping techniques may be used to incorporate dopants into the lower source / drain regions. Dopant techniques include, but are not limited to, ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid-phase doping, solid-phase doping, in-situ epitaxy growth, or any suitable combination of these techniques. In a preferred embodiment, the S / D epitaxial growth conditions promote in-situ boron-doped SiGe for p-type transistors and phosphorus- or arsenic-doped silicon or Si:C for n-type transistors. The doping concentration in the S / D regions 350 may range from 1×10 19 cm −3 to 2×10 21 cm −3 , or preferably between 2×10 20 cm −3 and 7×10 20 cm −3 .

[0089] In particular implementations, the S / D regions 350 may be grown such that their bottom surfaces contact the isolation region 312 and their top surfaces are above the top surface of the nonlinear channel 310. For clarity, as shown in the X cross-sectional view of Figure 12, the first S / D region 350 may be a source region for the nonlinear channel 310, and the second S / D region 350 may be a drain region for the nonlinear channel 310. For clarity, two different S / D regions 350 grown from separate nonlinear channels 310 may effectively merge to form a single S / D region 350 that can function as a source or drain for the separate nonlinear channels 310.

[0090] In another fabrication stage, an interlevel dielectric 395 is formed over the isolation regions 312 and over the S / D regions 350, the sacrificial gate is removed, and a replacement gate 390 is formed in its place.

[0091] An interlayer dielectric 395 may be formed over one or more S / D regions 350 and over the top surface of isolation region 312. Interlayer dielectric 395 may be formed by depositing a dielectric material, such as silicon oxide, silicon nitride, SiBCN, SiNC, SiN, SiCO, SiNOC, or a combination thereof, or the like, as a blanket layer over isolation region 312, S / D regions 350, and gate spacer 380. In one embodiment, interlayer dielectric 395 may be formed to a thickness over the top surface of semiconductor device 300, followed by planarization by chemical mechanical polishing (CMP) or etching such that the top surface of the sacrificial gate is exposed (e.g., the sacrificial gate cap has been removed by CMP) and is coplanar with the top surfaces of sacrificial interlayer dielectric 395 and gate spacer 380.

[0092] Once a portion of the sacrificial gate is exposed, it is removed by etching, which may expose the nonlinear channel 310 between the gate spacers 380 previously associated with it, may expose the gate dielectric underneath, and / or the like.

[0093] A replacement gate structure is then formed in place of the removed sacrificial gate between the gate spacers 380 and over and around the nonlinear channel 310. The replacement gate structure may include a gate dielectric (not shown) and a replacement gate 390. The gate dielectric is the gate dielectric associated with the replacement gate structure, or the subsequent gate dielectric if removed, which may include any suitable dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, high-k material, or any combination of these materials. The gate dielectric may be formed by any suitable deposition process or the like. In some embodiments, the gate dielectric has a thickness in the range of 1 nm to 5 nm, although smaller and larger thicknesses are also contemplated.

[0094] The replacement gate 390 may be made of doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), etc.). The conductive material may comprise any suitable conductive material, including, but not limited to, tantalum (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO), cobalt silicide (CoSi), nickel silicide (NiSi), transition metal aluminides (e.g., TiAl, ZrAl), TaC, TaMgC, carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0095] The replacement gate 390 may further include a dopant incorporated during or after deposition. In some embodiments, the replacement gate 390 may further include a work function setting layer (not shown) between the gate dielectric and the replacement gate 390. The work function setting layer may be a work function metal (WFM). The replacement gate 390 and the WFM may be formed by any suitable process, or any suitable combination of processes, including, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser-assisted deposition, chemical solution deposition, etc.

[0096] The replacement gate structure may be formed by first forming a gate dielectric layer between the gate spacers around the nonlinear channel 310 and on the top surface of the isolation region 312. The replacement gate structure may be further formed by subsequently forming a gate conductor layer on the gate dielectric layer. The gate conductor layer and gate dielectric layer may be patterned using lithography and etching processes to remove unwanted portions and retain desired portions, respectively. The retained desired portions of the gate conductor layer and gate dielectric layer may form the replacement gate dielectric layer and replacement gate 390, respectively. CMP, an etching process, or another subtractive removal technique may remove the unwanted portions of the replacement gate structure such that the top surface of the replacement gate structure is coplanar with the top surface of the gate spacer 380, interlayer dielectric 395, or the like. In some implementations, the replacement gate 390 may be recessed below the top surface of the semiconductor device 300, and a dielectric gate cap (not shown) may be formed on the recessed replacement gate 390.

[0097] 13, nonlinear channel 310 may be formed over isolation region 312, and a replacement gate structure may be formed over a semiconductor substrate underlying and immediately adjacent to the footprint of nonlinear channel 310. Furthermore, lateral surface 381 of nonlinear channel 310 may be coplanar with an opposing lateral surface 383 of substrate 302. Generally, surface 381 is the surface facing opposite surface 383.

[0098] More specifically, to achieve expected finFET functionality, the electric field of the replacement gate 390 of the semiconductor device 300 generally controls the nonlinear channel 310, while the electric field of the drain (e.g., one of the S / D regions 350) has a lesser effect on the nonlinear channel 310. The nonlinear channel 310 includes arcuate, curved, segmented, or the like sidewalls that define a nonlinear fin or channel width 181 and a fin or channel length 185. As shown, the nonlinear fin or channel width 181 can be constant across the fin or channel length 185 below the replacement gate 390. The nonlinearity of the nonlinear channel 310 results in a relative increase in the channel or fin length 185 compared to a linear fin with the same fin width. Thus, the channel or fin length 185 of the nonlinear channel 310 can be relatively increased within the confines of the footprint of the replacement gate 390. In other words, the relative increase in channel or fin length 185 within the footprint of replacement gate 390 may limit short channel effects by suppressing the electric field along nonlinear channel 310.

[0099] 14 illustrates a method 400 for fabricating a semiconductor device 300 including a nonlinear channel 310 according to an embodiment of the present disclosure. The method 400 begins at block 402 by forming one or more fin mandrels 304 on a substrate 302, patterning or opening a portion of the underlying semiconductor substrate 302, and forming an isolation region 312 within the pattern or opening in the semiconductor substrate 302.

[0100] The method 400 continues at block 404 by forming nonlinear fins on sidewalls of the one or more fin mandrels 304 (thereby forming the nonlinear channels 310) to form one or more nonlinear channels 310. In an example, one or more of the nonlinear channels 310 may be patterned. The method 400 continues at block 406 by removing the one or more fin mandrels 304, forming one or more sacrificial gate structures, and forming gate spacers 308 on sidewalls of each of the one or more sacrificial gate structures.

[0101] The method 400 continues at block 408 by recessing one or more portions of the nonlinear channel 310 that are not protected by a sacrificial gate structure and / or that are not protected by gate spacers 308. The method 400 continues at block 410 by forming respective S / D regions 350 on or in physical contact with opposing end faces of the one or more nonlinear channels 310. The method 400 may continue by removing the sacrificial gate structure between the gate spacers 308 and instead forming replacement gate structures around the nonlinear channel 310 and between the gate spacers 308, and forming an interlayer dielectric 395.

[0102] The description of various embodiments of the present disclosure has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles, practical applications, or technical improvements over commercially available technologies of the embodiments, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A finFET comprising a nonlinear channel beneath a gate, the nonlinear channel having a first nonlinear sidewall.

2. The finFET of claim 1 , wherein the nonlinear channel has a second nonlinear sidewall opposite the first nonlinear sidewall.

3. The finFET of claim 2 , wherein the first nonlinear sidewall is a first curved nonlinear sidewall.

4. The finFET of claim 3 , wherein the second nonlinear sidewall is a second curved nonlinear sidewall.

5. The finFET of claim 4 , wherein the first curved nonlinear sidewall and the second curved nonlinear sidewall are parallel.

6. The finFET of claim 4 , wherein the first curved nonlinear sidewall and the second curved nonlinear sidewall share a same central axis of curvature.

7. The finFET of claim 1 , further comprising a source in physical contact with a first end face of the nonlinear channel and a drain in physical contact with an opposing second end face of the nonlinear channel.

8. The finFET of claim 7 further comprising a gate spacer around the gate.

9. The finFET of claim 1 , wherein a channel length of the nonlinear channel is greater than a gate length of the gate.

10. the first nonlinear channel below the gate; a second nonlinear channel below the gate; a source in physical contact with each end face of the first nonlinear channel and the second nonlinear channel; and a drain in physical contact with each of the opposing end faces of the first nonlinear channel and the second nonlinear channel; A finFET comprising:

11. The finFET of claim 10 , wherein the first nonlinear channel has a first nonlinear sidewall and a second nonlinear sidewall opposite the first nonlinear sidewall.

12. The finFET of claim 11 , wherein the first nonlinear sidewall is a first curved sidewall and the second nonlinear sidewall is a second curved sidewall.

13. The finFET of claim 12 , wherein the second nonlinear channel has a third nonlinear sidewall and a fourth nonlinear sidewall opposite the third nonlinear sidewall.

14. The finFET of claim 13 , wherein the third nonlinear sidewall is a third curved sidewall and the fourth nonlinear sidewall is a fourth curved sidewall.

15. The finFET of claim 14 , wherein the first curved sidewall and the second curved sidewall are parallel, and the third curved sidewall and the fourth curved sidewall are parallel.

16. 16. The finFET of claim 15, wherein the first curved sidewall, the second curved sidewall, the third curved sidewall, and the fourth curved sidewall share a same central axis of curvature.

17. The finFET of claim 16 further comprising a gate spacer around the gate.

18. The finFET of claim 10 , wherein a channel length of the first nonlinear channel is greater than a gate length of the gate.

19. The finFET of claim 18 , wherein a channel length of the second nonlinear channel is longer than the gate length.

20. forming a nonlinear fin on a semiconductor substrate; forming a sacrificial gate on the nonlinear fin; forming gate spacers on respective sidewalls of the sacrificial gate; forming a source in physical contact with a first end surface of the nonlinear fin; forming a drain in physical contact with a second end surface of the nonlinear fin; removing the sacrificial gate between the gate spacers; and forming a replacement gate between the gate spacers; Equipped with the nonlinear fin is a nonlinear channel for the finFET, and a channel length of the nonlinear channel is longer than the replacement gate length; finFET manufacturing method.

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