Method for generating efficient dynamic sampling plans and accurately predicting probe die losses

Abstract

A method for generating an inspection tool sampling plan is disclosed. More specifically, a method for generating an inspection tool sampling plan for more accurate die loss prediction assuming a non-uniform defect density or distribution on a wafer is disclosed. A method for optimizing an inspection tool sampling plan is disclosed. More specifically, a method for optimizing wafer area definitions and sampling budget allocations to improve die loss prediction without relying on predetermined wafer area definition variables and sampling budget allocation variables is disclosed. A computational probabilistic prediction model, a sampling plan optimizer, and a die loss prediction formula are disclosed for predicting die loss with improved accuracy and versatility to guide different wafers for inspection.

Description

Technical Field

[0001] Cross - reference to Related Applications

[0001] This application claims the priority of U.S. Patent Application No. 63 / 458,625, filed on April 11, 2023, and U.S. Patent Application No. 63 / 465,043, filed on May 9, 2023, and the entire contents of both applications are incorporated herein by reference.

[0002]

[0002] The embodiments provided herein relate to the generation of inspection tool sampling plans, and more specifically, to methods for improving die loss prediction from inspection results, or methods for optimizing wafer area definition and sampling budget allocation to predict die loss with improved accuracy without relying on user input (e.g., predetermined variables).

Background Art

[0003]

[0003] In the manufacturing process of integrated circuits (ICs), incomplete or completed circuit components are manufactured according to the design and inspected to ensure there are no defects. Inspection systems that utilize optical microscopes or charged particle (e.g., electron) beam microscopes such as scanning electron microscopes (SEM) can be employed. As the physical size of IC components continues to shrink, the accuracy and yield of defect detection become more important. Various metrology tools have been developed and used to confirm whether an IC is manufactured correctly. To improve the performance of defect inspection, computer - guided inspection (CGI) machine - learning models may be used to assist the tool by indicating the area of the wafer to be inspected.

Summary of the Invention

[0004]

[0004] The embodiments provided herein disclose a method for generating an inspection tool sampling plan, more specifically, a method for improving the prediction of die loss from inspection results, or a method for optimizing wafer area definition and sampling budget allocation to improve die loss prediction.

[0005]

[0005] Some embodiments provide an apparatus for generating an inspection tool sampling plan, comprising: a memory for storing a set of instructions; and at least one processor configured to cause the apparatus to perform a method for generating an inspection tool sampling plan by executing the set of instructions. The method includes: providing wafer input data to a computational defect probability prediction model; dividing the wafer into a plurality of wafer regions having a plurality of dies; calculating a defect die probability for each wafer region from the computational defect probability prediction model; selecting at least one die from each wafer region of the plurality of wafer regions using the calculated defect die probabilities; and generating a wafer sampling plan based on the selected dies.

[0006]

[0006] In some embodiments, an apparatus for optimizing an inspection tool sampling plan is disclosed, comprising: a memory for storing a set of instructions; and at least one processor configured to perform a method for optimizing the inspection tool sampling plan by executing the set of instructions. The method comprises: providing wafer input data to a computational defect probability prediction model; and allocating a sampling budget for a region of a wafer based on the expected defect die count of that region compared to the expected defect die count of the wafer, wherein the expected defect die count of the region is the sum of the expected defect die probabilities of that region; the expected defect die count of the wafer is the sum of the expected defect die probabilities of the wafer; and the expected defect die probabilities of the region and the expected defect die probabilities of the wafer are obtained from the computational defect probability prediction model.

[0007]

[0007] In some embodiments, an apparatus for optimizing an inspection tool sampling plan is disclosed, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions and cause the apparatus to perform a method for optimizing the inspection tool sampling plan. The method includes: providing wafer input data to a computational defect probability prediction model; calculating a defective die probability for each die of the wafer from the computational defect probability prediction model; generating a sampling plan; evaluating wafer regions from the defective die probability for each die of the wafer; evaluating a sampling budget allocation for each evaluated wafer region; and using the sampling plan together with the evaluated wafer regions and sampling budget allocation to guide wafer inspection of the wafer.

[0008]

[0008] Other advantages of the present disclosure will become apparent from reading the following description in conjunction with the accompanying drawings, which illustrate and illustrate specific embodiments of the present disclosure.

[0009]

[0009] The above and other aspects of the present disclosure will become more apparent from reading the description of the exemplary embodiments in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1]

[0010] This is a schematic diagram showing an exemplary charged particle beam inspection system consistent with embodiments of the present disclosure. [Figure 2]

[0011] This is a schematic diagram showing an exemplary multi-beam tool that may be part of the exemplary charged particle beam inspection system shown in Figure 1, consistent with embodiments of the present disclosure. [Figure 3]

[0012] This schematic block diagram shows the throughput for generating input data, consistent with the embodiments of this disclosure. [Figure 4]

[0013] This is an illustrative flowchart of a conventional method for predicting die loss from inspection results using a sampling plan generated from input data that defines the wafer area and the sampling budget allocation per wafer. [Figure 5]

[0014] This is an illustrative diagram of the inputs required for an empirical sampling design using conventional methods. [Figure 6]

[0015] This is an illustrative flowchart of a method for generating a dynamic sampling plan for a wafer and predicting die loss from inspection results according to a non-uniform defect density distribution within the wafer predicted by a computational model. [Figure 7]

[0016] This is an exemplary flowchart of a method for generating a dynamic sampling plan for a wafer without a predetermined sampling budget allocation per wafer region, consistent with embodiments of the present disclosure. [Figure 8]

[0017] This is an exemplary sampling plan or estimated defect die probability map consistent with embodiments of the present disclosure. [Figure 9]

[0018] This is an illustrative flowchart of a method for generating a dynamic sampling plan for a wafer without defining a predetermined wafer region and allocating a sampling budget per wafer region, consistent with embodiments of the present disclosure. [Figure 10A]

[0019] This is an example of an estimated defect die probability map used to evaluate wafer region definitions, consistent with embodiments of the present disclosure. [Figure 10B]

[0019] An exemplary cumulative defective die probability plot consistent with embodiments of the present disclosure. [Figure 11]

[0020] This is an exemplary flowchart illustrating a method for directly optimizing wafer region definition and sampling budget allocation based on die loss prediction R2 correlation scores, consistent with embodiments of the present disclosure. [Modes for carrying out the invention]

[0011]

[0021] Herein, exemplary embodiments are described in detail, examples of which are shown in the accompanying drawings. The following description refers to the accompanying drawings, where, unless otherwise noted, the same numbers in different drawings represent the same or similar elements. The implementations described below in the exemplary embodiments do not represent all implementations. Rather, they are merely examples of apparatus and methods consistent with the aspects relating to the disclosed embodiments as enumerated in the accompanying claims. For example, some embodiments are described in the context of utilizing electron beams, but this disclosure is not limited in that way. Other types of charged particle beams (including, for example, protons, ions, muons, or any other charge-carrying particles) may be applied as well. Furthermore, other imaging systems such as optical imaging, photon detection, X-ray detection, and ion detection may be used.

[0012]

[0022] Electronic devices are constructed from circuits formed on a semiconductor material piece called a substrate. Semiconductor materials may include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium. Many circuits may be formed together on the same silicon piece, and these are called integrated circuits or ICs. The size of these circuits has decreased dramatically, allowing more circuits to fit on a single substrate. Improving the computing power of electronic devices while reducing their physical size can be achieved by significantly increasing the density of circuit components such as transistors, capacitors, and diodes on an IC chip. For example, a smartphone IC chip, while about the size of a thumbnail, can contain over 2 billion transistors, each transistor being less than 1 / 1000th the size of a human hair.

[0013]

[0023] ICs may be manufactured using lithography, a manufacturing process that involves creating complex circuit patterns drawn on a mask deposited on a substrate. Lithography may be carried out by a lithography apparatus, which is a machine that applies a radiation source (e.g., light or X-rays) onto a target area of ​​a substrate to form a desired pattern. The target area of ​​the substrate may be covered with a pattern device (e.g., a mask) which may be removed or developed after exposure to the radiation source. This process of transferring the desired pattern onto the substrate is called the patterning process. The patterning process may include a patterning step of transferring the pattern from the pattern device (e.g., a mask) onto the substrate. There may also be one or more related patterning steps, such as mask development with a developing apparatus, baking of the substrate using a baking tool, etching of the pattern onto the substrate using an etching apparatus, or other chemical and physical processing steps involved in creating the pattern on the substrate. Variations in experimental parameters (e.g., stochastic variations, errors, or noise caused by inspection or pattern processing tools) can potentially limit lithography implementation or process yield for high-volume production (HVM) of ICs and may result in defects in the IC structure.

[0014]

[0024] In the manufacturing of ICs using lithography equipment, typically many lithographic patterning processes are performed, thereby forming functional features on continuous layers on a substrate. Therefore, a critical aspect of the lithography equipment's performance is its ability to correctly and accurately position the applied pattern relative to features placed on previous layers. For this purpose, the substrate is provided with one or more sets of alignment marks. Each mark is a structure with a position that can be measured later, for example, using an electron beam inspection tool. Defects can occur if the applied pattern structure or pattern layer is not positioned correctly relative to the reference marks, or if the manufacturing conditions are not optimal. The reference marks or layout define the desired structure, the dimensions of the structure, and the distances between IC structures (gates, capacitors, etc.) or between interconnection lines. This ensures that IC devices or lines do not interact with each other in undesirable ways. The structural constraints imposed by the reference layout are typically called critical dimensions. The critical dimensions of a circuit can be defined as the minimum width of a line or hole, or the minimum distance between two lines or two holes. Therefore, critical dimensions determine the overall size and mounting density of the designed IC. The goal of IC fabrication is to faithfully reproduce the original IC design on the substrate. If errors occur during fabrication, such as the created IC design pattern not conforming to the reference design, defects may occur in the IC structure, potentially rendering the IC inoperable.

[0015]

[0025] Manufacturing these ICs, which have multiple extremely small structures or components, is a complex, time-consuming, and expensive process that often involves hundreds of individual steps. Even a single error in the process can dramatically impact the functionality of the final product. Even a single "killer defect" can cause device failure. The goal of the manufacturing process is to improve the overall yield of the process. For example, to achieve a 75% yield for a 50-step process, the yield of each individual step must be over 99.4%, and if the yield of each individual step is 95%, the overall process yield drops to 7%.

[0016]

[0026] In IC chip manufacturing facilities, high process yield is desirable, but maintaining high wafer throughput, defined as the number of wafers processed per hour, is also essential. In particular, if operator intervention is required to check for defects, the presence of defects can affect both high process yield and high wafer throughput. Therefore, high-throughput detection and identification of micro and nano-sized defects are desirable. One factor that can improve process yield and wafer throughput is monitoring the IC manufacturing process to ensure that the desired number of defect-free ICs are produced. One method of monitoring the manufacturing process is to inspect the chip circuit structure at various stages of manufacturing the chip circuit structure. In this regard, inspection using tools such as charged particle beam inspection tools may be used to maintain high process yield and high wafer throughput. In wafer inspection using electron beam inspection tools, images of the wafer may be generated to measure the dimensions of the IC structure. The measured dimensions may be compared to a defect-free reference structure to determine the presence of defects in the imaged structure. If a defect is found in the structure, the manufacturing process can be adjusted to reduce the likelihood of the defect recurring. However, since wafers can contain up to 1 billion IC structures, inspecting ICs for defect detection is often a time-consuming process, and sometimes the wafer is not being inspected in the correct location to identify defects.

[0017]

[0027] To mitigate the limitations of IC inspection for detecting defects across the entire wafer, conventional methods have been applied to estimate or predict the total number of defective dies on a wafer at end of manufacturing using wafer inspection results during HVM. The total number of defective dies on a wafer is called the die loss per wafer. Conventional methods rely on empirical or fixed sampling plans to guide the inspection of each wafer inspected during HVM. The sampling plan is a two-dimensional map of the wafer showing where specific defective dies may be located. Conventional methods generate the sampling plan using historical inspection results that identify defective dies from previously inspected wafers. The sampling plan is divided into wafer regions, each wafer region having a determined number of dies to inspect (e.g., a sampling budget). Wafer inspection can be performed in-line with wafer fabrication, and each wafer inspected during wafer fabrication is inspected according to this sampling plan. After obtaining wafer inspection results using empirical and fixed sampling plans, the die loss of the wafer at end of manufacturing is predicted, assuming a uniform defect density or distribution within each wafer region. Using predicted die loss, it is possible to verify that satisfactory wafer yield is maintained throughout the manufacturing process and to estimate the defect rate at the end of manufacturing or the actual die loss per wafer. Wafer processing continues until a batch of wafers is completely manufactured, after which the actual die loss is measured by applying probe tests to the wafers manufactured in the batch. The final metric for evaluating the accuracy of conventional methods is the R of the difference between the predicted die loss per wafer and the actual die loss per wafer. 2 Alternatively, you could calculate the correlation score.

[0018]

[0028] However, the conventional methods described above may have limitations in their accuracy in predicting die loss per wafer from inspection results. Guiding the inspection of all wafers inspected during HVM using a fixed sampling plan may not be sensitive to the variations between wafers that occur during wafer processing. Therefore, this may not be optimal in terms of efficiently capturing defective dies within each inspected wafer. Conventional methods for predicting die loss also assume a uniform defect density or distribution within each wafer, which may not accurately reflect the actual defect density or distribution within the wafer. Furthermore, the wafer area and the sampling budget allocated to each wafer area may not be optimal with a fixed sampling plan to ensure a high defect capture rate for each wafer inspected. Therefore, conventional methods that guide inspection using a fixed sampling plan and assume a uniform defect density or distribution may not be able to accurately predict defective dies in wafers during HVM.

[0019]

[0029] Embodiments of this disclosure can provide a model-based method for generating a dynamic sampling plan by generating defect probability estimates based on incoming wafer metrometry data. The dynamic sampling plan may be used to guide the inspection of wafers in HVM. In some embodiments, this disclosure can provide a method for more accurately predicting die loss without assuming a uniform defect density or distribution within the wafer, using model-based scaling factors. In some embodiments, this disclosure can provide a method for optimizing the definition of wafer regions or the sampling budget allocation per wafer region without predetermined values ​​from input data. Some embodiments of this disclosure can provide a model-based method for optimizing the sampling budget allocation of wafer regions using predetermined wafer regions. Some embodiments of this disclosure can provide a model-based method for optimizing wafer regions and the sampling budget per wafer region without predetermined values ​​from input data. Some embodiments of this disclosure provide a defective die prediction R 2An optimization-based method can also be provided that directly optimizes parameterized wafer region variables and wafer region-specific sampling budget variables by optimizing correlation scores. Some embodiments of this disclosure can provide methods for improving the performance and versatility of computational models for guiding wafer inspection. Some embodiments of this disclosure can provide methods for improving the accuracy of defect inspection and the yield of defect-free wafers across the entire HVM.

[0020]

[0030] The relative dimensions of components in the drawings may be exaggerated for clarity. In the following description of the drawings, the same or similar reference numerals refer to the same or similar components or entities, and only the differences relating to individual embodiments are described. Where used herein, unless otherwise specified, the term “or” encompasses all possible combinations unless impossible. For example, where it is stated that a component may include A or B, the component may include A or B, or A and B, unless otherwise specified or impossible. As a second example, where it is stated that a component may include A, B, or C, the component may include A or B, or C, or A and B, or A and C, or B and C, or A and B and C, unless otherwise specified or impossible.

[0021]

[0031] Figure 1 shows an exemplary electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure. The EBI system 100 can be used for imaging. As shown in Figure 1, the EBI system 100 includes a main chamber 101, a loading / locking chamber 102, a beam tool 104, and an instrument front-end module (EFEM) 106. The beam tool 104 is located in the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 may include additional loading ports. The first loading port 106a and the second loading port 106b receive a wafer front-opening integrated pod (FOUP) containing a wafer to be inspected (e.g., a semiconductor wafer or a wafer made of other material) or a sample (wafers and samples may be used interchangeably). A “lot” is a group of wafers that can be loaded for wafer processing as a batch.

[0022]

[0032] One or more robotic arms (not shown) of the EFEM106 may transport a wafer to the loading / locking chamber 102. The loading / locking chamber 102 is connected to a loading / locking vacuum pump system (not shown) that removes gas molecules from within the loading / locking chamber 102 to a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) may transport the wafer from the loading / locking chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pump system (not shown) that removes gas molecules from within the main chamber 101 to a second pressure below the first pressure. After reaching the second pressure, the wafer is inspected by a beam tool 104. The beam tool 104 may be a single-beam system or a multi-beam system.

[0023]

[0033] The controller 109 is electronically connected to the beam tool 104. The controller 109 may also be a computer configured to perform various controls of the EBI system 100. In Figure 1, the controller 109 is shown as being outside the structure, which includes the main chamber 101, the loading / locking chamber 102, and the EFEM 106, but it should be understood that the controller 109 may also be part of this structure.

[0024]

[0034] In some embodiments, the controller 109 may include one or more processors (not shown). A processor may be a general-purpose or dedicated electronic device capable of manipulating or processing information. For example, a processor may include any number and any combination of a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a composite programmable logic device (CPLD), a field-programmable gate array (FPGA), a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), and any type of circuitry capable of data processing. Alternatively, a processor may be a virtual processor comprising one or more processors distributed across multiple machines or devices connected via a network.

[0025]

[0035] In some embodiments, the controller 109 may further include one or more memories (not shown). The memories may be general-purpose or dedicated electronic devices capable of storing code and data accessible by the processor (e.g., via a bus). For example, the memories may include any number and any combination of random access memory (RAM), read-only memory (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any type of storage device. The code and data may include an operating system (OS) and one or more application programs (or "apps") for a particular task. The memories may also be virtual memory, including one or more memories distributed across multiple machines or devices connected via a network.

[0026]

[0036] Figure 2 shows a schematic diagram of an exemplary multibeam tool 104 (also referred to herein as apparatus 104) and an image processing system 290 that may be configured for use in an EBI system 100 (Figure 1), consistent with embodiments of the present disclosure.

[0027]

[0037] The beam tool 104 includes a charged particle source 202, a gun aperture 204, a focusing lens 206, a primary charged particle beam 210 emitted from the charged particle source 202, a source conversion unit 212, multiple beamlets 214, 216, and 218 of the primary charged particle beam 210, a primary projection optical system 220, an electric wafer stage 280, a wafer holder 282, multiple secondary charged particle beams 236, 238, and 240, a secondary optical system 242, and a charged particle detection device 244. The primary projection optical system 220 may include a beam separator 222, a deflection scanning unit 226, and an objective lens 228. The charged particle detection device 244 may include detection sub-regions 246, 248, and 250.

[0028]

[0038] The charged particle source 202, gun aperture 204, focusing lens 206, source conversion unit 212, beam separator 222, deflection scanning unit 226, and objective lens 228 may be aligned with the primary optical axis 260 of the device 104. The secondary optical system 242 and charged particle detection device 244 may be aligned with the secondary optical axis 252 of the device 104.

[0029]

[0039] The charged particle source 202 can emit one or more types of charged particles, such as electrons, protons, ions, muons, or any other charge-carrying particles. In some embodiments, the charged particle source 202 may be an electron source. For example, the charged particle source 202 may include a cathode, an extractor, or an anode, and primary electrons can be emitted from the cathode, extracted, or accelerated to form a primary charged particle beam 210 (in this case, a primary electron beam) with a (virtual or actual) crossover 208. For the sake of ease of explanation without causing ambiguity, electrons are used as examples in some parts of this specification. However, it should be noted that in any embodiment of this disclosure, any charged particle can be used, not limited to electrons. The primary charged particle beam 210 can be visualized as being emitted from the crossover 208. The gun aperture 204 can block surrounding charged particles from the primary charged particle beam 210 to reduce the Coulomb effect. The Coulomb effect can increase the size of the probe spot.

[0030]

[0040] The source conversion unit 212 may include an array of image-forming elements and an array of beam-limiting apertures. The array of image-forming elements may include an array of micro-deflectors or micro-lenses. The array of image-forming elements can form multiple parallel images (virtual or real images) of the crossover 208 with multiple beamlets 214, 216, and 218 of the primary charged particle beam 210. The array of beam-limiting apertures can limit the multiple beamlets 214, 216, and 218. Figure 2 shows three beamlets 214, 216, and 218, but embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the apparatus 104 may be configured to generate a first number of beamlets. In some embodiments, the first number of beamlets may be in the range of 1 to 1000. In some embodiments, the first number of beamlets may be in the range of 200 to 500. In an exemplary embodiment, the apparatus 104 may generate 400 beamlets.

[0031]

[0041] The focusing lens 206 can focus the primary charged particle beam 210. The currents in the beamlets 214, 216, and 218 downstream of the source conversion unit 212 can be changed by adjusting the focusing force of the focusing lens 206 or by changing the radial size of the corresponding beam limiting aperture in the beam limiting aperture array. The objective lens 228 can focus the beamlets 214, 216, and 218 onto the wafer 230 for imaging and can form multiple probe spots 270, 272, and 274 on the surface of the wafer 230.

[0032]

[0042] The beam separator 222 can be a Wien filter type beam separator that generates an electrostatic dipole field and a magnetic dipole field. In some embodiments, when these fields are applied, the force exerted by the electrostatic dipole field on the charged particles (e.g., electrons) of the beamlets 214, 216, and 218 may be substantially equal in magnitude and opposite in direction to the force exerted by the magnetic dipole field on the charged particles. Thus, the beamlets 214, 216, and 218 can pass straight through the beam separator 222 with zero deflection angle. However, the total dispersion of the beamlets 214, 216, and 218 generated by the beam separator 222 may be non-zero. The beam separator 222 can separate the secondary charged particle beams 236, 238, and 240 from the beamlets 214, 216, and 218 and guide the secondary charged particle beams 236, 238, and 240 toward the secondary optical system 242.

[0033]

[0043] The deflection scanning unit 226 can deflect beamlets 214, 216, and 218 to scan probe spots 270, 272, and 274 across the surface area of ​​wafer 230. As beamlets 214, 216, and 218 are incident on probe spots 270, 272, and 274, secondary charged particle beams 236, 238, and 240 may be emitted from wafer 230. The secondary charged particle beams 236, 238, and 240 may contain charged particles (e.g., electrons) with an energy distribution. For example, the secondary charged particle beams 236, 238, and 240 may be secondary electron beams containing secondary electrons (energy ≤ 50 eV) and backscattered electrons (energy between 50 eV and the landing energies of beamlets 214, 216, and 218). The secondary optical system 242 can focus the secondary charged particle beams 236, 238, and 240 onto the detection subregions 246, 248, and 250 of the charged particle detection device 244. The detection subregions 246, 248, and 250 may be configured to detect the corresponding secondary charged particle beams 236, 238, and 240 and generate corresponding signals (e.g., voltage, current, etc.) used to reconstruct an SCPM image of the surface area or subsurface structure of the wafer 230.

[0034]

[0044] The generated signals can represent the intensities of the secondary charged particle beams 236, 238, and 240 and may be provided to an image processing system 290, which communicates with a charged particle detection device 244, a primary projection optical system 220, and an electric wafer stage 280. The movement speed of the electric wafer stage 280 may be synchronized and coordinated with beam deflection controlled by a deflection scanning unit 226 so that the scan probe spots (e.g., scan probe spots 270, 272, and 274) can be moved to cover the region of interest on the wafer 230 in an orderly manner. Such synchronization and coordination parameters may be adjusted to suit wafers 230 of different materials. For example, wafers 230 of different materials may have different resistive-capacitive characteristics, which may result in different signal sensitivities to the movement of the scan probe spots.

[0035]

[0045] The intensities of the secondary charged particle beams 236, 238, and 240 may vary depending on the external or internal structure of the wafer 230, and thus can indicate whether the wafer 230 contains defects. Furthermore, as described above, the beamlets 214, 216, and 218 may be projected onto different locations on the upper surface of the wafer 230 or different sides of local structures of the wafer 230 to generate secondary charged particle beams 236, 238, and 240 which may have different intensities. Therefore, by mapping the intensities of the secondary charged particle beams 236, 238, and 240 to areas of the wafer 230, the image processing system 290 may reconstruct an image that reflects the characteristics of the internal or external structure of the wafer 230.

[0036]

[0046] In some embodiments, the image processing system 290 may include an image acquisition unit 292, storage 294, and a controller 296. The image acquisition unit 292 may include one or more processors. For example, the image acquisition unit 292 may include a computer, server, mainframe host, terminal, personal computer, any kind of mobile computing device, etc., or a combination thereof. The image acquisition unit 292 may be communicatively coupled to the charged particle detection device 244 of the beam tool 104 through a medium such as a conductor, optical fiber cable, portable storage medium, IR, Bluetooth, the internet, wireless network, radio, or a combination thereof. In some embodiments, the image acquisition unit 292 may receive signals from the charged particle detection device 244 and construct an image. Thus, the image acquisition unit 292 may acquire an SCPM image of the wafer 230. The image acquisition unit 292 may also perform various post-processing functions such as contour generation and overlaying indicators onto the acquired image. The image acquisition unit 292 may be configured to adjust the brightness and contrast of the acquired image. In some embodiments, the storage 294 may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), or other types of computer-readable memory. The storage 294 may be coupled with the image acquisition unit 292 and may be used to store scanned raw image data as the original image and to store the post-processed image. The image acquisition unit 292 and the storage 294 may be connected to the controller 296. In some embodiments, the image acquisition unit 292, the storage 294, and the controller 296 may be integrated together as a single control unit.

[0037]

[0047] In some embodiments, the image acquisition unit 292 may acquire one or more SCPM images of the wafer based on imaging signals received from the charged particle detection device 244. The imaging signals may correspond to scanning operations for charged particle imaging. The acquired image may be a single image containing multiple imaging areas. This single image may be stored in storage 294. This single image may be a source image that can be divided into multiple regions. Each of these regions may contain one imaging area containing features of the wafer 230. The acquired image may include multiple images of a single imaging area of ​​the wafer 230 sampled multiple times over time. These multiple images may be stored in storage 294. In some embodiments, the image processing system 290 may be configured to perform image processing steps using multiple images of the same location on the wafer 230.

[0038]

[0048] In some embodiments, the image processing system 290 may include a measurement circuit (e.g., an analog-to-digital converter) for acquiring the distribution of detected secondary charged particles (e.g., secondary electrons). The charged particle distribution data collected during the detection time window can be used in combination with the corresponding scanning path data of beamlets 214, 216, and 218 incident on the wafer surface to reconstruct an image of the wafer structure under inspection. The reconstructed image can be used to reveal various features of the internal or external structures of the wafer 230, thereby revealing any defects that may be present in the wafer.

[0039]

[0049] In some embodiments, the charged particles may be electrons. When electrons from the primary charged particle beam 210 are projected onto the surface of the wafer 230 (e.g., probe spots 270, 272, and 274), the electrons from the primary charged particle beam 210 may penetrate the surface of the wafer 230 to a certain depth and interact with the particles of the wafer 230. Some of the electrons from the primary charged particle beam 210 may interact elastically with the material of the wafer 230 (e.g., in the form of elastic scattering or collision) and may be reflected or bounced off the surface of the wafer 230. Elastic interactions conserve the total kinetic energy of the interacting objects (e.g., electrons from the primary charged particle beam 210), where the kinetic energy of the interacting objects is not converted into other forms of energy (e.g., heat, electromagnetic energy, etc.). Such reflected electrons produced from elastic interactions are sometimes called backscattered electrons (BSEs). Some electrons from the primary charged particle beam 210 may interact inelastically with the material of the wafer 230 (e.g., in the form of inelastic scattering or collision). Inelastic interactions do not conserve the total kinetic energy of the interacting objects, where some or all of the kinetic energy of the interacting objects is converted into other forms of energy. For example, inelastic interactions can cause the kinetic energy of some electrons from the primary charged particle beam 210 to cause electron excitation and atomic transitions in the material. Such inelastic interactions may also generate electrons that emanate from the surface of the wafer 230, and these electrons are sometimes called secondary electrons (SE). The yield or emission rate of BSE and Se depends, for example, among other things, on the material being inspected and the landing energy of the electrons from the primary charged particle beam 210 that land on the surface of the material. The energy of the electrons from the primary charged particle beam 210 may be partially imparted by an accelerating voltage (e.g., the accelerating voltage between the anode and cathode of the charged particle source 202 in Figure 2). The amounts of BSE and Se may be greater than or less than (or even equal to) the amount of electrons injected by the primary charged particle beam 210.

[0040]

[0050] Images generated by SCPM may be used for defect inspection. For example, a generated image capturing a test device region of a wafer may be compared to a reference image capturing the same test device region. The reference image may be predetermined (e.g., by simulation) and may not contain known defects. If the difference between the generated image and the reference image exceeds an acceptable level, a potential defect may be identified. In another example, SCPM may scan multiple regions of a wafer, each containing a test device region designed to be the same, and SCPM may generate multiple images capturing those manufactured test device regions. The multiple images may be compared to each other. If the difference between the multiple images exceeds an acceptable level, a potential defect may be identified.

[0041]

[0051] While this disclosure may refer to ICs, it should be understood that this disclosure may also be applicable to other possible applications or designs. For example, this disclosure may be applicable to integrated optical systems, magnetic domain memories, liquid crystal display panels, thin-film magnetic heads, and other nanoscale structures. It should be further understood that the terms “die,” “structure,” and “IC structure” are used interchangeably in this disclosure.

[0042]

[0052] Referring now to Figure 3, which is an exemplary block diagram for generating input data consistent with embodiments of the present disclosure. The input data may be generated using two steps as shown in Figure 3. A wafer may be fabricated using a lithography projection apparatus 301 under certain fabrication conditions (e.g., radiation source focus and dose). Metrology information of structures formed on the wafer produced by the lithography projection apparatus 301 may be measured using an inspection tool 302 (e.g., the EBI system 100 in Figure 1 or the multibeam tool 104 in Figure 2). Metrology information may include, but is not limited to, necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, and bridge defects of the IC structure on the wafer. A processor 303 having memory (e.g., the controller 109 in Figure 1) may be communicatively connected to the inspection tool 302 to store the measured metrology information.

[0043]

[0053] The images generated by the inspection tool 302 may be used for wafer inspection. For example, a generated image capturing a test device region of a wafer may be compared with a reference image capturing the same test device region. The reference image may be predetermined (e.g., by simulation) and may not contain known defects. If the difference between the generated image and the reference image exceeds an acceptable level, a potential defect may be identified. In another example, the inspection tool 302 may scan multiple regions of a wafer, each region containing a test device region designed to be the same, and the inspection tool 302 may generate multiple images capturing those manufactured test device regions. The multiple images may be compared with each other. If the differences between the multiple images exceed an acceptable level, a potential defect may be identified.

[0044]

[0054] In some embodiments, the processor 303 may be a general-purpose or dedicated electronic device capable of manipulating or processing information. For example, the processor 303 may include any number and any combination of the following: a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a composite programmable logic device (CPLD), a field-programmable gate array (FPGA), a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), and any type of circuitry capable of data processing. Alternatively, the processor 303 may be a virtual processor comprising one or more processors distributed across multiple machines or devices connected via a network.

[0045]

[0055] In some embodiments, the processor 303 may further include one or more memories (not shown). The memories may be general-purpose or dedicated electronic devices that can store code and data accessible by the processor (e.g., via a bus). For example, the memories may include any number and any combination of random access memory (RAM), read-only memory (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any type of storage device. The code and data may include an operating system (OS) and one or more application programs (or "apps") for a particular task. The memories may also be virtual memory, which includes one or more memories distributed across multiple machines or devices connected via a network.

[0046]

[0056] Current prediction methods for estimating the formation of defective dies during wafer processing and predicting die loss at the end of wafer processing rely on the use of empirical and fixed sampling plans for wafer inspection. The sampling plan may be generated by compiling past inspection results that identify specific locations of wafer defects. Conventional sampling plans are also used for each wafer inspected during wafer processing and are therefore considered "fixed" or "static." Once wafer inspection results are obtained via a conventional sampling plan, the predicted die loss can be calculated via the following formula.

number

[0047]

[0057] In Equation 1,

number

number

number

number

number

[0048]

[0058] In addition to assuming a uniform defect density or distribution within the wafer region, conventional methods require a predetermined wafer region definition and a wafer region-specific sampling budget allocation in the sampling plan. However, this can limit the accuracy of the predicted die loss (e.g., below optimal R). 2 (Correlation score). This is because defect density or distribution may not be uniform within a wafer region, and given wafer region definitions and per-wafer region sampling budget allocations can be highly empirical. Furthermore, conventional methods maintain the same wafer region definition and per-wafer region sampling budget allocation for all incoming wafers. This can limit the versatility of conventional methods for accurately predicting die loss across various wafers, because each wafer may have a different optimal wafer region definition or per-wafer region sampling budget. This can lead to inaccurate wafer inspection in the HVM and sampling plans that miss defects, thus resulting in inaccurate die loss predictions (e.g., below optimal R). 2 (Correlation score). Therefore, this reduces the yield and throughput of defect-free wafers in HVM.

[0049]

[0059] Refer to Figure 4 here. Figure 4 is an illustrative flowchart of a conventional method for predicting wafer die loss according to inspection results collected from an empirical and static (e.g., constant across wafers) sampling plan with fixed wafer region definitions and per-wafer region sampling budget allocation. The steps in Figure 4 may be performed by computer devices and inspection tools.

[0050]

[0060] In step 401, an empirical sampling plan is generated. The sampling plan may be generated based on historical data from a previously inspected wafer or a batch of previously inspected wafers. The historical data may be inspection images containing identified defects on the wafer. Therefore, the generated sampling plan may include these historical defect signatures. Furthermore, the sampling plan is generated according to a predetermined wafer area definition and a sampling budget per wafer area.

[0051]

[0061] Step 402 guides wafer inspection using inspection tools with an empirical sampling plan. Wafer inspection is performed according to a predetermined sampling budget for each wafer area in the sampling plan. Wafer inspection is performed inline with the HVM. The number of dies inspected in the first wafer area is equal to the sampling budget for the first wafer area, and the same applies to the second wafer area.

[0052]

[0062] In step 403, the obtained inspection results are used to predict the die loss of the wafer at the end of the wafer processing. The die loss prediction may be performed as described above in Equations 1 and 2 (for example, assuming that the defect density or distribution within the wafer region is uniform).

[0053]

[0063] In step 404, the actual die loss is obtained by applying a probe test to the wafer at the end of wafer processing. The probe test determines whether or not each die on the wafer is defective. In step 405, R 2 The correlation score is evaluated from the actual die loss and the predicted die loss. 2It should be understood that the correlation score can be determined from a set of wafers. The first and second wafers may be examined according to step 402, and the two predicted die loss values ​​may be determined according to step 403. The first and second wafers at the end of wafer processing may be measured according to step 404 to obtain the two actual die loss values.

[0054]

[0064] Refer to Figure 5 here. Figure 5 is an illustrative diagram of the inputs required for an empirical sampling plan using a conventional method. Figure 5 shows a wafer 501 having a first wafer region 502, a second wafer region 503, and a third wafer region 504. Each wafer region has a corresponding sampling budget. Each wafer region definition and the corresponding sampling budget per wafer region do not necessarily have to be adjusted according to a conventional method. Furthermore, each wafer region definition is kept constant for each wafer being inspected.

[0055]

[0065] Conventional methods for generating empirical sampling plans with predetermined wafer area definitions and per-wafer sampling budget allocations can inaccurately guide wafer inspection and reduce inspection yield throughput. Furthermore, relying on a constant wafer area definition and per-wafer sampling budget allocation for all incoming wafers, and assuming a uniform defect density distribution within each wafer area, makes it difficult to accurately predict die loss for different wafers during HVM, and therefore difficult to reliably maintain the desired wafer yield.

[0056]

[0066] Embodiments of the present disclosure can provide a model-based approach for predicting die losses during wafer processing. A computer-guided inspection (CGI) process guides inspection tools to locations on the wafer that are likely to have defects. A machine learning-based CGI model receives inputs from various data sources such as wafer characteristic data (which may include scanner data, metrology data, and fabrication process data), and trains the model using inspection results. The CGI machine learning model can be constructed and used to output a sampling plan indicating locations on the wafer where defects are likely to be formed after a wafer processing step. Thereby, the inspection tool moves to the sampling locations and performs inspections with higher efficiency than inspecting wafer locations based on experience (e.g., history of previous defects detected during scanning). The CGI process is performed inline with wafer fabrication and enhances the efficiency of the inspection tool by increasing the accuracy of finding defects on the wafer with a defect discovery capture rate higher than the baseline value. Using the inspection results, it can be confirmed that a satisfactory wafer yield is maintained throughout manufacturing, and the defect rate or die loss per wafer can be predicted at the end of manufacturing. This predicted defect rate may be compared with the results of the wafer probe test, in which the defect rate of each die fabricated on the wafer is determined. The ultimate metric for CGI model usage cases can be the R 2 correlation score between the estimated die defects and the measured die defects of the wafer.

[0057]

[0067] A CGI model may be applied to characteristic wafer data to estimate the defect probability of each die on the wafer. A sampling plan optimizer or sampling plan generator then converts the estimated defect die probability for each die on the wafer into a die-level sampling decision wafer map (also known as a sampling plan). The sampling plan may be generated according to input information defining predetermined wafer area definitions and sampling budgets per wafer area, as well as user-specified sampling options. The sampling plan may provide die-level binary sampling decisions (e.g., whether to inspect or not inspect certain dies on the wafer). The sampling plan may then be used to guide inspection tools (e.g., scanning electron microscopes, SEMs, or optical tools) to areas on the wafer that have a set number of dies to inspect (e.g., a sampling budget). The inspection results obtained through the sampling plan indicate the actual number of defective dies present, and these results may then be used to predict the estimated die loss of the wafer. R for defect die prediction provided by the CGI model sampling plan 2 The correlation score may be determined by collecting “ground truth” results for the wafer. “Ground truth” results represent the actual defective die results of the wafer at the end of manufacturing and correspond to probe test results of a fully completed wafer. Therefore, probe test results provide accurate identification of defects in each die on the wafer. The final metric for the CGI model and sampling plan optimizer is the correlation R between the predicted estimated die loss determined by the CGI model and the actual die loss determined by the probe test results. 2 A score is also acceptable.

[0058]

[0068] The CGI model provides output of defective die probabilities at the inter-die level. This means that the CGI model estimates the defect probability of each die on the wafer, which may vary from die to die and from wafer to wafer. The estimated defective die probabilities may be collected to generate a wafer sampling plan. Since the sampling plan may be generated for each wafer based on a specific defective die probability for each die on the wafer, the sampling plan generated by the CGI model is sometimes called a “dynamic” sampling plan. The dynamic sampling plan may be used to guide wafer inspection and predict the die loss of the wafer at the end of wafer processing.

[0059]

[0069] In some embodiments of this disclosure, the predicted die loss is calculated without assuming a uniform defect density or distribution within the wafer region. As described above, the die loss may be predicted after collecting inspection results from an inspection tool guided by a CGI-generated dynamic sampling plan. The predicted die loss may be calculated via the following formula, which is consistent with embodiments of this disclosure.

number

[0060]

[0070] In Equation 3, N dd This is the number of defective dies,

number

[0061]

[0071] Now, refer to Figure 6. Figure 6 is an illustrative flowchart of Method 600, which generates a dynamic sampling plan for a wafer and predicts die loss from inspection results, assuming a non-uniform defect density or distribution within the wafer. The steps of Method 600 may be performed by a computer device (e.g., processor 303 in Figure 3). It should be understood that Method 600 as illustrated may be modified by changing the order of the steps or by including additional steps.

[0062]

[0072] In step 601, input data is acquired and supplied to the CGI model. The input data may correspond to images displaying metronome information collected from a first and second wafer acquired via wafer processing during HVM. Wafer processing may be lithography focus and dose conditions. The input data may include predetermined wafer area definitions and sampling budget allocations. Metrology information may include, but is not limited to, necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, and bridge defects on the wafer.

[0063]

[0073] In step 602, the estimated defective die probability for each die on the first wafer is calculated based on the input data of the first wafer. The calculation may be based on identified defects in the input data and may be affected by the quality of the input data. The calculation may be performed by a processor (e.g., processor 303 in Figure 3) capable of applying a CGI model to the first wafer.

[0064]

[0074] In step 603, the estimated defective die probabilities for all dies on the first wafer are ranked. The estimated defective die probabilities are ranked for each wafer region as follows: Top N i The top N with the highest estimated defect die probability i Each die may be ranked by wafer region so as to be considered. As mentioned above, N i This is the sampling budget for each wafer area.

[0065]

[0075] In step 604, the sampling plan for the first wafer is determined based on the wafer region definition and the top N of each wafer region determined in step 603. i It is generated based on individual dies.

[0066]

[0076] In step 605, the sampling plan generated for the first wafer is used to guide the inspection of the first wafer using the inspection tool. The inspection tool collects inspection results of the first wafer according to the predicted defects identified by the sampling plan. In step 606, the CGI model predicts the die loss of the first wafer according to the inspection results collected in step 605 and according to equations 3 and 4.

[0067]

[0077] In step 607, the estimated defective die probability for each die on the second wafer is calculated based on the input data for the second wafer. The calculation may be performed by one or more processors (e.g., processor 303 in Figure 3) capable of applying a CGI model to the second wafer. The input data for the second wafer is as described above in step 601 and may include wafer region definitions and sampling budget allocation for the second wafer. The estimated defective die probabilities for all dies on the second wafer may be ranked by wafer region, a sampling plan may be generated based on the ranked estimated defective die probabilities, and die losses may be predicted for the second wafer by repeating steps 603 to 606.

[0068]

[0078] In step 608, once the wafer processing is complete, probe test results can be obtained for the first and second wafers. In step 609, R 2 The correlation score is evaluated by comparing the actual defective die results (e.g., actual die loss) of the first and second wafers with the estimated defective die probability (e.g., predicted die loss), as described above.

[0069]

[0079] It should be understood that Method 600 can provide a dynamic sampling plan that can direct inspection to areas on the wafer that are likely to contain a higher concentration of dies expected to be defective, compared to conventional methods. Furthermore, Method 600 can provide a more robust method for predicting die loss at the end of the wafer processing stage. Thus, the die loss predicted by Method 600 may better agree with the ground truth results, and the resulting R 2 The correlation score may increase compared to that obtained using conventional methods.

[0070]

[0080] Now, refer to Figure 7. Figure 7 is an exemplary flowchart of Method 700 for generating a dynamic sampling plan for a wafer without a predetermined sampling budget allocation per wafer region, consistent with embodiments of the present disclosure. The steps of Method 700 may be performed by a computer device (e.g., processor 303 in Figure 3). It should be understood that Method 700 as illustrated may be modified by changing the order of the steps and including additional steps.

[0071]

[0081] In step 701, input data is acquired and supplied to the CGI model. The input data may correspond to images displaying metronome information collected from a first and second wafer acquired via wafer processing during HVM. Wafer processing may be lithography focus and dose conditions. The input data may include a predetermined wafer region definition. Metrology information may include, but is not limited to, necking, line pullback, line thinning, limit dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, and bridge defects on the wafer.

[0072]

[0082] In step 702, the estimated defective die probability for each die on the first wafer is calculated based on the input data of the first wafer. The calculation may be based on identified defects in the input data and may be affected by the quality of the input data. The calculation may be performed by a processor (e.g., processor 303 in Figure 3) capable of applying a CGI model to the first wafer.

[0073]

[0083] In step 703, the sampling budget for each region on the first wafer is allocated according to the estimated defect die probability for each wafer region. The calculations performed in step 703 may be as follows:

number

[0074]

[0084] In Equation 5, SB i,j represents the sampling budget for region i on the wafer, SB w This represents the sampling budget for the entire wafer. Therefore, the sampling budget for a region on the wafer may be calculated by multiplying the sampling budget for the entire wafer by the ratio of the sum of the defect die probabilities in that region of the wafer to the sum of the defect die probabilities on the entire wafer. In Equation 6,

number

[0075]

[0085] In step 704, a sampling plan for the first wafer is generated based on the wafer region definition and the allocated sampling budget for each wafer region calculated in step 703.

[0076]

[0086] In step 705, the sampling plan generated for the first wafer is used to guide the inspection of the first wafer using the inspection tool. The inspection tool collects inspection results of the first wafer according to the predicted defects identified by the sampling plan. In step 706, the CGI model predicts the die loss of the first wafer according to the inspection results collected in step 705. Die loss prediction may be performed through equations 3 and 4.

[0077]

[0087] In step 707, the estimated defective die probability for each die on the second wafer is calculated based on the input data for the second wafer. The calculation may be performed by a processor capable of applying a CGI model to the second wafer (e.g., processor 303 in Figure 3). The input data for the second wafer is as described above in step 701 and may include the wafer region definition and total sampling budget for the second wafer. The sampling budget may be allocated to each wafer region, a sampling plan may be generated based on the estimated defective die probability, and die losses may be predicted by repeating steps 703 to 706 for the second wafer.

[0078]

[0088] In step 708, once the wafer processing is complete, probe test results can be obtained for the first and second wafers. In step 709, R 2 The correlation score is evaluated by comparing the actual defective die results (e.g., actual die loss) of the first and second wafers with the estimated defective die probability (e.g., predicted die loss), as described above.

[0079]

[0089] Method 700 should be understood to provide a sampling plan that allocates a larger proportion of the total sampling budget to wafer regions identified as containing a higher density of defective and expected dies, compared to conventional methods. Therefore, the estimated defective die probability map may better agree with the ground truth results, and the resulting R 2 The correlation score may increase compared to that obtained using conventional methods.

[0080]

[0090] Now, refer to Figure 8. Figure 8 is an exemplary sampling plan or estimated defective die probability map generated by Method 700, consistent with embodiments of the present disclosure. Figure 8 corresponds to wafer 801, which includes dies 802. Each die 802 is represented as a square on wafer 801 with a black outline. As stated above, Method 700 uses a predetermined wafer region definition, so the estimated defective die probability map in Figure 8 may include, for example, the same definition and number of wafer regions as in Figure 5. Figure 8 is for illustrative purposes only, and it should be understood that wafer regions may be of any shape or size, and the number of wafer regions may not be so limited. Figure 8 is presented as a gradient image, where darker colors indicate higher defective die probabilities, and lighter colors indicate lower defective die probabilities. Figure 8 shows three wafer regions, where dotted line 803 represents the boundary of the first wafer region between the first and second wafer regions, and dotted line 804 represents the boundary of the second wafer region between the second and third wafer regions. The second wafer region (e.g., the region between dotted lines 803 and 804) shows the darkest color and therefore indicates the wafer region with the highest defect die probability. The sampling plan generated according to Method 700 (Figure 7) allocates a larger proportion of the total sampling budget to the second region and therefore directs inspection more toward the second wafer region compared to the other wafer regions. Since Method 700 can optimize the sampling budget allocation per wafer region and maintain a predetermined total sampling budget per wafer, the estimated defect die probability map in Figure 8 may show different defect die probabilities per wafer region compared to the estimated defect die probability map that could be generated for the one in Figure 5. Therefore, Figure 8 can show a more accurate die loss prediction, or an improved sampling plan, generated by optimizing the per-wafer region sampling budget allocation for wafer inspection while maintaining a predetermined wafer region definition and total per-wafer sampling budget, according to Method 700 (of Figure 7).

[0081]

[0091] Now, refer to Figure 9. Figure 9 is an exemplary flowchart of Method 900 for generating a wafer sampling plan without predetermined wafer area definitions and per-wafer area sampling budget allocation, consistent with embodiments of the present disclosure. The steps of Method 900 may be performed by a computer device (e.g., processor 303 in Figure 3). It should be understood that Method 900 as illustrated may be modified by changing the order of the steps and including additional steps.

[0082]

[0092] In step 901, input data is acquired and supplied to the CGI model. The input data may correspond to images displaying metronome information collected from a first and second wafer acquired via wafer processing during HVM. The wafer processing and metronome information may be as described above. However, the input data does not require a predetermined wafer region definition and a sampling budget allocation per wafer region.

[0083]

[0093] In step 902, the estimated defective die probability for each die on the first wafer is calculated based on the input data of the first wafer. The calculation may be based on identified defects in the input data and may be affected by the quality of the input data. The calculation may be performed by a processor (e.g., processor 303 in Figure 3) capable of applying a CGI model to the first wafer.

[0084]

[0094] In step 903, an estimated defective die probability map is generated for the first wafer by editing the defective die probabilities as described above. In step 904, the boundaries of the wafer region are evaluated to improve the uniformity of the defective die probability density on the defective die probability map. The uniformity of the defective die probability density may be improved by grouping the first die on the wafer with a second die that exhibits a similar defective die probability. Step 904 may be carried out in two optional steps. Step 904_1 may be carried out by applying the CGI generated sampling plan from step 903 and implementing an image segmentation technique, which may include, but is not limited to, graph cuts, Otsu's algorithm, edge-based segmentation, threshold-based segmentation, region-based segmentation, cluster-based segmentation, watershed segmentation, semantic segmentation, instance segmentation, panoptic segmentation, and other methods of dividing an image into multiple subgroups. The resulting image segmentation may define regions of dies on the wafer where the uniformity of the defective die probability density is improved. For example, the estimated defective die probability map or sampling plan shown in Figure 8 may correspond to the map or sampling plan generated in step 903. Instead of defining wafer region boundaries, optimizing the sampling budget allocation for each defined wafer region, and thus adjusting the resulting estimated defective die probability map, as described above, step 904_1 applies the wafer region boundaries to the estimated defective die probability map based on the radial distribution of defective die probabilities. Thus, dies on the wafer may be grouped more uniformly within the wafer regions.

[0085]

[0095] Alternatively, in step 904_2, the wafer region boundary is determined by integrating the estimated defective die probability map with respect to radial distance to generate a cumulative defective die probability map. The wafer region boundary may be evaluated by a region with a uniform slope or by a change in cumulative defective die probability. Thus, the evaluated wafer region may include dies on the wafer with similar defective die probabilities and improve the uniformity of the defective die probability density on the generated defective die probability map.

[0086]

[0096] In step 905, the sampling plan with the evaluated wafer region boundaries is used to guide the inspection of the first wafer using the inspection tool. In step 906, the CGI model predicts the die loss of the first wafer according to the inspection results collected in step 905. The die loss prediction may be performed through equations 3 and 4.

[0087]

[0097] In step 907, the estimated defective die probability for each die on the second wafer is calculated based on the input data of the second wafer. By repeating steps 903 to 906 for the second wafer, a sampling plan based on the estimated defective die probability may be generated, wafer regions may be evaluated, and die loss may be predicted. In step 908, once fully processed at the end of wafer processing, probe test results can be obtained for the first and second wafers. In step 909, R 2 The correlation score is evaluated by comparing the actual defective die results (e.g., actual die loss) of the first and second wafers with the estimated defective die probability (e.g., predicted die loss), as described above.

[0088]

[0098] Method 900 should be understood as being able to provide a sampling plan with increased versatility for different wafers. The evaluated wafer region of Method 900 can be decoupled from the predetermined and constant wafer region definition of conventional methods, and the inspection can be directed toward areas with a larger defect die probability.

[0089]

[0099] Refer now to Figures 10A and 10B. These figures are exemplary estimated defective die probability maps and exemplary cumulative defective die probability plots used to evaluate wafer region definitions consistent with embodiments of the present disclosure. Figure 10A may show step 903 of method 900 (see Figure 9). As shown in Figure 10A, the defective die probability map of wafer 1001 may include a first probability boundary 1002 and a second probability boundary 1003 indicating differences in defective die probabilities. For example, the first probability boundary 1002 shows separation from areas of wafer 1001 with higher defective die probabilities (e.g., shown as gray) and areas of wafer 1001 with lower defective die probabilities (e.g., shown as white). The same may be observed for the second probability boundary 1003. The radial distance 1004 is shown as starting from the center of wafer 1001, passing through the first probability boundary 1002, passing through the second probability boundary 1003, and ending at the edge of wafer 1001 (e.g., the radius of wafer 1001).

[0090]

[0100] Now, refer to Figure 10B. Figure 10B is an exemplary figure consistent with embodiments of the present disclosure, in which wafer region definitions are evaluated by integrating a wafer defect die probability map with respect to radial distance. Figure 10B may correspond to step 904_2 of Method 900 (see Figure 9). The plot shown in Figure 10B may be obtained by integrating the wafer defect die probability map of wafer 1001 shown in Figure 10A with respect to radial distance 1004. Thus, Figure 10B represents the cumulative defect die probability 1005 as a function of the radial distance 1004 of wafer 1001. The multiple dotted lines in Figure 10B, starting from the origin and appearing from left to right, represent the first probability boundary 1002, then the second probability boundary 1003, and the edge of wafer 1001. Since the radial distance 1004 starts at the center of wafer 1001, the cumulative defect die probability 1005 starts at 0 and increases as the radial distance 1004 increases. The radial distance between the origin and the first probability boundary 1002 may correspond to the first wafer region 1006, which may correspond to the gray area enclosed by the first probability boundary 1002 in Figure 10A. The same can be observed for the second wafer region 1007 and the third wafer region 1008. Since the first wafer region 1006 has a higher concentration or density of defects according to Figure 10A, the first wafer region 1006 shows a steeper slope in the plotted cumulative defective die probability. The same can be observed for the third wafer region 1008. Since the second wafer region 1007 showed a lower density of defective die probability in Figure 10A, the slope in the corresponding section in Figure 10B is gentler. The difference in slopes in each region in Figure 10B may be used to evaluate the wafer region definition of wafer 1001. In some embodiments, the wafer region may be defined such that the defective die probability density is uniform within the wafer region. For example, as shown in Figure 10B, this may correspond to the slope of the cumulative defective die probability plotted across the entire wafer region remaining constant. Then, wafer region boundaries may be applied to the defective die probability map at the corresponding radial distances (e.g., wafer region boundaries 803 and 804 in Figure 8).

[0091]

[0101] Now, refer to Figure 11. Figure 11 shows a die loss prediction R consistent with the embodiments of this disclosure. 2 This is an illustrative flowchart of Method 1100, which directly optimizes wafer region definition and sampling budget allocation based on correlation scores. Method 1100 uses parameterized wafer region definition variables and wafer region-specific sampling budget variables as optimization variables to predict die loss R based on a wafer training set. 2 The correlation score may be optimized. Method 1100 is used for wafers that have been inspected using an inspection tool according to a sampling plan generated by CGI and inspected via probe testing to obtain ground truth results, 2 This may be performed after the correlation score has been obtained. 2 The correlation score is used to guide the optimization of parameterized wafer area definition variables and sampling budget allocation variables, so the wafer may be called a “training wafer.” Method 1100 may be performed without a predetermined wafer area definition and per-wafer area sampling budget allocation. The steps of Method 1100 may be performed by a computer device (e.g., processor 303 in Figure 3). It should be understood that Method 1100 as illustrated may be modified by changing the order of the steps and including additional steps.

[0092]

[0102] In step 1101, input data is supplied to the CGI model. The input data may include probe test results and images of the training wafer obtained through wafer processing, including the metronome information described above.

[0093]

[0103] In step 1102, the wafer region definition and the sampling budget per wafer region are parameterized for the training wafer. For example, the wafer region definition may be parameterized if the wafer contains two wafer region variables. These parameterized variables may be r1 and r2, where r1 is the radial distance from the center of the wafer to the first wafer region boundary, and r2 is the radial distance from the center of the wafer to the second wafer region boundary. Given this definition, r1 is less than r2 and 0 <r1、r2<r max Constrained by, here r max r is the maximum radial distance from the center of the wafer to the edge of the wafer. max It may be 150 mm. The third wafer region is r2 and r max It should be understood that it is defined by the radial distance between them. It should also be understood that a wafer may contain fewer than three or more wafer regions. The sampling budget per wafer region may be parameterized to variables N1, N2, and N3, where N1 corresponds to the sampling budget for the first wafer region, N2 corresponds to the sampling budget for the second wafer region, and N3 corresponds to the sampling budget for the third wafer region. N1, N2, and N3 may be constrained so that the sampling budget for a wafer region does not exceed the total number of dies in the wafer region, where N1 + N2 + N3 = N budget And here N budget This is the predetermined total sampling budget for wafers to be tested.

[0094]

[0104] In step 1103, the parameterized wafer region variable and the parameterized wafer region sampling budget variable are used in R 2The optimization is optimized to maximize the correlation score. The optimization is an arbitrary constrained global optimization technique that uses a forward solver to parameterize wafer region variables or parameterized wafer region-specific sampling budget variables based on the training wafer and the defect die loss R 2 This may be carried out by a constrained global optimization technique that maps to correlation scores. Constrained global optimization techniques include, but are not limited to, Bayesian optimization, coordinate descent, adaptive coordinate descent, cuckoo search, beetle antenna search, online nonlinear extremum search for databases, evolutionary strategies, genetic algorithms, multilevel coordinate search algorithms, Nelder-Mead method, particle swarm optimization, pattern search, random search, simulated annealing, stochastic optimization, subgradient methods, or any other derivative-free optimization algorithm. Step 1103 is performed using the maximum R 2 This process may be repeated until the parameterized variables described above are simultaneously optimized to produce a correlation score.

[0095]

[0105] In step 1104, a sampling plan is generated using concurrently optimized parameterized wafer region variables and wafer region sampling budget variables. In step 1105, the generated sampling plan is applied to the first and second wafers in the test set to guide the inspection of the first and second wafers in the test set. The updated sampling plan may show different wafer region definitions and wafer region sampling budget allocations compared to the sampling plan used to guide the inspection of the training wafers before method 1100 was performed.

[0096]

[0106] In step 1106, the die loss of the first and second wafers in the test set is predicted using the test results collected for the first and second wafers in the test set. The die loss prediction may be performed through equations 3 and 4. In step 1107, after the wafer processing is complete, the actual die loss is obtained by collecting the probe test results of the first and second wafers in the test set. In step 1108, verification R 2 The correlation score is evaluated. Validation R 2 The correlation score is calculated using the starting R of method 1100. 2 It is compared with the correlation score. Validation R 2 The correlation score is at the start of R 2 If the correlation score is higher, the concurrently optimized parameterized wafer region variables and wafer region-specific sampling budget allocation variables may be applied to the wafer for subsequent wafer processing.

[0097]

[0107] Method 1100 should be understood as providing an optimization-based technique for generating optimal fixed sampling plan settings (e.g., wafer region definitions or sampling budget allocations) that offer improved versatility for predicting defective dies on different wafers with enhanced accuracy. It should also be understood that optimized parameterized wafer region definitions and sampling budget definitions determined from Method 700 or Method 900 can be applied as initial inferences in Method 1100. This may reduce the time and computational costs associated with the optimization of Method 1100.

[0098]

[0108] Refer to Table 1 here. Table 1 shows the R values ​​determined by methods 600 and 700 of this disclosure compared to conventional methods for three wafer datasets. 2This demonstrates an improvement in correlation scores. Specifically, each dataset includes a batch of more than 100 wafers from which a sampling plan is generated to guide inspection according to Methods 600 and 700 of this disclosure. For a portion of the wafers in batch 1 of dataset 1, the predicted die loss was calculated and probe test results were obtained, while for each wafer in datasets 2 and 3, the predicted die loss was calculated and probe test results were obtained. It should be understood that the die loss was predicted for both Methods 600 and 700 using Equations 3 and 4 (assuming, for example, a non-uniform defect density or distribution). 2 The correlation score was determined as described above. If either Method 600 or Method 700 was applied instead of the conventional method, R was applied to each dataset of wafers. 2 It was found that the correlation score improved. For all three datasets when Method 600 was applied, R was improved compared to the conventional method. 2 The improved correlation score indicates that assuming a heterogeneous defect density or distribution is beneficial in die loss prediction. 2 The correlation scores were shown to be further improved for datasets 2 and 3 when method 700 was applied compared to method 600. Therefore, R 2 The correlation score may be further improved by applying model-based sampling budget allocation, in addition to assuming a non-uniform defect density or distribution in die loss prediction.

[0099] [Table 1]

[0100]

[0110] The advantages provided by the embodiments of this disclosure are that, without the need for input variables, the R of the actual die loss is improved compared to the predicted die loss using a CGI model. 2 A correlation score may be obtained. In some embodiments, the disclosure predicts die loss without assuming that the defect density or distribution is uniform within the wafer region, and R 2Methods for improving correlation scores may be provided. In some embodiments, the wafer sampling budget allocation or wafer region definition is optimized to improve R 2 The correlation score may be improved. In some embodiments, R 2 An optimization-based model is provided that can further improve the correlation score. Some embodiments of this disclosure may provide a method for improving the performance and versatility of a CGI model to guide wafer inspection. Some embodiments of this disclosure may provide a method for improving the accuracy of defect inspection and the yield of defect-free wafers across the entire HVM.

[0101]

[0111] Non-temporary computer-readable media may be provided which, among other things, store instructions for the processor of a controller (e.g., controller 109 in Figure 1) to perform image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, focusing lens adjustment, activation of charged particle sources, beam deflection; determine sample input data, perform method 600 in Figure 6, perform method 700 in Figure 7, perform method 900 in Figure 9, perform method 1100 in Figure 1100; and perform other executable functions relating to wafer area definition for inspection in HVM or modeling and optimization of per-wafer area sampling budget allocation. Common forms of non-temporary media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, compact disk read-only memory (CD-ROM), any other optical data storage media, any physical media having a pattern of holes, random access memory (RAM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM), flash EPROM or any other flash memory, non-volatile random access memory (NVRAM), caches, registers, any other memory chips or cartridges, and network-connected versions thereof.

[0102]

[0112] Embodiments may be further described using the following clauses. 1. A method for generating a sampling plan for an inspection tool, Providing wafer input data to a computational defect probability prediction model, Dividing a wafer into multiple wafer regions having multiple dies, Calculating the defect die probability for each wafer region from a computational defect probability prediction model, Using the calculated defective die probability, select at least one die from each wafer region of multiple wafer regions, A method comprising generating a wafer sampling plan based on a selected die. 2. The input data is as described in Clause 1, including an image containing wafer metronome information. 3. The input data is as described in Clause 1 or 2, including a predetermined wafer area definition and a sampling budget for each wafer area. 4. Using the calculated defective die probability, it is further possible to select at least one die from each wafer region of multiple wafer regions. Ranking the calculated defect die probability for each wafer region, The method according to Clause 3, comprising selecting the number of dies for each wafer region of multiple wafer regions based on the calculated ranking of defective die probabilities, wherein the number of dies is less than or equal to the sampling budget for each wafer region. 5. Using a sampling plan to guide wafer inspection, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 1 to 4, further comprising evaluating the correlation score. 6. The predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer, as described in Clause 5. 7. The inspection tool is a scanning charged particle microscope or an optical tool, as described in any one of the items 1 to 6. 8. The computational defect probability prediction model is a computational guided test model, as described in any one of the provisions 1 to 7. 9. A method for optimizing the sampling plan of an inspection tool, Providing wafer input data to a computational defect probability prediction model, This includes allocating a sampling budget for a region of a wafer based on the expected number of defective die counts in that region compared to the expected number of defective die counts in the wafer, The expected number of defective die counts in that region is the sum of the predicted defective die probabilities in that region, and the expected number of defective die counts for that wafer is the sum of the predicted defective die probabilities for that wafer. The predicted defect die probability for that region and the predicted defect die probability for that wafer are obtained from a computational defect probability prediction model. 10. The input data includes an image containing wafer metronome information, as described in Clause 9. 11. Input data as described in Clause 9 or 10, including a predetermined wafer area definition and sampling budget for the wafer. 12. To generate a sampling plan and guide wafer inspection of wafers, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 9 to 11, further comprising evaluating the correlation score. 13. The inspection tool is a scanning charged particle microscope or an optical tool, as described in any one of the provisions of Clauses 9 to 12. 14. A computational defect probability prediction model is a computational guided test model, as described in any one of the provisions 9 to 13. 15. A method for optimizing the sampling plan of an inspection tool, Providing wafer input data to a computational defect probability prediction model, The process involves calculating the defect die probability for each die of a wafer using a computational defect probability prediction model, and Generating a sampling plan, Evaluating wafer regions from the defect die probability of each die on the wafer, Evaluate the sampling budget allocation for each evaluated wafer region, A method comprising guiding wafer inspection of a wafer using a sampling plan along with evaluated wafer areas and sampling budget allocation. 16. Input data as described in Clause 15, including an image containing wafer metronome information. 17. Input data as described in Clause 15 or 16, including a predetermined sampling budget for the wafer. 18. The method according to any one of the clauses 15 to 17, wherein the wafer area is evaluated by integrating the calculated defective die probability of each die on the wafer over the radial direction on the wafer. 19. The wafer region is evaluated by image segmentation of the calculated defective die probability of each die of the wafer, as described in any one of clauses 15 to 17. 20. Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The method described in any one of clauses 15 to 19, further comprising evaluating the correlation score. 21. The inspection tool is a scanning charged particle microscope or an optical tool, as described in any one of the clauses 15 to 20. 22. A computational defect probability prediction model is a computational guided test model, as described in any one of the provisions 15 to 21. 23. A method for optimizing the sampling plan of an inspection tool, Providing wafer input data to a computational defect probability prediction model, Parameterizing the wafer region definition and the wafer region sampling budget, wherein the parameterized wafer region definition and wafer region sampling budget have certain constraints. A method including optimizing a wafer area definition parameterized according to the specific constraints and a sampling budget of the parameterized wafer area to maximize a predicted value. 24. The method according to clause 23, wherein the input data includes probe test results of the wafer. 25. The input data is R 2 The method according to clause 23 or 24, wherein the input data includes a correlation score. 26. The method according to any one of clauses 23 to 25, wherein the wafer area definition is parameterized using a first variable and a second variable. 27. The first variable is r1 and the second variable is r2 、 The method according to clause 26, wherein r1 is the radial distance from the center of the wafer to the first wafer area boundary, and r2 is the radial distance from the center of the wafer to the second wafer area boundary. 28. The constraints on the first variable and the second variable are 0 < r1, r2 < r max including, r max The method according to clause 27, wherein r is the radius of the wafer. 29. The method according to clause 27 or 28, wherein the constraints on the first variable and the second variable include r1 < r2. 30. The method according to any one of clauses 23 to 29, wherein the sampling budget of the wafer area on the wafer is parameterized using a first variable, a second variable, and a third variable. 31. The first variable is N1, the second variable is N2, and the third variable is N3. N1 is the sampling budget of the first wafer area, N2 is the sampling budget of the second wafer area, and N3 is the sampling budget of the third wafer area. The method according to clause 30. 32. The constraints on N1, N2, and N3 include N1 + N2 + N3 = N budget including, N budget The method according to clause 31, wherein N is the total sampling budget of the wafer. 33. The method according to Clause 31 or 32, wherein N1, N2, and N3 are less than the total number of dies in the first wafer region, the second wafer region, and the third wafer region, respectively. 34. Optimizing the parameterized wafer region definition and the sampling budget of the parameterized wafer region, including the use of constrained global optimization techniques, as described in any one of the provisions of Clauses 23 to 33. 35. A constrained global optimization technique is a derivative-free optimization algorithm as described in Clause 34. 36. The predicted values ​​were generated by optimizing the parameterized wafer region definition and the sampling budget of the parameterized wafer region. 2 The correlation score is determined by the method described in any one of clauses 23 to 35. 37. To generate a sampling plan and guide the wafer inspection of the second wafer, Using the inspection results of the second wafer, calculate the predicted die loss, To obtain the probe test results for the second wafer, R 2 The method described in any one of clauses 23 to 36, further comprising evaluating the correlation score. 38. The inspection tool is a scanning charged particle microscope or an optical tool, as described in any one of the provisions of Clauses 23 to 37. 39. A computational defect probability prediction model is a computational guided test model, as described in any one of the provisions 23 to 38. 40. Apparatus for generating inspection tool sampling plans, A memory for storing a set of instructions, and At least one processor, which executes a set of instructions, to the device, Providing wafer input data to a computational defect probability prediction model, Dividing a wafer into multiple wafer regions having multiple dies, Calculating the defect die probability for each wafer region from a computational defect probability prediction model, Using the calculated defective die probability, select at least one die from each wafer region of multiple wafer regions, An apparatus including at least one processor configured to perform operations including generating a wafer sampling plan based on a selected die. 41. The apparatus described in Clause 40, the input data includes an image containing wafer metronome information. 42. The apparatus as described in Clause 40 or 41, wherein the input data includes a predetermined wafer area definition and a sampling budget per wafer area. 43. Using the calculated defective die probability, at least one die can be selected from each wafer region of multiple wafer regions. Ranking the calculated defect die probability for each die in each wafer region, The apparatus according to Clause 42, further comprising selecting the number of dies for each wafer region of a plurality of wafer regions based on the calculated ranking of defective die probabilities, wherein the number of dies is less than or equal to the sampling budget for each wafer region. 44. The operation is, Using a sampling plan to guide wafer inspection, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The apparatus described in any one of clauses 40 to 43, further comprising evaluating the correlation score. 45. The apparatus described in Clause 44, in which the predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer. 46. ​​The inspection tool is a scanning charged particle microscope or an optical tool, as described in any one of the clauses 40 to 45. 47. The computational defect probability prediction model is a computational guided inspection model, as described in any one of clauses 40 to 46. 48. Apparatus for optimizing the sampling plan of inspection tools, A memory for storing a set of instructions, and At least one processor, which executes a set of instructions, to the device, Providing wafer input data to a computational defect probability prediction model, Includes at least one processor configured to perform an operation that includes allocating a sampling budget for a region of a wafer based on the expected number of defective die counts in that region compared to the expected number of defective die counts in that wafer, The expected number of defective die counts in that region is the sum of the predicted defective die probabilities in that region, and the expected number of defective die counts for that wafer is the sum of the predicted defective die probabilities for that wafer. The predicted defect die probability for that region and the predicted defect die probability for that wafer are obtained from a computational defect probability prediction model in the apparatus. 49. The apparatus described in Clause 48, in which the input data includes an image containing wafer metronome information. 50. The apparatus described in Clause 48 or 49, the input data including a predetermined wafer area definition and sampling budget of the wafer. 51. The operation is, To generate a sampling plan and guide wafer inspection of wafers, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The apparatus described in any one of clauses 48 to 50, further comprising evaluating the correlation score. 52. The inspection tool is a scanning charged particle microscope or an optical tool, as described in any one of the clauses 48 to 51. 53. The computational defect probability prediction model is a computational guided inspection model, as described in any one of clauses 48 to 52. 54. Apparatus for optimizing the sampling plan of inspection tools, A memory for storing a set of instructions, and At least one processor, which executes a set of instructions, to the device, Providing wafer input data to a computational defect probability prediction model, The process involves calculating the defect die probability for each die of a wafer using a computational defect probability prediction model, and Generating a sampling plan, Evaluating wafer regions from the defect die probability of each die on the wafer, Evaluate the sampling budget allocation for each evaluated wafer region, An apparatus including at least one processor configured to perform operations including guiding wafer inspection of a wafer using a sampling plan along with evaluated wafer regions and sampling budget allocation. 55. The apparatus described in Clause 54, in which the input data includes an image containing wafer metronome information. 56. The apparatus described in Clause 54 or 55, including a predetermined sampling budget for the wafer as input data. 57. The apparatus described in any one of clauses 54 to 56, wherein the wafer area is evaluated by integrating the calculated defective die probability of each die on the wafer over the radial direction on the wafer. 58. Apparatus described in any one of clauses 54 to 56, wherein the wafer region is evaluated by image segmentation of the generated defect die probability map of the wafer. 59. The operation is, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 The apparatus described in any one of clauses 54 to 58, further comprising evaluating the correlation score. 60. The inspection tool is a scanning charged particle microscope or an optical tool, as described in any one of the clauses 54 to 59. 61. The computational defect probability prediction model is a computational guided inspection model, as described in any one of clauses 54 to 60. 62. Apparatus for optimizing the sampling plan of inspection tools, A memory for storing a set of instructions, and At least one processor, which executes a set of instructions, to the device, Providing wafer input data to a computational defect probability prediction model, Parameterizing the wafer region definition and the wafer region sampling budget, wherein the parameterized wafer region definition and wafer region sampling budget have certain constraints. An apparatus including at least one processor configured to perform operations including optimizing a parameterized wafer region definition and a sampling budget for the parameterized wafer region in accordance with specific constraints to maximize predicted values. 63. Input data, including wafer probe test results, for the apparatus as described in Clause 62. 64. Input data is R 2 The apparatus according to clause 62 or 63, including a correlation score. 65. The apparatus described in any one of clauses 62 to 64, wherein the wafer area definition is parameterized using a first variable and a second variable. 66. The first variable is r1, and the second variable is r2. 、 The apparatus according to Clause 65, where r1 is the radial distance from the center of the wafer to the first wafer region boundary, and r2 is the radial distance from the center of the wafer to the second wafer region boundary. 67. The constraints on the first and second variables are 0 <r1、r2<r max Includes, r max The apparatus as described in Clause 66, wherein the radius is that of the wafer. 68. The apparatus according to clause 66 or 67, where the constraints on the first variable and the second variable include r1 < r2. 69. The apparatus according to any one of clauses 62 - 68, where the sampling budget of the wafer regions on the wafer is parameterized using the first variable, the second variable, and the third variable. 70. The apparatus according to clause 69, where the first variable is N1, the second variable is N2, the third variable is N3, N1 is the sampling budget of the first wafer region, N2 is the sampling budget of the second wafer region, and N3 is the sampling budget of the third wafer region. 71. The constraints on N1, N2, and N3 include N1 + N2 + N3 = N budget where N budget is the total sampling budget of the wafer. The apparatus according to clause 70. 72. The apparatus according to clause 70 or 71, where N1, N2, and N3 are each less than the total number of dies in the first wafer region, the second wafer region, and the third wafer region, respectively. 73. Optimizing the parameterized wafer region definition and the sampling budget of the parameterized wafer region includes using constrained global optimization techniques. The apparatus according to any one of clauses 62 - 72. 74. The constrained global optimization technique is a derivative - free optimization algorithm. The apparatus according to clause 73. 75. The predicted value is the R 2 correlation score generated by optimizing the parameterized wafer region definition and the sampling budget of the parameterized wafer region. The apparatus according to any one of clauses 62 - 74. 76. The operations are generating a sampling plan to guide the wafer inspection of the second wafer, calculating the predicted die loss using the inspection results of the second wafer, obtaining the probe test results of the second wafer, R 2The apparatus described in any one of clauses 62 to 75, further comprising evaluating the correlation score. 77. The inspection tool is a scanning charged particle microscope or an optical tool, as described in any one of the clauses 62 to 76. 78. The computational defect probability prediction model is a computational guided inspection model, as described in any one of clauses 62 to 77. 79. A non-temporary computer-readable medium containing a set of instructions executable by one or more processors of a computer device to cause the computer device to perform an action for generating an inspection tool sampling plan, wherein the action is: Providing wafer input data to a computational defect probability prediction model, Dividing a wafer into multiple wafer regions having multiple dies, Calculating the defect die probability for each wafer region from a computational defect probability prediction model, Using the calculated defective die probability, select at least one die from each wafer region of multiple wafer regions, A non-temporary computer-readable medium, including generating a wafer sampling plan based on a selected die. 80. Input data includes images containing wafer metrology information, in non-temporary computer-readable media as described in Clause 79. 81. Input data is a non-temporary computer-readable medium as described in Clause 79 or 80, including a predetermined wafer area definition and a sampling budget per wafer area. 82. Using the calculated defective die probability, at least one die can be selected from each wafer region of multiple wafer regions. Ranking the calculated defect die probability for each die in each wafer region, A non-temporary computer-readable medium as described in Clause 81, further comprising selecting the number of dies for each wafer region of a plurality of wafer regions based on a calculated ranking of the defect die probability, wherein the number of dies is less than or equal to the sampling budget for each wafer region. 83. The operation is, Using a sampling plan to guide wafer inspection, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 A non-temporary computer-readable medium as described in any one of clauses 79 to 82, further including the evaluation of correlation scores. 84. Predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer, as described in the non-transient computer-readable media of Clause 83. 85. The inspection tool is a scanning charged particle microscope or an optical tool, a non-temporary computer-readable medium as described in any one of clauses 79 to 82. 86. A computational defect probability prediction model is a computational guided inspection model, provided for a non-temporary computer-readable medium as described in any one of clauses 79-85. 87. A non-temporary computer-readable medium containing a set of instructions executable by one or more processors of a computer device to cause the computer device to perform an action to optimize the inspection tool sampling plan, wherein the action is: Providing wafer input data to a computational defect probability prediction model, This includes allocating a sampling budget for a region of a wafer based on the expected number of defective die counts in that region compared to the expected number of defective die counts in the wafer, The expected number of defective die counts in that region is the sum of the predicted defective die probabilities in that region, and the expected number of defective die counts for that wafer is the sum of the predicted defective die probabilities for that wafer. The predicted defect die probability for that region and the predicted defect die probability for that wafer are obtained from a computational defect probability prediction model in a non-temporal, computer-readable medium. 88. Input data includes images containing wafer metrology information, in non-temporary computer-readable media as described in Clause 87. 89. Input data is a non-temporary computer-readable medium as described in Clause 87 or 88, including a predetermined wafer area definition and sampling budget of the wafer. 90. The operation is, To generate a sampling plan and guide wafer inspection of wafers, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 A non-temporary computer-readable medium as described in any one of clauses 87 to 89, further including the evaluation of correlation scores. 91. The inspection tool is a scanning charged particle microscope or an optical tool, a non-temporary computer-readable medium as described in any one of clauses 87 to 90. 92. A computational defect probability prediction model is a computational guided inspection model, provided for a non-temporary computer-readable medium as described in any one of clauses 87-91. 93. A non-temporary computer-readable medium containing a set of instructions executable by one or more processors of a computer device to cause the computer device to perform an action to optimize the inspection tool sampling plan, wherein the action is: Providing wafer input data to a computational defect probability prediction model, The process involves calculating the defect die probability for each die of a wafer using a computational defect probability prediction model, and Generating a sampling plan, Evaluating wafer regions from the defect die probability of each die on the wafer, Evaluate the sampling budget allocation for each evaluated wafer region, A non-temporary computer-readable medium, including guiding wafer inspection of a wafer using a sampling plan along with evaluated wafer areas and evaluated sampling budget allocation. 94. Input data includes images containing wafer metrology information, in non-temporary computer-readable media as described in Clause 93. 95. Input data shall be a non-temporary computer-readable medium as described in Clause 93 or 94, including a predetermined sampling budget for the wafer. 96. A non-temporary computer-readable medium as described in any one of clauses 93 to 95, where the wafer area is evaluated by integrating the calculated defective die probability of each die on the wafer over the radial direction on the wafer. 97. A non-temporary computer-readable medium as described in any one of clauses 93 to 95, where the wafer area is evaluated by image segmentation of the generated defect die probability map of the wafer. 98. The operation is, Using wafer inspection results, calculate the predicted die loss, Obtaining wafer probe test results, By comparing the probe test results with the predicted die loss, R 2 A non-temporary computer-readable medium as described in any one of clauses 93 to 97, further including the evaluation of correlation scores. 99. The inspection tool is a scanning charged particle microscope or an optical tool, a non-temporary computer-readable medium as described in any one of clauses 93 to 98. 100. A computational defect probability prediction model is a computational guided inspection model, provided for non-temporary computer-readable media as described in any one of clauses 93-99. 101. A non-temporary computer-readable medium containing a set of instructions executable by one or more processors of a computer device to cause the computer device to perform an action to optimize the inspection tool sampling plan, wherein the action is: Providing wafer input data to a computational defect probability prediction model, Parameterizing the wafer region definition and the wafer region sampling budget, wherein the parameterized wafer region definition and wafer region sampling budget have certain constraints. A non - transient computer - readable medium, including optimizing a wafer area definition parameterized according to the specific constraints and a sampling budget of the parameterized wafer area to maximize a predicted value. 102. The input data is the non - transient computer - readable medium according to clause 101, including the probe test results of the wafer. 103. The input data is R 2 The non - transient computer - readable medium according to clause 101 or 102, including a correlation score. 104. The wafer area definition is parameterized using a first variable and a second variable, and is the non - transient computer - readable medium according to any one of clauses 101 - 103. 105. The first variable is r1 and the second variable is r2 、 r1 is the radial distance from the center of the wafer to the first wafer area boundary, and r2 is the radial distance from the center of the wafer to the second wafer area boundary, and is the non - transient computer - readable medium according to clause 104. 106. The constraints on the first variable and the second variable are 0 < r1, r2 < r max including, r max is the radius of the wafer, and is the non - transient computer - readable medium according to clause 105. 107. The constraints on the first variable and the second variable include r1 < r2, and is the non - transient computer - readable medium according to clause 105 or 106. 108. The sampling budget of the wafer area on the wafer is parameterized using a first variable, a second variable, and a third variable, and is the non - transient computer - readable medium according to any one of clauses 101 - 107. 109. The first variable is N1, the second variable is N2, the third variable is N3, N1 is the sampling budget of the first wafer area, N2 is the sampling budget of the second wafer area, and N3 is the sampling budget of the third wafer area, and is the non - transient computer - readable medium according to clause 108. 110. The constraints on N1, N2, and N3 are N1 + N2+N3 = Nbudget Including N budget This is the total sampling budget of the wafer, as defined in Clause 109, for non-temporary computer-readable media. 111. Non-temporary computer-readable media as described in Clause 109 or 110, wherein N1, N2, and N3 are less than the total number of dies in the first wafer region, the second wafer region, and the third wafer region, respectively. 112. Optimizing parameterized wafer area definitions and sampling budgets for parameterized wafer areas, including using constrained global optimization techniques, in a non-temporary computer-readable medium as described in any one of Clauses 101 to 111. 113. Constrained global optimization techniques are derivative-free optimization algorithms, as described in Clause 112 for non-temporal computer-readable media. 114. Predicted values ​​were generated by optimizing the parameterized wafer region definition and the sampling budget of the parameterized wafer region. 2 A correlation score, which is a non-temporary computer-readable medium as described in any one of clauses 101 to 113. 115. The operation is, To generate a sampling plan and guide the wafer inspection of the second wafer, Using the inspection results of the second wafer, calculate the predicted die loss, To obtain the probe test results for the second wafer, R 2 A non-temporary computer-readable medium as described in any one of clauses 101 to 114, further including the evaluation of correlation scores. 116. The inspection tool is a scanning charged particle microscope or an optical tool, a non-temporary computer-readable medium as described in any one of clauses 101 to 115. 117. A computational defect probability prediction model is a computational guided inspection model, provided for a non-temporary computer-readable medium as described in any one of clauses 101 to 116. 118. A system for generating inspection tool sampling plans using a computational model, One or more processors, in this system, Providing wafer input data to a computational defect probability prediction model, Dividing a wafer into multiple wafer regions having multiple dies, Calculating the defect die probability for each wafer region from a computational defect probability prediction model, Using the calculated defective die probability, select at least one die from each wafer region of multiple wafer regions, A system comprising one or more processors configured to generate a wafer sampling plan based on a selected die and to execute instructions to carry out this plan.

[0103]

[0113] The block diagrams in the figures may illustrate the architecture, functionality, and operation of possible embodiments of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in the schematic diagram may represent a specific arithmetic or logical operation that may be implemented using hardware such as electronic circuits. A block may also represent a module, segment, or portion of code containing one or more executable instructions for performing a specified logical function. In some alternative embodiments, the functions shown in the blocks may occur in an order different from the order shown in the figures. For example, depending on the functions involved, two consecutively shown blocks may be executed or performed substantially simultaneously, or two blocks may sometimes be executed in reverse order. Some blocks may be omitted. It should also be understood that each block in the block diagram, and combinations of blocks, may be implemented by a dedicated hardware-based system or by a combination of dedicated hardware and computer instructions to perform a specified function or operation.

[0104]

[0114] It will be understood that the embodiments of this disclosure are not limited to the structures shown above and in the accompanying drawings, and that various modifications and variations can be made without departing from their scope. Although this disclosure has been described in relation to various embodiments, other embodiments will be apparent to those skilled in the art from examining the specifications and practices of the technology disclosed herein. This specification and examples are to be considered merely illustrative, and the true scope and spirit of this disclosure are intended to be shown by the following claims.

Claims

1. A device for generating an inspection tool sampling plan, A memory for storing a set of instructions, and At least one processor, which executes the set of instructions to the device, Providing wafer input data to a computational defect probability prediction model, The wafer is divided into multiple wafer regions having multiple dies, The defective die probability for each wafer region is calculated from the aforementioned computational defect probability prediction model, Using the calculated defective die probability, select at least one die from each wafer region of the plurality of wafer regions. To generate a sampling plan for the wafer based on the selected die, At least one processor configured to perform operations including, A device that includes this.

2. The apparatus according to claim 1, wherein the input data includes an image containing the metronome information of the wafer.

3. The apparatus according to claim 1, wherein the input data includes a predetermined wafer region definition and a sampling budget for each wafer region.

4. Using the calculated defective die probability, selecting at least one die from each wafer region of the plurality of wafer regions is: Ranking the calculated defect die probability for each die in each wafer region, For each of the plurality of wafer regions, the number of dies is selected based on the ranking of the calculated defective die probabilities, wherein the number of dies is less than or equal to the sampling budget for each of the wafer regions. The apparatus according to claim 3, further comprising:

5. The aforementioned operation is, Using the sampling plan described above, the wafer inspection of the wafer is guided, Using the inspection results of the wafer, the predicted die loss is calculated, To obtain the probe test results of the aforementioned wafer, By comparing the probe test results with the predicted die loss, R ２ Evaluating the correlation score, The apparatus according to claim 1, further comprising:

6. The apparatus according to claim 5, wherein the predicted die loss is calculated by assuming a non-uniform defect density or distribution in the wafer.

7. The apparatus according to claim 1, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

8. The apparatus according to claim 1, wherein the computational defect probability prediction model is a computational guided inspection model.

9. A device for optimizing the sampling plan of inspection tools, A memory for storing a set of instructions, and At least one processor, which executes the set of instructions to the device, Providing wafer input data to a computational defect probability prediction model, The sampling budget for a given region of a wafer is allocated based on the expected number of defective die counts in that region compared to the expected number of defective die counts in the wafer. At least one processor configured to perform operations including, Includes, The expected number for the defect die count in the region is the sum of the predicted defect die probabilities for the region, and the expected number for the defect die count of the wafer is the sum of the predicted defect die probabilities for the wafer. The predicted defect die probability of the region and the predicted defect die probability of the wafer are obtained from the computational defect probability prediction model of the apparatus.

10. The apparatus according to claim 9, wherein the input data includes an image containing the metronome information of the wafer.

11. The apparatus according to claim 9, wherein the input data includes a predetermined wafer region definition and sampling budget of the wafer.

12. The aforementioned operation is, To generate a sampling plan and guide the wafer inspection of the wafer, Using the inspection results of the wafer, the predicted die loss is calculated, To obtain the probe test results of the aforementioned wafer, By comparing the probe test results with the predicted die loss, R ２ Evaluating the correlation score, The apparatus according to claim 9, further comprising:

13. The apparatus according to claim 9, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

14. The apparatus according to claim 9, wherein the computational defect probability prediction model is a computational guided inspection model.

15. A device for optimizing the sampling plan of inspection tools, A memory for storing a set of instructions, and At least one processor, which executes the set of instructions to the device, Providing wafer input data to a computational defect probability prediction model, The defective die probability of each die of the wafer is calculated from the computational defect probability prediction model, Generating a sampling plan, Evaluating the wafer region from the defect die probability of each die of the wafer, Evaluate the sampling budget allocation for each evaluated wafer region, Using the sampling plan along with the evaluated wafer area and the sampling budget allocation, the wafer inspection of the wafer is guided. At least one processor configured to perform operations including, A device that includes this.

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