Hetero-epitaxial semiconductor devices with high heat dissipation

Abstract

A method for forming a semiconductor device structure includes the step of forming a pattern on the surface of a semiconductor substrate, wherein the semiconductor substrate comprises a material having a thermal conductivity of more than about 50 W / m·K. The method further includes the steps of conformally forming a heteroepitaxial layer structure on the surface of the semiconductor substrate and forming a semiconductor device on the heteroepitaxial layer structure. Semiconductor device structures according to some embodiments include a semiconductor substrate having a patterned surface. The semiconductor substrate is formed of a material having a thermal conductivity of more than about 50 W / m·K. The device structure comprises a heteroepitaxial layer structure conformally formed on the patterned surface of the semiconductor substrate and at least one metal contact on the heteroepitaxial layer structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices formed on a heteroepitaxial structure.

Background Art

[0002] Semiconductor devices such as high electron mobility transistors (HEMTs), metal oxide semiconductor field effect transistors (MOSFETs), metal semiconductor field effect transistors (MESFETs), and junction field effect transistors (JFETs), and other devices may be formed on or within a heteroepitaxial semiconductor structure.

[0003] FIG. 1 shows a simplified cross-section of an exemplary GaN-based high electron mobility transistor (HEMT) 100 comprising a silicon carbide substrate. The HEMT 100 is formed in a semiconductor epitaxial structure 115 comprising a plurality of epitaxial layers 116, 118 of group III nitride materials on a substrate 102. The HEMT 100 is specifically formed in an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) material system, and the substrate 102 is formed of silicon carbide (SiC). The substrate 102 is a semi-insulating substrate formed in a 4H crystal structure of SiC. Optional SiC crystal structures include 3C, 6H, and 15R crystal structures. Alternative materials for the substrate 102 may include sapphire (Al2O3), aluminum nitride (AlN), AlGaN, GaN, silicon (Si), gallium arsenide (GaAs), zinc oxide (ZnO), and indium phosphide (InP). The substrate 102 generally has a thickness of 300 micrometers to 1000 micrometers.

[0004] To facilitate heteroepitaxial crystal growth on the substrate 102, a nucleating layer (not shown) may be formed on the surface of the substrate 102, which enables appropriate crystal structure transitions between the SiC of the substrate 102 and the various epitaxial layers to be formed on the substrate 102. "Heteroepitaxial growth" or "heteroepitaxis" refers to the crystal growth of a layer of material on a substrate having a different material composition from the epitaxial growth layer. Therefore, for example, the growth of a GaN or GaN-based crystal layer on a SiC substrate is called heteroepitaxial growth. In contrast, epitaxial growth of a layer on a substrate having the same material composition as the substrate, such as the epitaxial growth of a SiC layer on a SiC substrate, is called "homoepitaxis".

[0005] The nucleating layer may be a single layer or a series of layers. The nucleating layer is generally 10 nm to 60 nm thick. The epitaxial structure 115 may further comprise layers or sublayers such as a cap layer, a buffer layer, and other layers.

[0006] The channel layer 116 is formed on the nucleation layer. The channel layer 116 is formed by one or more epitaxial layers. In this example, the channel layer 116 may be GaN. However, more generally, the channel layer 116 may be a group III nitride such as GaN, AlXGa1-XN, indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN), where 0 ≤ X < 1. The channel layer 116 may not be doped, or may be at least unintentionally doped, and may be grown to a thickness greater than about 2 nm. In certain embodiments, the channel layer 116 may use a multilayer structure such as a superlattice or alternating layers of different group III nitrides such as GaN and AlGaN.

[0007] The barrier layer 118 is formed on the channel layer 116. The barrier layer 118 may have a band gap larger than that of the underlying channel layer 116. The barrier layer 118 may also have a smaller electron affinity than that of the channel layer 116. In this illustrated embodiment, the barrier layer 118 is AlGaN. However, the barrier layer 118 may be AlGaN, AlInGaN, AlN, or various combinations of these layers. The thickness of the barrier layer 118 is generally between 2 nm and 40 nm, but the barrier layer 118 should not be so thick that it causes cracking or significant defect formation within the barrier layer. The barrier layer 118 may be undoped, or at least unintentionally doped, or with an n-type dopant of about 1E19 cm -3 It may be doped to a concentration of less than 1. In particular, the channel layer 116 and the barrier layer 118 together form the main part of the HEMT 100 semiconductor.

[0008] As shown in Figure 1, the surface dielectric layer 126 is formed on the surface of the barrier layer 118 facing the channel layer 116 and etched to the illustrated shape using a known etching technique. In this embodiment, the surface dielectric layer 126 is silicon nitride (SiN). However, the surface dielectric layer 126 may be formed of another suitable dielectric, such as silicon dioxide (SiO2), aluminum silicon nitride (AlSiN), or silicon oxynitride (SiON). The terms "SixNy," "SiN," and "silicon nitride" will be understood to be used interchangeably herein to refer to both stoichiometric and non-stoichiometric SiN. Other materials that may be used for the surface dielectric layer 126 include, for example, magnesium oxide, scandium oxide, aluminum oxide, and / or aluminum oxynitride. The surface dielectric layer 126 may further be a single layer or comprise multiple layers of uniform or non-uniform composition. The material of the surface dielectric layer 126 needs to be able to withstand relatively high temperatures, and at least a portion of it needs to be removable without causing significant damage to the underlying barrier layer 118.

[0009] The surface dielectric layer 126 can generally enable a relatively high breakdown electric field strength and a relatively low interface trap density at the interface with the underlying group III nitride layer, such as the barrier layer 118. The surface dielectric layer 126 may have high etching selectivity for the material of the barrier layer 118 and may be non-reactive to the material of the barrier layer 118. The surface dielectric layer 126 may also have a relatively low level of impurities within the layer. For example, the surface dielectric layer 126 may have relatively low levels of hydrogen, as well as other impurities including oxygen, carbon, fluorine, and chlorine. The surface dielectric layer 126 is generally 80 nm to 200 nm thick.

[0010] The surface dielectric layer 126 is etched as shown, exposing the surface portions 122A, 122B, and 122C of the barrier layer 118. The area below surface portion 122A corresponds to the drain region, and the area below surface portion 122B corresponds to the source region. The areas below surface portions 122A and 122B corresponding to the drain and source regions undergo "shallow implantation" of dopant ions, forming shallow implantation regions 124, respectively. The shallow implantation regions 124 penetrate the barrier layer 118 and extend at least partially into the channel layer 116. Thus, the ions of the doping material remain both below surface portions 122A and 122B, in the barrier layer 118 and at least in the upper portion of the channel layer 116.

[0011] As used herein, the term “shallow implantation” means that during implantation, there is no substantial capping or protective layer covering the surface portions 122A and 122B of the barrier layer 118, and the implantation is performed directly within the barrier layer 118. The ions of the doping material to be implanted may be implanted such that the peak of the implantation profile is located just below the interface between the channel layer 116 and the barrier layer 118, where a plane of two-dimensional electron gas (2-DEG) is formed during operation and the electronic conductivity is modulated. The doping concentration may be changed based on the desired performance parameters, but a first exemplary doping condition is 1 × 10⁻⁶. 18 cm -3 This can enable a shallow injection region 124 with peak doping concentrations and scattering of less than 50 nanometers (nm). In some embodiments, the injection volume and injection energy are, for example, about 5 × 10⁻⁶. 19 cm -3 The peak doping concentration and scattering of approximately 30 nm may be selected to enable this. To form an n-type shallow implantation region 124 in the nitride barrier layer 118, the implanted ions may include Si ions, sulfur ions, oxygen ions, or a combination thereof.

[0012] A drain contact 114 is formed on the surface portion 122A. The drain contact 115 is an ohmic contact that works in cooperation with a shallow injection region 124 located beneath the surface portion 122A to enable a low-resistance connection of the HEMT 100 to the drain region. Similarly, a source contact 110 is formed on the surface portion 122B. The source contact 110 is an ohmic contact that works in cooperation with a shallow injection region 124 located beneath the surface portion 122B to enable a low-resistance connection of the HEMT 100 to the source region. The source and drain regions are connected to both sides of the 2-DEG plane, directly beneath the junction of the channel layer 116 and the barrier layer 118.

[0013] The surface dielectric layer 126 is similarly etched, as mentioned above, so as to expose the surface portion 122C of the barrier layer 118. The surface portion 122C is located between surface portions 122A and 122B and corresponds to the gate region of the HEMT 100. The gate contact 112 is formed on the surface portion 122C of the barrier layer 118 with one or more metal layers.

[0014] Referring further to Figure 1, a portion of the gate contact 112 may be formed directly on the barrier layer 118, and the barrier layer 118 itself may be formed from multiple epitaxial layers. Typically, the opening is etched through the surface dielectric layer 126, exposing the surface portion 122C. The gate contact 112 may have a portion located within the opening and in contact with the surface portion 122C, as shown, as well as a portion located along the sidewall of the opening, and portions located in contact with the upper surfaces of the surface dielectric layer 126 on both sides of the opening.

[0015] The gate contact 112 may form a non-ohmic contact with the barrier layer 118, and more specifically, a Schottky contact with the barrier layer 118.

[0016] A second dielectric layer 128 is formed on the surface dielectric layer 126 and the gate contact 112. The drain metallize layer 132 penetrates the second dielectric layer 128 and contacts the drain contact 115, and the source metallize layer 134 penetrates the second dielectric layer 128 and contacts the source contact 110. The field plate 122 is electrically connected to the source contact 110 via the source metallize layer 134 and extends over the gate contact 112. The field plate 122 reduces the adverse effects of the electromagnetic field near the gate contact 112 of the HEMT 100. The source metallize 134 is connected to the back source electrode 123 via a back via 118 that penetrates the substrate 102. [Overview of the Initiative] [Means for solving the problem]

[0017] A method for forming a semiconductor device structure includes the step of forming a pattern on the surface of a semiconductor substrate, wherein the semiconductor substrate is made of a material having a thermal conductivity of more than approximately 50 W / m·K. The method further includes the steps of conformally forming a heteroepitaxial layer structure on the surface of the semiconductor substrate and forming a semiconductor device within the heteroepitaxial layer structure.

[0018] In some embodiments, the step of forming a pattern on the surface of a semiconductor substrate includes the step of etching a plurality of features onto the semiconductor substrate.

[0019] Multiple features may include trenches, depressions, protrusions, and / or bases on the surface of the semiconductor substrate.

[0020] The presence of surface features on the semiconductor substrate results in a larger surface area at the interface between the heteroepitaxial layer structure and the semiconductor substrate compared to when there are no features on the semiconductor substrate surface.

[0021] In some embodiments, the total surface area of ​​the interface between the semiconductor substrate and the heteroepitaxial layer structure is at least about 50% larger than the total surface area of ​​the interface in the absence of features.

[0022] In some embodiments, multiple features have a rectangular cross-section. In some embodiments, multiple features have a U-shaped or V-shaped cross-section.

[0023] In some embodiments, the features include trenches, which extend in a direction consistent with the direction of charge carrier flow during device operation.

[0024] The substrate may contain silicon carbide, and the heteroepitaxial layer structure may contain gallium nitride-based material. The semiconductor substrate may have a thermal conductivity exceeding approximately 100 W / m·K. The semiconductor device may be a high electron mobility transistor.

[0025] In some embodiments, the step of patterning the surface of the substrate includes forming an etching mask on the surface of the substrate, forming a plurality of openings in the etching mask, and anisotropically etching the surface of the substrate through the plurality of openings in the etching mask to form a plurality of concave-shaped bodies on the surface of the substrate. The step of anisotropically etching the surface of the substrate may be performed using reactive ion etching.

[0026] A semiconductor device structure according to some embodiments includes a semiconductor substrate having a patterned surface. The semiconductor substrate is formed of a material having a thermal conductivity greater than about 50 W / m·K. The device structure includes a heteroepitaxial layer structure conformally formed on the patterned surface of the semiconductor substrate and at least one metal contact on the heteroepitaxial layer structure.

Brief Description of the Drawings

[0027] [Figure 1] It is a diagram of a simplified cross-section of a conventional high electron mobility transistor (HEMT). [Figure 2] It is a diagram of a cross-section of a HEMT device structure according to some embodiments. [Figure 3A] It is a plan view of a HEMT device structure according to some embodiments. [Figure 3B] It is a plan view of a HEMT device structure according to some embodiments. [Figure 4A] It is a cross-sectional view showing the process of forming a HEMT device structure according to various embodiments. [Figure 4B] It is a cross-sectional view showing the process of forming a HEMT device structure according to various embodiments. [Figure 4C] It is a cross-sectional view showing the process of forming a HEMT device structure according to various embodiments. [Figure 4D] It is a cross-sectional view showing the process of forming a HEMT device structure according to various embodiments. [Figure 4E]This is a cross-sectional view showing the process of forming a HEMT device structure according to various embodiments. [Figure 4F] This is a cross-sectional view showing the process of forming a HEMT device structure according to various embodiments. [Figure 5A] These are cross-sectional diagrams of HEMT device structures according to several examples. [Figure 5B] These are cross-sectional diagrams of HEMT device structures according to several examples. [Figure 5C] These are cross-sectional diagrams of HEMT device structures according to several examples. [Figure 6] This flowchart shows the process of forming a HEMT device structure according to several embodiments. [Figure 7A] This is a schematic block diagram of a multiple amplifier circuit in which an RF power amplifier incorporating transistor devices according to the embodiment may be used. [Figure 7B] This is a schematic block diagram of a multiple amplifier circuit in which an RF power amplifier incorporating transistor devices according to the embodiment may be used. [Figure 7C] This is a schematic block diagram of a multiple amplifier circuit in which an RF power amplifier incorporating transistor devices according to the embodiment may be used. [Figure 8] These are schematic plan views of RF power amplifiers for monolithic microwave integrated circuits, based on several embodiments. [Figure 9A] This schematic cross-sectional view shows two exemplary ways in which RF transistor devices, according to several embodiments, can be packaged to realize an RF power amplifier. [Figure 9B] This schematic cross-sectional view shows two exemplary ways in which RF transistor devices, according to several embodiments, can be packaged to realize an RF power amplifier. [Modes for carrying out the invention]

[0028] The embodiments described below provide the information necessary to enable those skilled in the art to practice the embodiments and represent the best way to practice them. Those skilled in the art will understand the concepts of this disclosure and recognize examples of applications of such concepts that are not specifically covered herein by referring to the accompanying drawings. It should be understood that such concepts and applications are included in this disclosure and the accompanying claims.

[0029] As mentioned above, some of the advantages of GaN-based HEMT transistors include their ability to operate at high power levels and high frequencies while maintaining high thermal stability. However, one of the main limitations of GaN-based HEMT performance is the self-heating effect, where the heat generated by switching large currents at high frequencies causes heat to accumulate within the device. Specifically, the self-heating effect increases the channel temperature due to the transfer of energy from electrons to the crystal lattice. Self-heating can degrade the drain saturation current and transconductance characteristics of the device, potentially leading to reliability issues.

[0030] The thermal energy generated by self-heating needs to be efficiently dissipated. While SiC substrates themselves are efficient thermal conductors, HEMT devices require further improvements in thermal performance, especially as the demand for higher drive voltages increases.

[0031] Some embodiments are based on the understanding that there is thermal resistance at the interface between the epitaxial structure 115 of a GaN-based HEMT device and the SiC substrate 102. In some embodiments, the thermal resistance at the interface with the epitaxial structure is reduced by forming a pattern on the surface of the SiC substrate so as to increase the surface area of ​​the interface between the epitaxial structure 115 and the substrate 102, before epitaxial growth of the epitaxial structure 115 on the SiC substrate. Thermal resistance is inversely proportional to the cross-sectional area of ​​the path through which heat flows, as is known in the art. Therefore, as the cross-sectional area of ​​the path increases, the thermal resistance of the path decreases.

[0032] The surface pattern of the substrate 102 may be any pattern that increases the surface area of ​​the interface between the substrate 102 and the epitaxial structure 115. The pattern may be, for example, a grooved pattern, a recessed pattern, a corrugated pattern, a based pattern, etc.

[0033] In some embodiments, a pattern is etched into the SiC substrate to a specific depth before growing the epitaxial structure 115, effectively increasing the total surface area of ​​the interface between the substrate 102 and the epitaxial structure 115 in the HEMT. In some embodiments, the depth of the pattern may range from less than 0.1 micrometers to several micrometers, depending on the width of the pattern feature, for example.

[0034] By increasing the total contact area between the HEMT epitaxial structure 115 and the substrate 102, the thermal resistance of heat dissipation from the epitaxial structure 115 to the substrate 102 can be reduced, thereby enabling more efficient heat removal from the channel region of the HEMT device.

[0035] Figure 2 shows HEMT device structures 200 according to several embodiments. Specifically, Figure 2 is a cross-sectional view of the HEMT device structure 200 cut along line A-A' in Figure 3A or Figure 3B, which is a plan view of the HEMT device structure according to various embodiments. Referring to Figures 2, 3A, and 3B, the HEMT device structure 200 comprises a substrate with high thermal conductivity on which a heteroepitaxial layer structure 215 is formed. The substrate 202 may have a thermal conductivity exceeding about 50 W / m·K, and in some embodiments exceeding about 100 W / m·K. The substrate 202 may contain, for example, silicon carbide having a thermal conductivity of about 120 W / m·K. In contrast, substrate materials with low thermal conductivity, such as sapphire, may have a thermal conductivity of less than about 50 W / m·K.

[0036] The heteroepitaxial layer structure 215 comprises a nucleation layer 205 on a substrate, a channel layer 116 on the nucleation layer 205, and a barrier layer 118 on the channel layer 116. The nucleation layer 205 may contain, for example, aluminum nitride or other suitable material, and may have a thickness of several nanometers to several hundred nanometers. The metal gate contact 112 is located on the barrier layer 118.

[0037] As shown in Figures 2, 3A, and 3B, the surface of the substrate 202 on which one or more epitaxial layers are to be formed is patterned to increase the surface area of ​​the interface between the substrate and the epitaxial layer. The structure may be able to dissipate heat more efficiently from the epitaxial layer to the substrate 202 due to the increased surface area of ​​the interface.

[0038] In some embodiments, the substrate 202 has an alternating arrangement of three-dimensional features, specifically, trenches 210 or depressions 220 adjacent to raised portions 225. The raised portions 225 may be, for example, ridges or bases. The trenches 210 or depressions 220 may be formed, for example, by etching the SiC substrate 202, and may have a depth of about 0.1 micrometers to several micrometers and a width of about 0.1 micrometers to several micrometers. In specific embodiments, the trenches 210 or depressions 220 may have a depth of about 0.2 micrometers and a width of about 1 micrometer. In some embodiments, the trenches 210 or depressions 220 are deeper than they are wide in order to increase the vertical surface area of ​​the trenches 210 or depressions 220 and promote higher heat dissipation.

[0039] In some embodiments, the total surface area of ​​the interface between the substrate 202 and the heteroepitaxial layer structure 215 may be at least about 50% larger than the total surface area of ​​the interface without three-dimensional features. In some embodiments, the total surface area of ​​the interface between the substrate 202 and the heteroepitaxial layer structure 215 may be at least about 75% larger than the total surface area of ​​the interface without three-dimensional features. In some embodiments, the total surface area of ​​the interface between the substrate 202 and the heteroepitaxial layer structure 215 may be at least about 100% larger than the total surface area of ​​the interface without three-dimensional features.

[0040] The recess 220 may be formed to have different peripheral shapes when viewed from above the substrate. The recess 220 may have a square peripheral shape, as shown in Figure 3B. However, other shapes can also be used. The recess 220 may be, for example, circular, rectangular, or hexagonal.

[0041] The nucleation layer 205 promotes epitaxial growth on the side walls and bottom of the trench 210 or depression 220, as well as on the upper surface of the raised portion 225.

[0042] Etching of the SiC substrate 202 may be performed using an anisotropic dry etching process, such as a reactive ion etching (RIE) process. Anisotropic dry etching processes such as RIE can allow for precise control of the etching depth.

[0043] The substrate 202 may be treated by a process that prepares the surface of the substrate 202 for epitaxial growth after forming trenches 210 or depressions 220 in the substrate 202. Such a process may include H2 etching, oxidation / exfoliation, wet etching, or other processes.

[0044] After the formation of the trench 210 or depression 220 and optionally one or more surface treatments of the substrate 202, a nucleation layer 205 may be formed on the substrate 202. The nucleation layer 205 may comprise an AlN layer, as mentioned above, and may be formed on the sidewalls and bottom of the trench 210 or depression 220, and on the upper surface of the raised portion 225. The nucleation layer 205 may be provided to promote epitaxial growth in both vertical and lateral directions, not only from the sidewalls and bottom of the trench 210 or depression 220, but also on the upper surface of the raised portion 225. Such growth may be in contrast to pendeoepitaxial growth techniques, which promote preferential growth from, for example, the sidewalls or top of the trench or pillar, and facilitate lateral growth of the GaN layer.

[0045] Furthermore, the use of RIE to etch the trench 210 or depression 220 may result in a rougher morphology of the bottom surface of the trench 210 or depression 220, which may further promote epitaxial growth from the bottom surface of the trench 210 or depression 220.

[0046] In fact, during the epitaxial growth of the heteroepitaxial layer structure 215, initial epitaxial growth may be faster, or even more favorable, from the bottom of the trench 210 or depression 220 than from the sidewalls of the trench 210 or depression 220.

[0047] After the formation of the nucleation layer 205, a heteroepitaxial layer structure 215 comprising a channel layer 116 and a barrier layer 118 may be formed. The heteroepitaxial layer structure 215 may include other layers between the nucleation layer 205 and the channel layer 116, such as a buffer layer 117. The buffer layer 117 may be made of GaN, and may be doped with a deep-level dopant, such as carbon or iron, to make the buffer layer 117 semi-insulating.

[0048] As described above, the purpose of forming the trenches 210 or depressions 220 and the raised portions 225 is to increase the surface area of ​​the interface between the heteroepitaxial layer structure 215 and the substrate 202 in order to facilitate increased heat transfer from the heteroepitaxial layer structure 215 to the substrate 202. Heat can be transferred from the heteroepitaxial layer structure 215 to the substrate 202 through the side walls and bottom of the trenches 210 or depressions 220 and the upper surface of the raised portions 225, as indicated by the arrows in Figure 2. As further described above, increasing the surface area of ​​the interface between the heteroepitaxial layer structure 215 and the substrate 202 can reduce the thermal resistance of the heat path from the heteroepitaxial layer structure 215 to the substrate 202.

[0049] Furthermore, although we do not wish to be bound by a specific operating theory, it is currently thought that providing a patterned interface between the heteroepitaxial layer structure 215 and the substrate 202 may reduce the scattering of phonons at the interface of phonons generated within the active region of the device when charges pass through the channel region between the source region and drain region 124 of the device. Heteroepitaxial interfaces have high-density boundary regions, defects, and dislocations due to lattice mismatch, all of which hinder thermal transport by phonon scattering. However, there is evidence that interface scattering is more dominant in cross-plane transport than in-plane transport. The sidewalls of the trench 210 or depression 220 constitute an in-plane interface, while the bottom and top surfaces of 210 or 220 constitute a cross-plane interface. That is, the sidewall interface allows for less phonon scattering and therefore has higher thermal conductivity than the bottom and top surfaces of the trench 210 or depression 220.

[0050] Referring to Figure 3A, in embodiments in which a trench 210 is formed in the substrate 202, in some embodiments the trench 210 may extend along a direction that matches the direction of the current flowing through the channel of the HEMT device 200 from the source contact 110 to the drain contact 114. This arrangement can reduce the scattering of charge carriers as they pass through the channel below the gate contact 112 during device operation, thereby improving the noise characteristics of the device.

[0051] Figures 4A to 4F show the process of forming the HEMT structure 200 according to several embodiments. Referring to Figure 4A, a silicon carbide substrate 202 is prepared. The substrate 202 may be formed of silicon carbide having a 2H, 4H, 6H, 3C, or 15R type crystal structure and may be undoped. Referring to Figure 4B, a mask 402 is formed on the upper surface of the substrate 202 and patterned to form openings 404 in the mask 402. The substrate 202 is then etched using an anisotropic etching process such as RIE, as shown in Figure 4C, to form trenches 210 or depressions 220 in the substrate 202 below the openings 404 in the mask, and raised portions 225 adjacent to the trenches 210 or depressions 220.

[0052] The substrate 202 may then optionally be subjected to a process to prepare the surface of the substrate 202 for epitaxial growth. Such a process may include H2 etching, oxidation / exfoliation, wet etching, or other processes.

[0053] Referring to Figure 4D, after trenches 210 or depressions 220 are formed in the substrate 202, a heteroepitaxial layer structure is then formed on the substrate 202. The heteroepitaxial layer structure is formed conformally to the patterned surface of the substrate 202. First, a nucleation layer 205 containing, for example, aluminum nitride (AlN) is formed conformally to the patterned surface of the substrate 202. The nucleation layer 205 is formed on the bottom and side walls of the trenches 210 or depressions 220, as well as on the raised surfaces 225 adjacent to the trenches 210 or depressions 220.

[0054] After the formation of the nucleation layer 205, the heteroepitaxial layer structure 215 is grown. Specifically, a GaN buffer layer 117 may be conformally formed on the nucleation layer 117. The buffer layer 117 may be made of GaN, and may be doped with a deep-level dopant such as carbon or iron to make the buffer layer 117 semi-insulating.

[0055] As described above, epitaxial growth from the nucleation layer 117 may preferentially proceed from the bottom of the trench 210 or depression 220 compared to the side walls of the trench 210 or depression 220. The buffer layer 117 can completely or partially fill the trench 210 or depression 220, as shown in Figure 4D.

[0056] Referring to Figure 4E, the remaining portion of the heteroepitaxial layer structure 215, comprising at least the channel layer 116 and the buffer layer 118, is then formed.

[0057] Referring to Figure 4F, the metal contacts include the source contact 110 and drain contact 114 (Figure 3A), as well as the gate 112.

[0058] Figure 5A shows HEMT device structures 200 according to several embodiments. Specifically, Figure 5A is a simplified cross-section of the HEMT device structure 200B cut along line B-B' in Figure 3B. Figure 5B shows a recess 220 in a substrate 202 on which a heteroepitaxial layer structure comprising a GaN buffer layer 117, a channel layer 116, and a barrier layer 118 is formed. Source contacts 110, gate contacts 112, and drain contacts 115 are formed on the barrier layer 118. Source / drain regions 124 injected into the barrier layer 118 and the channel layer 116 facilitate the formation of ohmic contacts to the heteroepitaxial layer structure by the source contacts 110 and drain contacts 115.

[0059] For example, the trench shown in Figure 2 has a square or rectangular cross-sectional profile, but the trench 210 may have a different cross-sectional profile. For example, Figure 5B shows an embodiment in which the substrate 202 includes a trench 210 having a V-shaped cross-sectional profile, and Figure 5C shows an embodiment in which the substrate 202 includes a trench 210 having a U-shaped or rounded cross-sectional profile. In each embodiment, the nucleation layer 205 and the heteroepitaxial layer grown thereon conform to the shape of the surface of the substrate 202 on which the heteroepitaxial layer is grown.

[0060] Figure 6 shows the process of forming a semiconductor device structure according to several embodiments. Specifically, in block 602, a substrate such as a silicon carbide substrate is patterned or textured, and a patterned or textured surface is formed. Specifically, the substrate may be patterned or textured by etching a plurality of trenches or depressions into the substrate.

[0061] In block 604, the heteroepitaxial layer structure is conformally formed on the surface of a patterned or textured substrate. Since the surface of the substrate on which the heteroepitaxial layer structure is conformally formed is patterned or textured, the surface area of ​​the interface between the heteroepitaxial layer structure and the substrate surface is increased. This increase in the surface area of ​​the interface between the heteroepitaxial layer structure and the substrate surface reduces the thermal resistance of the heat path between the heteroepitaxial layer structure and the substrate.

[0062] In block 606, transistor devices such as GaN HEMT devices are formed on the epitaxial structure.

[0063] Although the above description primarily concerns GaN HEMT devices, the structures and / or methods according to the embodiments described herein may be applicable to all types of semiconductor devices formed using heteroepitaxiality where it is desirable to reduce the thermal resistance between the heteroepitaxial layer structure and the substrate. Therefore, the embodiments described herein may be useful in other types of GaN-based devices formed on non-GaN substrates, including, for example, MESFETs, JFETs, MOSFETs, and other types of devices.

[0064] The transistor devices described herein may be used in amplifiers operating in a variety of different frequency bands. In some embodiments, an RF power amplifier incorporating the transistor devices described herein may be configured to operate at frequencies above 1 GHz. In other embodiments, the RF power amplifier may be configured to operate at frequencies above 2.5 GHz. In yet another embodiment, the RF power amplifier may be configured to operate at frequencies above 3.1 GHz. In yet another embodiment, the RF power amplifier may be configured to operate at frequencies above 5 GHz. In some embodiments, the RF power amplifier may be configured to operate in at least one of the following frequency bands or portions of frequency bands: 2.5–2.7 GHz, 3.4–4.2 GHz, 5.1–5.8 GHz, 12–18 GHz, 18–27 GHz, 27–40 GHz, or 40–75 GHz.

[0065] While embodiments of the concept of the present invention have been discussed above in relation to HEMT devices, it will be understood that the concept of the present invention described herein may also be applied to other types of semiconductor devices, such as MOSFETs, DMOS transistors, and / or laterally diffused MOS (LDMOS) transistors.

[0066] RF power amplifiers incorporating the transistor devices described herein can be used in standalone RF power amplifiers and / or in multiple RF power amplifiers. Examples of how some embodiments of RF power amplifiers can be used in applications involving multiple amplifiers will be discussed with reference to Figures 7A to 7C.

[0067] Referring to Figure 7A, an RF power amplifier 700A is schematically shown, comprising an electrically series-connected preamplifier 710 and a main amplifier 730. As shown in Figure 7A, the RF power amplifier 700A comprises an RF input 701, a preamplifier 710, an interstage impedance matching network 720, a main amplifier 730, and an RF output 702. The interstage impedance matching network 720 may comprise, for example, inductors and / or capacitors arranged in any suitable configuration to form a circuit that improves impedance matching between the output of the preamplifier 710 and the input of the main amplifier 730. Although not shown in Figure 7A, the RF power amplifier 700A may further comprise an input matching network interposed between the RF input 701 and the preamplifier 710, and / or an output matching network interposed between the main amplifier 730 and the RF output 702. The RF power amplifier according to this embodiment may be used to implement either or both of the preamplifier 710 and the main amplifier 730.

[0068] Referring to Figure 7B, an RF power amplifier 700B is schematically shown, comprising an RF input 701, a pair of preamplifiers 710-1 and 710-2, a pair of interstage impedance matching networks 720-1 and 720-2, a pair of main amplifiers 730-1 and 730-2, and an RF output 702. A distributor 703 and a combiner 704 are also provided. Preamplifiers 710-1 and 730-1 (connected in electrical series) are electrically arranged in parallel with preamplifiers 710-2 and 730-2 (connected in electrical series). Similar to the RF power amplifier 700A in Figure 7A, the RF power amplifier 700B may further include an input matching network interposed between the RF input 701 and preamplifiers 710-1 and 710-2, and / or an output matching network interposed between the main amplifiers 730-1 and 730-2 and the RF output 702.

[0069] As shown in Figure 7C, RF power amplifiers according to some embodiments may also be used to implement a Doherty amplifier. A Doherty amplifier circuit comprises a first and a second (or more) power combining amplifier, as is known in the art. The first amplifier is called the “main” amplifier or “carrier” amplifier, and the second amplifier is called the “peak” amplifier. The two amplifiers may be biased separately. In one common embodiment of a Doherty amplifier, for example, the main amplifier may include a Class AB or Class B amplifier, while the peak amplifier may be a Class C amplifier. A Doherty amplifier can operate more efficiently than a balanced amplifier operating at a power level backed off from the saturation level. The RF signal input to the Doherty amplifier is distributed (e.g., using a quadrature coupler) and the outputs of the two amplifiers are coupled. The main amplifier is configured to turn on first (i.e., at a lower input power level), so that only the main amplifier operates at a lower power level. As the input power level increases toward the saturation level, the peak amplifier turns on, and the input RF signal is distributed between the main amplifier and the peak amplifier.

[0070] The Doherty RF power amplifier 700C comprises an RF input 701, an input distributor 703, a main amplifier 740, a peak amplifier 750, an output coupler 704, and an RF output 702, as shown in Figure 7C. The Doherty RF power amplifier 700C includes a 90° transformer 707 at the input of the peak amplifier 750 and a 90° transformer 705 at the input of the main amplifier 740, and may optionally include an input matching network and / or an output matching network (not shown). The main amplifier 740 and / or the peak amplifier 750 may be implemented using any of the RF power amplifiers according to the embodiments described above.

[0071] The RF power amplifiers according to the embodiments may be formed as individual devices or as part of a monolithic microwave integrated circuit (MMIC). An MMIC refers to an integrated circuit that operates with radio and / or microwave frequency signals, in which all circuit configurations for a specific function are integrated on a single semiconductor chip. An exemplary MMIC device is a power amplifier with associated matching circuits, power supply networks, etc., all implemented on a common substrate. An MMIC transistor amplifier typically comprises multiple unit-cell HEMT transistors connected in parallel.

[0072] Figure 8 is a plan view of an MMIC RF power amplifier 800 according to an embodiment of the concept of the present invention. The MMIC RF power amplifier 800 comprises an integrated circuit chip 830 housed in a package 810, as shown in Figure 8. The package 810 may include a protective enclosure that surrounds and protects the integrated circuit chip 830. The package 810 may be formed of, for example, a ceramic material.

[0073] Package 810 comprises input leads 812 and output leads 818. The input leads 812 may be mounted on input lead pads 814, for example, by soldering. One or more input coupling wires 820 may electrically connect the input lead pads 814 to input coupling pads on the integrated circuit chip 830. The integrated circuit chip 830 comprises an input power supply network 838, an input impedance matching network 850, a first RF power amplifier stage 860, an intermediate impedance matching network 840, a second RF power amplifier stage 862, an output impedance matching stage 870, and an output power supply network 882.

[0074] The package 810 further comprises output leads 818, which are connected to output lead pads 816, for example, by soldering. One or more output coupling wires 890 may electrically connect the output lead pads 816 to the output coupling pads on the integrated circuit chip 830. The first RF power amplifier stage 860 and / or the second RF power amplifier stage 862 may be implemented using any of the RF power amplifiers according to embodiments of the concept of the present invention.

[0075] RF power amplifiers according to embodiments of the concept of the present invention may be designed to operate in a variety of different frequency bands. In some embodiments, such RF power amplifier dies may be configured to operate in at least one of the following frequency bands, or portions thereof: 0.6–2.7 GHz, 3.4–4.2 GHz, 5.1–5.8 GHz, 12–18 GHz, 18–27 GHz, 27–40 GHz, or 90–75 GHz. Techniques according to embodiments of the concept of the present invention may be particularly advantageous for RF power amplifiers operating at frequencies above 10 GHz.

[0076] Figures 9A and 9B are schematic cross-sectional views showing several exemplary transistor amplifier packages, including an RF power amplifier device according to an embodiment of the concept of the present invention.

[0077] Figure 9A is a schematic side view of a packaged Group III nitride-based RF power amplifier 900A. As shown in Figure 9A, the packaged RF power amplifier 900A comprises an RF power amplifier die 90 packaged within an open cavity package 910A. The package 910A comprises a metal gate lead 922A, a metal drain lead 924A, a metal submount 930, a side wall 940, and a lid 942.

[0078] The submount 930 may include a material configured to assist in the thermal management of the package 900A. The submount 930 may include, for example, copper and / or molybdenum. In some embodiments, the submount 930 may consist of multiple layers and / or include vias / interconnections. In an exemplary embodiment, the submount 930 may be a multilayer copper / molybdenum / copper metal flange comprising a core molybdenum layer together with a copper cladding layer on one of the main surfaces of the core molybdenum layer. In some embodiments, the submount 930 may include a metal heat sink, which is part of the lead frame or metal slag. In some embodiments, the sidewall 940 and / or lid 942 may be formed of or include an insulating material. The sidewall 940 and / or lid 942 may be formed of or include a ceramic material, for example.

[0079] In some embodiments, the side wall 940 and / or lid 942 may be formed of, for example, Al2O3. The lid 942 may be bonded to the side wall 940 using epoxy adhesive. The side wall 940 may be attached to the submount 930, for example, by brazing. The gate lead 922A and drain lead 924A may be configured to extend through the side wall 940, but embodiments of the concept of the present invention are not limited thereto.

[0080] The RF power amplifier die 90 is mounted on the upper surface of the metal submount 930 within an air-filled cavity 912 defined by the metal submount 930, ceramic sidewalls 940, and ceramic lid 942. The gate and drain terminals of the RF power amplifier die 90 may be on the upper side of the semiconductor layer structure 150, while the source terminal is on the bottom side of the semiconductor layer structure 150.

[0081] The gate lead 922A may be connected to the gate terminal of the RF power amplifier die 90 by one or more coupling wires 954. Similarly, the drain lead 924A may be connected to the drain terminal of the RF power amplifier die 90 by one or more coupling wires 954. The source terminal may be mounted on a metal submount 930 using, for example, a conductive die mounting material (not shown). The metal submount 930 may include an electrical connection to the source terminal 936 and may also function as a heat dissipation structure for dissipating heat generated within the RF power amplifier die 90.

[0082] Heat is primarily generated in the upper portion of the RF power amplifier die 90, where relatively high current densities are produced. However, this heat can be transferred from the semiconductor layer structure to the source terminal and then to the metal submount 930.

[0083] Figure 9B is a schematic side view of another packaged Group III nitride-based RF power amplifier 900B. RF power amplifier 900B differs from RF power amplifier 900A in that it has a different package 910B. Package 910B includes a metal submount 930, as well as metal gate leads 922B and metal drain leads 924B. RF power amplifier 900B also includes a plastic overmolding 960 that at least partially surrounds the RF power amplifier die 90, leads 922B, 924B, and the metal submount 930.

[0084] Other components of RF power amplifier 900B may be the same as the numbered components of RF power amplifier 900A, so further description of them will be omitted. While the abstract embodiments of the present invention have been described above in relation to gallium nitride-based RF power amplifiers, it will be understood that the conceptual embodiments of the present invention are not limited thereto. For example, the transistors described above may further be used as power transistors in switching and other applications.

[0085] Embodiments of the concept of the present invention have been described above with reference to the accompanying drawings illustrating embodiments of the concept of the present invention. However, the concept of the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Rather, such embodiments are provided so that this disclosure may be sufficient and complete and the scope of the concept of the present invention may be fully conveyed to those skilled in the art. The same number refers to the same element throughout. In this specification and in the figures, two-part reference numbers (i.e., two numbers separated by a dash, such as 100-1) may be used to identify the same element. When such two-part reference numbers are used, the entire reference number may be used to refer to a specific example of the element, while the first part of the reference number may be used to refer to the element collectively.

[0086] Terms such as "first," "second," etc., may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the concept of the present invention, the first element may be called the second element, and similarly, the second element may be called the first element. The term "and / or" as used herein includes any combination of one or more of the related enumerated items. The glossary used herein is intended solely to describe specific embodiments and is not intended to limit the concept of the present invention. The terms "comprises," "comprising," "includes," and / or "including" as used herein identify the existence of the described features, integers, steps, actions, elements, and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0087] When an element such as a layer, region, or substrate is said to be "on" or "onto" another element, it can be understood that this element is directly on the other element, can directly extend onto the other element, or may have an intervening element. In contrast, when an element is said to be "directly on" or "directly onto" another element, there is no intervening element. When an element is said to be "connected" or "coupled" to another element, it can be understood that this element can directly connect or couple to the other element, or may have an intervening element. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there is no intervening element. Terms indicating relationships, such as "below," "above," "upper," "lower," "horizontal," "lateral," or "vertical," may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region shown in the figure.

[0088] While embodiments of the concept of the present invention have been described in considerable detail with reference to their specific configurations, other versions are also possible. The field plate and gate can also have many different shapes and can be connected to the source contact in many different ways. Therefore, the spirit and scope of the concept of the present invention should not be limited to the specific embodiments described above.

Claims

1. A method for forming a semiconductor device structure, wherein the method is A step of forming a pattern on the surface of a semiconductor substrate, wherein the semiconductor substrate includes a material having a thermal conductivity of more than approximately 50 W / m·K, The steps include conformally forming a heteroepitaxial layer structure on the surface of the semiconductor substrate, The steps include forming a semiconductor device on the heteroepitaxial layer structure and Methods that include...

2. The method according to claim 1, wherein the step of forming a pattern on the surface of the semiconductor substrate includes the step of etching a plurality of features onto the semiconductor substrate.

3. The method according to claim 2, wherein the plurality of features include trenches, depressions, protrusions, and / or bases on the surface of the semiconductor substrate.

4. The method according to claim 2, wherein the presence of the feature on the surface of the semiconductor substrate makes the surface area of ​​the interface between the heteroepitaxial layer structure and the semiconductor substrate larger than it would be if the feature were not present on the surface of the semiconductor substrate.

5. The method according to claim 4, wherein the surface area of ​​the interface between the semiconductor substrate and the heteroepitaxial layer structure is at least about 50% larger than the surface area of ​​the interface in the absence of the feature.

6. The method according to claim 2, wherein the plurality of shapes have a rectangular cross-section.

7. The method according to claim 2, wherein the plurality of shapes have a U-shaped or V-shaped cross-section.

8. The method according to claim 2, wherein the plurality of features include trenches, and the trenches extend in a direction consistent with the direction in which charge carriers flow during device operation.

9. The method according to claim 1, wherein the substrate contains silicon carbide and the heteroepitaxial layer structure contains a gallium nitride-based material.

10. The method according to claim 1, wherein the semiconductor device includes a high electron mobility transistor.

11. The step of forming a pattern on the surface of the substrate is The steps include forming an etching mask on the surface of the substrate, The etching mask comprises the step of forming a plurality of openings, The steps include: anisotropically etching the surface of the substrate through the multiple openings of the etching mask in order to form a plurality of concave features on the surface of the substrate; The method according to claim 1, including the method described in claim 1.

12. The method according to claim 10, wherein the step of anisotropically etching the surface of the substrate is performed using reactive ion etching.

13. The method according to claim 1, wherein the substrate includes a material having a thermal conductivity of more than approximately 100 W / m·K.

14. A semiconductor substrate having a patterned surface, wherein the semiconductor substrate includes a material having a thermal conductivity of more than approximately 50 W / m·K, A heteroepitaxial layer structure conformally formed on the patterned surface of the semiconductor substrate, At least one metal contact on the heteroepitaxial layer structure and A semiconductor device structure comprising the above.

15. The semiconductor device structure according to claim 14, wherein the surface of the semiconductor substrate comprises a plurality of three-dimensional features of the semiconductor substrate.

16. The semiconductor device structure according to claim 15, wherein the plurality of features include trenches, depressions, protrusions, and / or bases on the surface of the semiconductor substrate.

17. The semiconductor device structure according to claim 15, wherein the presence of the feature on the surface of the semiconductor substrate results in a larger surface area at the interface between the heteroepitaxial layer structure and the semiconductor substrate than in the case where the feature is not present on the surface of the semiconductor substrate.

18. The semiconductor device structure according to claim 17, wherein the surface area of ​​the interface between the semiconductor substrate and the heteroepitaxial layer structure is at least about 50% larger than the surface area of ​​the interface in the absence of the feature.

19. The semiconductor device structure according to claim 15, wherein the plurality of features have a rectangular cross-section.

20. The semiconductor device structure according to claim 15, wherein the plurality of features have a U-shaped or V-shaped cross-section.

21. The semiconductor device structure according to claim 15, wherein the plurality of features include trenches, and the trenches extend in a direction consistent with the direction of charge carrier flow during device operation.

22. The semiconductor device structure according to claim 14, wherein the substrate contains silicon carbide and the heteroepitaxial layer structure contains a gallium nitride-based material.

23. The semiconductor device structure according to claim 14, wherein the semiconductor device includes a high electron mobility transistor.

24. The semiconductor device structure according to claim 14, wherein the substrate includes a material having a thermal conductivity of more than approximately 100 W / m·K.

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