Shifter implementation of cyclic permutation matrix operations

Abstract

To provide an integrated circuit and a method for implementing a shifter implementation of a cyclic permutation matrix operation.SOLUTION: A cyclic shifter using shifter implementation of cyclic permutation matrix operation includes a forward shifter configured to shift each successive value of a target segment forward by a shift amount to generate a forward shifted partial segment, a reverse shifter configured to shift each successive value of the target segment backward by a reverse shift value equal to the segment length minus the shift amount to generate a backward shifted partial target segment, a combiner configured to combine the forward shifted partial target segment and the backward shifted partial target segment according to the shift amount and the segment length to generate a shifted target segment, and a mask selector configured to select at least one of a merge mask corresponding to the shift amount and the segment length and a filter mask corresponding to the segment length.SELECTED DRAWING: Figure 5

Description

[Background technology]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to Provisional Application No. 63 / 502,417, filed May 16, 2023, the contents of which are incorporated herein by reference in their entirety. [Background technology] Wireless data communication has become ubiquitous in modern society. As digital data transmission became more prevalent, the usefulness of reliable, error-free communication over noisy wireless channels became apparent. This led to the creation of forward error correction (FEC) codes. FEC codes are mathematical algorithms used to add redundant information to transmitted data, allowing the receiver to correct errors that may have occurred during transmission. FEC codes became essential as wireless communication systems expanded, especially with the emergence of mobile telephony and data-intensive applications. Without FEC, wireless data transmissions would suffer from higher error rates, leading to data corruption and costly retransmissions. FEC codes, such as low-density parity-check (LDPC) codes, are essential components of modern wireless technology, improving data integrity and mitigating the effects of channel impairments, making wireless communication reliable and efficient. [Brief explanation of the drawings]

[0002] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, according to standard industry practice, various features have not been drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0003] [Figure 1] 1 is a schematic diagram of a system for low-density parity-check (LDPC) data transmission in accordance with at least one embodiment of the present invention.

[0004] [Figure 2] FIG. 1 is a schematic diagram of an integrated circuit encoder for LDPC data encoding, in accordance with at least one embodiment of the present invention.

[0005] [Figure 3] 1 is a schematic diagram of an integrated circuit decoder for LDPC data decoding in accordance with at least one embodiment of the present invention.

[0006] [Figure 4] FIG. 1 is a schematic diagram of a processor utilizing a shifter-implemented cyclic permutation matrix operation in accordance with at least some embodiments of the present invention.

[0007] [Figure 5] FIG. 1 is a schematic diagram of a cyclic shifter utilizing a shifter-implemented cyclic permutation matrix operation, in accordance with at least some embodiments of the present invention.

[0008] [Figure 6A] FIG. 1 is a diagram of the original position of a target segment, in accordance with at least one embodiment of the present invention.

[0009] [Figure 6B] FIG. 10 is a diagram of a shifted target segment having a segment length of 3 and shifted by 2, in accordance with at least one embodiment of the present invention.

[0010] [Figure 6C] FIG. 10 is a diagram of a shifted target segment having a segment length of 4 and shifted by 2, in accordance with at least one embodiment of the present invention.

[0011] [Figure 6D] FIG. 10 is a diagram of a shifted target segment having a segment length of 5 and shifted by 2, in accordance with at least one embodiment of the present invention.

[0012] [Figure 6E]FIG. 10 is a diagram of a shifted target segment having a segment length of 6 and shifted by 2, in accordance with at least one embodiment of the present invention.

[0013] [Figure 7] 1 is an operational flow for LDPC data decoding utilizing paged buffering, in accordance with at least some embodiments of the present invention.

[0014] [Figure 8] 10 is an operational flow for data probability value segment decoding utilizing a shifter-implemented cyclic permutation matrix operation in accordance with at least one embodiment of the present invention.

[0015] [Figure 9] 1 is an operational flow for applying a shifter-implemented cyclic permutation matrix operation in accordance with at least one embodiment of the present invention.

[0016] [Figure 10] FIG. 1 is a diagram of a data segment undergoing a shifter-implemented cyclic permutation matrix operation, in accordance with at least one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, or arrangements, etc., are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, or arrangements, etc., are contemplated. In addition, the disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purposes of brevity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0018] Efficient decoding of data encoded with FEC codes plays a key role in the proliferation of wireless communications to a vast and diverse range of connected devices, such as Internet of Things (IoT) devices, many of which have limited power and processing capabilities.

[0019] FIG. 1 is a schematic diagram of a system for low-density parity-check (LDPC) data transmission in accordance with at least one embodiment of the present invention. The system includes an encoder 101, a transmitter 103, a receiver 106, and a decoder 108. In at least some embodiments, the encoder 101 and the transmitter 103 are part of a single device, such as a transmission tower of a wireless access network. In at least some embodiments, the receiver 106 and the decoder 108 are part of a single device, such as a smartphone, that communicates with the wireless access network. In at least some embodiments, such a single device includes the encoder, transmitter, receiver, and decoder, enabling two-way communication. In FIG. 1, the encoder 101 and the transmitter 103 are not part of the same device as the receiver 106 and the decoder 108 because the transmitter 103 is in direct communication with the receiver 106.

[0020] Encoder 101 is configured to receive original data 100 and transmit coded data 102 to transmitter 103. In at least some embodiments, encoder 101 is configured to receive original data 100 in one or more blocks of a predetermined length. In at least some embodiments, encoder 101 is configured to apply FEC coding to original data 100 to generate coded data 102. In at least some embodiments, encoder 101 is configured to apply LDPC coding to original data 100 to generate coded data 102. In at least some embodiments, encoder 101 is an integrated circuit such as a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like. In at least some embodiments, encoder 101 is a computer having a processor and a memory that stores instructions for execution by the processor.

[0021] The transmitter 103 is configured to receive the encoded data 102 from the encoder 101 over wireless communication and transmit binary values ​​104 of the encoded data 102 to the receiver 106. In at least some embodiments, the transmitter 103 is configured to transmit the encoded data 102 in one or more blocks of a predetermined length. In at least some embodiments, the transmitter 103 is configured to transmit the binary values ​​104 in accordance with a standard wireless protocol, such as 5G, BLUETOOTH, BLE, WiFi, 3G GPRS, 3G EVDO, 3G HSPA, 4G WiMAX, 4G E-UTRAN (LTE), etc. Although not all of the aforementioned standards, such as 3G and 4G, currently utilize LDPC, in at least some embodiments, the transmitter 103 includes configurations for multiple standard wireless protocols. In at least some embodiments, the transmitter 103 is configured to transmit in a frequency and timing scheme in accordance with the standard wireless protocol. In at least some embodiments, the transmitter 103 is configured to transmit the binary value 104 over a data channel and other information for decoding the encoded data 102, such as information representing a parity check matrix, over a control channel.

[0022] Receiver 106 is configured to receive probability values ​​105 through wireless reception and transmit encoded probability values ​​107 to decoder 108. In at least some embodiments, receiver 106 is configured to record probability values ​​105 when attempting to receive binary values ​​104, where probability values ​​105 represent one or more probabilities that the binary value received from transmission of binary values ​​104 as transmitted by transmitter 103 will represent a 1 or a 0. In at least some embodiments, receiver 106 records probability values ​​during reception with a reliability proportional to the signal-to-noise ratio. In at least some embodiments, receiver 106 is configured to record more reliable probability values ​​during instances of a higher signal-to-noise ratio and record less reliable probability values ​​during instances of a lower signal-to-noise ratio. In at least some embodiments, the received values ​​are represented as follows: z i =y i +n i formula 1 where z i represents the received value, and y i represents the transmitted value, and n i represents Additive White Gaussian Noise (AWGN), where i ranges from 1 to N, where N is the number of received coded probability values. In at least some embodiments, receiver 106 converts the received values ​​into the Log-Likelihood Ratio (LLR) domain as follows:

number

[0023] In at least some embodiments, receiver 106 is configured to use multiple bits of data to record one or more of probability values ​​105 corresponding to one of binary values ​​104. In at least some embodiments, the number of bits of data used to record each of probability values ​​105 depends on the hardware capabilities of receiver 106 or decoder 108. In at least some embodiments, receiver 106 is configured to use 6 bits of data to record one or more of probability values ​​105 corresponding to one of binary values ​​104. In at least some embodiments, receiver 106 is configured to receive probability values ​​105 in one or more predetermined length blocks. In at least some embodiments, receiver 106 is configured to assemble probability values ​​105 into coded probability values ​​107 using a format that defines a correspondence between one of probability values ​​107 and a binary value of coded data 102. In at least some embodiments, the receiver 106 is configured to receive the probability values ​​105 over a data channel and other information for decoding the encoded data 102, such as information representing a parity check matrix, over a control channel.

[0024] Decoder 108 is configured to receive coded probability values ​​107 from receiver 106 and output decoded data 109. In at least some embodiments, decoder 108 is configured to decode coded probability values ​​107 into decoded data 109. In at least some embodiments, decoder 108 is configured to apply FEC decoding to coded probability values ​​107 to generate decoded data 109. In at least some embodiments, decoder 108 is configured to apply LDPC decoding to coded probability values ​​107 to generate decoded data 109. In at least some embodiments, decoder 108 is an integrated circuit such as an FPGA, an ASIC, etc. In at least some embodiments, decoder 108 is a computer having a processor and a memory that stores instructions for execution by the processor.

[0025] 2 is a schematic diagram of an integrated circuit encoder 201 for LDPC data encoding in accordance with at least one embodiment of the present invention. The integrated circuit encoder 201 includes a segmentation processor 210, an encoding processor 213, a concatenation processor 216, and a parameter processor 219.

[0026] The segmentation processor 210 is configured to receive the original data block 200 and transmit data segments 211 to the encoding processor 213 and the concatenation processor 216. In at least some embodiments, the segmentation processor 210 is configured to divide the original data block 200 into multiple data segments. In at least some embodiments, the segmentation processor 210 is configured to divide the original data block 200 into one or more segments of a predetermined length. In at least some embodiments, the segmentation processor 210 is configured to divide the original data block 200 into segments having lengths according to the length of the original data block 200. In at least some embodiments, the segmentation processor 210 is configured to divide the original data block into multiple data segments according to the columns of the LDPC base graph. In at least some embodiments, the original data block 200 corresponds to an "information block" in the 5G standard, which is the result of a previous segmentation of a transport block that is not performed by the segmentation processor 210.

[0027] The encoding processor 213 is configured to receive the data segments 211 and send the parity segments 214 to the concatenation processor 216. In at least some embodiments, the encoding processor 213 is configured to apply a parity check matrix to the data segments 211 to generate the parity segments 214. In at least some embodiments, the encoding processor 213 is configured to apply an LDPC parity check matrix to the data segments 211 to generate the parity segments 214. In at least some embodiments, the encoding processor 213 is configured to apply one or more cyclic shifts to each data segment 211 according to the parity check matrix to generate the parity segments 214. In at least some embodiments, the encoding processor 213 is configured to apply one or more cyclic shifts to some parity segments, such as "core" parity segments, of the parity segments 214 according to the parity check matrix to generate other parity segments among the parity segments 214. In at least some embodiments, the encoding processor 213 is configured to input a value to each bit of each parity segment such that the sum of the bit values ​​and binary values ​​in the subset of values ​​of one or more data segments and other parity segments corresponding to that bit is an even number.

[0028] Concatenation processor 216 is configured to receive data segments 211 and parity segments 214 and output encoded data block 202. In at least some embodiments, concatenation processor 216 is configured to concatenate data segments 211 with parity segments 214 to generate encoded data block 202. In at least some embodiments, concatenation processor 216 is configured to concatenate data segments 211 with parity segments 214 into a format that makes clear the correspondence between subsets of values ​​in data segments 211 and parity segments 214.

[0029] Parameter processor 219 is configured to receive parameter stream 218 and send information to segmentation processor 210, encoding processor 213, and concatenation processor 216. In at least some embodiments, parameter processor 219 is configured to receive parameter stream 218 over a control channel. In at least some embodiments, parameter processor 219 is configured to receive information representing a parity check matrix corresponding to original data block 200 in parameter stream 218. In at least some embodiments, parameter processor 219 is configured to send associated parameters to each of segmentation processor 210, encoding processor 213, and concatenation processor 216. In at least some embodiments, parameter processor 219 is configured to send information representing segment size to segmentation processor 210. In at least some embodiments, parameter processor 219 is configured to send information representing the parity check matrix corresponding to original data block 200 to encoding processor 213. In at least some embodiments, parameter processor 219 is configured to send information representing the parity check matrix corresponding to original data block 200 to concatenation processor 216.

[0030] 3 is a schematic diagram of an integrated circuit decoder 308 for LDPC data decoding in accordance with at least one embodiment of the present invention. The integrated circuit decoder 308 includes a segmentation processor 320, one or more decoding processors 323, a concatenation processor 326, and a parameter processor 329.

[0031] The segmentation processor 320 is configured to receive the coded probability value data block 307 and transmit probability value segments 321 to the decoding processor 323. In at least some embodiments, the probability value segments 321 include data probability value segments and parity probability value segments. In at least some embodiments, the segmentation processor 320 is configured to divide the coded probability value data block 307 into a plurality of data probability value segments and a plurality of parity probability value segments, with each probability value in the coded data block representing a likelihood between binary values. In at least some embodiments, the segmentation processor 320 is configured to divide the coded probability value data block 307 into segments of one or more predetermined lengths. In at least some embodiments, the segmentation processor 320 is configured to divide the coded probability value data block 307 into segments having lengths according to the length of the coded probability value data block 307.

[0032] The decoding processors 323 are each configured to receive the probability value segments 321 and send decoded binary value segments 324 to the concatenation processor 326. In at least some embodiments, each decoding processor 323 is configured to adjust the probability values ​​of the encoded data block based on a parity check matrix according to an iteration variable accuracy parameter, the parity check matrix defining the correspondence between the data probability value segments and the parity probability value segments, where the iteration variable accuracy parameter represents a trade-off between accuracy and computational efficiency. In at least some embodiments, the decoding processors 323 are each configured to apply the parity check matrix to the probability value segments 321 to generate the decoded binary value segments 324. In at least some embodiments, the decoding processors 323 are each configured to apply the LDPC parity check matrix to the probability value segments 321 to generate the decoded binary value segments 324. In at least some embodiments, each of the decode processors 323 is configured to apply one or more circular shifts to each data probability value segment and each parity probability value segment of the probability value segments 321 according to the parity check matrix to generate a decoded binary value segment 324. In at least some embodiments, each of the decode processors 323 is configured to compare the binary values ​​in the subsets of values ​​of the corresponding data probability value segment and parity probability value segment to ensure that the sum of the values ​​is even. In at least some embodiments, each of the decode processors 323 includes a sorter for sorting the probability values ​​into segments to find a minimum value, a calculator for calculating an update value from the minimum value, a function selector for selecting an accuracy function for determining an adjustment amount based on the minimum value, and an accuracy parameter selector for selecting an iteration variable accuracy parameter.

[0033] The concatenation processor 326 is configured to receive the decoded binary value segments 324 and output a decoded data block 309. In at least some embodiments, the concatenation processor 326 is configured to concatenate likely binary values ​​that satisfy a parity check matrix associated with the probability values ​​of each data probability value segment to form a decoded data block. In at least some embodiments, the concatenation processor 326 is configured to concatenate the decoded binary value segments 324 to generate the decoded data block 309. In at least some embodiments, the concatenation processor 326 is configured to concatenate the decoded binary value segments 324 to form the same format as the original data block.

[0034] Parameter processor 329 is configured to receive parameter stream 328 and send information to segmentation processor 320, decoding processor 323, and concatenation processor 326. In at least some embodiments, parameter processor 329 is configured to send a plurality of parameters to each of segmentation processor 320, decoding processor 323, and concatenation processor 326, where the plurality of parameters corresponds to an encoded data block. In at least some embodiments, parameter processor 329 is configured to receive parameter stream 328 over a control channel. In at least some embodiments, parameter processor 329 is configured to receive information representing a parity check matrix corresponding to data block 307 of coded probability values ​​in parameter stream 328. In at least some embodiments, parameter processor 329 is configured to send associated parameters to each of segmentation processor 320, decoding processor 323, and concatenation processor 326. In at least some embodiments, parameter processor 329 is configured to send information representing segment size to segmentation processor 320. In at least some embodiments, parameter processor 329 is configured to send information representing a parity check matrix corresponding to data block 307 of coded probability values ​​to decoding processor 323. In at least some embodiments, parameter processor 329 is configured to send information representing a parity check matrix corresponding to data block 307 of coded probability values ​​to concatenation processor 326.

[0035] Generally, applying a parity check matrix to a data segment and a probability value segment is implemented by multiplying the segment by a circulant permutation matrix (CPM). In LDPC encoding, for each original data block, hundreds of operations may be required to be performed on the bit data segment. In LDPC decoding, for each encoded data block, hundreds of operations may be required to be performed on the multi-bit value probability value segment, such as an LLR value.

[0036] Due to the specific structure of the parity check matrix, these multiplication operations can be replaced with cyclic shift operations according to at least some embodiments of the present subject disclosure. In at least some embodiments of the present subject disclosure, the computational elements used for the cyclic shift operations have better performance per unit size than computational elements performing segment multiplication by CPM. In at least some embodiments, the number of consecutive values ​​in a segment, i.e., the segment length, ranges from 2 to 384. In at least some embodiments, the magnitude of the cyclic shift operation, i.e., the shift amount, ranges from 0 to one less than the segment length. In at least some embodiments, the parity check matrix may require a shift amount several times larger than the segment length, but the actual shift amount is the remainder when the shift amount is divided by the segment length. For example, if the shift amount is 25 and the segment length is 4, dividing 25 by 4 yields 6 with a remainder of 1.

[0037] In at least some embodiments, each segment is stored in a memory block of fixed capacity. In at least some embodiments, the fixed capacity is the maximum segment length for a given application. In at least some embodiments, the fixed capacity for LDPC applications is 384 bits for data segments and 384 times the bit width of the LLR values ​​for probability value segments. In at least some embodiments, data segments and probability value segments of less than the maximum segment length are stored in a memory block with a fixed capacity corresponding to the maximum segment length. In at least some embodiments, a cyclic shift of a given shift amount is performed differently depending on the segment length. In at least some embodiments, forward and backward shifts are performed independently, and the results are combined based on a mask to perform the cyclic shift. In at least some embodiments, a large multiplexer for CPM operations is not required. In at least some embodiments, a series of cyclic shift operations is pipelined to achieve a desired frequency. In at least some embodiments, the cyclic shift is scalable from the maximum segment length to the minimum segment length.

[0038] 4 is a schematic diagram of a processor utilizing a shifter-implemented cyclic permutation matrix operation in accordance with at least some embodiments of the present invention. A processor 430 includes an input selector 432, one or more cyclic shifters 434, and one or more accumulators 436.

[0039] Input selector 432 is configured to receive data segments 431 and parameter stream 438 and send data segments 433 to circular shifter 434. In at least some embodiments, input selector 432 is configured to receive data segments 431 from a segmentation processor, such as segmentation processor 210 of FIG. 2. In at least some embodiments, input selector 432 is configured to select data segments 433 from data segments 431 for further processing. In at least some embodiments, input selector 432 is configured to receive parameter stream 438 from a parameter processor, such as parameter processor 219 of FIG. 2. In at least some embodiments, input selector 432 is configured to perform an operation according to parameter stream 438.

[0040] Each circular shifter 434 is configured to receive a data segment 433 from the input selector 432 and send a shifted data segment 435 to the accumulator 436. In at least some embodiments, each circular shifter 434 is configured to apply a circular shift to the data segment 433 to generate a shifted data segment 435. In at least some embodiments, each circular shifter 434 is configured to receive a parameter stream 438 from a parameter processor, such as parameter processor 219 of FIG. 2. In at least some embodiments, each circular shifter 434 is configured to perform operations according to the parameter stream 438. In at least some embodiments, more than one circular shifter 434 is used to process shift operations in parallel. In at least some embodiments, each circular shifter 434 includes the configuration of FIG. 5, described below.

[0041] Each accumulator 436 is configured to receive a shifted data segment 435 from one of the circular shifters 434 and transmit the shifted data segment downstream. In at least some embodiments, each accumulator 436 is configured to accumulate parity bits to generate a parity segment. In at least some embodiments, each accumulator 436 is configured to accumulate statistical information for updating probability values ​​to generate a decoded binary value segment. In at least some embodiments, the number of accumulators 436 is equal to the number of circular shifters 434. In at least some embodiments, each accumulator 436 is configured to receive a parameter stream 438 from a parameter processor, such as parameter processor 219 of FIG. 2. In at least some embodiments, each accumulator 436 is configured to perform an operation according to the parameter stream 438.

[0042] In at least some embodiments, processor 430 includes additional computational elements for pre-processing data segment 431, post-processing the output from accumulator 436, distributing parameters in parameter stream 438, etc. In at least some embodiments, processor 430 is a coding processor, such as coding processor 213 of FIG. 2. In at least some embodiments, the coding processor utilizes multiple circular shifters, each circular shifter applying a circular shift to one of the one or more probability value segments. While processing of data segment 431 is shown in FIG. 4, in at least some embodiments, processor 430 is configured to process probability value segments, such as probability value segment 321 of FIG. 3. In at least some embodiments, processor 430 is a decoding processor, such as decoding processor 323 of FIG. 3. In at least some embodiments, multiple decoding processors operate in parallel, each utilizing a single circular shifter.

[0043] 5 is a schematic diagram of a circular shifter that utilizes a shifter-implemented cyclic permutation matrix operation, in accordance with at least some embodiments of the present invention. Circular shifter 544 includes a filter 550, a backward shifter 551, a forward shifter 553, a mask selector 555, and a combiner 557.

[0044] Filter 550 is configured to receive target segment 543 and mask 556 and send target segment 543 to reverse shifter 551 and forward shifter 553. In at least some embodiments, filter 550 is configured to direct each successive value of target segment 543 to the input of reverse shifter 551 and forward shifter 553 that corresponds to the unmasked indicator in mask 556. In at least some embodiments, filter 550 is configured to discard values ​​that are not part of target segment 543 according to mask 556, the result remaining as target segment 543 but without any values ​​outside the segment length, such as those left over from a previous iteration. In at least some embodiments, filter 550 includes multiple multiplexers arranged in parallel. In at least some embodiments, filter 550 is configured to control the multiple multiplexers according to mask 556, which corresponds to the shift amount and the segment length of segment length 548. In at least some embodiments, filter 550 is configured to control each multiplexer according to a corresponding one-bit flag in mask 556 .

[0045] Reverse shifter 551 is configured to receive target segment 543 and shift amount and segment length 548 and send reverse-shifted partial target segment 552 to combiner 557. In at least some embodiments, reverse shifter 551 includes multiple multiplexers arranged in layers. In at least some embodiments, reverse shifter 551 includes a cascade of parallel 2x1 multiplexers. In at least some embodiments, reverse shifter 551 is configured to control at least some of the multiplexers with signals corresponding to shift amount and segment length 548. In at least some embodiments, reverse shifter 551 is configured to reverse-shift each successive value of target segment 543 by a reverse shift value equal to segment length minus shift amount to generate reverse-shifted partial target segment 552. In at least some embodiments, reverse shifter 551 is configured to discard each successive value of target segment 543 having an original position that is less than or equal to the reverse shift value from the opposite side. In at least some embodiments, reverse shifter 551 is configured to send each remaining consecutive value of target segment 543 to an input of combiner 557 that represents a position shifted backward by the reverse shift value from the original position of that remaining consecutive value. In at least some embodiments, reverse shifter 551 is configured to perform a logical shift backward by the reverse shift value.

[0046] The forward shifter 553 is configured to receive the target segment 543 and at least the shift amount 548 and transmit the forward-shifted partial target segment 554 to the combiner 557. In at least some embodiments, the forward shifter 553 includes multiple multiplexers arranged in layers. In at least some embodiments, the forward shifter 553 includes a cascade of parallel 2x1 multiplexers. In at least some embodiments, the forward shifter 553 is configured to control at least some of the multiplexers with signals corresponding to the shift amount and the segment length 548. In at least some embodiments, the forward shifter 553 is configured to shift each successive value of the target segment 543 forward by the shift amount to generate the forward-shifted partial segment 554. In at least some embodiments, the forward shifter 553 is configured to discard each successive value of the target segment 554 having an original position less than or equal to the shift amount from the forward side. In at least some embodiments, forward shifter 553 is configured to send each remaining consecutive value of target segment 554 to an input of combiner 557 that represents a position shifted forward by the shift amount from the original position of that remaining consecutive value. In at least some embodiments, forward shifter 551 is configured to perform a logical shift forward by the shift value.

[0047] The mask selector 555 is configured to receive the shift amount and the segment length 548 and transmits the mask 556 to the filter 550 and / or the combiner 557. In at least some embodiments, the mask selector 555 is configured to select the mask 556 corresponding to at least one of the shift amount and the segment length 548. In at least some embodiments, the mask selector 555 is a look-up table (LUT). In at least some embodiments, the mask selector 555 is configured to generate the mask 556 based on a function of the shift amount and the segment length. In at least some embodiments, the mask 556 is a merge mask including a string of forward position indicators at consecutive positions equal to the backward shift value from the forward side and a backward position indicator at consecutive positions equal to the shift amount from the nearest forward position indicator on the opposite side. In at least some embodiments, the mask 556 is a filter mask including a string of unmasked indicators at consecutive positions from the forward side equal to the segment length. In at least some embodiments, the mask 556 is a string of one-bit indicators, i.e., ones and zeros. In at least some embodiments, the forward position indicator is represented by a 0 and the backward position indicator is represented by a 1. In at least some embodiments, the unmasked indicator is represented by a 1 and the remainder of the string is represented by a 0.

[0048] Combiner 557 is configured to receive backward-shifted partial target segments 552 and forward-shifted partial target segments 554 and to transmit shifted target segment 545. In at least some embodiments, combiner 557 is configured to combine forward-shifted partial target segments 554 and backward-shifted partial target segments 552 according to mask 556 to generate shifted target segment 545. In at least some embodiments, combiner 557 is configured to route each successive value of forward-shifted partial target segment 554 to an input of an accumulator, such as accumulator 436 of FIG. 4 , that corresponds to the forward position indicator in mask 556. In at least some embodiments, combiner 557 is configured to route each successive value of backward-shifted partial target segment 552 to an input of an accumulator that corresponds to the backward position indicator in mask 556. In at least some embodiments, combiner 557 includes multiple multiplexers arranged in parallel. In at least some embodiments, combiner 557 controls multiple multiplexers with a mask 556 corresponding to the shift amount and segment length 548. In at least some embodiments, each multiplexer is controlled according to a corresponding one-bit flag in mask 556. In at least some embodiments, combiner 557 includes multiple OR gates arranged in parallel. In at least some embodiments, the multiple OR gates are configured to combine forward-shifted partial target segment 554 and backward-shifted partial target segment 552 to generate shifted target segment 545 without a merge mask. In at least some embodiments, the multiple OR gates do not require a merge mask, provided that filter 550 applies a filter mask. In at least some embodiments, combiner 557 is configured to discard each successive value of forward-shifted partial target segment 554 that lacks a corresponding forward position indicator in mask 556.In at least some embodiments, combiner 557 is configured to discard each successive value of backward shifted partial target segment 554 that lacks a corresponding backward position indicator in mask 556. In at least some embodiments, combiner 557 is further configured to perform the operation of filter 550 to filter shifted target segment 545 according to a filter mask.

[0049] In at least some embodiments, the circular shift is implemented in some other manner, such as clockwise, counterclockwise, or relative to some other reference point. In at least some embodiments, a forward shift is implemented as a right shift, and a backward shift is implemented as a left shift. In at least some embodiments, a forward shift is implemented as a left shift, and a backward shift is implemented as a right shift. In at least some embodiments, the discarding of consecutive values ​​is performed by a passive action or lack of action, such as ignoring consecutive values. In at least some embodiments, the discarding of consecutive values ​​is achieved by not passing consecutive values ​​to the input of a subsequent stage in the pipeline. In at least some embodiments, the discarding of consecutive values ​​is referred to as "shifting out" during a logical shift. In at least some embodiments, the mask selector is configured to operate selectively. In at least some embodiments, the mask selector is configured to send only the merge mask to the combiner, send only the filter mask, or send both the merge mask and the filter mask to the combiner in response to receiving the shift amount and the segment length. In at least some embodiments, such as those in which the combiner includes multiple multiplexers or in which the combiner also performs the function of a filter, the circular shifter does not include a filter.

[0050] FIG. 6A is a diagram of the original positions of a target segment, in accordance with at least one embodiment of the present invention. Target segment 643 has a segment length of six and therefore includes six consecutive values, designated A, B, C, D, E, and F from the right, which is a forward implementation in this embodiment. Each consecutive value is routed to an input representing the original position of that consecutive value. In at least some embodiments, each consecutive value is routed by an input selector, such as input selector 432 of FIG. 4, to an input of a circular shifter, such as circular shifter 434 of FIG. 4, representing the original position of that consecutive value. For example, the consecutive value designated "B" is routed to input 658A representing the second position from the right, and the consecutive value designated "C" is routed to input 659A representing the third position from the right.

[0051] FIG. 6B is a diagram of a shifted target segment having a segment length of 3 and shifted by 2, in accordance with at least one embodiment of the present invention. Shifted target segment 645B is the result of a circular shift of a target segment, such as target segment 643, but with only three consecutive values, A, B, and C, from the right side. As a result of the shift amount of 2, the consecutive value designated as "C" occupies a new position that is shifted two positions to the right from "C's" original position. The consecutive value designated as "C" is sent to input 659B, which represents the first position from the right side. In at least some embodiments, the consecutive value designated as "C" is sent to input 659B of an accumulator, such as accumulator 436 of FIG. 4, which represents the first position from the right side. As a result of the shift amount of 2, the consecutive value designated as "B" occupies a new position. The new position occupied by the consecutive value designated as "B" does not appear to be shifted two positions to the right, but rather appears to be shifted one position to the left. This is because in a circular shift, a shift to the right position beyond the first position is a shift to the left position to the first position. The successive value designated as "B" is sent to input 658B, which represents the third position from the right.

[0052] FIG. 6C is a diagram of a shifted target segment having a segment length of 4 and shifted by 2, in accordance with at least one embodiment of the present invention. Shifted target segment 645C is the result of a circular shift of a target segment such as target segment 643, but with only four consecutive values ​​A, B, C, and D from the right side. As a result of the shift amount 2, the consecutive value designated as "C" occupies a new position that is shifted two positions to the right from the original position of "C." The consecutive value designated as "C" is sent to input 659C, which represents the first position from the right side. As a result of the shift amount 2, the consecutive value designated as "B" occupies a new position corresponding to a shift of two positions to the right from the original position of "B." The consecutive value designated as "B" is sent to input 658C, which represents the fourth position from the right side.

[0053] 6D is a diagram of a shifted target segment having a segment length of 5 and shifted by 2, in accordance with at least one embodiment of the present invention. Shifted target segment 645D is the result of a circular shift of a target segment such as target segment 643, but with only five consecutive values ​​A, B, C, D, and E from the right. As a result of the shift amount of 2, the consecutive value designated as "C" occupies a new position shifted two positions to the right from the original position of "C." The consecutive value designated as "C" is sent to input 659D, which represents the first position from the right. As a result of the shift amount of 2, the consecutive value designated as "B" occupies a new position corresponding to a shift of two positions to the right from the original position of "B." The consecutive value designated as "B" is sent to input 658D, which represents the fifth position from the right.

[0054] 6E is a diagram of a shifted target segment having a segment length of 6 and shifted by 2, in accordance with at least one embodiment of the present invention. Shifted target segment 645D is the result of a circular shift of a target segment, such as target segment 643. As a result of the shift amount of 2, the successive value denoted as "C" occupies a new position that is shifted two positions to the right from the original position of "C." The successive value denoted as "C" is sent to input 659E, which represents the first position from the right. As a result of the shift amount of 2, the successive value denoted as "B" occupies a new position that corresponds to a shift of two positions to the right from the original position of "B." The successive value denoted as "B" is sent to input 658E, which represents the sixth position from the right.

[0055] 7 is an operational flow for LDPC data decoding utilizing a shifter-implemented cyclic permutation matrix operation, in accordance with at least some embodiments of the present invention. The operational flow provides a method for LDPC data decoding utilizing a shifter-implemented cyclic permutation matrix operation. In at least some embodiments, the method is performed by an integrated circuit, such as integrated circuit decoder 308 shown in FIG. 3.

[0056] At S760, the segmentation processor segments the LDCP-encoded data block. In at least some embodiments, the segmentation processor segments the low-density parity-check (LDPC)-encoded probability value data block by dividing the encoded data block into a plurality of data probability value segments and a plurality of parity probability value segments, each probability value of the encoded data block representing a likelihood between binary values. In at least some embodiments, the segmentation processor divides the encoded data block into segments of one or more predetermined lengths. In at least some embodiments, the segmentation processor divides the encoded data block into segments having lengths according to the length of the encoded data block.

[0057] At S763, the decoding processor decodes the data probability value segment. In at least some embodiments, the decoding processor applies a parity check matrix to the data probability value segment and the parity probability value segment to generate a decoded binary value segment. In at least some embodiments, the decoding processor applies an LDPC parity check matrix to the data probability value segment and the parity probability value segment to generate a decoded binary value segment. In at least some embodiments, the decoding processor applies one or more cyclic shifts to the data probability value segment and the parity probability value segment according to the parity check matrix to generate a decoded binary value segment. In at least some embodiments, the decoding processor compares the binary values ​​in the subsets of values ​​of corresponding data probability value segment and parity probability value segment to ensure that the values ​​sum to an even number. In at least some embodiments, the decoding processor decodes the encoded data block by adjusting the probability values ​​of the encoded data block based on a parity check matrix according to an iterative variable accuracy parameter, the parity check matrix defining a correspondence between data probability value segments and parity probability value segments, where the iterative variable accuracy parameter represents a trade-off between accuracy and computational efficiency. In at least some embodiments, the decoding processor performs the operational flow shown in FIG. 8, which is described below.

[0058] At S769, the concatenation processor concatenates the likely binary values. In at least some embodiments, the concatenation processor concatenates the likely binary values ​​that fill the parity check matrix associated with the probability values ​​of each data probability value segment to form a decoded data block. In at least some embodiments, the concatenation processor concatenates the likely binary value segments to generate the decoded data block. In at least some embodiments, the concatenation processor concatenates the likely binary value segments to form a format identical to the original data block.

[0059] 8 is an operational flow for data probability value segment decoding utilizing a shifter-implemented cyclic permutation matrix operation, in accordance with at least one embodiment of the present invention. The operational flow provides a method for data probability value segment decoding utilizing a shifter-implemented cyclic permutation matrix operation. In at least some embodiments, the method is performed by an integrated circuit, such as the integrated circuit decoder 308 shown in FIG. 3.

[0060] At S870, the decoder selects an input. In at least some embodiments, the decoder selects one or more probability value segments for further processing from among the probability value segments received from a segmentation processor, such as segmentation processor 321 of Figure 3. In at least some embodiments, the decoder selects the input using an input selector.

[0061] At S873, the decoder applies a circular shift. In at least some embodiments, the decoder applies a circular shift to one or more probability value segments to generate shifted probability value segments. In at least some embodiments, the decoder utilizes a circular shifter to apply the circular shift to one or more probability value segments. In at least some embodiments, the decoder utilizes the circular shifter to apply the circular shift to the probability value segments over multiple clock cycles by shifting a portion of the successive values ​​of the probability value segments in each clock cycle. In at least some embodiments, shifting a portion of the successive values ​​of the probability value segments allows for the use of smaller shifters, which allows for smaller circuit size.

[0062] At S876, the decoder accumulates statistical information. In at least some embodiments, the decoder accumulates statistical information for updating the probability values ​​to generate decoded binary value segments. In at least some embodiments, the decoder utilizes a circular shifter to accumulate statistical information from one or more shifted probability value segments. In at least some embodiments, the decoder utilizes multiple accumulators, each accumulator accumulating statistical information from one shifted probability value segment of the one or more shifted probability value segments.

[0063] 9 is an operational flow for applying a shifter-implemented cyclic permutation matrix operation in accordance with at least one embodiment of the present invention. The operational flow provides a method for applying a shifter-implemented cyclic permutation matrix operation. In at least some embodiments, the method is performed by an integrated circuit cyclic shifter, such as cyclic shifter 544 shown in FIG. 5.

[0064] At S982, the circular shifter selects a mask. In at least some embodiments, the circular shifter selects the mask by utilizing a look-up table (LUT). In at least some embodiments, the circular shifter selects a merge mask corresponding to the shift amount and the segment length via a mask selector in the integrated circuit. In at least some embodiments, the circular shifter generates the merge mask based on a function of the shift amount and the segment length. In at least some embodiments, the merge mask includes forward position indicators at successive positions equal to the reverse shift value from the forward side and backward position indicators at successive positions equal to the shift amount from the forward position indicator closest to the opposite side. In at least some embodiments, the circular shifter selects a filter mask corresponding to the segment length via the mask selector. In at least some embodiments, the filter mask includes unmasked position indicators at successive positions from the forward side equal to the segment length.

[0065] At S984, the circular shifter shifts the target segment forward. In at least some embodiments, the circular shifter shifts each consecutive value of the target segment forward by the shift amount using an integrated circuit forward shifter to generate a forward-shifted partial target segment. In at least some embodiments, the circular shifter discards each consecutive value of the target segment having an original position less than or equal to the shift amount from the forward side. In at least some embodiments, the circular shifter sends each remaining consecutive value of the target segment to an input of a combiner, such as combiner 557 of FIG. 5, representing a position shifted forward by the shift amount from the original position of that remaining consecutive value.

[0066] At S985, the circular shifter shifts the target segment in the reverse direction. In at least some embodiments, the circular shifter, using an integrated circuit reverse shifter, shifts each successive value of the target segment in the reverse direction by a reverse shift value equal to the segment length minus the shift amount to generate a reverse-shifted partial target segment. In at least some embodiments, the circular shifter discards each successive value of the target segment having an original position that is less than or equal to the reverse shift value from the opposite side. In at least some embodiments, the circular shifter sends each remaining successive value of the target segment to an input of the combiner, representing a position shifted in the reverse direction by the reverse shift value from the original position of the remaining successive value.

[0067] At S987, the circular shifter combines the partial segments. In at least some embodiments, the circular shifter combines the forward-shifted partial target segment and the backward-shifted partial target segment using a combiner in an integrated circuit to generate a shifted target segment. In at least some embodiments, the circular shifter routes each successive value of the forward-shifted partial target segment to an input of an accumulator, such as accumulator 436 of FIG. 4, corresponding to the shift amount and segment length. In at least some embodiments, the circular shifter routes each successive value of the backward-shifted partial target segment to an input of an accumulator, such as accumulator 436 of FIG. 4, corresponding to the shift amount and segment length. In at least some embodiments, the circular shifter discards each successive value of the forward-shifted partial target segment that does not correspond to the shift amount and segment length. In at least some embodiments, the circular shifter discards each successive value of the backward-shifted partial target segment that does not correspond to the shift amount and segment length. In at least some embodiments, the circular shifter combines the forward-shifted partial target segment and the backward-shifted partial target segment according to the merge mask using a combiner in the integrated circuit to generate a shifted target segment. In at least some embodiments, the circular shifter routes each successive value of the forward-shifted partial target segment to an input of an accumulator, such as accumulator 436 of FIG. 4, that corresponds to a forward position indicator in the merge mask. In at least some embodiments, the circular shifter routes each successive value of the backward-shifted partial target segment to an input of an accumulator that corresponds to a backward position indicator in the merge mask. In at least some embodiments, the circular shifter discards each successive value of the forward-shifted partial target segment that lacks a corresponding forward position indicator in the merge mask. In at least some embodiments, the circular shifter discards each successive value of the backward-shifted partial target segment that lacks a corresponding backward position indicator in the merge mask.

[0068] At S989, the circular shifter filters the shifted target segment. In at least some embodiments, the circular shifter filters the shifted target segment according to a filter mask via a combiner. In at least some embodiments, the circular shifter sends each successive value of the shifted target segment to an input of an accumulator corresponding to an unmasked indicator in the filter mask. In at least some embodiments, the circular shifter discards values ​​that are not part of the shifted target segment according to the filter mask, and the result remains the shifted target segment, but without any values ​​outside the segment length, such as those left over from a previous iteration. In at least some embodiments, the circular shifter controls multiple multiplexers according to a filter mask that corresponds to the shift amount and the segment length of segment length 548. In at least some embodiments, the circular shifter controls each multiplexer according to a corresponding one-bit flag in mask 556.

[0069] In at least some embodiments of applying a circular shift, the circular shifter does not select a merge mask. In at least some embodiments of applying a circular shift, filtering is optional, so the circular shifter does not select a filter mask or filter the shifted target segment. In at least some embodiments, the operations at S984 and S985 can be performed in any order, even overlapping times or simultaneously, as long as the operations at S984 and S985 are performed before the operation at S987. In at least some embodiments, the circular shifter filters the target segment with a filter before the target segment is shifted in S984 and S985.

[0070] FIG. 10 is a diagram of a data segment undergoing a shifter-implemented cyclic permutation matrix operation with a shift amount of 2, in accordance with at least one embodiment of the present invention. The target segment 1043 has a segment length of 5 and therefore includes five consecutive values, denoted A, B, C, D, and E from the right, which is a forward implementation in this embodiment. Each consecutive value is sent to an input representing the original position of that consecutive value. In at least some embodiments, each consecutive value is sent by an input selector, such as input selector 432 in FIG. 4, to an input of a circular shifter, such as circular shifter 434 in FIG. 4, representing the original position of that consecutive value. In this embodiment, there are six inputs representing the maximum segment length of the operation. In this embodiment, the value denoted as "F" is not part of the target segment 1043, but six inputs are utilized in each shift operation to avoid the need for different hardware configurations or software instructions for each target segment length.

[0071] 9 , shifting the target segment 1043 forward results in a forward-shifted partial target segment 1054. In operation, values ​​designated as "A" and "B" are discarded because they occupy positions less than or equal to the shift amount, and values ​​designated as "C," "D," "E," and "F" are shifted forward by two positions. In at least some embodiments, each of the consecutive values ​​designated as "C," "D," "E," and "F" is sent by a forward shifter, such as forward shifter 553 of FIG. 5 , to the input of a combiner, such as combiner 557 of FIG. 5 , representing a position shifted forward by two positions from the consecutive value's original position. The value designated as "F" is shifted despite the fact that this value is not part of the target segment 1043.

[0072] 9 , shifting the target segment 1043 backward results in a backward-shifted partial target segment 1052. In operation, a backward shift value, which is equal to the segment length minus the shift amount, is determined to be 3. In operation, the values ​​designated as “D,” “E,” and “F” are discarded because they occupy positions less than or equal to the backward shift value, and the values ​​designated as “A,” “B,” and “C” are shifted backward by three positions. In at least some embodiments, each of the consecutive values ​​designated as “A,” “B,” and “C” is sent by a backward shifter, such as backward shifter 551 of FIG. 5 , to the input of a combiner, such as combiner 557 of FIG. 5 , representing a position shifted backward by three positions from the consecutive value's original position.

[0073] Optionally, as a result of a mask selection, such as the operation at S982 of FIG. 9 , a merge mask 1056 is retrieved. The merge mask 1056 includes contiguous indicators represented by “1” and “0.” Values ​​represented by “1” are forward position indicators. The forward position indicators occupy positions corresponding to successive values ​​of the forward-shifted partial target segment 1054 that exactly occupy positions in the shifted target segment 1045. Values ​​represented by “0” are backward position indicators. The backward position indicators occupy positions corresponding to successive values ​​of the backward-shifted partial target segment 1052 that exactly occupy positions in the shifted target segment 1045. Positions in the merge mask 1056 are indicated by binary indicators, and thus positions intended to remain unoccupied are represented by “0,” even though they are also backward position indicators. In at least some embodiments, the circular shifter is configured so that values ​​in positions intended to remain unoccupied are ignored or masked to 0 before reaching the shifter.

[0074] Optionally, as a result of a mask selection, such as the operation at S982 of FIG. 9 , a filter mask 1090 is retrieved. The filter mask 1090 includes continuity indicators represented by "0" and "1". In at least some embodiments, the continuity indicator is a 1-bit flag. A value represented by "0" is a masked position indicator. A masked position indicator occupies a position in the shifted target segment 1045 that corresponds to an unoccupied position or a position masked to 0. A value represented by "1" is an unmasked position indicator. An unmasked position indicator occupies a position in the shifted target segment 1045 that corresponds to an occupied position.

[0075] 9 , the forward-shifted partial target segment 1054 and the backward-shifted partial target segment 1052 are combined according to a shift amount of 2 and a segment length of 5, optionally using one or both of a merge mask 1056 and a filter mask 1090, to generate a shifted target segment 1045. The value indicated as “C” occupies the corresponding position in the forward-shifted partial target segment 1054, and the corresponding position in the merge mask 1056 is occupied by the forward position indicator “F,” so that the first position on the right, or forward side, of the shifted target segment 1045 is occupied by the value indicated as “C.” Similarly, each other position of the shifted target segment 1045 is occupied by the value of the corresponding position in either the forward-shifted partial target segment 1054 or the backward-shifted partial target segment 1052. In at least some embodiments, each successive value is sent by a combiner, such as combiner 557 of Figure 5, to the input of an accumulator, such as accumulator 436 of Figure 4, that represents a position shifted forward by two positions from the original position of that successive value according to a circular shift amount of 2 and a segment length of 5. The sixth position to the right or forward of the shifted target segment 1045 corresponds to a value designated as "C", but this value is not part of the shifted target segment 1045.

[0076] In at least some embodiments, the apparatus is a separate device capable of processing logical functions to perform the operations herein. In at least some embodiments, the controller and storage unit need not be entirely separate devices, and in some embodiments, share circuitry or one or more computer-readable media. In at least some embodiments, the storage unit includes a hard drive that stores both computer-executable instructions and data accessed by the controller, and the controller includes a combination of a central processing unit (CPU) and RAM into which the computer-executable instructions can be copied, in whole or in part, for execution by the CPU during performance of the operations herein.

[0077] At least some embodiments are described with reference to flowcharts and block diagrams, whose blocks represent (1) process steps in which operations are performed or (2) sections of a controller responsible for performing operations. In at least some embodiments, particular steps and sections are implemented by dedicated circuitry, programmable circuitry provided with computer-readable instructions stored on a computer-readable medium, and / or a processor provided with computer-readable instructions stored on a computer-readable medium. In at least some embodiments, dedicated circuitry includes digital and / or analog hardware circuitry, including integrated circuits (ICs) and / or discrete circuits. In at least some embodiments, programmable circuitry includes reconfigurable hardware circuitry, such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), etc., including logical AND, OR, XOR, NAND, NOR, and other logic operations, flip-flops, registers, memory elements, etc.

[0078] In at least some embodiments, a computer-readable storage medium comprises a tangible device capable of retaining and storing instructions for use by an instruction-execution device. In some embodiments, a computer-readable storage medium comprises, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves on which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as being a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through a fiber optic cable), or an electrical signal transmitted through a wire.

[0079] In at least some embodiments, the computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a respective computing / processing device or to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. In at least some embodiments, the network includes copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. In at least some embodiments, a network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within the respective computing / processing device.

[0080] In at least some embodiments, the computer-readable program instructions that perform the operations described above are either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk® or C++, and traditional procedural programming languages ​​such as the “C” programming language or similar programming languages. In at least some embodiments, the computer-readable program instructions execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In at least some embodiments, in the latter scenario, the remote computer is connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection is made to an external computer (e.g., through the Internet using an Internet Service Provider). In at least some embodiments, electronic circuitry, including, for example, programmable logic circuitry, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), executes computer-readable program instructions by utilizing state information in the computer-readable program instructions to individualize the electronic circuitry to perform aspects of the present invention.

[0081] Although embodiments of the present invention have been described, the technical scope of any subject matter described in the claims is not limited to the above-described embodiments. Those skilled in the art will understand that various modifications and improvements to the above-described embodiments are possible. Those skilled in the art will also understand that embodiments to which such modifications or improvements have been made fall within the technical scope of the present invention, based on the scope of the claims.

[0082] The operations, procedures, steps, and stages of each process performed by the apparatus, system, program, and method shown in the claims, embodiments, or figures can be performed in any order, unless the order is indicated by "prior to" or "before," etc., and unless output from a previous process is used in a later process. Even when a process flow is described in the claims, embodiments, or figures using phrases such as "first" or "next," such description does not necessarily mean that the processes must be performed in the order described.

[0083] In at least some embodiments, the shifter-implemented cyclic permutation matrix operation is realized by an integrated circuit that includes: a forward shifter configured to shift each successive value of the target segment forward by the shift amount to generate a forward-shifted partial segment; a reverse shifter configured to shift each successive value of the target segment backward by a reverse shift value equal to the segment length minus the shift amount to generate a backward-shifted partial target segment; a combiner configured to combine the forward-shifted partial target segment and the backward-shifted partial target segment according to the shift amount and the segment length to generate a shifted target segment; and a mask selector configured to select at least one of a merge mask corresponding to the shift amount and the segment length and a filter mask corresponding to the segment length.

[0084] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that this disclosure may readily be used as a basis for designing or modifying other processes and structures which carry out the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure. According to this specification, the following items are also disclosed. [Item 1] a forward shifter configured to shift each successive value of the target segment forward by a shift amount to generate a forward-shifted partial segment; a reverse shifter configured to reverse shift each successive value of said target segment by a reverse shift value equal to a segment length minus said shift amount to generate a reverse shifted partial target segment; a combiner configured to combine the forward-shifted partial target segments and the backward-shifted partial target segments to generate a shifted target segment; and A mask selector, a merge mask corresponding to the shift amount and the segment length; and Filter mask corresponding to the above segment length a mask selector configured to select at least one of 1. An integrated circuit comprising: [Item 2] The forward shifter is Discarding each successive value of the target segment having an original position that is less than or equal to the shift amount from the forward side; and sending each remaining consecutive value of the target segment to an input of the combiner, the input representing a position shifted forward from the original position of the remaining consecutive value by the shift amount; Item 1. The integrated circuit of item 1, further configured as follows: [Item 3] The reverse shifter is Discarding each successive value of said target segment having an original position that is less than or equal to said reverse shift value from the opposite side; and sending each remaining consecutive value of the target segment to an input of the combiner, the input representing a position of the remaining consecutive value shifted backward from the original position by the reverse shift value; Item 1. The integrated circuit of item 1, further configured as follows: [Item 4] The coupler comprises: sending each successive value of the forward shifted partial target segment to an input corresponding to the shift amount and the segment length; Sending each successive value of the backward shifted partial target segment to an input corresponding to the shift amount and the segment length. Item 1. The integrated circuit of item 1, further configured as follows: [Item 5] Item 1. The integrated circuit of item 1, wherein the combiner is further configured to combine the forward-shifted partial target segments and the backward-shifted partial target segments according to the merge mask. [Item 6] The above merge mask is a forward position indicator at a successive position equal to said reverse shift value from the forward side; and a reverse position indicator at successive positions equal to said shift from the oppositely nearest forward position indicator; Item 1. The integrated circuit of item 1, comprising: [Item 7] a filter configured to filter the target segment according to the filter mask before the target segment is shifted forward and backward; Item 1. The integrated circuit of item 1, further comprising: [Item 8] The coupler comprises: Filter the shifted target segment according to the filter mask. Item 1. The integrated circuit of item 1, further configured as follows: [Item 9] Item 2. The integrated circuit of item 1, wherein the filter mask includes unmasked position indicators at successive positions from the front side equal to the segment length. [Item 10] a forward shifter of the integrated circuit shifting each successive value of the target segment forward by a shift amount to generate a forward-shifted partial target segment; a reverse shifter of the integrated circuit reverse shifting each successive value of the target segment by a reverse shift value equal to a segment length minus the shift amount to generate a reverse-shifted partial target segment; a combiner of the integrated circuit combining the forward shifted partial target segment and the backward shifted partial target segment to generate a shifted target segment; and The mask selector of the integrated circuit is a merge mask corresponding to the shift amount and the segment length; and Filter mask corresponding to the above segment length selecting at least one of A method for providing [Item 11] The forward shifting step includes: discarding each successive value of the target segment having an original position less than or equal to the shift amount from the forward side; and sending each remaining successive value of the target segment to an input of the combiner representing a position shifted forward by the shift amount from the original position of the remaining successive value; Item 11. The method according to Item 10, comprising: [Item 12] The step of shifting in the opposite direction comprises: discarding each successive value of the target segment having an original position that is less than or equal to the reverse shift value from the opposite side; and sending each remaining consecutive value of the target segment to an input of the combiner representing a position shifted backward from the original position of the remaining consecutive value by the reverse shift value; Item 11. The method according to Item 10, comprising: [Item 13] The bonding step comprises: sending each successive value of the forward shifted partial target segment to an input corresponding to the shift amount and the segment length; sending each successive value of the backward shifted partial target segment to an input corresponding to the shift amount and the segment length; Item 11. The method according to Item 10, comprising: [Item 14] Item 11. The method of item 10, wherein the forward shifted partial target segment is combined with the backward shifted partial target segment according to the merge mask. [Item 15] The above merge mask is a forward position indicator at a successive position equal to said reverse shift value from the forward side; and a reverse position indicator at successive positions equal to said shift from the oppositely nearest forward position indicator; Item 11. The method according to item 10, comprising: [Item 16] a filter in the integrated circuit filtering the target segment according to the filter mask before the target segment is shifted forward and backward; Item 11. The method of item 10, further comprising: [Item 17] the mask selector selecting a filter mask; and the combiner filtering the shifted target segment according to the filter mask. Item 11. The method of item 10, further comprising: [Item 18] Item 11. The method of item 10, wherein the filter mask includes unmasked position indicators at successive positions from the anterior side equal to the segment length.

Claims

1. a forward shifter configured to shift each successive value of the target segment forward by a shift amount to generate a forward-shifted sub-segment; a reverse shifter configured to reverse shift each successive value of the target segment by a reverse shift value equal to a segment length scalable from a maximum segment length to a minimum segment length minus the shift amount to generate a reverse-shifted partial target segment; a combiner configured to combine the forward-shifted partial target segments and the backward-shifted partial target segments to generate a shifted target segment; and A mask selector, a mask selector configured to generate a merge mask corresponding to the shift amount and the segment length, the merge mask including a forward position indicator indicating a position corresponding to successive values ​​of the forward shifted partial target segment and a backward position indicator indicating a position corresponding to successive values ​​of the backward shifted partial target segment. Equipped with The combiner is an integrated circuit that combines the forward shifted partial target segments and the backward shifted partial target segments according to the merge mask.

2. The mask selector a filter mask corresponding to the segment length, the filter mask including unmasked position indicators at successive positions from the front side equal to the segment length; further configured to select a filter configured to filter the target segment according to the filter mask before the target segment is shifted forward and backward; The integrated circuit of claim 1 further comprising:

3. The forward shifter Discarding each successive value of the target segment having an original position less than or equal to the shift amount from the forward side; and Sending each remaining consecutive value of the target segment to an input of the combiner at a position shifted forward by the shift amount from the original position of the remaining consecutive value.

3. The integrated circuit of claim 1, further configured as follows:

4. The backward shifter Discarding each successive value of the target segment having an original position that is less than or equal to the reverse shift value from the opposite side; and Sending each remaining consecutive value of the target segment to an input of the combiner at a position that is shifted backward from the original position of the remaining consecutive value by the reverse shift value.

3. The integrated circuit of claim 1, further configured as follows:

5. The coupler comprises: sending each successive value of the forward shifted partial target segment to an input corresponding to the shift amount and the segment length; Sending each successive value of the backward shifted partial target segment to an input corresponding to the shift amount and the segment length.

3. The integrated circuit of claim 1, further configured as follows:

6. The merge mask is a forward position indicator at successive positions equal to said reverse shift value from the forward side; and a reverse position indicator at successive positions equal to said shift from the oppositely closest forward position indicator; 3. The integrated circuit of claim 1, comprising:

7. The coupler comprises: Filtering the shifted target segment according to the filter mask.

3. The integrated circuit of claim 2, further configured as follows:

8. a forward shifter of the integrated circuit shifting each successive value of the target segment forward by a shift amount to generate a forward-shifted partial target segment; a reverse shifter of the integrated circuit reversely shifting each successive value of the target segment by a reverse shift value equal to a segment length scalable from a maximum segment length to a minimum segment length minus the shift amount to generate a reverse-shifted partial target segment; a combiner in the integrated circuit combining the forward shifted partial target segment and the backward shifted partial target segment to generate a shifted target segment; and a mask selector for the integrated circuit, generating a merge mask corresponding to the shift amount and the segment length, the merge mask including a forward position indicator indicating a position corresponding to successive values ​​of the partial target segment shifted in the forward direction and a backward position indicator indicating a position corresponding to successive values ​​of the partial target segment shifted in the backward direction; Equipped with The forward shifted partial target segments are merged with the backward shifted partial target segments according to the merge mask.

9. The mask selector: selecting a filter mask corresponding to the segment length, the filter mask including unmasked position indicators at successive positions from the front side equal to the segment length; and a filter in the integrated circuit filtering the target segment according to the filter mask before the target segment is shifted forward and backward; The method of claim 8 further comprising:

10. The forward shifting step includes: discarding each successive value of the target segment having an original position less than or equal to the shift amount from the forward side; and sending each remaining consecutive value of the target segment to an input of the combiner at a position shifted forward by the shift amount from the original position of the remaining consecutive value; 10. The method of claim 8 or 9, comprising:

11. The step of shifting in the opposite direction comprises: discarding each successive value of the target segment having an original position that is less than or equal to the reverse shift value from the opposite side; and sending each remaining consecutive value of the target segment to an input of the combiner at a position shifted backward from the original position of the remaining consecutive value by the reverse shift value; 10. The method of claim 8 or 9, comprising:

12. The binding step comprises: sending each successive value of the forward shifted partial target segment to an input corresponding to the shift amount and the segment length; sending each successive value of the backward shifted partial target segment to an input corresponding to the shift amount and the segment length; 10. The method of claim 8 or 9, comprising:

13. The merge mask is a forward position indicator at successive positions equal to said reverse shift value from the forward side; and a reverse position indicator at successive positions equal to said shift from the oppositely closest forward position indicator; 10. The method of claim 8 or 9, comprising:

14. the combiner filtering the shifted target segment according to the filter mask. The method of claim 9 further comprising:

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