Pixel circuit

Abstract

A pixel circuit including an LED, a first / second internal node setting transistor, and a brightness control transistor is provided. The LED is electrically connected to a supply voltage line. The first internal node setting transistor is electrically connected to the LED and a first internal node. The second internal node setting transistor is electrically connected to a second internal node and a data signal line. The voltage of the data signal line during a data voltage writing duration is equivalent to a pixel data setting voltage. During a pixel emission duration, a pixel current starting from a supply voltage line to a ground voltage line flows through the LED, the first internal setting transistor, and the brightness control transistor. The current value of the pixel current is related to the voltage of the first internal node and the voltage of the second internal node during the pixel emission duration. The voltage of the second internal node during the pixel emission duration is related to the threshold voltage of the brightness control transistor and the pixel data setting voltage.

Description

[Technical Field]

[0001] The present invention relates to a pixel circuit, and more particularly to a pixel circuit that simplifies the control of the brightness variables of micro-light-emitting diodes (μLEDs) (m, n) and improves the aperture ratio of the display panel. [Previous Technology]

[0002] In recent years, micro light emitting diode (μLED) display panels have become increasingly popular due to their advantages such as high efficiency and low power consumption. Please refer to Figure 1, which is a schematic diagram of a μLED display panel 10. The μLED display panel 10 is electrically connected to a timing control circuit through M data signal lines DAT[1]~DAT[M] and N gate signal lines GL[1]~GL[N]. The timing control circuit may further include a timing controller, a source driver, a row driver, etc. The internal circuitry and operation of the timing control circuit will not be described in detail here.

[0003] The timing control circuit, with a frame period of Tframe, determines the screen content displayed by the μLED display panel 10 during X frame periods Tframe[1] to Tframe[X] by controlling the voltage of the data signal lines DAT[1]~DAT[M] and the gate signal lines GL[1]~GL[N]. For ease of explanation, the same symbols are used to represent both signal lines and signals on the signal lines. For example, DAT[m] represents both the data signal line and the data signal.

[0004] The μLED display panel 10 includes pixel circuits PXL(1, 1) to PXL(M, N) arranged in M ​​rows and N columns. The pixel circuits PXL(m, n) are electrically connected to the data signal line DAT[m] of the m-th row and the gate signal line GL[n] of the n-th column. During the x-th frame Tframe[x], the timing control circuit controls the gate signal lines GL[1] to GL[N] to generate pulses column by column to enable the pixel circuits PXL(1~M, 1) to PXL(1~M, N) located in the n=1~N columns. Where m, n, x, M, N, and X are all positive integers, m≤M, n≤N, and x≤X.

[0005] In addition, the luminance of each pixel circuit PXL(1, 1) to PXL(M, N) during the x-th frame period Tframe[x] varies with the voltage of the data signal lines DAT[1] to DAT[M] of each row (m=1~M). For example, when the grayscale corresponding to Tframe[x] of pixel circuit PXL(m, n) during the x-th frame period is L255, the voltage of data signal line DAT[m] is the lowest (e.g., 2V); or, when the grayscale corresponding to Tframe[x] of pixel circuit PXL(m, n) during the x-th frame period is L0, the voltage of data signal line DAT[m] is the highest (e.g., 10V).

[0006] Please refer to Figure 2, which is a schematic diagram of a conventional μLED pixel circuit. The pixel circuit PXLo(m, n) is electrically connected to the supply voltage line Vdd (e.g., 10V), the ground voltage line Vss (e.g., 0V), the data signal line DAT[m], the light-emitting enable gate signal line EM[n], and the pixel data writing gate signal line WS[n]. The light-emitting enable gate signal line EM[n] and the pixel data writing gate signal line WS[n] belong to the same subclass of the gate signal line GL[n].

[0007] The brightness of the micro-light-emitting diode μLED(m, n) within the pixel circuit PXLo(m, n) depends on the magnitude of the pixel current ILED(m, n) flowing through the micro-light-emitting diode μLED(m, n). In this diagram, the magnitude of the pixel current ILED(m, n) can be expressed according to the transistor current formula as Equation 1. In Equation 1, Vgs represents the voltage difference between the gate G and source S of the brightness control transistor Tled(m, n), K is a constant, and Vth is the threshold voltage of the brightness control transistor Tled(m, n). Wherein, when the micro-light-emitting diode μLED(m, n) emits light, the voltage difference Vgs between the gate G and source S of the brightness control transistor Tled(m, n) can be further expressed as the difference between the supply voltage Vdd and the data signal DAT[m], that is, Vgs = (DAT[m] - Vdd). ILED(m, n)=K(Vgs-Vth)2 =K((DAT[m]-Vdd)-Vth)2…………………………………………(Equation 1)

[0008] As can be seen from Equation 1, the magnitude of the pixel current ILED(m, n) flowing through the micro-light-emitting diode μLED(m, n) (ILED(m, n) = K((DAT[m] - Vdd) - Vth)2) is affected not only by the voltage of the data signal DAT[m], but also by the supply voltage Vdd and the critical voltage Vth of the brightness control transistor Tled(m, n). However, since the supply voltage Vdd needs to be supplied to M*N pixel circuits PXL(1, 1)~PXL(M, N) on the display panel simultaneously, fluctuations or instability may occur during operation. Moreover, the critical voltage Vth of the brightness control transistor Tled(m, n) may vary depending on the transistor's manufacturing process. Consequently, when the timing control circuit controls the brightness of the micro-light-emitting diode μLED(m, n), it must consider many variables in order to accurately control the brightness of the pixel circuit PXLo(m, n). [Summary of the Invention]

[0009] This invention relates to a pixel circuit. The pixel circuit of this invention has a high aperture ratio, and the brightness of the light-emitting diodes within the pixel circuit is not affected by the critical voltage of the brightness control transistor.

[0010] According to a first aspect of the present invention, a pixel circuit is provided. The pixel circuit includes: a light-emitting diode, a first inner node setting transistor, a first second inner node setting transistor, and a brightness control transistor. One end of the light-emitting diode is electrically connected to a supply voltage line. The first inner node setting transistor is electrically connected to the other end of the light-emitting diode and the first inner node. The first second inner node setting transistor is electrically connected to the second inner node and a data signal line. The voltage value of the data signal line during data voltage writing is equal to the pixel data voltage value. The brightness control transistor is electrically connected to the first inner node, the second inner node, and a ground voltage line. The voltage value of the supply voltage line is greater than the voltage value of the ground voltage line. During pixel illumination after the data voltage writing period ends, a pixel current flows from the supply voltage line through the light-emitting diode, the first inner node setting transistor, the first inner node, and the brightness control transistor to the ground voltage line. The pixel current value is related to the voltage values ​​of the first and second inner nodes during pixel illumination. The voltage value of the second inner node during pixel illumination is related to the threshold voltage of the brightness control transistor and the pixel data voltage value.

[0011] According to a second aspect of the present invention, another pixel circuit is provided. The pixel circuit includes: a light-emitting diode (LED), a light-emitting transistor (LED), a brightness control transistor, a first inner node setting transistor, and a second inner node setting transistor. One end of the LED is electrically connected to a ground voltage line. The LED is electrically connected to the other end of the LED. The brightness control transistor is electrically connected to the LED, the first inner node, and the second inner node. The first inner node setting transistor is electrically connected to the first inner node and a supply voltage line. The voltage value of the supply voltage line is greater than the voltage value of the ground voltage line. The second inner node setting transistor is electrically connected to the first inner node and a data signal line. The voltage value of the data signal line during data voltage writing is equal to the pixel data voltage value. During pixel illumination after the data voltage writing period ends, a pixel current flows from the supply voltage line through the first inner node setting transistor, the first inner node, the brightness control transistor, the LED, and the LED to the ground voltage line. The pixel current value is related to the voltage values ​​of the first and second inner nodes during pixel illumination. The voltage value of the second inner node during pixel emission is related to the critical voltage of the brightness control transistor and the pixel data voltage value.

[0012] In order to better understand the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:

Implementation Method

[0013] To make it easier for the timing control circuit to control the brightness of the pixel circuit PXL(m, n), this disclosure provides several embodiments of the pixel circuit PXL(m, n) designed in different ways. In the following embodiments, the variables affecting the pixel current ILED(m, n) flowing through the micro-light-emitting diode μLED(m, n) are fewer than the pixel current ILED(m, n) of the conventional pixel circuit PXLo(m, n) in Figure 2, which simplifies the complexity of the timing control circuit in controlling the brightness of the pixel circuit PXL(m, n).

[0014] The timing control circuit uses the data signal DAT[m] to transmit the pixel data voltage value Vdata(m, n) to the pixel circuit PXL(m, n). Depending on the control method, it can be divided into several types: controlling the pixel data voltage value Vdata(m, n) using Pulse Width Modulation (PWM), controlling the pixel data voltage value Vdata(m, n) using Pulse Amplitude Modulation (PAM), and controlling the pixel data voltage value Vdata(m, n) using a combination of PWM and PAM. Below, this disclosure provides two pixel circuits that control the pixel data voltage value Vdata(m, n) using PAM.

[0015] First, this disclosure describes a first-type embodiment of a pixel circuit controlled in a PAM manner. Please refer to Figure 3, which is a pixel circuit PXLa(m, n) conceived according to this disclosure. The pixel circuit PXLa(m, n) is electrically connected to the ground voltage line Vss, the supply voltage line Vdd, the preset voltage line Vini, the pixel data writing gate signal line WS[n], the reset gate signal line RS[n], the light emission enable gate signal line EM[n], and the data signal line DAT[m]. The supply voltage line Vdd provides the supply voltage Vdd (e.g., 10V), and the ground voltage line Vss provides the ground voltage (e.g., 0V).

[0016] When the supply voltage Vdd simultaneously supplies power to M*N pixel circuits, it may be impossible to stably provide the voltage value of the supply voltage Vdd, resulting in such unexpected voltage drops. In the first embodiment, to avoid unexpected voltage drops in the supply voltage Vdd, a preset voltage Vini that can stably provide a voltage value equal to the supply voltage Vdd (e.g., 10V) can be set. The voltages of the pixel data writing gate signal WS[n], the reset gate signal RS[n], and the light emission enable gate signal EM[n] are between the gate control low voltage VGL (e.g., -5V) and the gate control high voltage VGH (e.g., 15V).

[0017] The pixel circuit PXLa(m, n) includes: a capacitor C(m, n), a micro-light-emitting diode μLED(m, n), and inner node setting transistors Tgset1, Tgset2, Tgset3, Tqset1, Tqset2, Tsset2, Tsset1, and a brightness control transistor Tled(m, n). Among them, inner node setting transistors Tgset1, Tgset2, and Tgset3 are used to set the voltage of the inner node NDg(m, n); inner node setting transistors Tqset1 and Tqset2 are used to set the voltage of the inner node NDq(m, n); and inner node setting transistors Tsset1 and Tsset2 are used to set the voltage of the inner node NDs(m, n). The connection relationship of these components is described below.

[0018] The two ends of the capacitor C(m, n) are electrically connected to the inner nodes NDq(m, n) and NDs(m, n), respectively. The anode of the micro-light-emitting diode μLED(m, n) is electrically connected to the supply voltage line Vdd, and the cathode is electrically connected to the source of the inner node set transistor Tsset1.

[0019] The source of the internal node setting transistor Tgset2 is electrically connected to the internal node NDg(m, n), the gate is electrically connected to the gate signal line WS[n] for pixel data writing, and the drain is electrically connected to the data signal line DAT[m]. The source of the internal node setting transistor Tgset1 is electrically connected to the internal node NDg(m, n), the gate is electrically connected to the reset gate signal line RS[n], and the drain is electrically connected to the preset voltage line Vini. The source of the brightness control transistor Tled(m, n) is electrically connected to the internal node NDs(m, n), the gate is electrically connected to the internal node NDg(m, n), and the drain is electrically connected to the ground voltage line Vss. The source of the internal node setting transistor Tqset1 is electrically connected to the ground voltage line Vss, the gate is electrically connected to the gate signal line WS[n] for pixel data writing, and the drain is electrically connected to the internal node NDq(m, n). The source of the internal node setting transistor Tqset2 is connected to the ground voltage line Vss, the gate is connected to the reset gate signal line RS[n], and the drain is connected to the internal node NDq(m, n). The source of the internal node setting transistor Tgset3 is connected to the internal node NDq(m, n), the gate is connected to the light-emitting enable gate signal line EM[n], and the drain is connected to the internal node NDg(m, n). The source of the internal node setting transistor Tsset2 is connected to the preset voltage line Vini, the gate is connected to the reset gate signal line RS[n], and the drain is connected to the internal node NDs(m, n). The source of the internal node setting transistor Tsset1 is connected to the cathode of the micro-light-emitting diode μLED(m, n), the gate is connected to the light-emitting enable gate signal line EM[n], and the drain is connected to the internal node NDs(m, n).

[0020] Please refer to Figure 4, which is a waveform diagram of the timing control circuit controlling the pixel circuit PXLa(m, n) of Figure 3 to emit light. In this diagram, the horizontal axis represents time; the vertical axis from top to bottom represents: the reset gate signal RS[n] received from the timing control circuit, the pixel data writing gate signal WS[n], the data signal line DAT[m], the light emission enable gate signal EM[n]; and the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) located inside the pixel circuit PXLa(m, n). The process of the timing control circuit controlling the pixel circuit PXLa(m, n) to emit light is between time points t1 and t8, where the interval between each time point and the time points before and after it is equal. The following explains in sequence how the reset gate signal RS[n], pixel data writing gate signal WS[n], data signal DAT[m], and light emission enable gate signal EM[n] received by the timing control circuit from the pixel circuit PXLa(m, n) change at time points t1 to t8.

[0021] The gate reset signal RS[n] decreases from the gate control high voltage VGH to the gate control low voltage VGL at time t1, and then rises from the gate control low voltage VGL back to the gate control high voltage VGH at time t2. Furthermore, the gate reset signal RS[n] remains at the gate control high voltage VGH after time t2. This disclosure defines the period from time t1 to t2 when the voltage of the gate reset signal RS[n] is equal to the gate control low voltage VGL as the brightness setting reset period TRS.

[0022] The gate signal WS[n] for writing pixel data is maintained at a high gate control voltage VGH before time point t3; a low gate control voltage VGL during time points t3 to t4; and a high gate control voltage VGH again at time point t4. The gate signal WS[n] for writing pixel data is maintained at a high gate control voltage VGH after time point t4. This disclosure defines the period from time point t3 to t4 when the voltage of the gate signal WS[n] for writing pixel data is equal to the low gate control voltage VGL as the data voltage writing period Tdat_wrt.

[0023] For ease of explanation, it is assumed here that the data signal DAT[m] is ground voltage Vss before time point t3 and after time point t4. The pixel data voltage value Vdata(m, n) during time points t3~t4 depends on the grayscale value (L0~L255) set by the timing control circuit for the pixel circuit PXLa(m, n). For example, when the pixel circuit PXLa(m, n) corresponds to the grayscale value L0, the pixel data voltage value Vdata(m, n) on the data signal DAT[m] is 6V; and when the pixel circuit PXLa(m, n) corresponds to the grayscale value L255, the pixel data voltage value Vdata(m, n) on the data signal DAT[m] is 2V.

[0024] The light-emitting gate signal EM[n] is maintained at a high gate control voltage VGH before time point t5; it is at a low gate control voltage VGL from time point t5 to t8 (during pixel emission); and it is switched back from the low gate control voltage VGL to the high gate control voltage VGH at time point t8. This disclosure defines the period from time point t5 to t8 when the voltage of the light-emitting gate signal EM[n] is equal to the low gate control voltage VGL as the pixel emission period Tem.

[0025] This disclosure defines the period during which the voltage of the reset gate signal RS[n] is equal to the gate control low voltage VGL as the brightness setting reset period TRS; the period during which the pixel data writing gate signal WS[n] is maintained at the gate control low voltage VGL is defined as the data voltage writing period Tdat_wrt; and the period during which the voltage of the light emission enabling gate signal EM[n] is equal to the gate control low voltage VGL is defined as the pixel light emission period Tem.

[0026] To simplify the control timing of the switching signals, when the gate signal RS[n] switches from the low gate control voltage VGL to the high gate control voltage VGH at time t2, the pixel data writing gate signal WS[n] will not immediately switch from the high gate control voltage VGH to the low gate control voltage VGL, but will wait for a transition period Ttr1 before switching. Similarly, when the pixel data writing gate signal WS[n] switches from the low gate control voltage VGL to the high gate control voltage VGH at time t4, the light emission enabling gate signal EM[n] will not immediately switch from the high gate control voltage VGH to the low gate control voltage VGL, but will wait for a transition period Ttr2 before switching.

[0027] In other words, the waveforms of the reset gate signal RS[n], the pixel data writing gate signal WS[n], the data signal DAT[m], and the light emission enable gate signal EM[n] during the transition periods Ttr1 and Ttr2 are determined based on the purpose of control buffering. Therefore, when describing the circuit behavior related to the pixel circuit PXL(m, n) below, we will focus on the brightness setting reset period Trs, the data voltage writing period Tdat_wrt, and the pixel light emission period Tem.

[0028] Furthermore, since the data signal line DAT[m] is simultaneously connected to N pixel circuits PXLa(m, 1) to PXLa(m, N) located in the m-th row, and the timing control circuit enables the pixel circuits PXLa(m, 1) to PXLa(m, N) in turn according to the order of each column n=1 to N, the timing control circuit can use the transition period Ttr2 to pre-set the data signal DAT[m] to the pixel data voltage value Vdata(m, n+1) corresponding to the gray level of PXLa(m, n+1) located in the m-th row and (n+1)-th column before starting to control the pixel circuit PXLa(m, n+1). That is, starting from time point t4, the pixel data voltage value Vdata(m, n+1) corresponding to the gray level of the pixel circuit PXLa(m, n+1) located in the same row but next column as the pixel circuit PXLa(m, n) is prepared in advance. Similarly, the voltage of the data signal line DAT[m] before time t3 may also be the pixel data voltage value Vdata(m, n) corresponding to the grayscale of the pixel circuit PXLa(m, n) that was preset by the timing controller after the data voltage writing period Tdat_wrt corresponding to the pixel circuit PXLa(m, n) in column (n-1) ends. The application variations in this part will not be detailed in this paper.

[0029] Regarding how the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) located inside the pixel circuit PXLa(m, n) change in response to voltage changes in the reset gate signal RS[n], the pixel data writing gate signal WS[n], the data signal DAT[m], and the light emission enable gate signal EM[n], and how these changes occur in Trs during the brightness setting reset period, Tdat_wrt during the data voltage writing period, and Tem during the pixel light emission period, please refer to the explanation in Figures 4 and 5A to 5C. In this document, dashed arrows represent the direction of voltage conduction; crosses represent transistors in the off state.

[0030] Please refer to Figure 5A, which is a state diagram of the pixel circuit PXLa(m, n) in Figure 3 operating during the brightness setting reset period TRS. Please also refer to Figures 3, 4, and 5A. During the brightness setting reset period TRS (time points t1~t2 in Figure 4), the voltage of the reset gate signal RS[n] is the low voltage VGL for gate control (RS[n]=VGL); the voltage of the pixel data writing gate signal WS[n] is the high voltage VGH for gate control (WS[n]=VGH); the data signal DAT[m] is the ground voltage Vss (DAT[m]=Vss); and the voltage of the light emission enable gate signal EM[n] is the high voltage VGH for gate control (EM[n]=VGH). Consequently, the internal node setting transistors Tgset1, Tqset2, and Tsset2 are turned on when the reset gate signal RS[n] = VGL; the internal node setting transistors Tgset2 and Tqset1 are turned off when the gate control voltage VGH (WS[n] = VGH) of the pixel data writing gate signal WS[n] is applied; and the internal node setting transistors Tgset3 and Tsset1 are turned off when the gate control voltage VGH (EM[n] = VGH) of the light emission enabling gate signal EM[n] is applied. Based on the on / off states of the internal node setting transistors Tgset2, Tgset1, Tqset1, Tqset2, Tgset3, Tsset2, and Tsset1, the following describes how the transistors related to the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) affect the voltage values ​​of the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) during the brightness setting reset; and how the voltage values ​​of the internal nodes NDg(m, n) and NDs(m, n) affect the on / off state of the brightness control transistor Tled(m, n).

[0031] During the brightness setting reset period TRS, the inner node setting transistor Tqset2, in the on state, conducts the ground voltage Vss to the inner node NDq(m, n); the inner node setting transistor Tqset1, in the off state, does not affect the voltage value of the inner node NDq(m, n). Therefore, during the brightness setting reset period TRS, the voltage value of the inner node NDq(m, n) is equal to the ground voltage Vss (NDq(m, n) = Vss). Additionally, during the brightness setting reset period TRS, the inner node setting transistors Tgset2 and Tgset3, in the off state, do not affect the voltage value of the inner node NDg(m, n); the inner node setting transistor Tgset1, in the on state, conducts the preset voltage Vini to the inner node NDg(m, n). Therefore, during the brightness setting reset period TRS, the voltage value of the inner node NDg(m, n) is equal to the preset voltage Vini (NDg(m, n) = Vini).

[0032] Furthermore, during the brightness setting reset TRS, the internal node setting transistor Tsset1, which is in the off state, does not affect the voltage value of the internal node NDs(m, n); the internal node setting transistor Tsset2, which is in the on state, conducts the preset voltage Vini to the internal node NDs(m, n). Therefore, during the brightness setting reset TRS, the voltage value of the internal node NDs(m, n) is equal to the preset voltage Vini (NDs(m, n) = Vini).

[0033] The source S of the brightness control transistor Tled(m, n) is electrically connected to the inner node NDs(m, n), and the gate G is electrically connected to the inner node NDg(m, n). As explained above, during the brightness setting reset period TRS, the voltage of the inner node NDs(m, n) is the preset voltage Vini (NDs(m, n) = Vini), and the voltage of the inner node NDg(m, n) is also the preset voltage Vini (NDg(m, n) = Vini). Therefore, the brightness control transistor Tled(m, n) is disconnected because the voltage difference Vgs between the gate G and the source S is 0. At this time, no pixel current ILED(m, n) flows through the micro-light-emitting diode μLED(m, n). Therefore, the micro-light-emitting diode μLED(m, n) will not emit light during the brightness setting reset period TRS.

[0034] Please refer to Figure 5B, which is a state diagram of the pixel circuit PXLa(m, n) in Figure 3 operating during the data voltage writing period Tdat_wrt. Please also refer to Figures 3, 4, and 5B. During the data voltage writing period Tdat_wrt (time points t3~t4 in Figure 4), the voltage of the reset gate signal RS[n] is the gate control high voltage VGH (RS[n]=VGH); the voltage of the pixel data writing gate signal WS[n] is the gate control low voltage VGL (WS[n]=VGL); the data signal DAT[m] is the pixel data voltage value Vdata(m, n) (DAT[m]=Vdata(m, n)); and the voltage of the light emission enable gate signal EM[n] is the gate control high voltage VGH (EM[n]=VGH).

[0035] In conjunction with this, the internal node setting transistors Tgset1, Tqset2, and Tsset2 are turned off by the high voltage VGH (RS[n]=VGH) for gate control of the reset gate signal RS[n]; the internal node setting transistors Tgset2 and Tqset1 are turned on by the low voltage VGL (WS[n]=VGL) for gate control of the pixel data writing gate signal WS[n]; and the internal node setting transistors Tgset3 and Tsset1 are turned off by the high voltage VGH (EM[n]=VGH) for gate control of the light emission enabling gate signal EM[n]. Based on the on / off states of the internal node-defined transistors Tgset2, Tgset1, Tqset1, Tqset2, Tgset3, Tsset2, and Tsset1, the following explains how the transistors associated with the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) affect the voltage values ​​of the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) during data voltage writing; and how the voltage values ​​of the internal nodes NDg(m, n) and NDs(m, n) affect the on / off state of the brightness control transistor Tled(m, n).

[0036] During the data voltage writing period Tdat_wrt, the inner node setting transistor Tqset1 in the on state conducts the ground voltage Vss to the inner node NDq(m, n); the inner node setting transistor Tqset2 in the off state does not affect the voltage value of the inner node NDq(m, n). Therefore, during the data voltage writing period Tdat_wrt, the inner node NDq(m, n) is equal to the ground voltage Vss (NDq(m, n) = Vss). In addition, during the data voltage writing period Tdat_wrt, the inner node setting transistors Tgset1 and Tgset3 in the off state do not affect the voltage value of the inner node NDg(m, n); the inner node setting transistor Tgset2 in the on state conducts the pixel data voltage value Vdata(m, n) on the data signal DAT[m] to the inner node NDg(m, n). Therefore, during the data voltage writing period Tdat_wrt, the internal node NDg(m, n) is equal to the pixel data voltage value Vdata(m, n) on the data signal DAT[m]. That is, NDg(m, n) = DAT[m] = Vdata(m, n).

[0037] Furthermore, during the data voltage writing period Tdat_wrt, the disconnected inner node setting transistors Tsset2 and Tsset1 do not affect the voltage value of the inner node NDs(m, n). Therefore, during the data voltage writing period Tdat_wrt, the inner node NDs(m, n) is equal to the difference between the inner node NDg(m, n) and the critical voltage Vth (e.g., -1.5V) of the brightness control transistor Tled(m, n) with a negative voltage value. That is, NDs(m, n) = NDg(m, n) - Vth = Vdata(m, n) - Vth. In Figure 5B, because the inner node setting transistor Tsset1 is disconnected, even if the brightness control transistor Tled(m, n) can be turned on, no pixel current ILED(m, n) flows through the micro-light-emitting diode μLED(m, n) during this period.

[0038] Please refer to Figure 5C, which is a state diagram of the pixel circuit PXLa(m, n) in Figure 3 operating during the pixel emission period Tem. Please also refer to Figures 3, 4, and 5C. During the pixel emission period Tem (time points t5~t8 in Figure 4), the voltage of the reset gate signal RS[n] is the gate control high voltage VGH (RS[n]=VGH); the voltage of the pixel data writing gate signal WS[n] is the gate control high voltage VGH (WS[n]=VGH); the data signal DAT[m] is the ground voltage Vss (DAT[m]=Vss); and the voltage of the emission enable gate signal EM[n] is the gate control low voltage VGL (EM[n]=VGL). Consequently, the internal node setting transistors Tgset1, Tqset2, and Tsset2 are turned off by the high voltage VGH (RS[n]=VGH) for gate control of the reset gate signal RS[n]; the internal node setting transistors Tgset2 and Tqset1 are turned off by the high voltage VGH (WS[n]=VGH) for gate control of the pixel data writing gate signal WS[n]; and the internal node setting transistors Tgset3 and Tsset1 are turned on by the low voltage VGL (EM[n]=VGL) for gate control of the light emission enable gate signal EM[n]. Based on the on / off states of the internal node-defined transistors Tgset2, Tgset1, Tqset1, Tqset2, Tgset3, Tsset2, and Tsset1, the following explains how the transistors associated with the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) affect the voltage values ​​of the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) during pixel emission; and how the voltage values ​​of the internal nodes NDg(m, n) and NDs(m, n) affect the on / off state of the brightness control transistor Tled(m, n).

[0039] During pixel illumination Tem, the disconnected inner node setting transistors Tqset1 and Tqset2 do not affect the voltage value of the inner node NDq(m, n). At this time, the voltage value of the inner node NDq(m, n) is equal to the voltage value of the inner node NDg(m, n) because the inner node setting transistor Tgset3 is turned on. That is, NDq(m, n) = NDg(m, n) = Vdd - (Vdata(m, n) - Vth). During pixel illumination Tem, the disconnected inner node setting transistors Tgset2 and Tgset1 do not affect the voltage value of the inner node NDg(m, n). Furthermore, during pixel illumination Tem, the disconnected inner node setting transistor Tsset2 does not affect the voltage value of the inner node NDs(m, n), and the supply voltage Vdd is conducted to the inner node NDs(m, n) via the micro-light-emitting diode μLED(m, n) and the turned-on inner node setting transistor Tsset1. That is, NDs(m, n) = Vdd.

[0040] Continuing from the above, the voltage difference Vgs between the gate G and source S of the brightness control transistor Tled(m, n) is equal to the voltage difference between the inner nodes NDg(m, n) and NDs(m, n). That is, Vgs = NDg(m, n) - NDs(m, n) = [Vdd - (Vdata(m, n) - Vth)] - Vdd = -Vdata(m, n) + Vth. At this time, the pixel current ILED(m, n) flowing through the micro-light-emitting diode μLED(m, n) can be expressed as Equation 2. ILED(m, n)=K(Vgs-Vth)2 =K[(NDg(m, n)-NDs(m, n))-Vth]2 =K{[[Vdd-(Vdata(m, n)-Vth)]-Vdd]-Vth}2 =K{[-Vdata(m, n)+Vth]-Vth]2 =KV(-Vdata(m, n))2……………………………………………………(Equation 2)

[0041] As can be seen from Equation 2, the pixel current ILED(m, n) flowing through the micro-LED(m, n) is only related to the pixel data voltage value Vdata(m, n) and is not affected by the supply voltage Vdd and the threshold voltage Vth. Therefore, when controlling the brightness of the pixel circuit PXLa(m, n), the timing control circuit only needs to consider the pixel data voltage value Vdata(m, n). Compared with conventional technology, the timing control circuit controls the brightness of the pixel circuit PXLa(m, n) in a relatively simple way.

[0042] Table 1 summarizes the voltage values ​​of each signal in Figure 4 during the brightness setting reset period (Trs), the data voltage writing period (Tdat_wrt), and the pixel emission period (Tem). Please also refer to Table 1 and Figures 4, 5A to 5C.

[0043] Table 1 Pixel circuit PXLa(m, n) period Signal TRS during brightness setting reset Data voltage write period Tdat_wrt During pixel emission Tem Self-timing control circuit Received signal Reset gate signal RS[n] VGL VGH Gate signal WS[n] is used for writing pixel data. VGH VGL VGH Data signal DAT[m] Vss Vdata(m, n) Vss Light-emitting gate signal EM[n] VGH VGL internal nodes Internal node NDq(m, n) Vss Vdd-(Vdata(m, n)-Vth) Internal node NDg(m, n) Vini Vdata(m, n) Vdd-(Vdata(m, n)-Vth) Internal nodes NDs(m, n) Vini (Vdata(m, n)-Vth) Vdd

[0044] Please refer to Figure 6A, which shows the pixel circuit PXLb1(m, n) according to the present disclosure. Please also refer to Figures 3 and 6A. The connection method of the inner node setting transistors Tgset2, Tgset1, Tqset1, Tqset2, Tgset3 and the brightness control transistor Tled(m, n) of the pixel circuit PXLa(m, n) in Figure 3 is roughly similar to the connection method of the inner node setting transistors Tgset2, Tgset1, Tqset1, Tqset2, Tgset3 and the brightness control transistor Tled(m, n) of the pixel circuit PXLb1(m, n) in Figure 6A. The difference between Figures 3 and 6A is that in the pixel circuit PXLa(m, n) in Figure 3, the source S of the inner node setting transistors Tqset1 and Tqset2, which are used to set the voltage of the inner node NDq(m, n), are both electrically connected to the ground voltage line Vss. However, in the pixel circuit PXLb1(m, n) in Figure 6A, the sources S of the inner node setting transistors Tqset1 and Tqset2, which are used to set the voltage of the inner node NDq(m, n), are both electrically connected to the preset voltage line Vini.

[0045] Please refer to Figure 6B, which is a waveform diagram of the timing control circuit controlling the pixel circuit PXLb1(m, n) in Figure 6A. The waveform sequence in this diagram is the same as in Figure 4, and will not be repeated here. Please also refer to Figures 3, 4, 6A, and 6B.

[0046] According to the concept disclosed herein, the waveforms of the reset gate signal RS[n], pixel data writing gate signal WS[n], data signal line DAT[m], and light-emitting enable gate signal EM[n] transmitted by the timing control circuit to the pixel circuit PXLb1(m, n) in Figure 6A are similar to the waveforms of the reset gate signal RS[n], pixel data writing gate signal WS[n], data signal line DAT[m], and light-emitting enable gate signal EM[n] transmitted to the pixel circuit PXLa(m, n) in Figure 3. Therefore, the waveforms of the reset gate signal RS[n], pixel data writing gate signal WS[n], data signal line DAT[m], and light-emitting enable gate signal EM[n] in Figure 6B are the same as the waveforms of these signals in Figure 4, and will not be repeated here.

[0047] Compared to Figure 3, in Figure 6A, the source S of the inner node setting transistors Tqset1 and Tqset2 is changed to be connected to the preset voltage line Vini. Therefore, in Figure 6B, the voltage of the inner node NDq(m, n) during the brightness setting reset Trs and the data voltage writing Tdat_wrt is the preset voltage Vini (NDq(m, n)=Vini), which is different from the voltage of the inner node NDq(m, n) during the brightness setting reset Trs and the data voltage writing Tdat_wrt in Figure 4, which is the ground voltage Vss (NDq(m, n)=Vss). The voltage of the inner node NDq(m, n) during the pixel emission period Tem in Figure 6A is Vdd-(Vdata(m, n)-Vth), which is the same as the voltage of the inner node NDq(m, n) during the pixel emission period Tem in Figure 4 (NDq(m, n)=Vdd-(Vdata(m, n)-Vth)). Furthermore, the voltages of the inner nodes NDg(m, n) and NDs(m, n) during the brightness setting reset Trs, the data voltage writing Tdat_wrt, and the pixel emission Tem are the same as those of the inner nodes NDg(m, n) and NDs(m, n) in Figure 4 during the same periods.

[0048] As can be seen from the foregoing explanation, since the voltage of the inner node NDq(m, n) during the brightness setting reset Trs and the data voltage writing Tdat_wrt does not affect the voltage difference Vgs between the gate G and source S of the brightness control transistor Tled(m, n), in Figure 6A, replacing the source of the inner node setting transistors Tqset1 and Tqset2 from the ground voltage Vss in Figure 3 to the preset voltage Vini in Figure 6A will not affect the magnitude of the pixel current ILED(m, n) generated by Tem during pixel emission. Therefore, the current formula in Equation 2 can also be applied to the pixel circuit PXLb1(m, n) in Figure 6A.

[0049] Table 2 summarizes the voltage values ​​of the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) in Figure 6B during the brightness setting reset period (Trs), the data voltage writing period (Tdat_wrt), and the pixel emission period (Tem). In Figures 3 and 6A, the waveforms of the reset gate signal RS[n], the pixel data writing gate signal WS[n], the data signal line DAT[m], and the emission enable gate signal EM[n] received from the timing control circuit are the same, and will not be repeated in Table 2. Please refer to Table 2, Figures 6A and 6B at the same time.

[0050] Table 2 Pixel circuit PXLb1(m, n) period Signal TRS during brightness setting reset Data voltage write period Tdat_wrt During pixel emission Tem internal nodes NDq(m, n) Vini Vdd-(Vdata(m, n)-Vth) internal nodes NDg(m, n) Vini Vdata(m, n) Vdd-(Vdata(m, n)-Vth) internal nodes NDs(m, n) Vini (Vdata(m, n)-Vth) Vdd

[0051] Based on the foregoing description, the embodiments of pixel circuits PXLb2(m, n) and PXLb3(m, n) shown in Figures 7 and 8 respectively use two other connection methods to change the source terminals of the internal node setting transistors Tqset1 and Tqset2. Similarly, the waveforms of the reset gate signal RS[n], the pixel data writing gate signal WS[n], the data signal line DAT[m], and the light emission enable gate signal EM[n] received from the timing control circuit are the same as those in Figures 3 and 4, and will not be repeated here. The difference between the embodiments shown in Figures 7 and 8 and the embodiments in Figures 3 and 4 is that the voltage values ​​of the internal node NDq(m, n) during the brightness setting reset period TRS and during the data voltage writing period Tdat_wrt are different. The voltage values ​​of the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) will be presented in tabular form below.

[0052] Please refer to Figure 7, which shows the pixel circuit PXLb2(m, n) according to the present disclosure. In Figure 7, the source of the inner node setting transistor Tqset1 is electrically connected to the ground voltage line Vss, and the source of the inner node setting transistor Tqset2 is electrically connected to the preset voltage line Vini. Table 3 summarizes the voltage values ​​of the inner nodes NDq(m, n), NDg(m, n), and NDs(m, n) of the pixel circuit PXLb2(m, n) in Figure 7 during the brightness setting reset period Trs, the data voltage writing period Tdat_wrt, and the pixel emission period Tem.

[0053] Table 3 Pixel circuit PXLb2(m, n) period Signal TRS during brightness setting reset Data voltage write period Tdat_wrt During pixel emission Tem internal nodes NDq(m, n) Vini Vss Vdd-(Vdata(m, n)-Vth) internal nodes NDg(m, n) Vini Vdata(m, n) Vdd-(Vdata(m, n)-Vth) internal nodes NDs(m, n) Vini (Vdata(m, n)-Vth) Vdd

[0054] Please refer to Figure 8, which shows the pixel circuit PXLb3(m, n) according to the present disclosure. In Figure 8, the source of the inner node setting transistor Tqset1 is electrically connected to the preset voltage line Vini, and the source of the inner node setting transistor Tqset2 is electrically connected to the ground voltage line Vss. Table 4 summarizes the voltage values ​​of the inner nodes NDq(m, n), NDg(m, n), and NDs(m, n) of the pixel circuit PXLb3(m, n) in Figure 8 during the brightness setting reset period Trs, the data voltage writing period Tdat_wrt, and the pixel emission period Tem.

[0055] Table 4 Pixel circuit PXLb3(m, n) period Signal TRS during brightness setting reset Data voltage write period Tdat_wrt During pixel emission Tem internal nodes NDq(m, n) Vss Vini Vdd-(Vdata(m, n)-Vth) internal nodes NDg(m, n) Vini Vdata(m, n) Vdd-(Vdata(m, n)-Vth) internal nodes NDs(m, n) Vini (Vdata(m, n)-Vth) Vdd

[0056] Based on the consideration of reducing the number of transistors in the pixel circuit PXL(m, n), this disclosure provides an embodiment with reduced transistor count, as shown in Figure 9. Please refer to Figure 9, which is a pixel circuit PXLc(m, n) conceived according to this disclosure.

[0057] The components included in the pixel circuit PXLc(m, n) are roughly similar to those in Figures 3, 6A, 7, and 8, and will not be described again here. Compared with Figures 3, 6A, 7, and 8, Figure 9 no longer sets the internal node setting transistor Tqset2, and no longer uses the pixel data writing gate signal WS[n] to control the internal node setting transistor Tqset1. Instead, it uses the control gate signal MCTL[n] to control the control transistor Tmctl. The voltage of the control gate signal MCTL[n] is between the low gate control voltage VGL and the high gate control voltage VGH.

[0058] In the pixel circuit PXLc(m, n), the source of the control transistor Tmctl is electrically connected to the ground voltage line Vss (see Figure 10A) or the preset voltage line Vini (see Figure 10B), the gate of the control transistor Tmctl is electrically connected to the control gate signal line MCTL[n], and the drain of the control transistor Tmctl is electrically connected to the inner node NDq(m, n). Figures 10A and 10B show the waveforms of the signals related to Figure 9 when the source of the control transistor Tmctl in the pixel circuit PXLc(m, n) is electrically connected to the ground voltage line Vss and the preset voltage line Vini, respectively.

[0059] Please refer to Figures 10A and 10B, which are waveform diagrams assuming that the source of the concurrent control transistor Tmctl in the pixel circuit PXLc(m, n) of Figure 9 is electrically connected to the ground voltage line Vss and the preset voltage line Vini, respectively. In Figures 10A and 10B, the horizontal axis represents time; the vertical axis from top to bottom represents: the concurrent control gate signal MCTL[n], the reset gate signal RS[n], the pixel data writing gate signal WS[n], the data signal line DAT[m], the light emission enable gate signal EM[n] received from the timing control circuit; and the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) located inside the pixel circuit PXLc(m, n). Compared with Figure 4, the timing control circuit must additionally transmit the concurrent control gate signal MCTL[n] for the pixel circuit PXLc(m, n) of Figure 9.

[0060] The voltage of the control gate signal line MCTL[n] before time point t1 is a high voltage VGH for gate control; during time points t1 to t4, it is a low voltage VGL for gate control; and at time point t4, it is switched back from the low voltage VGL for gate control to the high voltage VGH for gate control. The period during which the voltage of the control gate signal line MCTL[n] is the low voltage VGL for gate control covers the period during which the voltage of the reset gate signal RS[n] is the low voltage VGL for gate control, the period during which the voltage of the pixel data writing gate signal WS[n] is the low voltage VGL for gate control, and the transition period Ttr1 between the two.

[0061] In other words, the period during which the control gate signal MCTL[n] is the gate control low voltage VGL covers the brightness setting reset period Trs, the transition period Ttr1, and the data voltage write period Tdat_wrt. With this design, the concurrent control transistor Tmctl in the pixel circuit PXLc(m, n) of Figure 9 is turned on because the voltage of the concurrent control gate signal MCTL[n] during the brightness setting reset period Trs is equal to the gate control low voltage VGL (MCTL[n]=VGL), thereby setting the voltage value of the inner node NDq(m, n). This is similar to the behavior of the inner node setting transistor Tqset2 in Figure 4, which is turned on because the voltage of the reset gate signal RS[n] during the brightness setting reset period Trs is equal to the gate control low voltage VGL (RS[n]=VGL), thereby setting the voltage value of the inner node NDq(m, n). Furthermore, the behavior of the concurrent control transistor Tmctl in Figure 9, which sets the voltage value of the inner node NDq(m, n), is similar to that of the inner node setting transistor Tqset1 in Figure 4, which sets the voltage value of the inner node NDq(m, n) because the voltage of the pixel data writing gate signal WS[n] is equal to the low gate control voltage VGL (WS[n]=VGL) during the data writing period.

[0062] Please also refer to Figures 4, 10A, and 10B. Since the waveforms and timing relationships of the reset gate signal RS[n], pixel data writing gate signal WS[n], data signal line DAT[m], and light emission enable gate signal EM[n] transmitted by the timing control circuit to the pixel circuit PXLc(m, n) in Figures 10A and 10B are the same as those in Figure 4, the waveforms of these signals will not be repeated here.

[0063] Table 5 summarizes the voltage values ​​of each signal in Figures 10A and 10B during the brightness setting reset period (Trs), the data voltage writing period (Tdat_wrt), and the pixel emission period (Tem). Please also refer to Table 5, Figures 9, 10A, and 10B.

[0064] Table 5 Pixel circuit PXLc(m, n) period Signal TRS during brightness setting reset Data voltage write period Tdat_wrt During pixel emission Tem Self-timing control circuit Received signal And use the control gate signal line MCTL[n] VGL VGH Reset gate signal RS[n] VGL VGH Gate signal WS[n] is used for writing pixel data. VGH VGL VGH Data signal DAT[m] Vss Vdata(m, n) Vss Light-emitting gate signal EM[n] VGH VGL internal nodes The internal node NDq(m, n) of graph 10A Vss Vdd-(Vdata(m, n)-Vth) The internal node NDq(m, n) of graph 10B Vini Vdd-(Vdata(m, n)-Vth) internal nodes NDg(m, n) Vini Vdata(m, n) Vdd-(Vdata(m, n)-Vth) internal nodes NDs(m, n) Vini (Vdata(m, n)-Vth) Vdd

[0065] According to the concept disclosed herein, the voltage value of the supply voltage Vdd in such embodiments may be greater than the voltage value of the preset voltage Vini (Vdd > Vini), less than the voltage value of the preset voltage Vini (Vdd < Vini), or equal to the voltage value of the preset voltage Vini. Because the voltage value of the supply voltage Vdd in such embodiments can be equal to the voltage value of the preset voltage Vini (Vdd = Vini), in practical applications, the preset voltage (line) Vini in such embodiments can be further replaced by the supply voltage (line) Vdd.

[0066] However, since the supply voltage Vdd is a voltage source shared by M*N pixel circuits PXL(1, 1)~PXL(M, N), the pixel currents ILED(1, 1)~ILED(M, N) flowing from the supply voltage Vdd to the pixel circuits PXL(1, 1)~PXL(M, N) may cause a slight voltage drop in the supply voltage Vdd. Even if the supply voltage Vdd is designed to be equal to the preset voltage Vini (Vdd=Vini) during circuit design, the stability of the supply voltage Vdd is still slightly worse than that of the separately set preset voltage Vini. In other words, in practical applications, the voltage value of the supply voltage Vdd may fluctuate and fail to be stably maintained at a fixed voltage value (e.g., 10V).

[0067] If the preset voltage (line) Vini in the aforementioned embodiment is replaced with the supply voltage (line) Vdd, it must be ensured that even the highest voltage value (max{Vdata(m, n)}) of the pixel data voltage value Vdata(m, n) must be less than the lowest voltage value (min{Vdd}) that the supply voltage Vdd may drop to due to fluctuations. That is, max{Vdata(m, n)} < min{Vdd}. For example, if the supply voltage Vdd may drop from the preset 10V to 8V (min{Vdd}=8V) of Tframe[x] during the xth frame period due to fluctuations, it must be ensured that the maximum value (max{Vdata(m, n)}) of the pixel data voltage value Vdata(m, n) is 6V.

[0068] Next, embodiments of the present disclosure concept for another type of pixel circuit controlled in a PAM manner will be described with reference to Figures 11-15. Please refer to Figure 11, which shows a pixel circuit PXLd1(m, n) according to the present disclosure concept. The pixel circuit PXLd1(m, n) is electrically connected to the ground voltage line Vss, the supply voltage line Vdd, the preset voltage line Vini, the pixel data writing gate signal line WS[n], the reset gate signal line RS[n], the light emission enable gate signal line EM[n], and the data signal line DAT[m]. The supply voltage line Vdd provides a supply voltage Vdd (e.g., 10V), and the ground voltage line Vss provides a ground voltage (e.g., 0V). In this type of embodiment, the preset voltage line Vini provides a preset voltage Vini (e.g., 12V) slightly higher than the supply voltage Vdd.

[0069] The pixel data writing gate signal WS[n], the reset gate signal RS[n], and the light-emitting enable gate signal EM[n] are logic control signals generated by the timing control circuit. The voltages of the pixel data writing gate signal WS[n], the reset gate signal RS[n], and the light-emitting enable gate signal EM[n] are between the gate control low voltage VGL (e.g., -5V) and the gate control high voltage VGH (e.g., 15V).

[0070] The pixel circuit PXLd1(m, n) includes: a capacitor C(m, n), a micro-light-emitting diode μLED(m, n), and inner node setting transistors Tqset1, Tqset2, Tsset1, Tsset2, Tgset1, Tgset2, inner node bridging transistor Tqs, light-emitting diode Tonen, and brightness control transistor Tled(m, n). Among them, inner node setting transistors Tgset1 and Tgset2 are used to set the voltage of inner node NDg(m, n); inner node setting transistors Tqset1 and Tqset2 are used to set the voltage of inner node NDq(m, n); and inner node setting transistors Tsset1 and Tsset2 are used to set the voltage of inner node NDs(m, n). The connection relationship of these components is described below.

[0071] The two ends of capacitor C(m, n) are electrically connected to the inner nodes NDq(m, n) and NDg(m, n), respectively. The anode of the micro-LED(m, n) is electrically connected to the drain of the light-emitting diode Tonen, and the cathode is electrically connected to the ground voltage line Vss. The source of the inner node setting transistor Tqset1 is electrically connected to the preset voltage line Vini, the gate is electrically connected to the pixel data writing gate signal line WS[n], and the drain is electrically connected to the inner node NDq(m, n). The source of the inner node setting transistor Tqset2 is electrically connected to the preset voltage line Vini, the gate is electrically connected to the reset gate signal line RS[n], and the drain is electrically connected to the inner node NDq(m, n). The source of the inner node bridging transistor Tqs is electrically connected to the inner node NDs(m, n), the gate is electrically connected to the light-emitting gate signal line EM[n], and the drain is electrically connected to the inner node NDq(m, n). The source of the internal node setting transistor Tsset1 is connected to the supply voltage line Vdd, the gate is connected to the light-emitting gate signal line EM[n], and the drain is connected to the internal node NDs(m, n). The source of the internal node setting transistor Tsset2 is connected to the data signal line DAT[m], the gate is connected to the pixel data writing gate signal line WS[n], and the drain is connected to the internal node NDs(m, n). The source of the brightness control transistor Tled(m, n) is connected to the internal node NDs(m, n), the gate is connected to the internal node NDg(m, n), and the drain is connected to the drain of the internal node setting transistor Tgset2 and the source of the light-emitting transistor Tonen. The gate of the light-emitting transistor Tonen is connected to the light-emitting gate signal line EM[n], and the drain is connected to the anode of the micro-light-emitting diode μLED(m, n). The source of the internal node setting transistor Tgset2 is electrically connected to the internal node NDg(m, n), and the gate is electrically connected to the gate signal line WS[n] for pixel data writing. The source of the internal node setting transistor Tgset1 is electrically connected to the internal node NDg(m, n), the gate is electrically connected to the reset gate signal line RS[n], and the drain is electrically connected to the ground voltage line Vss.

[0072] In Figure 11, the voltage value of the inner node NDq(m, n) changes with the on / off state of the inner node setting transistors Tqset1, Tqset2, and the inner node bridging transistor Tqs; the voltage value of the inner node NDs(m, n) changes with the on / off state of the inner node setting transistors Tsset1 and Tsset2; and the voltage value of the inner node NDg(m, n) changes with the on / off state of the inner node setting transistors Tgset1 and Tgset2. The voltage value of the inner node NDg(m, n) is used to control the on / off state of the brightness control transistor Tled(m, n).

[0073] Please refer to Figure 12, which is a waveform diagram of the pixel circuit PXLd1(m, n) in conjunction with Figure 11. In this diagram, the horizontal axis represents time; the vertical axis, from top to bottom, represents: the reset gate signal RS[n] received from the timing control circuit, the pixel data writing gate signal WS[n], the data signal line DAT[m], the light emission enable gate signal EM[n]; and the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) located inside the pixel circuit PXLd1(m, n). The process of the timing control circuit controlling the pixel circuit PXLd1(m, n) to emit light occurs between time points t1 and t8, wherein the interval between each time point and the time points before and after it is equal. In this embodiment, the way and timing of the timing control circuit generating the reset gate signal RS[n], the pixel data writing gate signal WS[n], the data signal DAT[m], and the light emission enable gate signal EM[n] are similar to those in Figure 4, and will not be repeated here.

[0074] Please refer to Figure 13A, which is a state diagram of the pixel circuit PXLd1(m, n) in Figure 11 during the brightness setting reset period of TRS. Please also refer to Figures 11, 12, and 13A.

[0075] During the brightness setting reset period TRS (time points t1~t2 in Figure 12), the voltage of the reset gate signal RS[n] is the low voltage VGL for gate control (RS[n]=VGL); the voltage of the pixel data writing gate signal WS[n] is the high voltage VGH for gate control (WS[n]=VGH); the data signal DAT[m] is the ground voltage Vss (DAT[m]=Vss); and the voltage of the light emission enabling gate signal EM[n] is the high voltage VGH for gate control (EM[n]=VGH). Consequently, the internal node setting transistors Tgset1 and Tqset2 are turned on when the reset gate signal RS[n] = VGL; the internal node setting transistors Tgset2, Tqset1, and Tsset2 are turned off when the gate control voltage VGH (WS[n] = VGH) of the pixel data writing gate signal WS[n] is applied; and the internal node bridging transistor Tqs, the internal node setting transistor Tsset1, and the light-emitting enable transistor Tonen are turned off when the gate control voltage VGH (EM[n] = VGH) of the light-emitting enable gate signal EM[n] is applied. Based on the on / off states of the internal node setting transistors Tqset1, Tqset2, Tsset1, Tsset2, Tgset1, Tgset2, internal node bridging transistor Tqs, luminescent transistor Tonen, and brightness control transistor Tled(m, n), the following describes how the transistors related to the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) affect the voltage values ​​of the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) during the brightness setting reset; and how the voltage values ​​of the internal nodes NDg(m, n) and NDs(m, n) affect the on / off state of the brightness control transistor Tled(m, n).

[0076] During the brightness setting reset period TRS, the inner node setting transistor Tqset2, in the on state, conducts the preset voltage Vini to the inner node NDq(m, n); the inner node setting transistor Tqset1, in the off state, does not affect the voltage value of the inner node NDq(m, n). Therefore, during the brightness setting reset period TRS, the inner node NDq(m, n) is equal to the preset voltage Vini (NDq(m, n) = Vini). Additionally, during the brightness setting reset period TRS, the inner node setting transistor Tgset2, in the off state, does not affect the voltage of the inner node NDg(m, n); the inner node setting transistor Tgset1, in the on state, conducts the ground voltage Vss to the inner node NDg(m, n). Therefore, during the brightness setting reset period TRS, the voltage value of the inner node NDg(m, n) is equal to the ground voltage Vss (NDg(m, n) = Vss).

[0077] Furthermore, during the brightness setting reset TRS, the disconnected inner node setting transistors Tsset1, Tsset2, and inner node bridging transistor Tqs do not affect the voltage value of the inner node NDs(m, n). During the brightness setting reset TRS, the voltage value of the inner node NDs(m, n) remains equal to the voltage value of the inner node NDs(m, n) during the pixel emission period Tem in the (x-1)th frame Tframe[x-1] (i.e., equal to the supply voltage Vdd).

[0078] The source S of the brightness control transistor Tled(m, n) is electrically connected to the inner node NDs(m, n), and the gate G is electrically connected to the inner node NDg(m, n). As explained above, during the brightness setting reset period Trs, the voltage of the inner node NDs(m, n) is maintained equal to the voltage of the inner node NDs(m, n) in the (x-1)th frame period Tframe[x-1], which is equal to the supply voltage Vdd (NDs(m, n) = Vdd), and the voltage of the inner node NDg(m, n) is equal to the ground voltage Vss (NDg(m, n) = Vss). Therefore, the brightness control transistor Tled(m, n) can be in the conducting state because the voltage difference Vgs between the gate G and the source S is less than the critical voltage Vth (Vgs = Vss - Vdd < Vth). However, because both the light-emitting transistor Tonen and the internal node setting transistor Tsset1 are disconnected, the pixel current ILED(m, n) cannot flow through the brightness control transistor Tled(m, n) and the micro-LED(m, n). Therefore, the micro-LED(m, n) will not emit light during the brightness setting reset period.

[0079] Please refer to Figure 13B, which is a state diagram of the pixel circuit PXLd1(m, n) in Figure 11 operating during the data voltage write period Tdat_wrt. Please also refer to Figures 11, 12, and 13B.

[0080] During the data voltage writing period Tdat_wrt (time points t3~t4 in Figure 12), the voltage of the reset gate signal RS[n] is the gate control high voltage VGH (RS[n]=VGH); the voltage of the pixel data writing gate signal WS[n] is the gate control low voltage VGL (WS[n]=VGL); the data signal DAT[m] is the pixel data voltage value Vdata(m, n) (DAT[m]=Vdata(m, n)); and the voltage of the light emission enabling gate signal EM[n] is the gate control high voltage VGH (EM[n]=VGH).

[0081] In conjunction with this, the inner node setting transistors Tgset1 and Tqset2 are turned off by the high voltage VGH (RS[n]=VGH) for gate control of the reset gate signal RS[n]; the inner node setting transistors Tgset2, Tqset1, and Tsset2 are turned on by the low voltage VGL (WS[n]=VGL) for gate control of the pixel data writing gate signal WS[n]; and the inner node bridging transistor Tqs, the inner node setting transistor Tsset1, and the light-emitting enable transistor Tonen are turned off by the high voltage VGH (EM[n]=VGH) for gate control of the light-emitting enable gate signal EM[n]. Based on the on / off states of the internal node setting transistors Tqset1, Tqset2, Tsset1, Tsset2, Tgset1, Tgset2, internal node bridging transistor Tqs, light-emitting transistor Tonen, and brightness control transistor Tled(m, n), the following describes how the transistors related to the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) affect the voltage values ​​of the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) during data voltage writing; and how the voltage values ​​of the internal nodes NDg(m, n) and NDs(m, n) affect the on / off state of the brightness control transistor Tled(m, n).

[0082] During the data voltage write operation Tdat_wrt, the internal node setting transistor Tqset1, in the on state, conducts the preset voltage Vini to the internal node NDq(m, n); the internal node setting transistor Tqset2, in the off state, does not affect the voltage value of the internal node NDq(m, n). Therefore, during the data voltage write operation Tdat_wrt, the voltage value of the internal node NDq(m, n) is equal to the preset voltage Vini (NDq(m, n) = Vini). Additionally, during the data voltage write operation Tdat_wrt, the internal node setting transistor Tgset1 is off, and it does not affect the voltage value of the internal node NDg(m, n). Simultaneously, the internal node setting transistor Tgset2, in the on state, conducts the voltage value of the internal node NDg(m, n) at the source S to the drain D. Furthermore, the inner node setting transistor Tsset2 in the on state transmits the pixel data voltage value Vdata(m, n) of the data signal DAT[m] of the source S to the inner node NDs(m, n) of the drain D.

[0083] The source S of the brightness control transistor Tled(m, n) is electrically connected to the inner node NDs(m, n), the gate G is electrically connected to the inner node NDg(m, n), and the drain D is electrically connected to the drain D of the inner node setting transistor Tgset2. Because the source S of the brightness control transistor Tled(m, n) is electrically connected to the inner node NDs(m, n), the voltage of the source S of the brightness control transistor Tled(m, n) is equal to the pixel data voltage value Vdata(m, n). NDs(m, n) = Vdata(m, n).

[0084] During the data voltage write period Tdat_wrt, the brightness control transistor Tled(m, n) will operate in the saturation region. The voltage difference Vgs between the gate G and source S of the brightness control transistor Tled(m, n) in the saturation state is equal to the critical voltage Vth of the brightness control transistor Tled(m, n) (e.g., -1.5V). Based on the aforementioned relationship that the gate S voltage of the brightness control transistor Tled(m, n) is equal to the pixel data voltage value Vdata(m, n), and the voltage difference Vgs between the gate G and source S is equal to the critical voltage Vth, the voltage value of the inner node NDg(m, n) during the data voltage write period Tdat_wrt can be further calculated.

[0085] During the data voltage writing period Tdat_wrt, the voltage of the inner node NDg(m, n) is equal to the sum of the pixel data voltage value Vdata(m, n) and the critical voltage Vth of the brightness control transistor Tled(m, n) (Vdata(m, n) + Vth). That is, NDg(m, n) = (Vdata(m, n) + Vth). Because the critical voltage Vth of the brightness control transistor Tled(m, n) is a negative voltage value, during the data voltage writing period Tdat_wrt, the voltage value of the inner node NDg(m, n) will be lower than the voltage value of the inner node NDs(m, n). NDg(m, n) = (Vdata(m, n) + Vth) < NDs(m, n) = Vdata(m, n).

[0086] Because both the light-emitting enable transistor Tonen and the internal node setting transistor Tsset1 are turned off when the light-emitting enable gate signal EM[n] is connected to the gate control high voltage VGH (EM[n]=VGH), there is currently no pixel current ILED(m, n) flowing through the micro-light-emitting diode μLED(m, n). Therefore, the micro-light-emitting diode μLED(m, n) will not emit light during the data voltage writing period Tdat_wrt.

[0087] The two ends of capacitor C(m, n) are electrically connected to the inner nodes NDq(m, n) and NDg(m, n), respectively. Therefore, the capacitive voltage difference ΔVc(m, n) across capacitor C(m, n) can be expressed as the voltage difference between the inner nodes NDq(m, n) and NDg(m, n). In Figure 13B, the capacitive voltage difference ΔVc(m, n) can be expressed as Equation 3. ΔVc(m, n) = NDq(m, n) - NDg(m, n) = Vini - (Vdata(m, n) + Vth) = Vini - Vdata(m, n) - Vth...............................................................................(Equation 3)

[0088] Please refer to Figure 13C, which is a state diagram of the pixel circuit PXLd1(m, n) in Figure 11 during the pixel emission period Tem. Please also refer to Figures 11, 12, and 13C.

[0089] During the pixel emission period Tem (time points t5~t8 in Figure 12), the voltage of the reset gate signal RS[n] is the gate control high voltage VGH (RS[n]=VGH); the voltage of the pixel data writing gate signal WS[n] is the gate control high voltage VGH (WS[n]=VGH); the data signal DAT[m] is the ground voltage Vss (DAT[m]=Vss); and the voltage of the emission enable gate signal EM[n] is the gate control low voltage VGL (EM[n]=VGL). Consequently, the internal node setting transistors Tgset1 and Tqset2 are disconnected by the high gate control voltage VGH (RS[n]=VGH) of the reset gate signal RS[n]; the internal node setting transistors Tgset2, Tqset1, and Tsset2 are disconnected by the high gate control voltage VGH (WS[n]=VGH) of the pixel data writing gate signal WS[n]; and the internal node bridging transistor Tqs, the internal node setting transistor Tsset1, and the light-emitting enable transistor Tonen are turned on by the low gate control voltage VGL (EM[n]=VGL) of the light-emitting enable gate signal EM[n]. Based on the on / off states of the internal node setting transistors Tqset1, Tqset2, Tsset1, Tsset2, Tgset1, Tgset2, internal node bridging transistor Tqs, light-emitting transistor Tonen, and brightness control transistor Tled(m, n), the following explains in sequence how the internal node setting transistors related to internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) affect the voltage values ​​of internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) during pixel emission; and how the voltage values ​​of internal nodes NDg(m, n) and NDs(m, n) affect the on / off state of the brightness control transistor Tled(m, n).

[0090] During the pixel emission period Tem, the disconnected inner node setting transistors Tqset1 and Tqset2 do not affect the voltage value of the inner node NDq(m, n). At this time, the voltage value of the inner node NDq(m, n) is equal to the voltage value of the inner node NDs(m, n) because the inner node bridging transistor Tqs is turned on. That is, NDq(m, n) = NDs(m, n).

[0091] During pixel emission period Tem, the disconnected inner node setting transistor Tsset2 does not affect the voltage value of the inner node NDs(m, n). At this time, the voltage value of the inner node NDs(m, n) is equal to the supply voltage Vdd as the connected inner node setting transistor Tsset1 is connected. That is, NDs(m, n) = Vdd. The voltage value of the inner node NDs(m, n) during the pixel emission period Tem in the x-th frame period Tframe[x] (NDs(m, n) = Vdd) will continue into the brightness setting reset period Trs and transition period Ttr1 in the (x+1)-th frame period Tframe[x+1].

[0092] During the pixel emission period Tem, the disconnected inner node setting transistors Tgset1 and Tgset2 do not affect the voltage value of the inner node NDg(m, n). At this time, the voltage value of the inner node NDg(m, n) is equivalent to the voltage value of the inner node NDq(m, n) minus the voltage difference ΔVc(m, n) across capacitor C(m, n). The voltage value of the inner node NDq(m, n) is equal to the voltage value of the inner node NDs(m, n), and the voltage value of the inner node NDs(m, n) is equal to the supply voltage Vdd. NDq(m, n) = NDs(m, n) = Vdd. Therefore, the voltage calculation method of the inner node NDg(m, n) can be expressed as Equation 4. NDg(m, n)=NDq(m, n)-ΔVc(m, n) =Vdd-{Vini-Vdata(m, n)-Vth} =Vdd-Vini+Vdata(m, n)+Vth......................................................................(Equation 4)

[0093] Continuing from the above, the voltage difference Vgs between the gate G and source S of the brightness control transistor Tled(m, n) is equal to the voltage difference between the internal nodes NDg(m, n) and NDs(m, n) (Vgs = NDg(m, n) - NDs(m, n)). According to Equation 4, the voltage difference Vgs between the gate G and source S of the brightness control transistor Tled(m, n) is shown in Equation 5. Vgs = NDg(m, n) - NDs(m, n) = {Vdd - Vini + Vdata(m, n) + Vth} - Vdd = -Vini + Vdata(m, n) + Vth................................................................................(Equation 5)

[0094] Based on the voltage difference Vgs=-Vini+Vdata(m, n)+Vth between the gate G and source S of the brightness control transistor Tled(m, n) in Equation 5, when calculating the pixel current ILED(m, n) flowing through the micro-LED(m, n), the magnitude of the pixel current ILED(m, n) can be expressed by the transistor current formula as Equation 6. ILED(m, n)=K(Vgs-Vth)2 =K[(-Vini+Vdata(m, n)+Vth)-Vth]2 =K{-Vini+Vdata(m, n)}2…………………………………………….………………(Equation 6)

[0095] As can be seen from Equation 6, the magnitude of the pixel current ILED(m, n) flowing through the micro-light-emitting diode μLED(m, n) is only related to the preset voltage Vini and the pixel data voltage value Vdata(m, n), and is not affected by the critical voltage Vth. Compared with the conventional pixel circuit PXLo(m, n), the timing control circuit needs to consider fewer variables when controlling the brightness of the pixel circuit PXLd1(m, n).

[0096] Regarding the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) located inside the pixel circuit PXLd1(m, n), how do they change in response to voltage changes in the reset gate signal RS[n], the pixel data writing gate signal WS[n], the data signal DAT[m], and the light emission enable gate signal EM[n], and how do they change during the brightness setting reset Trs, the data voltage writing Tdat_wrt, and the pixel light emission Tem? Please refer to the explanation in Figures 12, 13A to 13C.

[0097] Table 6 summarizes the voltage values ​​of each signal in Figure 11 during the brightness setting reset period (Trs), the data voltage writing period (Tdat_wrt), and the pixel emission period (Tem). Please also refer to Table 6 and Figures 11, 12, and 13A~13C.

[0098] Table 6 Pixel circuit PXLd1(m, n) period Signal TRS during brightness setting reset Data voltage write period Tdat_wrt During pixel emission Tem Self-timing control circuit Received signal Reset gate signal RS[n] VGL VGH Gate signal WS[n] is used for writing pixel data. VGH VGL VGH Data signal DAT[m] Vss Vdata(m, n) Vss Light-emitting gate signal EM[n] VGH VGL internal nodes Internal node NDq(m, n) Vini Vdd Internal node NDg(m, n) Vss Vdata(m, n)-Vth Vdd-Vini+Vdata(m, n)- Vth Internal nodes NDs(m, n) Vdd Vdata(m, n) Vdd

[0099] Please refer to Figure 14, which is the pixel circuit PXLd2(m, n) according to the present disclosure. Since the components included in the pixel circuit PXLd2(m, n) are roughly similar to those in the pixel circuit PXLd1(m, n) of Figure 11, they will not be described again here. Compared with Figure 11, Figure 14 replaces the inner node setting transistors Tqset1 and Tqset2 with a control transistor Tmctl. The source of the control transistor Tmctl is connected to the preset voltage line Vini, the gate is connected to the control gate signal line MCTL[n], and the drain is connected to the inner node NDq(m, n). The control gate signal MCTL[n] is between the low voltage VGL for gate control and the high voltage VGH for gate control.

[0100] Please refer to Figure 15, which is a waveform diagram of the pixel circuit PXLd2(m, n) in conjunction with Figure 14. In Figure 15, the horizontal axis represents time; the vertical axis from top to bottom represents: the concurrent control gate signal MCTL[n] received from the timing control circuit, the reset gate signal RS[n], the pixel data writing gate signal WS[n], the data signal line DAT[m], the light emission enable gate signal EM[n]; and the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) located inside the pixel circuit PXLd2(m, n). Compared with Figure 11, the timing control circuit needs to transmit an additional concurrent control gate signal MCTL[n] for the pixel circuit PXLd2(m, n) in Figure 14, but it can reduce the use of one transistor.

[0101] The gate control signal MCTL[n] is used as a high voltage VGH for gate control before time t1 (MCTL[n]=VGH); as a low voltage VGL for gate control during time t1~t4 (MCTL[n]=VGL); and then, at time t4, it is switched from the low voltage VGL for gate control to the high voltage VGH for gate control again (MCTL[n]=VGH). The period during which the voltage of the gate control signal MCTL[n] is the low voltage VGL for gate control (MCTL[n]=VGL) (time t1~t4) covers the period during which the voltage of the reset gate signal RS[n] is the low voltage VGL for gate control (RS[n]=VGL) and the period during which the voltage of the pixel data writing gate signal WS[n] is the low voltage VGL for gate control (WS[n]=VGL), as well as the transition period Ttr1 between the two.

[0102] In other words, the period during which the voltage of the control gate signal MCTL[n] is the gate control low voltage VGL (MCTL[n]=VGL) covers the brightness setting reset period TRS, the transition period Ttr1, and the data voltage write period Tdat_wrt. With this design, the control transistor Tmctl in Figure 14 will be turned on because the voltage of the control gate signal MCTL[n] during the brightness setting reset period TRS is the gate control low voltage VGL (MCTL[n]=VGL), thereby setting the voltage value of the internal node NDq(m, n). This is similar to the behavior of the internal node setting transistor Tqset2 in Figure 11 being turned on because the voltage of the reset gate signal RS[n] during the brightness setting reset period TRS is the gate control low voltage VGL (RS[n]=VGL), thereby setting the voltage value of the internal node NDq(m, n). Furthermore, the behavior of the concurrent control transistor Tmctl in Figure 14, which sets the voltage value of the inner node NDq(m, n) because the concurrent control gate signal MCTL[n] is turned on during the data voltage writing period when the voltage of Tdat_wrt is the gate control low voltage VGL (MCTL[n]=VGL), is similar to the behavior of the inner node setting transistor Tqset1 in Figure 11, which sets the voltage value of the inner node NDq(m, n) because the pixel data writing gate signal WS[n] is turned on during the data voltage writing period when the voltage of Tdat_wrt is the gate control low voltage VGL (WS[n]=VGL). Therefore, by adding an additional concurrent control transistor Tmctl, Figure 14 can replace the two inner node setting transistors Tqset1 and Tqset2 in Figure 11.

[0103] Please also refer to Figures 14 and 15. Since the reset gate signal RS[n], pixel data writing gate signal WS[n], data signal line DAT[m], light emission enable gate signal EM[n], and the waveforms and timing relationships of the internal nodes NDq(m, n), NDg(m, n), and NDs(m, n) transmitted by the timing control circuit to the pixel circuit PXLd2(m, n) in Figure 15 are the same as those in Figure 12, they will not be repeated here.

[0104] As described above, Figures 3-10 of this disclosure provide an embodiment of pixel circuits PXLa(m, n), PXLb1(m, n), PXLb2(m, n), PXLb3(m, n), and PXLc(m, n) that control the pixel data voltage value Vdata(m, n) using PAM. This allows the timing control circuit to eliminate variables related to the critical voltage Vth and preset voltage Vini of the brightness control transistor Tled(m, n) when controlling the pixel current ILED(m, n), thus simplifying the design. On the other hand, Figures 11-15 of this disclosure provide another embodiment of pixel circuits PXLd1(m, n) and PXLd2(m, n) that control the pixel data voltage value Vdata(m, n) using PAM, which similarly simplifies the way the timing control circuit controls the pixel circuit.

[0105] The aperture ratio of a display panel represents the ratio between the light transmission area in the non-pixel wiring area and the pixel area of ​​the display panel. The higher the aperture ratio of the display panel, the higher the light transmission efficiency and the better the transparency of the display panel.

[0106] In the foregoing embodiments, most pixel circuits PXL(m, n) only require three voltage sources with fixed voltage values ​​(supply voltage Vdd, ground voltage Vss, and preset voltage Vini). In the first type of embodiment, the preset voltage Vini can be further replaced by the supply voltage Vdd. For the display panel, the fewer voltage sources that need to maintain a fixed voltage value, the higher the aperture ratio of the display panel. Furthermore, in some embodiments, the number of transistors in the pixel circuit can be further reduced and the aperture ratio increased by using the control transistor Tmctl.

[0107] In summary, although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0108] Figure 1 is a schematic diagram of a μLED display panel; Figure 2 is a schematic diagram of a conventional μLED pixel circuit; Figure 3 is an embodiment of the pixel circuit PXLa(m, n) according to the present disclosure; Figure 4 is a waveform diagram of the pixel circuit PXLa(m, n) in conjunction with Figure 3; Figure 5A is a state diagram of the pixel circuit PXLa(m, n) in Figure 3 operating during the brightness setting reset period TRS; Figure 5B is a state diagram of the pixel circuit PXLa(m, n) in Figure 3 operating during the data voltage writing period Tdat_wrt; Figure 5C is a state diagram of the pixel circuit PXLa(m, n) in Figure 3 operating during the pixel emission period Tem; Figure 6A is an embodiment of the pixel circuit PXLb1(m, n) according to the present disclosure; Figure 6B is a waveform diagram of the timing control circuit controlling the pixel circuit PXLb1(m, n) in Figure 6A. Figure 7 shows an embodiment of the pixel circuit PXLb2(m, n) according to the present disclosure; Figure 8 shows an embodiment of the pixel circuit PXLb3(m, n) according to the present disclosure; Figure 9 shows an embodiment of the pixel circuit PXLc(m, n) according to the present disclosure; Figures 10A and 10B show waveforms assuming that the source of the control transistor Tmctl in the pixel circuit PXLc(m, n) of Figure 9 is electrically connected to the ground voltage line Vss and the preset voltage line Vini, respectively; Figure 11 shows an embodiment of the pixel circuit PXLd1(m, n) according to the present disclosure; Figure 12 shows a waveform diagram of the pixel circuit PXLd1(m, n) in conjunction with Figure 11; Figure 13A shows the state diagram of the pixel circuit PXLd1(m, n) of Figure 11 operating during the brightness setting reset period TRS. Figure 13B is a state diagram of the pixel circuit PXLd1(m, n) of Figure 11 operating during the data voltage writing period Tdat_wrt; Figure 13C is a state diagram of the pixel circuit PXLd1(m, n) of Figure 11 operating during the pixel emission period Tem; Figure 14 is an embodiment of the pixel circuit PXLd2(m, n) according to the present disclosure; and Figure 15 is a waveform diagram of the pixel circuit PXLd2(m, n) in conjunction with Figure 14.

Claims

1. A pixel circuit, comprising: a light-emitting diode, one end of which is electrically connected to a supply voltage line; a first inner node setting transistor, electrically connected to the other end of the light-emitting diode and a first inner node; a first second inner node setting transistor, electrically connected to a second inner node and a data signal line, wherein the voltage value of the data signal line during a data voltage write is equal to a pixel data voltage value; and a brightness control transistor, electrically connected to the first inner node, the second inner node, and a ground voltage line, wherein the voltage value of the supply voltage line is greater than the voltage value of the ground voltage line, wherein... During a pixel emission period after the data voltage writing period ends, a pixel current flows from the supply voltage line through the light-emitting diode, the first inner node setting transistor, the first inner node and the brightness control transistor to the ground voltage line. The current value of the pixel current changes with the voltage values ​​of the first inner node and the second inner node during the pixel emission period, and the voltage value of the second inner node during the pixel emission period changes with a threshold voltage of the brightness control transistor and the pixel data voltage value.

2. The pixel circuit as described in claim 1, wherein, The first inner node is configured with a transistor electrically connected to a light-emitting enable gate signal line, which is turned on by the voltage of the light-emitting enable gate signal line during the pixel's light emission period. The first inner node is configured with a transistor electrically connected to a pixel data writing gate signal line, which is turned on by the voltage of the pixel data writing gate signal line during the data voltage writing period.

3. The pixel circuit as claimed in claim 2, further comprising: a second first inner node setting transistor electrically connected to a reset gate signal line, which is turned on due to the voltage of the reset gate signal line during a brightness setting reset period prior to the start of the data voltage writing period; a second second inner node setting transistor electrically connected to the second inner node and the reset gate signal line, which is turned on due to the voltage of the reset gate signal line during the brightness setting reset period; and a third second inner node setting transistor electrically connected to the second inner node, the third inner node and the light emission enable gate signal line, which is turned on due to the voltage of the light emission enable gate signal line during the pixel light emission period.

4. The pixel circuit as claimed in claim 3, wherein the second first inner node setting transistor and the second second inner node setting transistor system are electrically connected to one of the supply voltage line and a preset voltage line.

5. The pixel circuit as claimed in claim 3, further comprising: a capacitor electrically connected to the first inner node and the third inner node; a first and third inner node setting transistor electrically connected to the pixel data writing gate signal line and the third inner node, which is turned on due to the voltage of the pixel data writing gate signal line during the data voltage writing period; and a second and third inner node setting transistor electrically connected to the reset gate signal line and the third inner node, which is turned on due to the voltage of the reset gate signal line during the brightness setting reset period.

6. The pixel circuit as claimed in claim 5, wherein the first and third inner nodes are configured with transistors electrically connected to one of the ground voltage line, the supply voltage line and a preset voltage line, and the second and third inner nodes are configured with transistors electrically connected to one of the ground voltage line, the supply voltage line and the preset voltage line.

7. The pixel circuit as claimed in claim 3, further comprising: a capacitor electrically connected to the first inner node and a third inner node; and a concurrent control transistor electrically connected to the third inner node and a concurrent control gate signal line, which is turned on by the voltage of the concurrent control gate signal line during the brightness setting reset period and the data voltage writing period.

8. The pixel circuit as claimed in claim 7, wherein the control transistor is electrically connected to one of the ground voltage line, the supply voltage line and a preset voltage line.

9. The pixel circuit as claimed in claim 3, wherein the voltage of the reset gate signal line during the brightness setting reset period is equal to a gate control low voltage, and the voltage of the reset gate signal line during the data voltage writing period and the pixel emission period is equal to a gate control high voltage; the voltage of the pixel data writing gate signal line during the data voltage writing period is equal to the gate control low voltage, and the voltage of the pixel data writing gate signal line during the brightness setting reset period and the pixel emission period is equal to the gate control high voltage; and the voltage of the light emission enable gate signal line during the pixel emission period is equal to the gate control low voltage, and the voltage of the light emission enable gate signal line during the brightness setting reset period and the data voltage writing period is equal to the gate control high voltage.