Array substrate, display panel and manufacturing method of array substrate

Abstract

The application discloses an array substrate, which comprises a scan driving circuit, 2n clock lines arranged in sequence and pixel units arranged in an array. The scan driving circuit is used for receiving a clock signal from the clock lines and outputting a scan signal to the pixel units according to the clock signal, so that the pixel units receive a data signal for image display and perform image display. The array substrate further comprises n connection lines, the ith clock line is connected with the n+i clock line through the ith connection line, and the n connection lines are arranged in a preset area which is located at an edge position adjacent to the scan driving circuit and a display area in the array substrate. By reserving or cutting off the preset area, the array substrate can match different numbers of clock signals. The application further discloses a display panel comprising the array substrate and a manufacturing method of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to array substrates, display panels, and methods for manufacturing array substrates. Background Technology

[0002] With the development of LCD technology, narrow bezel displays have become a major trend in high-quality display development due to their advantages such as simplicity, aesthetics, and large viewable area for the same size. GOA technology utilizes the array process of LCD panels to fabricate the gate driving circuit on the array substrate. This technology not only reduces the material and manufacturing costs of display devices but also minimizes the bezel design, better aligning with the development trend of display panels.

[0003] However, since GOA technology is a combination design of Thin Film Transistor (TFT) devices, it is fabricated along with the array substrate process. If the product needs to change the number of clock signals (CLK) in the GOA circuit for some reason, the entire array substrate mask needs to be modified to achieve this, resulting in significant costs. Therefore, how to match different numbers of clock signals while reducing costs is an urgent problem to be solved. Summary of the Invention

[0004] In view of the shortcomings of the above-mentioned technical problems, this application provides an array substrate, a display panel, and a method for manufacturing the array substrate that can match different numbers of clock signals.

[0005] This application discloses an array substrate, including a scan driving circuit, 2n clock lines arranged sequentially, and pixel units arranged in an array, where n is an integer greater than or equal to 1. The scan driving circuit receives clock signals from the clock lines and outputs scan signals to the pixel units according to the clock signals to control the pixel units to receive data signals for image display and perform image display. The array substrate also includes n connecting lines, where the i-th clock line is connected to the (n+i)-th clock line through the i-th connecting line, where i is a positive integer greater than or equal to 1 and less than n. The n connecting lines are disposed in a preset area, which is located at the edge of the array substrate adjacent to the scan driving circuit and the display area.

[0006] Optionally, the display area includes multiple scan lines extending along a first direction, multiple data lines extending along a second direction, and multiple pixel units. The first direction is different from the second direction. A data driving circuit located in the non-display area is used to output data signals to the pixel units through multiple data lines to control the pixel units to display images. The preset area is located between the data driving circuit and the display area.

[0007] Optionally, the array substrate also includes n switching transistors, wherein the i-th switching transistor is connected to the i-th clock line and the (n+i)-th clock line through the i-th connection line, and when the i-th switching transistor is turned on, the i-th clock line and the (n+i)-th clock line transmit the same clock signal.

[0008] Optionally, the array substrate also includes a control unit, wherein the gate of the i-th switch is connected to the control unit, the source of the i-th switch is connected to the i-th clock line, and the drain of the i-th switch is connected to the n+i-th clock line. The control unit is used to output a control signal to the i-th switch to control the i-th switch to be turned on and off.

[0009] Optionally, when the control unit outputs a control signal of the first potential to the i-th switch, the i-th switch is turned on, and the i-th clock line is connected to the (n+i)-th clock line to transmit the i-th clock signal. When the control unit outputs a control signal of the second potential to the i-th switch, the i-th switch is turned off, and the i-th clock line is used to transmit the i-th clock signal, and the (n+i)-th clock line is used to transmit the (n+i)-th clock signal.

[0010] Optionally, when n=4, the array substrate includes eight clock lines and four switching transistors. The first clock line is connected to the fifth clock line through the first switching transistor, the second clock line is connected to the sixth clock line through the second switching transistor, the third clock line is connected to the seventh clock line, and the fourth clock line is connected to the eighth clock line through the fourth switching transistor. When the first to fourth switching transistors are turned on, the first to eighth clock lines are used to transmit four different clock signals. When the first to fourth switching transistors are turned off, the first to eighth clock lines are used to transmit eight different clock signals respectively.

[0011] Optionally, the gate of the first switch is connected to the control unit, the source of the first switch is connected to the first clock line, and the drain of the first switch is connected to the fifth clock line; the gate of the second switch is connected to the control unit, the source of the second switch is connected to the second clock line, and the drain of the second switch is connected to the sixth clock line; the gate of the third switch is connected to the control unit, the source of the third switch is connected to the third clock line, and the drain of the third switch is connected to the seventh clock line; the gate of the fourth switch is connected to the control unit, the source of the third switch is connected to the fourth clock line, and the drain of the fourth switch is connected to the eighth clock line; the control unit is used to output control signals to the gates of the first to fourth switches to control the first to fourth switches to be turned on or off.

[0012] Optionally, when the control unit outputs a control signal at the first potential, the first to fourth switching transistors are turned on, the first clock line is connected to the fifth clock line to transmit the first clock signal, the second clock line is connected to the sixth clock line to transmit the second clock signal, the third clock line is connected to the seventh clock line to transmit the third clock signal, and the fourth clock line is connected to the eighth clock line to transmit the fourth clock signal.

[0013] Optionally, when the control unit outputs the control signal of the second potential, the first to fourth switches are turned off, the first clock line is used to transmit the first clock signal, the second clock line is used to transmit the second clock signal, the third clock line is used to transmit the third clock signal, the fourth clock line is used to transmit the fourth clock signal, the fifth clock line is used to transmit the fifth clock signal, the sixth clock line is used to transmit the sixth clock signal, the seventh clock line is used to transmit the seventh clock signal, and the eighth clock line is used to transmit the eighth clock signal.

[0014] This application also discloses a display panel, including a timing control circuit, a data driving circuit, and the aforementioned array substrate. The timing control circuit is used to output clock signals to the scan driving circuit via multiple clock lines. The scan driving circuit is used to output scan signals according to the clock signals. The data driving circuit is used to output data signals. Pixel units are used to receive data signals and display images under the control of the scan signals.

[0015] This application also discloses a method for manufacturing an array substrate, wherein n connecting lines are set in a preset area of ​​the array substrate;

[0016] In the 2n clock lines and n connecting lines, the i-th clock line is connected to the (n+i)-th clock line through the i-th connecting line, where 1≤i≤n, and i and n are positive integers. The clock lines are used to transmit clock signals to the scan driving circuit in the array substrate, so as to control the scan driving circuit to output scan signals to the pixel units in the display area according to the clock signals. The scan signals control the pixel units to receive data signals for image display and perform image display. A preset area is set at the edge position of the array substrate adjacent to the scan driving circuit and the display area.

[0017] When the preset region is cut off, the i-th clock line and the (n+i)-th clock line transmit different clock signals; or when the preset region is retained, the i-th clock line and the (n+i)-th clock line transmit the same or different clock signals.

[0018] Optionally, the array substrate also includes n switching transistors, controlling the i-th switching transistor to connect the i-th clock line and the n+i-th clock line through the i-th connection line. When the i-th switching transistor is turned on, the i-th clock line and the n+i-th clock line transmit the same clock signal. When the i-th switching transistor is turned off, the i-th clock line is used to transmit different clock signals.

[0019] Compared to existing technologies, this method connects multiple clock lines in pairs via connecting lines and places these connecting lines in a preset area on the array substrate. This allows the preset area to be cut during the array substrate fabrication process. By retaining or removing the preset area, the array substrate can be matched with different numbers of clock signals. Furthermore, the connection of the clock lines can be controlled by a switching transistor, enabling the array substrate to match different numbers of clock signals. This avoids re-etching the array substrate, thus saving a significant amount of photomasks and reducing production costs. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a display device provided in the first embodiment of this application;

[0022] Figure 2 for Figure 1 A schematic diagram of the side structure of the display terminal;

[0023] Figure 3 for Figure 2 A schematic diagram of the planar layout of the array substrate in the display panel shown.

[0024] Figure 4 for Figure 3 A schematic diagram of the layout of the array substrate;

[0025] Figure 5 for Figure 4 Equivalent circuit diagram of the clock line;

[0026] Figure 6 A schematic diagram of a clock line connection provided in the second embodiment of this application;

[0027] Figure 7 for Figure 6 Equivalent circuit diagram of the clock line;

[0028] Figure 8 This is a flowchart illustrating a method for fabricating an array substrate according to a third embodiment of this application.

[0029] Explanation of reference numerals in the attached drawings: Display device - 100, Display panel - 10, Power module - 20, Support frame - 30, Display area - 10a, Non-display area - 10b, Array substrate - 10c, Opposing substrate - 10d, Dielectric layer - 10e, m data lines - S1~Sm, n scan lines - G1~Gn, First direction - F1, Second direction - F2, Timing control circuit - 11, Data driving circuit - 12, Scan driving circuit - 13, Pixel unit - P, Cutting line - X, Connecting line - L, Clock line - CL, Preset area - A, First clock signal - CLK1, Second clock signal - CLK1 Signal-CLK2, Third Clock Signal-CLK3, Fourth Clock Signal-CLK4, Fifth Clock Signal-CLK5, Sixth Clock Signal-CLK6, Seventh Clock Signal-CLK7, Eighth Clock Signal-CLK8, First Clock Line-CL1, Second Clock Line-CL2, Third Clock Line-CL3, Fourth Clock Line-CL4, Fifth Clock Line-CL5, Sixth Clock Line-CL6, Seventh Clock Line-CL7, Eighth Clock Line-CL8, First Connecting Line-L1, Second Connecting Line-L2, Third Connecting Line-L3, Fourth Connecting Line-L4, Control Unit-15. Detailed Implementation

[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0031] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.

[0033] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0035] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a display device 100 according to the first embodiment of this application. The display device 100 includes a display module 10, a power module 20, and a support frame 30. The display module 10 and the power module 20 are fixed to the support frame 30. The power module 20 is disposed on the back of the display module 10, that is, the non-display surface of the display module 10. The power module 20 is used to provide power voltage for the display module 10 to display images. The support frame 30 provides fixation and protection for the display module 10 and the power module 20.

[0036] Please see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the side structure of the display terminal 100.

[0037] like Figure 2As shown, the display panel 10 includes an image display area 10a and a non-display area 10b. The display area 10a is used for image display, and the non-display area 10b is disposed around the display area 10a to house other auxiliary components or modules. Specifically, the display panel 10 includes an array substrate 10c and a counter substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the counter substrate 10d. In this embodiment, the display medium in the display medium layer 10e can be a light-emitting semiconductor material such as MicroLED, Mini LED, or LED, or it can be a liquid crystal layer.

[0038] Please see Figure 3 , Figure 3 for Figure 2 A schematic diagram of the planar layout of the array substrate 10c in the display panel 10 shown. Figure 3 As shown, the corresponding image display area 10a in the array substrate 10c includes multiple m*n pixel units 15 arranged in a matrix, m data lines S1 to Sm, and n scan lines G1 to Gn, where m and n are natural numbers greater than 1.

[0039] The n scan lines G1 to Gn extend along the first direction F1 and are mutually insulated and arranged in parallel along the second direction F2. The m data lines S1 to Sm extend along the second direction F2 and are mutually insulated and arranged in parallel along the first direction F1. The first direction F1 and the second direction F2 are perpendicular to each other.

[0040] Corresponding to the non-display area 10b of the display panel 10 ( Figure 2 The display terminal 100 further includes a timing control circuit 11 for driving pixel units to display images, a data driving circuit 12, and a scanning driving circuit 13 disposed on the array substrate 10c.

[0041] The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, and is used to control the operating timing of the data driving circuit 12 and the scan driving circuit 13. That is, it outputs corresponding timing control signals to the data driving circuit 12 and the scan driving circuit 13 to control when to output the corresponding scan signal and data signal. The timing control circuit 11 is connected to the scan driving circuit 13 through multiple clock lines CL, and is used to output clock signals to the scan driving circuit 13.

[0042] The data driving circuit 12 is electrically connected to the m data lines S1 to Sm, and is used to transmit the data signal (Data) to be displayed to the plurality of pixel units 15 in the form of data voltage through the m data lines S1 to Sm.

[0043] The scan drive circuit 13 is electrically connected to the n scan lines G1 to Gn, and is used to control when the pixel unit 15 receives data signals by outputting scan signals through the n scan lines G1 to Gn according to the received clock signal. Specifically, the scan drive circuit 13 outputs scan signals from the n scan lines G1 to Gn in sequence according to their positional arrangement and in accordance with the scan cycle.

[0044] In this embodiment, the circuit elements in the scanning drive circuit 13 and the pixel units 15 in the array substrate 10c are fabricated in the array substrate 10c using the same process, which is GOA (Gate Driver on Array) technology.

[0045] Please see Figure 4 , Figure 4 for Figure 3 A schematic diagram of the layout of the array substrate. (See attached diagram.) Figure 4 As shown, the array substrate 10c further includes 2n clock lines CL and n connecting lines L, where n is an integer greater than or equal to 1. The 2n clock lines CL transmit clock signals to the scan driving circuit 13, which outputs scan signals based on the received clock signals to control the pixel unit P to receive data signals for image display. The 2n clock lines CL are connected to the scan driving circuit 13 via a preset region A, and the n connecting lines L are located in the preset region A. Each connecting line L connects two clock lines CL at a preset position, enabling the two clock lines CL to transmit the same clock signal. The preset region A is located at the edge of the array substrate 10c adjacent to the scan driving circuit 13 and the display area 10a.

[0046] The data driving circuit 12 outputs data signals to the pixel units in the display area 10a via the preset area A, meaning that the preset area A is located between the data driving circuit 12 and the display area 10a. Since the preset area A is located at the edge of the array substrate 10c, the preset area A can be cut, thereby retaining or removing the preset area A to retain the connecting line L, which is used to control the connection and disconnection of the two clock lines CL, and thus control the two clock lines CL to transmit the same or different clock signals.

[0047] Please refer to the following: Figure 5 , Figure 5 for Figure 4 A schematic diagram of the equivalent circuit of the clock line. (e.g.) Figure 5As shown, in the 2n clock lines CL, the i-th clock line is connected to the (n+i)-th clock line via the i-th connecting line, where i is a positive integer greater than or equal to 1 and less than or equal to n. The n connecting lines L are located in a preset region A. When the array substrate 10c retains the preset region A, the 2n clock lines CL are used to transmit n clock signals to control the pixel unit P to display an image. When the preset region A in the array substrate 10c is removed, the 2n clock lines CL are used to transmit 2n clock signals to control the pixel unit P to display an image.

[0048] For example, when n=4, the array substrate includes 8 clock lines and 4 connection lines. Among the 8 clock lines CL1 to CL8, the first clock line CL1 is connected to the fifth clock line CL5 through the first connection line L1, the second clock line CL2 is connected to the sixth clock line CL6 through the second connection line L2, the third clock line CL3 is connected to the seventh clock line CL7 through the third connection line L3, and the fourth clock line CL4 is connected to the eighth clock line CL8 through the fourth connection line L4. Multiple clock lines CL extend along the second direction F2 and are arranged sequentially along the first direction F1. Multiple connection lines, namely the first connection line L1 to the fourth connection line L4, are located in a preset area A. Multiple clock lines CL are connected to the scan driving circuit 13 to transmit the clock signal CLK to the scan driving circuit 13. The scan driving circuit 13 outputs the corresponding scan signal to the pixel unit P according to the clock signal CLK, thereby controlling the pixel unit P to receive the data signal for image display and perform image display.

[0049] During the fabrication of the array substrate 10c, when it is determined that the array substrate 10c needs to be configured as an 8CLK display panel, the array substrate 10c can be cut by the cutting line X, so that the first clock line CL1 to the eighth clock line CL8 are not electrically connected through the first connecting line L1 to the fourth connecting line L4, thereby maintaining that the eight clock lines transmit eight different clock signals respectively. When the array substrate 10c needs to be configured as a 4CLK display panel, a preset area A can be retained, that is, the preset area A is not cut, so that the first clock line CL1 is connected to the fifth clock line CL5 to transmit the same first clock signal CLK1, the second clock line CL2 is connected to the sixth clock line CL6 to transmit the same second clock signal CLK2, the third clock line CL3 is connected to the seventh clock line CL7 to transmit the same third clock signal CLK3, and the fourth clock line CL4 is connected to the eighth clock line CL8 to transmit the same fourth clock signal CLK4. This makes it suitable for display panels controlled by four clock signals.

[0050] Multiple clock lines are connected in pairs via connecting lines, which are then placed in a preset area on the array substrate, i.e., at the edge of the array substrate. This allows the preset area to be cut during the array substrate manufacturing process without affecting the overall layout and design of the array substrate. By retaining or removing the preset area, the array substrate can be matched with different numbers of clock signals, avoiding the need to re-etch the array substrate, thus saving a large number of photomasks and reducing production costs.

[0051] Please see Figure 6 , Figure 6 This is a schematic diagram of a clock line connection provided for the second embodiment of this application.

[0052] like Figure 6 As shown, the array substrate 10c includes 2n clock lines CL, n switching transistors, and n connection lines L. Among the n switching transistors, the i-th switching transistor is connected to the i-th clock line and the (n+i)-th clock line through the i-th connection line. When the i-th switching transistor is turned on, the i-th clock line and the (n+i)-th clock line are connected to transmit the same clock signal. When the i-th switching transistor is turned off, the i-th clock line and the (n+i)-th clock line are disconnected to transmit different clock signals. The 2n clock lines are connected to the timing control circuit 11 (…). Figure 4 ) and scanning drive circuit 13 ( Figure 4 The clock signal CLK is received from the timing control circuit 11 and transmitted to the scan drive circuit 13 to control the scan drive circuit 13 to output the scan signal.

[0053] For example, when n=4, the array substrate 10c includes 8 clock lines, 4 switching transistors and 4 connection lines. The 8 clock lines CL1 to CL8 transmit the first clock signal CLK1 to the eighth clock signal CLK8 to the scan driving circuit 13, respectively. The scan driving circuit 13 receives the first clock signal CLK1 to the eighth clock signal CLK8 and outputs n scan signals to the pixel unit P through the n scan lines G1 to Gn, so as to control the pixel unit P to receive data signals for image display.

[0054] In the first clock line CL1 to the eighth clock line CL8, the first clock line CL1 and the fifth clock line CL5 are connected to the first switch transistor T1 via the first connection line L1; the second clock line CL2 and the sixth clock line CL6 are connected to the second switch transistor T2 via the second connection line L2; the third clock line CL3 and the seventh clock line CL7 are connected to the third switch transistor T3 via the third connection line L3; and the fourth clock line CL4 and the eighth clock signal are connected to the fourth switch transistor T4 via the fourth connection line L4. The first switch transistor T1, the second switch transistor T2, the third switch transistor T3, and the fourth switch transistor T4 are used to receive a control signal and are turned on under the control of the control signal, thereby controlling the connection of the two clock lines.

[0055] Please refer to the following: Figure 7 , Figure 7 for Figure 6 Schematic diagram of the equivalent circuit of the clock line.

[0056] like Figure 7 As shown, the first clock line CL1 is connected to the source of the first switching transistor T1, the fifth clock line CL5 is connected to the drain of the first switching transistor T1, and the gate of the first switching transistor T1 is connected to the control unit 15 for receiving control signals from the control unit 15. The second clock line CL2 is connected to the source of the second switching transistor T2, the sixth clock line CL6 is connected to the drain of the second switching transistor T2, and the gate of the second switching transistor T2 is connected to the control unit 15 for receiving control signals from the control unit 15. The third clock line CL3 is connected to the source of the third switching transistor T3, the seventh clock line CL7 is connected to the drain of the third switching transistor T3, and the gate of the third switching transistor T3 is connected to the control unit 15 for receiving control signals from the control unit 15. The fourth clock line CL4 is connected to the source of the fourth switching transistor T4, the eighth clock line CL8 is connected to the drain of the fourth switching transistor T4, and the gate of the fourth switching transistor T4 is connected to the control unit 15 for receiving control signals from the control unit 15.

[0057] When the control unit 15 outputs a control signal at the first potential, the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 are turned on, connecting the first clock line CL1 to the fifth clock line CL5, the second clock line CL2 to the sixth clock line CL6, the third clock line CL3 to the seventh clock line CL7, and the fourth clock line CL4 to the eighth clock line CL8. At this time, the first clock line CL1 and the fifth clock line CL5 are used to transmit the first clock signal CLK1, the second clock line CL2 and the sixth clock line CL6 are used to transmit the second clock signal CLK2, the third clock line CL3 and the seventh clock line CL7 are used to transmit the third clock signal CLK3, and the fourth clock line CL4 and the eighth clock line CL8 are used to transmit the fourth clock signal CLK4. This can be applied to control the pixel unit P for image display using four clock signals.

[0058] When the control unit 15 outputs a control signal at the second potential, the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 are turned off, disconnecting the first clock line CL1 from the fifth clock line CL5, the second clock line CL2 from the sixth clock line CL6, the third clock line CL3 from the seventh clock line CL7, and the fourth clock line CL4 from the eighth clock line CL8. At this time, the first clock line CL1 is used to transmit the first clock signal CLK1, the second clock line CL2 is used to transmit the second clock signal CLK2, and so on, with the eighth clock line CL8 used to transmit the eighth clock signal CLK8. This can be applied to control pixel unit P for image display using eight clock signals.

[0059] In an exemplary embodiment, multiple clock lines can also be configured as 12 clock lines, which are connected in pairs to make the array substrate 10c suitable for both 12 clock signals and 6 clock signals. Of course, the number of clock lines can be set according to specific needs, and this application does not limit it.

[0060] By controlling the on and off states of the four switching transistors, the array substrate 10c can be compatible with two sets of clock signals simultaneously, meaning it can display images under the control of two separate clock signals. This avoids modifications to the array substrate, greatly reduces the consumption of photomasks during fabrication, and thus saves production costs.

[0061] Please see Figure 8 , Figure 8 This is a flowchart illustrating a method for fabricating an array substrate according to a third embodiment of this application.

[0062] like Figure 8 As shown, the specific steps are as follows:

[0063] S101, set n connecting lines in a preset area in the array substrate.

[0064] The array substrate 10c also includes 2n clock lines CL and n connecting lines L, where n is an integer greater than or equal to 1. The 2n clock lines CL are used to transmit clock signals to the scan driving circuit 13. The scan driving circuit 13 outputs scan signals based on the received clock signals to control the pixel unit P to receive data signals for image display. The 2n clock lines CL are connected to the scan driving circuit 13 via a preset area A. The n connecting lines L are disposed in the preset area A. Each connecting line L is used to connect two clock lines CL at a preset position, so that the two clock lines CL transmit the same clock signal.

[0065] S102, among the 2n clock lines and the n connecting lines, the i-th clock line is connected to the (n+i)-th clock line through the i-th connecting line, where 1≤i≤n, and i and n are positive integers. The clock lines are used to transmit clock signals to the scan driving circuit in the array substrate to control the scan driving circuit to output scan signals to the pixel units in the display area according to the clock signals. The scan signals control the pixel units to receive data signals for image display and perform image display.

[0066] In the 2n clock lines CL, the i-th clock line is connected to the (n+i)-th clock line through the i-th connecting line, where i is a positive integer greater than or equal to 1 and less than or equal to n, and the n connecting lines L are set in a preset area A.

[0067] S103, the preset area is set at the edge position of the array substrate adjacent to the scanning driving circuit and the display area.

[0068] A preset region A is located on the edge of the array substrate 10c, adjacent to the scan driving circuit 13 and the display area 10a. The data driving circuit 12 outputs data signals to the pixel units in the display area 10a via the preset region A, meaning that the preset region A is located between the data driving circuit 12 and the display area 10a. Since the preset region A is located at the edge of the array substrate 10c, it can be cut. By retaining or removing the preset region A, the connecting line L is retained to control the connection and disconnection of the two clock lines CL, thereby controlling the two clock lines CL to transmit the same or different clock signals.

[0069] S104, when the preset region is cut off, the i-th clock line and the (n+i)-th clock line transmit different clock signals; or when the preset region is retained, the i-th clock line and the (n+i)-th clock line transmit the same or different clock signals.

[0070] When the array substrate 10c retains the preset region A, 2n clock lines CL are used to transmit n clock signals to control the pixel unit P to display an image; that is, two clock lines CL are used to transmit the same clock signal. When the preset region A in the array substrate 10c is removed, 2n clock lines CL are used to transmit 2n clock signals to control the pixel unit P to display an image; that is, 2n clock lines CL are used to transmit different clock signals.

[0071] The array substrate 10c also includes n switching transistors. When the preset region A is reserved, among the n switching transistors, the i-th switching transistor is connected to the i-th clock line and the (n+i)-th clock line through the i-th connection line. When the i-th switching transistor is turned on, the i-th clock line and the (n+i)-th clock line are connected to transmit the same clock signal. When the i-th switching transistor is turned off, the i-th clock line and the (n+i)-th clock line are disconnected to transmit different clock signals. The 2n clock lines are connected to the timing control circuit 11. Figure 3 ) and scanning drive circuit 13 ( Figure 3 The clock signal CLK is received from the timing control circuit 11 and transmitted to the scan drive circuit 13 to control the scan drive circuit 13 to output the scan signal.

[0072] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. An array substrate, comprising a scan driving circuit, 2n clock lines arranged sequentially, and pixel units arranged in an array, wherein n is an integer greater than or equal to 1, the scan driving circuit being configured to receive clock signals from the clock lines and output scan signals to the pixel units according to the clock signals, so as to control the pixel units in the display area to receive data signals for image display and perform image display. Its features are, The array substrate further includes n connecting lines. The i-th clock line is connected to the (n+i)-th clock line through the i-th connecting line, where i is a positive integer greater than or equal to 1 and less than or equal to n. The n connecting lines are disposed in a preset area. The preset area is located at the edge of the array substrate adjacent to the scanning driving circuit and the display area. If the preset area is removed, the i-th clock line and the (n+i)-th clock line transmit different clock signals; or if the preset area is retained, the i-th clock line and the (n+i)-th clock line transmit the same or different clock signals.

2. The array substrate as described in claim 1, characterized in that, The display area includes multiple scan lines extending along a first direction, multiple data lines extending along a second direction, and multiple pixel units. The first direction is different from the second direction. A data driving circuit disposed in the non-display area is used to output the data signal to the pixel unit through the multiple data lines to control the pixel unit to display an image. The preset area is located between the data driving circuit and the display area.

3. The array substrate as described in claim 1, characterized in that, The array substrate further includes n switching transistors, wherein the i-th switching transistor is connected to the i-th clock line and the (n+i)-th clock line through the i-th connection line. When the i-th switching transistor is turned on, the i-th clock line and the (n+i)-th clock line transmit the same clock signal.

4. The array substrate as described in claim 3, characterized in that, The array substrate further includes a control unit. The gate of the i-th switch is connected to the control unit, the source of the i-th switch is connected to the i-th clock line, and the drain of the i-th switch is connected to the (n+i)-th clock line. The control unit is used to output a control signal to the i-th switch to control the i-th switch to be turned on and off.

5. The array substrate as described in claim 4, characterized in that, When the control unit outputs the control signal of the first potential to the i-th switch, the i-th switch is turned on, and the i-th clock line is connected to the (n+i)-th clock line to transmit the i-th clock signal. When the control unit outputs the control signal of the second potential to the i-th switch, the i-th switch is turned off, and the i-th clock line is used to transmit the i-th clock signal, and the (n+i)-th clock line is used to transmit the (n+i)-th clock signal.

6. The array substrate as described in claim 5, characterized in that, When n=4, the array substrate includes eight clock lines and four switching transistors. The first clock line is connected to the fifth clock line through the first switching transistor, the second clock line is connected to the sixth clock line through the second switching transistor, the third clock line is connected to the seventh clock line through the third switching transistor, and the fourth clock line is connected to the eighth clock line through the fourth switching transistor. When the first switching transistor to the fourth switching transistor is turned on, the first clock line to the eighth clock line is used to transmit four different clock signals. When the first switching transistor to the fourth switching transistor is turned off, the first clock line to the eighth clock line is used to transmit eight different clock signals respectively.

7. The array substrate as described in claim 6, characterized in that, The gate of the first switching transistor is connected to the control unit, the source of the first switching transistor is connected to the first clock line, and the drain of the first switching transistor is connected to the fifth clock line. The gate of the second switch is connected to the control unit, the source of the second switch is connected to the second clock line, and the drain of the second switch is connected to the sixth clock line. The gate of the third switch is connected to the control unit, the source of the third switch is connected to the third clock line, and the drain of the third switch is connected to the seventh clock line. The gate of the fourth switch is connected to the control unit, the source of the third switch is connected to the fourth clock line, and the drain of the fourth switch is connected to the eighth clock line. The control unit is used to output control signals to the gates of the first to the fourth switching transistors to control the first to the fourth switching transistors to be turned on or off.

8. The array substrate as described in claim 7, characterized in that, When the control unit outputs the control signal of the first potential, the first to the fourth switching transistors are turned on, the first clock line is connected to the fifth clock line to transmit the first clock signal, the second clock line is connected to the sixth clock line to transmit the second clock signal, the third clock line is connected to the seventh clock line to transmit the third clock signal, and the fourth clock line is connected to the eighth clock line to transmit the fourth clock signal.

9. The array substrate as claimed in claim 7, characterized in that, When the control unit outputs the control signal at the second potential, the first to the fourth switching transistors are turned off. The first clock line is used to transmit the first clock signal, the second clock line is used to transmit the second clock signal, the third clock line is used to transmit the third clock signal, the fourth clock line is used to transmit the fourth clock signal, the fifth clock line is used to transmit the fifth clock signal, the sixth clock line is used to transmit the sixth clock signal, the seventh clock line is used to transmit the seventh clock signal, and the eighth clock line is used to transmit the eighth clock signal.

10. A display panel, characterized in that, The system includes a timing control circuit, a data driving circuit, and an array substrate as described in any one of claims 1-9. The timing control circuit outputs a clock signal to the scan driving circuit via multiple clock lines. The scan driving circuit outputs a scan signal according to the clock signal. The data driving circuit outputs the data signal. The pixel unit receives the data signal and displays an image under the control of the scan signal.

11. A method for fabricating an array substrate, characterized in that, include: Set n connection lines in a preset area in the array substrate; In the 2n clock lines and the n connecting lines, the i-th clock line is connected to the (n+i)-th clock line through the i-th connecting line, where 1≤i≤n, and i and n are positive integers. The clock lines are used to transmit clock signals to the scan driving circuit in the array substrate to control the scan driving circuit to output scan signals to the pixel units in the display area according to the clock signals. The scan signals control the pixel units to receive data signals for image display and perform image display. The preset region is positioned at the edge of the array substrate adjacent to the scanning driving circuit and the display area; When the preset region is cut off, the i-th clock line and the (n+i)-th clock line transmit different clock signals; or When the preset region is retained, the i-th clock line and the (n+i)-th clock line transmit the same or different clock signals.

12. The method for fabricating an array substrate as described in claim 11, characterized in that, The array substrate also includes n switching transistors. The i-th switching transistor is controlled to connect the i-th clock line and the (n+i)-th clock line through the i-th connection line. When the i-th switching transistor is turned on, the i-th clock line and the (n+i)-th clock line transmit the same clock signal. When the i-th switching transistor is turned off, the i-th clock line is used to transmit different clock signals.

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