Semiconductor device, memory cell and method of forming the same

Abstract

A memory cell includes a bottom electrode, a memory element, a selector, a top electrode, and a connection structure. The memory element is disposed on the bottom electrode. The selector is disposed on the memory element. The top electrode is disposed on the selector. The connection structure electrically connects the memory element to the selector, wherein the connection structure includes a base portion and a post portion. The base portion is disposed on the memory element. The post portion is disposed on the base portion, wherein the post portion is substantially connected to the selector and includes angled post feet.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, a memory cell, and a method for forming the same. Prior Technology

[0002] Semiconductor devices and integrated circuits (ICs) are typically fabricated on a single semiconductor wafer. Wafer-level packaging (WPS) allows for the processing of wafer dies and the packaging of these dies with other semiconductor devices or dies, and various technologies have been developed for this purpose. Semiconductor processing for manufacturing semiconductor devices and ICs continues to evolve towards greater device density, higher numbers of semiconductor electronic components (e.g., transistors for logic processing and memory for storing information), and smaller device sizes. For example, memory includes non-volatile memory devices, which retain data even after power loss. Non-volatile memory devices include resistive random access memory (RAM) and / or phase-change random access memory (PCM). Summary of the Invention

[0003] This disclosure describes a memory unit including a bottom electrode, a memory element, a selector, a top electrode, and a connection structure. The memory element is disposed on the bottom electrode. The selector is disposed on the memory element. The top electrode is disposed on the selector. The connection structure electrically connects the memory element to the selector, wherein the connection structure includes a base portion and a post portion. The base portion is disposed on the memory element. The post portion is disposed on the base portion, wherein the post portion is substantially connected to the selector and includes angled post feet.

[0004] This disclosure describes a semiconductor device including a first interconnect structure, at least one memory cell, and a second interconnect structure. The first interconnect structure is disposed on a substrate. The at least one memory cell is disposed on the first interconnect structure, wherein the at least one memory cell includes a bottom electrode, a first memory element, a connection structure, a selector, and a top electrode. The bottom electrode is connected to the first interconnect structure. The first memory element is disposed on the bottom electrode. The connection structure is disposed on the memory element, wherein the connection structure includes a base portion and a pillar portion. The base portion is connected to the memory element, and the pillar portion protrudes from the base portion, wherein the width of the pillar portion near the base portion is wider than the top portion of the pillar portion away from the base portion. The selector is disposed on and connected to the pillar portion. The top electrode is disposed on the selector. The second interconnect structure is disposed on the at least one memory cell and electrically connected to the top electrode.

[0005] Another embodiment of this disclosure describes a method for forming a memory cell. The method includes the following steps: A bottom electrode is disposed. A stack of memory material is disposed on the bottom electrode, and a connecting material is disposed on the stack of memory material. A first patterning process is performed on the connecting material to define a base portion and a pillar portion, wherein the pillar portion includes beveled pillar feet. A selector material is formed on the connecting material. Electrode material is formed on the selector material. A second patterning process is performed to pattern the stack of memory material, connecting material, selector material, and electrode material to respectively form a memory element, a connecting structure having the base portion and the pillar portion, a selector, and a top electrode, wherein the connecting structure electrically connects the memory element to the selector. Simple Explanation of the Diagram

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will provide the best understanding of all aspects of this disclosure. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the key dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figures 1 to 12 are schematic cross-sectional views of various stages in a method for forming a memory cell according to some embodiments of the present disclosure. Figure 13 is a schematic cross-sectional view of a memory cell according to some other embodiments of the present disclosure. Figure 14 is a schematic cross-sectional view of a memory cell according to some other embodiments of the present disclosure. Figure 15 is a schematic cross-sectional view of a memory cell according to some other embodiments of the present disclosure. Figure 16 is a schematic cross-sectional view of a memory cell according to some other embodiments of the present disclosure. Figure 17 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figure 18 is a schematic cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are set forth below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a second feature on or over a first feature may include embodiments in which the second feature and the first feature are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the second feature and the first feature such that the second feature and the first feature are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for the purpose of brevity and clarity and is not, in itself, indicative of a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “on,” “over,” “overlying,” “above,” and “upper” are used herein to describe the relationship between one element or feature shown in the figures and another element or feature. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0009] The embodiments discussed herein can be described in a specific context (i.e., the method of forming the memory cell, which includes forming a selector on the memory element (or device)). In a memory cell implementing a selector (e.g., an ovonic threshold switch (OTS)), the selector is electrically connected to the corresponding memory element to control the corresponding memory element. Conventionally, the memory element is connected to the selector via a connection structure having conductive pillars. The conductive pillars can be formed by patterning (or etching) a connection material to form the conductive pillars, or by a deposition technique that fills openings in a dielectric layer with a connection material to define the conductive pillars.

[0010] However, in traditional methods, patterning (or etching) the interconnect material often results in sharp triangular profiles due to poor etch selectivity, and the resulting conductive pillars are unreliable in establishing the electrical connection between the memory element and the selector. Alternatively, if conductive pillars are formed using deposition techniques, the resulting pillars are often too large or have poor profiles due to insufficient material filling, as it is difficult to fill the small gaps or openings in the dielectric layer. Consequently, the connection between the selector and the memory element is weak, leading to manufacturing difficulties and low device yield.

[0011] According to some embodiments discussed herein, a patterned approach for forming a connection structure is used to securely achieve a connection between a selector and a memory element, the connection structure including pillar portions with high structural integrity and improved profile. This ensures the connection between the selector and the memory element and solves the problems caused by conventional conductive pillars.

[0012] Figures 1 to 12 are cross-sectional views of a method for forming a memory cell according to some embodiments of the present disclosure. In some embodiments, the memory cell is applied to a resistive random-access memory (RRAM) cell, which will be referred to as an RRAM cell hereinafter as shown in Figures 1 to 12. An RRAM cell may include one or more RRAM elements or means.

[0013] Referring to Figure 1, a bottom electrode 104 is provided. For example, the bottom electrode 104 is embedded in a dielectric layer 102. In some embodiments, the dielectric layer 102 comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, spin-on glass (SOG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, spin-on dielectric material, low-k dielectric material, and / or combinations thereof. It should be noted that low-k dielectric materials are generally dielectric materials with a dielectric constant lower than 3.9. Examples of low dielectric constant dielectric materials include BLACK DIAMOND® (Applied Materials, Santa Clara, California), Xerogel, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), Flare, SILK® (Dow Chemical Company, Midland, Michigan), hydrogen silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF) and / or combinations thereof.

[0014] In some embodiments, the dielectric layer 102 is formed by chemical vapor deposition (CVD) (e.g., flowable chemical vapor deposition (FCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma CVD (HDPCVD), or sub-atmospheric CVD (SACVD)), molecular layer deposition (MLD), spin coating, sputtering, or other suitable methods. In one embodiment, the dielectric layer 102 is a single-layer structure. In some other embodiments, the dielectric layer 102 is a multilayer structure. This disclosure is not limited thereto. In some embodiments, the dielectric layer 102 serves as an insulating layer and may be referred to as an inter-metal dielectric (IMD) layer.

[0015] As shown in Figure 1, the bottom electrode 104 is formed in the dielectric layer 102 using a single damascene process. For example, an opening (not shown) is formed in the dielectric layer 102, and the opening is filled with a conductive material. Subsequently, a planarization process (e.g., chemical-mechanical planarization, CMP) is performed to remove excess conductive material, thereby forming the bottom electrode 104. In some embodiments, the surface of the bottom electrode 104 is exposed from the top surface of the dielectric layer 102. In some embodiments, after the planarization process, the top surface of the bottom electrode 104 is substantially coplanar with the top surface of the dielectric layer 102.

[0016] In some embodiments, the bottom electrode 104 is electrically coupled to an overlying structure (e.g., coupled to a first conductive layer of a memory element formed in a subsequent step). In some embodiments, the bottom electrode 104 is configured to transmit a voltage applied to the bottom electrode 104 to a memory element located on the bottom electrode 104. The bottom electrode 104 can be a single-layer structure (of one material) or a multilayer structure (of two or more different structures), and can be formed using CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), combinations thereof, etc. For example, the material of the bottom electrode 104 includes aluminum (Al), copper (Cu), tungsten (W), some other low-resistivity materials, or combinations thereof. From the top view, the bottom electrode 104 can have a circular, square, or rectangular outline.

[0017] In some alternative embodiments, a barrier layer (not shown) is selectively formed between the bottom electrode 104 and the dielectric layer 102. For example, the barrier layer is located on the sidewall of the bottom electrode 104 to substantially separate the bottom electrode 104 from the dielectric layer 102. In some embodiments, the barrier layer comprises a material that prevents the bottom electrode 104 from diffusing into adjacent layers. The material of the barrier layer may include Ti, Ta, TiN, TaN, or other suitable materials, and may be formed using CVD, ALD, PVD, combinations thereof, etc. Furthermore, the barrier layer may have a different material than the material of the bottom electrode 104. For example, in one embodiment, the barrier layer comprises TaN, while the bottom electrode 104 comprises TiN.

[0018] After forming the dielectric layer 102 and the bottom electrode 104, the various steps of forming the memory element 106' and the connection structure 108' (as shown in FIG. 11) on the bottom electrode 104 will be described. Referring to FIG. 2, a memory material stack 106, a connection material 108, a first mask layer 110A (rigid mask), and a second mask layer 110B (rigid mask) are sequentially formed on the dielectric layer 102 and the bottom electrode 104 along a first direction D1 (e.g., the accumulation direction). In other words, the memory material stack 106, the connection material 108, the first mask layer 110A, and the second mask layer 110B are stacked along the first direction D1 and extend along the second direction D2. The second direction D2 is perpendicular to the first direction D1.

[0019] In some embodiments, forming the memory material stack 106 includes sequentially forming a conductive material 106A, a storage element material 106B, and a conductive material 106C on a dielectric layer 102 and a bottom electrode 104. For example, the conductive material 106A is conformally formed on the dielectric layer 102 and the bottom electrode 104. In some embodiments, the conductive material 106A is located between the dielectric layer 102 and the storage element material 106B, and also between the bottom electrode 104 and the storage element material 106B. In some embodiments, the conductive material 106A is in physical contact with the bottom electrode 104. That is, the conductive material 106A is electrically connected to the bottom electrode 104. The conductive material 106A may include conductive materials such as Ti, Co, Cu, AlCu, W, TiN, TiW, TiAl, TiAlN, TaN, Pt, or combinations thereof, and may be formed by any suitable method such as CVD, PVD, etc. In some embodiments, the conductive material 106A has a thickness of about 20 nm to about 50 nm.

[0020] In some embodiments, a storage element material 106B is conformally formed on a conductive material 106A, and the storage element material 106B is connected to the conductive material 106A. For example, the storage element material 106B is in physical contact with the conductive material 106A. The storage element material 106B is located between the conductive material 106A and the conductive material 106C. The storage element material 106B can be formed by any suitable method, such as PVD, ALD, etc. In some embodiments, the storage element material 106B comprises a variable-resistance dielectric material (also known as a resistance-changeable material) for an RRAM element or device. For example, variable resistance dielectric materials include transition metal oxide materials such as hafnium oxide (e.g., HfO or HfO₂), niobium oxide (NbO₂x), lanthanum oxide (LaO₂x), thorium oxide (GdO₂x), vanadium oxide (VO₂x), yttrium oxide (YO₂x), zirconium oxide (ZrO₂x), titanium oxide (TiO₂x), tantalum oxide (TaO₂x), nickel oxide (NiO₂x), tungsten oxide (WO₂x), chromium oxide (CrO₂x), copper oxide (CuO₂x), cobalt oxide (CoO₂x), or iron oxide (FeO₂x), and combinations thereof. The storage element material 106B can have a thickness of about 1 nm to about 10 nm.

[0021] In some embodiments, a conductive material 106C is conformally formed on the storage element material 106B. For example, the conductive material 106C is connected to the storage element material 106B. For example, the conductive material 106C includes conductive materials such as Ti, Co, Cu, AlCu, W, TiN, TiW, TiAl, TiAlN, TaN, Pt, or combinations thereof. In one embodiment, the material of the conductive material 106C is the same as the material of the conductive material 106A. For example, both the conductive material 106C and the conductive material 106A contain TiN. In an alternative embodiment, the material of the conductive material 106A is different from the material of the conductive material 106C. The conductive material 106C can be formed by any suitable method, such as CVD, PVD, etc. In some embodiments, the conductive material 106C has a thickness of about 20 nm to about 50 nm.

[0022] In some embodiments, an adhesive layer (not shown) is selectively formed between the conductive material 106C and the storage element material 106B to enhance adhesion between the conductive material 106C and the storage element material 106B. Due to the adhesive layer, delamination at the interface between the conductive material 106C and the storage element material 106B is prevented. The adhesive layer may be made of a transition metal (e.g., Ti, Ni, Hf, Nb, La, Y, Gd, Zr, Co, Fe, Cu, V, Ta, W, Cr, and combinations thereof) and may be formed by CVD, etc. For example, the adhesive layer contains Ti while the conductive material 106C contains TiN. In this disclosure, the material of the adhesive layer may be selected based on the materials of the layers located below and above the adhesive layer. In some embodiments, the adhesive layer has a thickness of about 10 nm to about 50 nm. Alternatively, the adhesive layer may be optional, provided that sufficient bonding between the conductive material 106C and the storage element material 106B can prevent delamination between the conductive material 106C and the storage element material 106B, and this disclosure is not limited thereto.

[0023] As further shown in Figure 2, in some embodiments, a connection material 108 is formed on the conductive material 106C of the memory material stack 106. For example, the connection material is in physical contact with and electrically connected to the conductive material 106C of the memory material stack 106. For example, the connection material 108 includes conductive materials such as W, Ti, Co, Cu, AlCu, TiN, TiW, TiAl, TiAlN, TaN, Pt, or combinations thereof. The connection material 108 can be formed by any suitable method such as CVD, PVD, etc. In some embodiments, the connection material 108 has a thickness of about 100 nm to about 200 nm. In one embodiment, the material of the connection material 108 is different from the material of the conductive material 106A and / or the material of the conductive material 106C. For example, the connection material 108 contains W. As shown in Figure 2, the dielectric layer 102 and the bottom electrode 104 are completely covered by the memory material stack 106 and the connection material 108.

[0024] In a subsequent step, a first masking layer 110A and a second masking layer 110B are disposed on the connecting material 108. For example, the first masking layer 110A is disposed between the connecting material 108 and the second masking layer 110B and is in physical contact with both the connecting material 108 and the second masking layer 110B. In some embodiments, the material of the first masking layer 110A is different from the material of the second masking layer 110B. For example, in one embodiment, the first masking layer 110A comprises TiN, while the second masking layer 110B comprises a high dielectric constant material, such as HfO2. Furthermore, the first masking layer 110A and the second masking layer 110B can be formed by any suitable method, such as CVD, PVD, ALD, etc.

[0025] Referring to Figures 3 to 6, the various steps of performing the first patterning process to define the base portion 108A and the column portion 108B (as shown in Figure 6) on the connecting material 108 will be described.

[0026] As shown in Figure 3, in some embodiments, the photoresist pattern PR1 is formed on the second mask layer 110B. The photoresist pattern PR1 may be located in the region corresponding to the center position of the bottom electrode 104. In other words, the photoresist pattern PR1 is stacked on the bottom electrode 104 in the first direction D1. In the top view, the photoresist pattern PR1 may have a circular, square, or rectangular outline, and the specific outline may be adjusted based on design requirements.

[0027] In one embodiment, the photoresist pattern PR1 can be formed by coating (e.g., spin coating) and lithography processes; however, this disclosure is not limited thereto. The material of the photoresist pattern PR1 includes, for example, a positive or negative resist suitable for patterning processes (e.g., masked or maskless lithography processes (e.g., electron beam writing or ion beam writing)). In this disclosure, the photoresist pattern PR1 is referred to as a photoresist layer or resist layer. As shown in FIG3, for example, the size of the photoresist pattern PR1 along the first direction D1 and the second direction D2 is larger than the size of the bottom electrode 104.

[0028] Referring to Figure 4, in some embodiments, a first etching process is performed to remove portions of the first masking layer 110A and portions of the second masking layer 110B. For example, in some embodiments, the first etching process includes a first step of etching the second masking layer 110B (e.g., a high dielectric constant material) using a Cl₂ / BCl₃ / O₂ type plasma, and a second step of etching the first masking layer 110A (e.g., TiN) using a Cl₂ / BCl₃ type plasma. After the first etching process, the sidewalls of the first masking layer 110A are aligned with the sidewalls of the second masking layer 110B and the sidewalls of the photoresist pattern PR1. Furthermore, the first masking layer 110A and the second masking layer 110B partially expose the top surface of the bonding material 108.

[0029] Referring to Figure 5, in subsequent steps, a trimming process is performed to further reduce the lateral dimensions of the first masking layer 110A and the second masking layer 110B. For example, the trimming process is performed to optimize the dimensions of the first masking layer 110A and the second masking layer 110B so that the pillar portion 108B of the connecting material 108 formed in subsequent steps (as shown in Figure 6) can have a desired width (minimum critical dimension). In some embodiments, a Cl₂ / HBr-type plasma is used to perform the trimming process to reduce the lateral dimensions of the first masking layer 110A and the second masking layer 110B. In some embodiments, the photoresist pattern PR1 is removed after the trimming process by an acceptable ashing process and / or a photoresist stripping process. For example, in one embodiment, a high-pressure oxygen plasma or the like is used to remove the photoresist pattern PR1. This disclosure is not limited thereto. After the photoresist pattern PR1 is removed, the trimmed first mask layer 110A and second mask layer 110B remain on the connecting material 108 and are stacked along the first direction D1.

[0030] Referring to Figure 6, in some embodiments, a second etching process is performed to remove portions of the bonding material 108 to define the base portion 108A and the pillar portion 108B. For example, an SF6 / O2 / Ar plasma is used to perform the second etching process to completely remove the second masking layer 110B and remove portions of the bonding material 108. This completes the first patterning process that defines the base portion 108A and the pillar portion 108B on the bonding material 108.

[0031] As shown in Figure 6, the first patterning process removes the second mask layer 110B, while a portion of the first mask layer 110A is retained. For example, the first mask layer 110A is retained on the pillar portion 108B of the connecting material 108. In some embodiments, the base portion 108A of the connecting material 108 is disposed on and in solid contact with the conductive material 106C of the memory material stack 106. The pillar portion 108B is disposed on the base portion 108A along a first direction D1 (accumulation direction), and the angle X1 of the sidewall 108B-SW of the pillar portion 108B relative to the base portion 108A is in the range of 30 degrees to 60 degrees. In some embodiments, the pillar portion 108B protrudes from the base portion 108A. Furthermore, the width of the pillar portion 108B decreases along the first direction D1 (accumulation direction). In some embodiments, the width of the column portion 108B near the base portion 108A is wider than the top of the column portion 108B away from the base portion 108A. For example, the column portion 108B has a first surface (bottom surface 108B-BS) and a second surface (top surface 108B-1TS) opposite to the first surface (bottom surface 108B-BS), the first surface (bottom surface 108B-BS) being in contact with the base portion 108A, and the width of the first surface (bottom surface 108B-BS) being greater than the width of the second surface (top surface 108B-1TS).

[0032] As further shown in Figure 6, the column portion 108B may include a column body 108B-1 and a column base 108B-2 (e.g., an angled column base). For example, the column body 108B-1 is disposed on the base portion 108A, while the column base 108B-2 extends from the column body 108B-1 and is disposed on the base portion 108A. In some embodiments, the column base 108B-2 surrounds the lower portion of the column body 108B-1. In some embodiments, the column body 108B-1 has a top surface 108B-1TS, the column base 108B-2 has an angled surface 108B-2TS (corresponding to the sidewall 108B-SW), and there is a stepped height difference between the top surface 108B-1TS and the angled surface 108B-2TS. In some embodiments, the angled surface 108B-2TS is in contact with the top surface 108A-TS of the base portion 108A. Furthermore, the column base 108B-2 has a sidewall 108B-SW with an angle X1 ranging from 30 degrees to 60 degrees. In some embodiments, the angle X1 is the included angle of the base of the column portion 108B (e.g., column base 108B-2), which is measured from the bottom surface 108B-BS of the column portion 108B to the inclined surface 108B-2TS of the column base 108B-2 (angled column base).

[0033] In an exemplary embodiment, by controlling the angle X1 of the column portion 108B (or column base 108B-2) within the range of 30 degrees to 60 degrees, the column portion 108B will have high structural integrity while avoiding line breakage. In contrast, if the angle X1 of the column portion 108B is outside the range of 30 degrees to 60 degrees, the column portion 108B may have a profile that is not conducive to providing electrical interconnection, or may experience problems such as line breakage / column collapse.

[0034] In various embodiments, the ratio of the width 108W1 (e.g., average width) of the column body 108B-1 to the width 108W2 (e.g., maximum width) of the column base 108B-2 is in the range of 1:1 to 4:1. Maintaining the ratio of width 108W1 to width 108W2 within this range can further improve the structural integrity of the column portion 108B. In some embodiments, the column portion has a width-to-height ratio (width 108W1 to height 108H) of 1:5 to 1:15. In one exemplary embodiment, the width 108W1 of the column body 108B-1 is in the range of 10 nm to 20 nm, and the width 108W2 is in the range of 5 nm to 10 nm. In some embodiments, the height 108H of the column portion 108B is in the range of 100 nm to 150 nm. By controlling the dimensions of the column portion 108B within the above ranges, the structural integrity and connection reliability of the column portion 108B can be further improved.

[0035] Referring to Figure 7, after the first patterning process, in a subsequent step, a dielectric material 112 is formed on the base portion 108A, and the dielectric material 112 surrounds the pillar portion 108B of the connecting material 108. For example, the dielectric material 112 covers the top surface 108A-TS of the base portion 108A, surrounds the pillar portion 108B, and further covers the first mask layer 110A. In some embodiments, the dielectric material 112 includes materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, spin-coated glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, spin-coated dielectric materials, low dielectric constant dielectric materials, and / or combinations thereof. It should be noted that low dielectric constant dielectric materials are generally dielectric materials with a dielectric constant below 3.9. Examples of low dielectric constant dielectric materials include Black Diamond® (Applied Materials, Santa Clara, California), xylene, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), Freyr, Silk® (Dow Chemical Company, Midland, Michigan), silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF) and / or combinations thereof. Dielectric material 112 can be formed by any suitable method (e.g., CVD (e.g., FCVD, PECVD, HDPCVD, or SACVD), MLD, spin coating, sputtering, or other suitable methods). As shown in FIG7, at this stage, the pillar portion 108B of the connecting material 108 and the first masking layer 110A are embedded in the dielectric material 112. In other words, the pillar portion 108B and the first masking layer 110A are not exposed.

[0036] Referring to FIG8, after the dielectric material 112 is formed, a planarization process is performed by a mechanical polishing process and / or a chemical mechanical polishing (CMP) process to remove the first mask layer 110A and some portions of the dielectric material 112. For example, as shown in FIG8, the planarization process is performed until the top surface 108B-1TS of the pillar portion 108B is exposed. In some embodiments, after the planarization process, the top surface 112-1TS of the dielectric material 112 is coplanar with the top surface 108B-1TS of the pillar portion 108B of the connecting material 108. In some embodiments, a cleaning step may be optionally performed after the mechanical polishing or chemical mechanical polishing (CMP) process. For example, a cleaning step is performed to clean and remove residues generated by the planarization process. However, this disclosure is not limited to this, and the planarization process may be performed by any other suitable method.

[0037] Referring to FIG9, in some embodiments, a selector material 114 and an electrode material 116 are sequentially formed on the dielectric material 112. For example, the selector material 114 is disposed between the dielectric material 112 and the electrode material 116, and is also disposed between the post portion 108B of the connecting material 108 and the electrode material 116. In some embodiments, the selector material 114 is in solid contact with the post portion 108B of the connecting material 108, and the electrode material 116 is in solid contact with the selector material 114.

[0038] In some embodiments, the selector material 114 is made of a bidirectional threshold switch (OTS) material. The OTS material responds to a voltage applied across the selector (114' shown in FIG. 11) formed in a subsequent step. When the applied voltage is less than a threshold voltage, the selector (114' in FIG. 11) remains in an "off" state (e.g., a non-conductive state). Alternatively, in response to a voltage applied across the selector (114' in FIG. 11) greater than the threshold voltage, the selector (114' in FIG. 11) enters an "on" state, such as a conductive state. That is, the selector (114' in FIG. 11) is referred to as a switch, used to determine whether to turn the memory element (106' in FIG. 11) on or off.

[0039] In some embodiments, the OTS material of the selector material 114 is different from the transition metal oxide material of the storage element material 106B. The OTS material of the selector material 114 may include GeTe, AsGeSe, GeSbTe, GeSiAsTe, GeSe, GeSbSe, GeSiAsSe, GeS, GeSbS, GeSiAsS, or combinations thereof. Alternatively, the OTS material of the selector material 114 may include BTe, CTe, BCTe, CSiTe, BSiTe, BSiTe, BTeN, CTeN, BCTeN, CSiTeN, BSiTeN, BSiTeN, BTeO, CCTeO, BCTeO, CSiTeO, BSiTeO, BSiTeO, BTeON, CCTeON, BCTeON, CSiTeON, BSiTeON, BSiTeON, BSiTeON, or combinations thereof. The selector material 114 may be formed by any suitable method, such as PVD, ALD, etc. In some embodiments, the selector material 114 has a thickness of about 5 nm to about 20 nm. For example, the material of selector material 114 is different from the material of storage element material 106B.

[0040] In some embodiments, electrode material 116 is conformally formed on and in physical contact with selector material 114. For example, electrode material 116 comprises a conductive material such as Ti, Co, Cu, AlCu, W, TiN, TiW, TiAl, TiAlN, TaN, Pt, or combinations thereof. Electrode material 116 can be formed by any suitable method, such as CVD, PVD, etc. In some embodiments, electrode material 116 has a thickness of about 20 nm to about 50 nm. In one embodiment, the material of electrode material 116 is the same as the material of connecting material 108. For example, electrode material 116 comprises W. Alternatively, the material of electrode material 116 may be the same as or different from the materials of conductive materials 106A and 106C.

[0041] Referring to FIG. 10, in some embodiments, after the selector material 114 and the electrode material 116 are formed, a photoresist pattern PR2 is formed on the electrode material 116 along a first direction D1. The photoresist pattern PR2 can be formed by coating (e.g., spin coating) and lithography processes; however, this disclosure is not limited thereto. The material of the photoresist pattern PR2 includes, for example, a positive or negative resist suitable for patterning processes (e.g., masked or maskless lithography processes (e.g., electron beam writing or ion beam writing)). In this disclosure, the photoresist pattern PR2 is referred to as a photoresist layer or a resist layer.

[0042] Referring to FIG11, a second patterning process is performed to pattern the memory material stack 106, the interconnect material 108, the selector material 114, and the electrode material 116 to form a memory element 106', an interconnect structure 108' having a base portion 108A and a pillar portion 108B, a selector 114', and a top electrode 116', respectively. For example, the second patterning process is performed using a photoresist pattern PR2 as a mask and independently includes an etching step, such as dry etching, wet etching, or a combination thereof. In some embodiments, the conductive material 106A, the storage element material 106B, and the conductive material 106C of the memory material stack 106 are patterned to form a first conductive layer 106A', a storage layer 106B', and a second conductive layer 106C' of the memory element 106'. For example, the first conductive layer 106A' is disposed on and physically connected to the bottom electrode 104. Storage layer 106B' is located between first conductive layer 106A' and second conductive layer 106C'. Second conductive layer 106C' is disposed on storage layer 106B' and is physically connected to base portion 108A of connection structure 108'.

[0043] In some embodiments, the memory element 106' is a metal-insulator-metal (MIM) structure and is referred to as a resistive random access memory (RRAM) device. In some embodiments, the first conductive layer 106A' is referred to as the bottom electrode of the RRAM and the second conductive layer 106C' is referred to as the top electrode of the RRAM.

[0044] Generally, RRAM devices or elements (e.g., memory element 106') operate based on the principle that a normally insulated dielectric material / dielectric layer can become conductive through a conductive path formed by a fuse or after applying a sufficiently high voltage. The formation of conductive paths can be achieved by various mechanisms, including but not limited to defects, metal migration, oxygen vacancies, etc. As described above, during a write operation on memory element 106', a "set" voltage is applied across the top and bottom electrodes to change the variable-resistivity dielectric material from a first resistivity (e.g., a high resistance state (HRS) where the fuse or conductive path between the top and bottom electrodes is broken) to a second resistivity (e.g., a low resistance state (LRS) where the fuse or conductive path between the top and bottom electrodes is established).

[0045] Similarly, a "reset" voltage is applied to both sides of the top and bottom electrodes to change the variable resistivity dielectric material from the second resistivity back to the first resistivity, for example, from LRS to HRS. Therefore, when LRS and HRS correspond to logic "1" and logic "0" states respectively (or vice versa), the "set" voltage and "reset" voltage can be used to store digital information bits in the RRAM cell (e.g., memory cell MC1 in FIG. 12) through the memory element 106 to provide the relevant storage function.

[0046] As further shown in Figure 11, a connection structure 108' is formed on the memory element 106', and the connection structure 108' includes a base portion 108A and a pillar portion 108B. The details of the base portion 108A and the pillar portion 108B are the same as those described for the connection material 108 shown in Figure 6, and therefore will not be repeated herein. In some embodiments, a dielectric material 112 is patterned during a second patterning process to form a dielectric layer 112'. For example, the dielectric layer 112' is disposed on the base portion 108A of the connection structure 108', and the dielectric layer 112' surrounds the pillar portion 108B of the connection structure 108'. Furthermore, the top surface 112-TS of the dielectric layer 112' is coplanar with the top surface 108B-1TS of the pillar portion 108B of the connection structure 108'. In some embodiments, the connection structure 108' is disposed on the memory element 106', and the memory element 106' is electrically connected to the selector 114'. Selector 114' is disposed on dielectric layer 112' and is in physical contact with pillar portion 108B of connection structure 108', while top electrode 116' is disposed on selector 114' and is in physical contact with selector 114'.

[0047] In some embodiments, after the second patterning process, the photoresist pattern PR2 is removed by an acceptable ashing process and / or a photoresist stripping process (e.g., using oxygen plasma, etc.); however, this disclosure is not limited thereto. After the second patterning process, the sidewalls 106A-SW of the first conductive layer 106A', the sidewalls 106B-SW of the storage layer 106B', the sidewalls 106C-SW of the second conductive layer 106C', the sidewalls 108A-SW of the base portion 108A, the sidewalls 112SW of the dielectric layer 112', the sidewalls 114SW of the selector 114', and the sidewalls 116SW of the top electrode 116' are substantially coplanar and aligned with each other.

[0048] Referring to Figure 12, in a subsequent step, a dielectric layer 120 is formed on the dielectric layer 102 to cover and surround the memory element 106', the connection structure 108', the selector 114', and the top electrode 116'. For example, the dielectric layer 120 covers the sidewalls 106A-SW of the first conductive layer 106A', the sidewalls 106B-SW of the storage layer 106B', the sidewalls 106C-SW of the second conductive layer 106C', the sidewalls 108A-SW of the base portion 108A, the sidewalls 112SW of the dielectric layer 112', the sidewalls 114SW of the selector 114', and the sidewalls 116SW of the top electrode 116'. In some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP)) is performed to remove excess dielectric material from dielectric layer 120, such that the top surface 120TS of dielectric layer 120 is substantially coplanar with the top surface 116TS of top electrode 116'. This realizes the memory cell MC1 according to some embodiments of the present disclosure. In some embodiments, dielectric layer 112' and dielectric layer 120 are collectively referred to as the interlayer dielectric (ILD) of memory cell MC1.

[0049] As shown in Figure 12, selector 114' is electrically coupled to memory element 106' in memory cell MC1. For example, the second conductive layer 106C' of memory element 106' is electrically connected to selector 114' via connection structure 108'. That is, memory element 106' is electrically coupled to selector 114' in series. In this configuration, voltage can be applied to selector 114' to control the state of memory element 106' (e.g., "on" or "off"). When memory element 106' is on, voltage is further applied to the first conductive layer 106A' and second conductive layer 106C' of memory element 106' to operate the storage function of memory element 106' (via HRS and LRS). As shown in Figure 12, memory cell MC1 has a selector 114' and a memory element 106' electrically connected to each other and located between an upper interconnect structure and a lower interconnect structure (not shown). In other words, the memory cell MC1 is implemented as a 1-selector-1-resistor (1S1R) configuration. However, this disclosure is not limited thereto, and in other embodiments, the memory cell may include a selector 114' and a plurality of memory elements electrically connected to said selector 114'. In some other embodiments, the memory cell MC1 is implemented as a 1-selector-1-transitor-1-resistor (1S1T1R) configuration.

[0050] In an exemplary embodiment, for the memory cell MC1, the pillar portion 108B of the connection structure 108' is designed to have sidewalls 108B-SW with an angle X1 ranging from 30 degrees to 60 degrees, and is formed using a patterning process employing a double hard mask method. This allows for appropriate control of the critical dimensions of the pillar portion 108B of the connection structure 108. Furthermore, the connection structure 108' will have higher structural integrity and an improved profile, and will ensure the connection between the selector 114' and the memory element 106'. Overall, issues such as wire breakage, peeling, or contact failures in the connection structure 108' at the memory cell boundaries can be avoided.

[0051] Figure 13 is a schematic cross-sectional view of a memory cell according to some other embodiments of the present disclosure. The memory cell MC2 shown in Figure 13 is similar to the memory cell MC1 shown in Figure 12. Therefore, the same element symbols are used to denote the same or similar elements, and will not be described again herein. The difference between the embodiments is that the memory cell MC2 also includes a second memory element 107. In the previous embodiments, the memory cell MC1 was configured with a 1-selector-1-resistor (1S1R). However, the present disclosure is not limited thereto. For example, referring to Figure 13, the memory cell MC2 is configured with a 1-selector-2-resistor (1S2R). In other words, it should be understood that the memory cell of the present disclosure can be implemented as any of the 1S1R configuration, 1S2R configuration, 1S3R configuration, 1S4R configuration…1SxR configuration, etc. Note that x represents a positive integer.

[0052] In some embodiments, in a memory cell MC2 with a 1S2R configuration, the memory cell MC2 includes a selector 114' and two memory elements 106' and 107. The selector 114' and memory element 106' are similar to the selector and memory element described in FIG. 12, and therefore will not be described again herein. As shown in FIG. 13, the memory cell MC2 also includes a second memory element 107 disposed between the memory element 106' and the bottom electrode 104. In other words, the memory element 106' is electrically connected to the bottom electrode 104 through the second memory element 107.

[0053] The second memory element 107 may include a first conductive layer 107A, a storage layer 107B, and a second conductive layer 107C. The first conductive layer 107A is electrically connected and physically connected to the bottom electrode 104. The storage layer 107B is disposed on the first conductive layer 107A and located between the first conductive layer 107A and the second conductive layer 107C. The second conductive layer 107C is disposed on the storage layer 107B and is in physical contact with the storage layer 107B. The method and materials for forming the memory element 107 are the same as or similar to those for forming the memory element 106' previously described, and therefore will not be repeated herein.

[0054] In some embodiments, the memory cell MC2 further includes an electrode layer 105 disposed on and in physical contact with the second conductive layer 107C. Furthermore, a dielectric layer 103 is formed to surround the memory element 107 and the electrode layer 105. The formation and material of the electrode layer 105 may be similar to those of the bottom electrode 104, and therefore will not be described further herein. Similarly, the formation and material of the dielectric layer 103 may be similar to those of the dielectric layer 102, and therefore will not be described further herein. Furthermore, the selector 114', the memory element 106', and the memory element 107 are electrically coupled in series with each other.

[0055] In an exemplary embodiment, with regard to the memory cell MC2, the pillar portion 108B of the connection structure 108' is designed to have sidewalls 108B-SW with an angle X1 ranging from 30 degrees to 60 degrees, and is formed using a patterning process employing a double hard mask method. This allows for appropriate control of the critical dimensions of the pillar portion 108B of the connection structure 108. Furthermore, the connection structure 108' will have higher structural integrity and an improved profile, ensuring the connection between the selector 114' and the memory element 106'. Overall, issues such as wire breakage, peeling, or contact failures in the connection structure 108' at the memory cell boundaries can be avoided.

[0056] Figure 14 is a schematic cross-sectional view of a memory cell according to some other embodiments of the present disclosure. The memory cell MC3 shown in Figure 14 is similar to the memory cell MC1 shown in Figure 12. Therefore, the same element symbols are used to denote the same or similar elements, and will not be described again herein. In the previous embodiments, the memory element 106' was intended for use in an RRAM device. However, the present disclosure is not limited thereto, and the memory element can be applied to a phase change random access memory (PCRAM) device. For example, referring to Figure 14, the memory cell MC3 includes a storage layer 106D located between a first conductive layer 106A' and a second conductive layer 106C', and thus the storage layer 106D contains a phase change material.

[0057] In some embodiments, the phase change material of the storage layer 106D includes chalcogenide materials, such as indium (In)-antimony (Sb)-tellurium (Te) (IST) or germanium (Ge)-antimony (Sb)-tellurium (Te) (GST). ISG materials may include In 2Sb 2Te 5, In 1Sb 2Te 4, In 1Sb 4Te 7, etc. GST materials may include Ge 8Sb 5Te 8, Ge 2Sb 2Te 5, Ge 1Sb 2Te 4, Ge 1Sb 4Te 7, Ge 4Sb 4Te 7, Ge 4SbTe 2, Ge 6SbTe 2, etc. As used herein, hyphenated chemical composition symbols refer to elements contained in a particular mixture or compound and are intended to indicate all stoichiometry involving the indicated element. Other phase change materials may include, for example, Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—S b—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—Sb—Ge, Te—Ge—Sb—S, Te—Ge —Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—Sb—Te—Pd, Ge—Sb—Te—Co, Sb—Te—Bi— Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, Ge—Te—Sn—Ni, Ge—Te—Sn—Pd, and Ge—Te—Sn—Pt. The formation of storage layer 106D can be similar to the formation of storage layer 106B' shown in FIG12 and can have substantially the same thickness.

[0058] Because the storage layer 106D contains a phase change material, it has a variable phase representing data bits. For example, the storage layer 106D has interchangeable crystalline and amorphous phases. The crystalline and amorphous phases can represent binary "1" and binary "0", respectively, or vice versa. Therefore, the storage layer 106D has a variable resistance that changes with the variable phase. For example, the storage layer 106D has high resistance in the amorphous phase and low resistance in the crystalline phase.

[0059] In the operation of memory cell MC3, the data state of memory cell MC3 is read by measuring the resistance of memory cell MC3 (i.e., the resistance from the first conductive layer 106A' (e.g., used as the bottom electrode) to the second conductive layer 106C' (e.g., used as the top electrode)). The phase of storage layer 106D represents the data state of memory cell MC3, the resistance of storage layer 106D, or the resistance of memory cell MC3. Furthermore, the data state of memory cell MC3 can be set and reset by changing the phase of storage layer 106D.

[0060] In some embodiments, the phase of the storage layer 106D is changed by heating. For example, a first conductive layer 106A' (or a second conductive layer 106C') heats the storage layer 106D to a first temperature, which causes the storage layer 106D to crystallize, thereby changing the storage layer 106D to a crystalline phase (e.g., to set the memory cell MC3). Similarly, the first conductive layer 106A' (or the second conductive layer 106C') heats the storage layer 106D to a second temperature, which causes the storage layer 106D to melt, thereby changing the storage layer 106D to an amorphous phase (e.g., to reset the memory cell MC3). The first temperature is lower than the second temperature. In some embodiments, the first temperature is 100°C to 200°C and the second temperature is 500°C to 800°C. In this disclosure, the first conductive layer 106A' may be referred to as a heater for the memory cell MC3, or the first conductive layer 106A' and the second conductive layer 106C' may be referred to together as a heater.

[0061] The heat generated by the first conductive layer 106A' (or the second conductive layer 106C') varies proportionally to the current applied to the first conductive layer 106A' (or the second conductive layer 106C'). That is, when current passes through the storage layer 106D, the storage layer 106D is heated to a temperature higher than the melting temperature (i.e., the second temperature). Then, the temperature rapidly drops below the crystallization temperature. In this case, a portion of the storage layer 106D changes to an amorphous state with high resistivity, and therefore the state of the memory cell MC3 changes to a high-resistivity state. Then, this portion of the storage layer 106D can be reset back to the crystalline state by heating the storage layer 106D to a temperature higher than the crystallization temperature but lower than the melting temperature (i.e., the first temperature) for a certain period of time.

[0062] In an exemplary embodiment, with regard to the memory cell MC3, the pillar portion 108B of the connection structure 108' is designed to have sidewalls 108B-SW with an angle X1 ranging from 30 degrees to 60 degrees, and is formed using a patterning process employing a double hard mask method. This allows for appropriate control of the critical dimensions of the pillar portion 108B of the connection structure 108. Furthermore, the connection structure 108' will have higher structural integrity and an improved profile, ensuring the connection between the selector 114' and the memory element 106'. Overall, issues such as wire breakage, peeling, or contact failures in the connection structure 108' at the memory cell boundaries can be avoided.

[0063] Figure 15 is a schematic cross-sectional view of a memory cell according to some other embodiments of the present disclosure. The memory cell MC4 shown in Figure 15 is similar to the memory cell MC1 shown in Figure 12. Therefore, the same element symbols are used to denote the same or similar elements, and will not be described again herein. The difference between the embodiments lies in the design of the column portion 108B of the connecting structure 108'.

[0064] As shown in FIG. 15, the connection structure 108' includes a base portion 108A disposed on the memory element 106' and a column portion 108B disposed on the base portion 108A. In some embodiments, the column portion 108B includes a column body 108B-1 and a column foot 108B-2 (or an angled column foot). For example, the column body 108B-1 is disposed on the base portion 108A, while the column foot 108B-2 extends from the column body 108B-1 and is disposed on the base portion 108A. In some embodiments, the column foot 108B-2 completely surrounds the column body 108B-1. In some embodiments, the column body 108B-1 has a top surface 108B-1TS, and the column foot 108B-2 has an angled surface 108B-2TS (corresponding to the sidewall 108B-SW), wherein the top surface 108B-1TS is in contact with the angled surface 108B-2TS. Furthermore, the inclined surface 108B-2TS is in contact with the top surface 108A-TS of the base portion 108A. In addition, the column base 108B-2 has a sidewall 108B-SW with an angle X1 ranging from 30 degrees to 60 degrees.

[0065] In an exemplary embodiment, with regard to the memory cell MC4, the pillar portion 108B of the connection structure 108' is designed to have sidewalls 108B-SW with an angle X1 ranging from 30 degrees to 60 degrees, and is formed using a patterning process employing a double hard mask method. This allows for appropriate control of the critical dimensions of the pillar portion 108B of the connection structure 108. Furthermore, the connection structure 108' will have higher structural integrity and an improved profile, ensuring the connection between the selector 114' and the memory element 106'. Overall, issues such as wire breakage, peeling, or contact failures in the connection structure 108' at the memory cell boundaries can be avoided.

[0066] Figure 16 is a schematic cross-sectional view of a memory cell according to some other embodiments of the present disclosure. The memory cell MC5 shown in Figure 16 is similar to the memory cell MC1 shown in Figure 12. Therefore, the same element symbols are used to denote the same or similar elements, and will not be described again herein. The difference between the embodiments lies in the design of the column portion 108B of the connecting structure 108'.

[0067] In a previous embodiment, the column base 108B-2 of the column portion 108B is shown to have an inclined surface 108B-2TS. However, this disclosure is not limited thereto. As shown in FIG16, in some embodiments, the column portion 108B includes a column body 108B-1 and a column base 108B-2 (e.g., an inclined column base), and the sidewall 108B-SW of the column portion 108B is a curved sidewall. Furthermore, the column base 108B-2 of the column portion 108B includes a curved sidewall. In some embodiments, the curved sidewall (sidewall 108B-SW) ​​extends from the top surface 108B-1TS of the column body 108B-1 toward the top surface 108A-TS of the base portion 108A.

[0068] In an exemplary embodiment, with regard to the memory cell MC5, the pillar portion 108B of the connection structure 108' is designed to have a sidewall 108B-SW (curved sidewall) with an angle X1 ranging from approximately 30 to 60 degrees, and is formed using a patterning process employing a double hard mask method. This allows for appropriate control of the critical dimensions of the pillar portion 108B of the connection structure 108. Furthermore, the connection structure 108' will have higher structural integrity and an improved profile, ensuring the connection between the selector 114' and the memory element 106'. Overall, issues such as wire breakage, peeling, or contact failures in the connection structure 108' at the memory cell boundaries can be avoided.

[0069] Figure 17 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. The memory cell MC1 shown in the following embodiments is applicable to, but not limited to, RRAM cells. The structure, materials, and processes may be similar to those shown in Figures 1 to 12 and discussed with reference to Figures 1 to 12. Therefore, they will not be described again here. It should be noted that other memory cells MC2, MC3, MC4, and MC5 may individually replace memory cell MC1 to form the semiconductor device of the examples described.

[0070] Referring to Figure 17, the semiconductor device SM1 includes a substrate 200, a device region 202, a first interconnect structure 210, a memory cell MC1, and a second interconnect structure 220. In some embodiments, the substrate 200 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 200 may be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 200 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a semiconductor material layer formed on an insulating layer. For example, the insulating layer is a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the substrate 100 includes elemental semiconductors (e.g., silicon or germanium), compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP), or combinations thereof.

[0071] In some embodiments, in a front-end-of-line (FEOL) process, a device region 202 is formed on a substrate 200. Device region 202 may include a wide variety of devices. In some embodiments, the devices include active elements, passive elements, or combinations thereof. In some other embodiments, the devices include integrated circuit devices. For example, the devices are transistors, capacitors, resistors, diodes, photodiodes, fuses, or other similar devices. In embodiments, device region 202 includes a gate structure, source and drain regions, and an isolation structure, such as a shallow trench isolation (STI) structure (not shown). Various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices (e.g., transistors or memory, etc.) may be formed and interconnected in device region 202 to perform one or more functions. Other devices (e.g., capacitors, resistors, diodes, photodiodes, fuses, etc.) may also be formed on the substrate 200. The device may include memory, processor, sensors, amplifiers, power distribution, input / output circuitry, etc.

[0072] As shown in Figure 17, a first interconnect structure 210 is disposed on a device region 202, and the device region 202 is disposed between a substrate 200 and the first interconnect structure 210. In some embodiments, the first interconnect structure 210 includes a plurality of accumulation layers (M1 to Mx-1, where x is 3 or a positive integer greater than 3; not indicated), wherein the plurality of accumulation layers form an insulating layer and a conductive layer. Specifically, the first interconnect structure 210 includes at least insulating layers 211, 213, 215, 217, vias 212, 216, and conductive layers 214, 218. The via 212 is disposed on and electrically connected to the device region 202. The conductive layer 214 is disposed on and electrically connected to the via 212. Insulating layers 211 and 213 are collectively referred to as intermetallic dielectric (IMD) layers, which laterally wrap around via 212 and conductive layer 214 to form accumulation layer M1. On the other hand, conductive layer 218 is disposed on and electrically connected to via 216. Insulating layers 215 and 217 are collectively referred to as IMD layers, which laterally wrap around via 216 and conductive layer 218 to form another accumulation layer Mx-1. For example, as shown in FIG17, accumulation layers M1 (211, 212, 213, 214) are electrically connected to accumulation layers Mx-1 (215, 216, 217, 218) through other accumulation layers (not shown). Alternatively, the accumulation layers M1 (211, 212, 213, 214) can be directly electrically connected to the accumulation layers Mx-1 (215, 216, 217, 218).

[0073] As further shown in Figure 17, the memory cell MC1 and the second interconnect structure 220 are stacked sequentially on the first interconnect structure 210 along the first direction D1 (accumulation direction). The memory cell MC1 is electrically connected to the first interconnect structure 210 and the second interconnect structure 220. The second interconnect structure 220 may include an insulating layer 222B and a connecting layer 222A. The insulating layer 222B is referred to as an IMD layer, which laterally wraps around the connecting layer 222A to form an accumulation layer (not labeled) or a portion thereof. The insulating layer 222B is disposed on the memory cell MC1 to partially cover the top electrode 116'. The connecting layer 222A is disposed in the insulating layer 222B to be electrically connected to the selector 114' included in the memory cell MC1. Furthermore, the bottom electrode 104 of memory cell MC1 is in contact with and electrically connected to the conductive layer 218 of the first interconnect structure 210, and the top electrode 116' of memory cell MC1 is in contact with and electrically connected to the connection layer 222A of the second interconnect structure 220. The connection layer 222A can provide voltage to the selector 114' to control the state of memory cell MC1 (e.g., "on" or "off" memory element 106'). Alternatively, the conductive layer 218 and the connection layer 222A can provide voltage to the memory element 106' of memory cell MC1 to operate the storage function of memory cell MC1. In other embodiments, any one of memory cells MC2, MC3, MC4, or MC5 can be used to replace memory cell MC1.

[0074] In some embodiments, insulating layers 211, 213, 215, 217, and 222B are independently formed of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, spin-coated dielectric material, or low dielectric constant dielectric material). Conductive layers 214, 218, and connection layer 222A can each be a conductive trace / wire / wiring. Conductive layers 214, 218, connection layer 222A, and vias 212, 216 may independently comprise a metal or metal alloy, including one or more of Al, AlCu, Cu, Ti, TiN, W, etc. Conductive layers 214, 218, and connection layer 222A are part of a current-driven circuit (not shown) for providing voltage to the memory cell MC1. In some embodiments, vias 212, 216, and conductive layers 214, 218 are formed using a dual damascene process. That is, vias 212, 216, and conductive layers 214, 218 can be formed simultaneously. In some embodiments, the memory cell MC1 may be disposed in any two adjacent conductive layers of a back-end-of-line (BEOL) structure. In some embodiments, the fabrication process of the memory cell MC1 may be compatible with the BEOL process of a semiconductor device, thereby simplifying the process steps and efficiently increasing integration density.

[0075] Figure 18 is a schematic cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure. The semiconductor device SM2 shown in Figure 18 is similar to the semiconductor device SM1 shown in Figure 17. Therefore, the same element symbols are used to denote the same or similar elements, and will not be described again herein. The difference between the embodiments is that the semiconductor device SM2 of Figure 18 has a plurality of memory cells MC1. For example, as shown in Figure 18, two memory cells MC1 are located between a first interconnect structure 210 and a second interconnect structure 220. In some embodiments, the two memory cells MC1 are electrically coupled to each other through the first interconnect structure 210. The two memory cells MC1 may correspond to the memory cell MC1 shown in Figure 12, and will not be described again herein.

[0076] Although two identical memory cells MC1 are described herein, it should be understood that a semiconductor device may include two identical memory cells (e.g., MC1, MC2, MC3, MC4, or MC5) or two different memory cells (e.g., MC1, MC2, MC3, MC4, and MC5). For example, a semiconductor device may include memory cells MC1 and MC2; a semiconductor device may include memory cells MC1 and MC3; a semiconductor device may include memory cells MC1 and MC4; a semiconductor device may include memory cells MC1 and MC5; a semiconductor device may include memory cells MC2 and MC3; a semiconductor device may include memory cells MC2 and MC4; a semiconductor device may include memory cells MC2 and MC5; a semiconductor device may include memory cells MC3 and MC4; a semiconductor device may include memory cells MC3 and MC5; or a semiconductor device may include memory cells MC4 and MC5. Furthermore, the number of memory cells (MC1, MC2, MC3, MC4, and MC5) located in the storage region MR of the semiconductor device is not limited to one or two, but may be three or more. In a semiconductor device, where there are multiple memory cells (MC1, MC2, MC3, MC4, and MC5), the memory cells (MC1, MC2, MC3, MC4, and MC5) can be used individually (all memory cells of the same type) or in combination (memory cells of different types).

[0077] In the above embodiments, in each memory cell, the pillar portion (or pillar foot) of the connection structure is designed to have an included angle ranging from approximately 30 to 60 degrees. The connection structure is formed using a dual hard mask method, which allows for control of the patterning / etching process of the connection structure, and one of the hard masks can be used as a stop layer after a planarization (e.g., CMP) step. This allows for appropriate control of the critical dimensions of the pillar portion of the connection structure while ensuring that the selector's connection structure has a small but reliable contact area. Furthermore, the connection structure will have higher structural integrity and an improved profile to provide a connection between the selector and the memory element. Overall, this structural design and process control avoids line breakage, peeling, or contact failures at the memory cell boundaries.

[0078] According to some embodiments of this disclosure, a memory unit includes a bottom electrode, a memory element, a selector, a top electrode, and a connection structure. The memory element is disposed on the bottom electrode. The selector is disposed on the memory element. The top electrode is disposed on the selector. The connection structure electrically connects the memory element to the selector, wherein the connection structure includes a base portion and a pillar portion. The base portion is disposed on the memory element. The pillar portion is disposed on the base portion, wherein the pillar portion is substantially connected to the selector and includes angled pillar feet.

[0079] In some embodiments, the width of the column portion decreases along the accumulation direction. In some embodiments, the beveled column foot has curved sidewalls. In some embodiments, the column portion includes: a column body disposed on the base portion; and the beveled column foot extending from the column body and disposed on the base portion, wherein the beveled column foot has an included angle of 30 degrees to 60 degrees. In some embodiments, the ratio of the width of the column body to the width of the beveled column foot is in the range of 1:1 to 4:1. In some embodiments, the memory cell further includes a dielectric layer disposed on the base portion of the connection structure and surrounding the column portion of the connection structure, wherein the top surface of the dielectric layer is coplanar with the top surface of the column portion of the connection structure. In some embodiments, the selector comprises a bidirectional threshold switch material.

[0080] According to some other embodiments of this disclosure, a semiconductor device includes a first interconnect structure, at least one memory cell, and a second interconnect structure. The first interconnect structure is disposed on a substrate. The at least one memory cell is disposed on the first interconnect structure, wherein the at least one memory cell includes a bottom electrode, a first memory element, a connection structure, a selector, and a top electrode. The bottom electrode is connected to the first interconnect structure. The first memory element is disposed on the bottom electrode. The connection structure is disposed on the memory element, wherein the connection structure includes a base portion and a pillar portion. The base portion is connected to the memory element, and the pillar portion protrudes from the base portion, wherein the width of the pillar portion near the base portion is wider than the top portion of the pillar portion away from the base portion. The selector is disposed on and connected to the pillar portion. The top electrode is disposed on the selector. The second interconnect structure is disposed on the at least one memory cell and electrically connected to the top electrode.

[0081] In some embodiments, the column portion has curved sidewalls. In some embodiments, the column portion includes a column body and a column base. The column body is disposed on the base portion. The column base extends from the column body and is disposed on the base portion, wherein the included angle measured from the bottom surface of the column portion to the inclined surface of the column base is in the range of 30 degrees to 60 degrees. In some embodiments, the column portion has a width-to-height ratio of 1:5 to 1:15. In some embodiments, the first memory element includes: a first conductive layer disposed on the bottom electrode; a second conductive layer disposed on the first conductive layer and connected to the connection structure; and a storage layer located between the first conductive layer and the second conductive layer. In some embodiments, the semiconductor device further includes: a second memory element disposed between the first conductive layer of the first memory element and the bottom electrode. In some embodiments, the semiconductor device further includes a dielectric layer disposed on the base portion of the connection structure and surrounding the column portion of the connection structure, wherein the top surface of the dielectric layer is coplanar with the top surface of the column portion of the connection structure. According to another embodiment of the disclosure, a method of forming a memory cell is described. The method includes the following steps: disposing a bottom electrode. A memory material stack is disposed on the bottom electrode, and a connecting material is disposed on the memory material stack. A first patterning process is performed on the connecting material to define a base portion and a pillar portion, wherein the pillar portion includes beveled pillar feet. A selector material is formed on the connecting material. Electrode material is formed on the selector material. A second patterning process is performed to pattern the stack of the memory material, the connecting material, the selector material, and the electrode material to respectively form a memory element, a connecting structure having the base portion and the pillar portion, a selector, and a top electrode, wherein the connecting structure electrically connects the memory element to the selector.

[0082] In some embodiments, the first patterning process includes: forming a first mask layer on the connecting material and forming a second mask layer on the first mask layer; forming a photoresist pattern on the second mask layer; performing a first etching process to remove portions of the first mask layer and portions of the second mask layer; removing the photoresist pattern; and performing a second etching process to remove portions of the connecting material to define the base portion and the pillar portion. In some embodiments, the method further includes: forming a dielectric material on the base portion of the connecting material after the first patterning process, the dielectric material surrounding the pillar portion of the connecting material; and performing a second patterning process to pattern the dielectric material together with the connecting material to form a dielectric layer and the connecting structure. In some embodiments, after the second patterning process, the sidewalls of the dielectric layer are aligned with the sidewalls of the selector and with the sidewalls of the base portion of the connecting structure. In some embodiments, the first patterning process removes the second masking layer while retaining a portion of the first masking layer, and the method further includes performing a planarization process after the first patterning process to remove the first masking layer and a portion of the dielectric material, wherein after the planarization process, the top surface of the dielectric material is coplanar with the top surface of the pillar portion of the connecting material. In some embodiments, after the first patterning process, the pillar portion is formed with a pillar body and the angled pillar foot, the pillar body being disposed on the base portion, and the angled pillar foot extending from the pillar body and disposed on the base portion, wherein the angled pillar foot has an included angle of 30 degrees to 60 degrees.

[0083] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0084] 102, 103, 112', 120: Dielectric layers 104: Bottom Electrode 105: Electrode layer 106: Stacking of memory materials 106': Memory element 106A, 106C: Conductive materials 106A', 107A: First conductive layer 106A-SW, 106B-SW, 106C-SW, 108A-SW, 108B-SW, 112SW, 114SW, 116SW: Sidewall 106B: Storage element material 106B', 106D, 107B: Storage layer 106C', 107C: Second conductive layer 107: Second memory element / memory element 108: Connecting materials 108': Connection structure 108A: Base section 108A-TS, 108B-1TS, 112-TS, 116TS, 120TS: Top surface 108B: Column section 108B-1: Main body of the column 108B-2: Column base 108B-2TS: Inclined Surface 108B-BS: Bottom surface 108H: Altitude 108W1, 108W2: Width 110A: First Cover Layer 110B: Second Cover Layer 112: Dielectric materials 114: Selector Material 114': Selector 116: Electrode Materials 116': Top electrode 200: Base 202: Device Area 210: First internal connection structure / First internal connection structure 211, 213, 215, 217, 222B: Insulation layer 212, 216: Through holes 214, 218: Conductive layer 220: Second internal connection structure 222A: Connector Layer D1: First Direction D2: Second Direction M1, Mx-1: Accumulation layer MC1, MC2, MC3, MC4, MC5: Memory Units PR1, PR2: Photoresist patterns SM1, SM2: Semiconductor devices X1: Angle

Claims

1. A memory unit, comprising: Bottom electrode; A memory element is disposed on the bottom electrode; A selector is disposed on the memory element; A top electrode is disposed on the selector; and a connection structure for electrically connecting the memory element to the selector, wherein the connection structure includes: a base portion disposed on the memory element, wherein the sidewall of the base portion is aligned with the sidewall of the memory element; A column portion, disposed on the base portion, wherein the column portion is physically connected to the selector and includes beveled column feet, and the column portion has a width-to-height ratio of 1:5 to 1:

15.

2. The memory cell as claimed in claim 1, wherein the angled column base has curved sidewalls.

3. A semiconductor device, comprising: The first internal interconnect structure is set on the base; At least one memory cell is disposed on the first interconnect structure, wherein the at least one memory cell includes: a bottom electrode connected to the first interconnect structure; a first memory element disposed on the bottom electrode; a connection structure disposed on the first memory element, wherein the connection structure includes: a base portion connected to the first memory element, wherein the sidewall of the base portion is aligned with the sidewall of the first memory element; a pillar portion protruding from the base portion, wherein the width of the pillar portion near the base portion is wider than the top portion of the pillar portion away from the base portion, and the pillar portion has a width-to-height ratio of 1:5 to 1:15; a selector disposed on the pillar portion and physically connected to the pillar portion; and a top electrode disposed on the selector. A second interconnect structure is disposed on the at least one memory cell and electrically connected to the top electrode.

4. The semiconductor device as claimed in claim 3, wherein the pillar portion comprises: The column body is mounted on the base portion; And a column base, extending from the column body and disposed on the base portion, wherein the included angle measured from the bottom surface of the column portion to the inclined surface of the column base is in the range of 30 degrees to 60 degrees.

5. A method for forming memory units, comprising: Provide bottom electrode; A memory material stack is disposed on the bottom electrode, and a connecting material is disposed on the memory material stack; A first patterning process is performed on the connecting material to define a base portion and a pillar portion, wherein the pillar portion includes beveled pillar feet; a selector material is formed on the connecting material; an electrode material is formed on the selector material; a second patterning process is performed to pattern the memory material stack, the connecting material, the selector material, and the electrode material to respectively form a memory element, a connecting structure having the base portion and the pillar portion, a selector, and a top electrode, wherein the connecting structure electrically connects the memory element to the selector, and the pillar portion is physically connected to the selector, and after performing the second patterning process, the sidewalls of the base portion are aligned with the sidewalls of the memory element, and the pillar portion has an aspect ratio of 1:5 to 1:

15.

6. A semiconductor device, comprising: The first internal interconnect structure is set on the base; The second interconnect structure is disposed on the substrate and located above the first interconnect structure; The system includes a memory unit disposed between the first interconnect structure and the second interconnect structure, wherein the memory unit comprises: a memory element disposed on the first interconnect structure; a connecting base disposed on the memory element, wherein the connecting base has a flat upper surface; and a connecting post disposed on the connecting base and partially covering the flat upper surface, wherein the connecting post comprises a post body and a post foot, wherein the post foot surrounds the lower part of the post body, and the connecting post has a width-to-height ratio of 1:5 to 1:

15.

7. The semiconductor device of claim 6, wherein the memory element comprises: First conductive layer; A storage layer is disposed on the first conductive layer; And a second conductive layer is disposed on the storage layer.

8. A semiconductor device, comprising: A memory unit includes: a memory element and a selector disposed on the memory element; and a connection structure that connects the memory element to the selector, wherein the connection structure includes: a base portion connected to the memory element; and a pillar portion disposed on the base portion, wherein the pillar portion is physically connected to the selector, and the pillar portion includes angled pillar feet, wherein the height of the pillar portion is greater than the thickness of the base portion, and the pillar portion has a width-to-height ratio of 1:5 to 1:

15.

9. The semiconductor device of claim 8, wherein the angled pin has a sidewall with an angle in the range of 30 degrees to 60 degrees.

10. A semiconductor device, comprising: A first memory cell includes: a first memory element; a first connection base disposed on the first memory element; a first connection post disposed on the first connection base, wherein the width of the first connection post near the first connection base is wider than the top of the first connection post away from the first connection base, and the first connection post has a width-to-height ratio of 1:5 to 1:15; a first selector disposed on the first connection post; a second memory cell disposed beside the first memory cell; and a dielectric layer laterally surrounding the first memory cell and the second memory cell, wherein the dielectric layer body contacts the first memory element, the first connection base and the first selector, and is separate from the first connection post body.

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