Method for fabricating and coupling word lines to memory cell array

Abstract

This specification describes techniques for creating word lines of a 3D memory cell array and coupling them to corresponding word lines in a word line connection region. One example is a method comprising positioning a memory cell array on a substrate adjacent to a word line connection region, the word line connection region comprising a plurality of layers alternating between a first material and a second material; replacing at least a portion of the layers of the first material with a third material; and replacing at least a portion of the layers of the second material with a fourth material, wherein the fourth material forms word lines in the word line connection region and is electrically coupled to memory cell word lines within the memory cell array.

Description

Technical Field

[0001] This manual pertains to semiconductor components, systems, processes, and equipment. Prior Technology

[0002] Conventionally, memory cells of memory elements are arranged in a two-dimensional column, such as an A×B arrangement. Each memory cell can store a binary bit value of logic zero or one. The cells in the column are electrically coupled by bit lines. In addition, each cell is electrically coupled to a word line. The intersection points of the bit lines and word lines define the memory address of a specific memory cell. To further increase bit density, some memory elements are formed by stacking memory cells in a three-dimensional manner to form an A×B×C memory cell array. Summary of the Invention

[0003] This specification describes techniques for coupling word lines of a 3D memory cell array to corresponding word lines in a word line connection region. This specification further describes processes for fabricating word lines within the word line connection region. Specifically, a memory cell array, such as a dynamic random access memory (DRAM) array, can be fabricated and then integrated with a word line connection region, in which word lines can be formed layer by layer and electrically coupled to the word lines of the memory cell array. In some embodiments, the word line connection region is fabricated with a specific layout of alternating layers of two different materials. Using a combination of etching and deposition processes, the layers of the word line connection region can be transformed into alternating layers of materials with dry etching selectivity. Further operations can be performed on the word line connection region to form word lines layer by layer to electrically couple each memory cell word line to an external electrical conduction path.

[0004] Typically, an innovative aspect of the object described in this specification can be embodied in a method. This method includes positioning a memory cell array on a substrate adjacent to a word line connection region, the word line connection region comprising a plurality of layers alternating between a first material and a second material; replacing at least a portion of the layers of the first material with a third material; and replacing at least a portion of the layers of the second material with a fourth material, wherein the fourth material forms word lines in the word line connection region and is electrically coupled to the memory cell word lines within the memory cell array.

[0005] Typically, another innovative aspect of the subject matter described in this specification can be embodied in a layout structure for manufacturing memory elements. This layout structure includes a substrate base; a word line connection region formed on a first portion of the substrate, the word line connection region comprising a plurality of layers alternating between a first material and a second material, the word line connection region further comprising one or more slits through the layers, wherein each of the one or more slits exposes the surface of each of the layers; and a 3D memory cell array comprising a plurality of memory cells arranged along the x, y, and z axes, the 3D memory cell array being positioned on a second portion of the substrate adjacent to the word line connection region.

[0006] Typically, another innovative aspect of the object described in this specification can be embodied in a method. This method includes positioning a memory cell array on a substrate adjacent to a word line connection region, the word line connection region comprising a plurality of layers alternating between a first material and a second material; forming one or more slits through the layers in the word line connection region, wherein each of the one or more slits exposes the surface of each of the layers in the word line connection region; using selective etching to recess at least a portion of each layer of the first material, wherein the one or more slits are used to approach the layers; and recessing a portion of a gate oxide layer adjacent to the recessed portions of the layers of the first material, wherein the recessed portions of the gate oxide layer expose the memory cell array. The surface of the word line region of the memory cell; partially recessing the word line region of the memory cell array; reducing the size of at least a portion of the second material layer; depositing a layer of third material in the recessed portions of the word line region of the memory cell and in the recessed space of the first material; recessing at least a portion of each layer of the second material; recessing the portion of the gate oxide layer of the memory cell array adjacent to the second material and the corresponding memory cell word line of the memory cell array; and depositing a layer of fourth material in the recessed space of the second material to form word lines in the word line connection region, each word line being electrically coupled to the corresponding memory cell word line.

[0007] The subject matter described in this specification can be implemented in these and other embodiments to achieve one or more of the following advantages. The layout and processes described in this specification facilitate the formation of layer-by-layer word line connections to memory cells in a 3D memory cell array, which can manage word line connections as bit density increases and therefore the size of the memory cell array increases. This allows for layer-by-layer word line connections within word line connection regions with compact and precisely specified geometric sizes. Furthermore, by fabricating the memory cell array and word line connection regions separately and then integrating them, the manufacturing process is simplified. Modifying the standard DRAM word line connection stack to a stack of materials with dry etching selectivity allows for more precise layer-by-layer creation of word line connections to the memory cell array. Simple Explanation of the Diagram

[0008] Figure 1 illustrates an exemplary DRAM memory cell.

[0009] Figure 2 illustrates an exemplary memory cell array.

[0010] Figure 3 is a flowchart of an exemplary process for manufacturing word lines and coupling them to a memory cell array.

[0011] Figure 4 is a diagram of an exemplary layout of the memory cell array and word line connection area.

[0012] Figure 5 shows the memory cell array integrated with the word line connection area.

[0013] Figure 6 is a diagram of a memory cell array integrated with a word line connection region having open slits, and includes a cross-sectional view of the magnified region.

[0014] Figure 7 is a diagram of a memory cell array integrated with the word line connection region, including a cross-sectional view of an enlarged region with a recessed SiGe layer.

[0015] Figure 8 is a diagram of a memory cell array integrated with the word line connection area, including a cross-sectional view of an enlarged area with gate oxide recesses.

[0016] Figure 9 is a diagram of a memory cell array integrated with the word line connection area, including a cross-sectional view of an enlarged area with cell word line recesses.

[0017] Figure 10 is a diagram of a memory cell array integrated with the word line connection area, including a cross-sectional view of an enlarged area with reduced silicon layers.

[0018] Figure 11 is a diagram of a memory cell array integrated with the word line connection area, including a cross-sectional view of an enlarged area with an added oxide layer.

[0019] Figure 12 is a diagram of a memory cell array that integrates word line connection areas with etched word line stepped openings.

[0020] Figure 13 is a diagram of a memory cell array integrated with a word line connection region having open slits, including a cross-sectional view of the magnified region.

[0021] Figure 14 is a diagram of a memory cell array integrated with the word line connection area, including a cross-sectional view of an enlarged area with a recessed silicon layer.

[0022] Figure 15 is a diagram of a memory cell array integrated with the word line connection area, including a cross-sectional view of an enlarged area with gate oxide recesses.

[0023] Figure 16 is a diagram of a memory cell array integrated with word line connection regions, including a cross-sectional view of an enlarged region with conductive word line deposition.

[0024] Similar reference numerals and symbols in the various figures indicate similar elements. Implementation

[0025] This specification describes techniques for coupling word lines of a 3D memory cell array to corresponding word lines in word line connection regions. This specification further describes techniques for fabricating word lines within word line connection regions to provide layer-by-layer word lines corresponding to columns of the 3D memory cell array.

[0026] Figure 1 illustrates an exemplary DRAM memory cell 100. The DRAM memory cell 100 comprises a transistor 102 and a pair of capacitors 104 configured to store one data bit. In some embodiments, metal-oxide-semiconductor (MOS) technology may be used to form the transistor and capacitor. The charging or discharging state of the capacitor corresponds to a logic zero or one for the information bit.

[0027] The internal structure shown is provided as an exemplary representation. Other memory cell configurations are possible. For example, in some alternative embodiments, a DRAM memory cell may be formed by two transistors without capacitors. Furthermore, although DRAM memory cells and arrays have been described, these techniques are applicable to other types of memory cells formed as 3D arrays.

[0028] Memory cell 100 is electrically coupled to bit line 106 and word line 108. Bit line 106 is electrically coupled to the source terminal of transistor 102, and word line is electrically coupled to the gate terminal of transistor 102. Read operations for reading the state of a capacitor and write operations for setting the state of a capacitor can be controlled by selectively sending or receiving power along the bit line and word line.

[0029] Figure 2 illustrates an exemplary three-dimensional (3D) memory cell array 200. The 3D memory cell array 200 is formed by an assembly of memory cells 202 arranged along three dimensions; for example, the array may have memory cells arranged in a cube having the height, width, and depth of the memory cells. Each memory cell may be, for example, a DRAM memory cell 100 as shown in Figure 1. In the example shown in Figure 2, the 3D memory cell array is a 3×4×2 array of 24 memory cells. A large number of memory cells may be formed as an array of memory elements (e.g., DRAM memory elements having millions to billions of memory cells).

[0030] In an exemplary 3D memory cell array 200, word lines 204a-c are electrically coupled to memory cells 202 along a first axis, while bit lines 206a-d are electrically coupled to memory cells 202 along a second vertical axis. Thus, for example, word line 204a is coupled to the gate terminals of the memory cell transistors in memory cells 202a and 202b. As the size of the memory cell array increases, the number of externally coupled word lines needs to increase within relatively constrained geometric regions. Due to the complexity of multilayer and multimaterial fabrication, such external couplings typically need to be fabricated separately from the memory cell array. Figures 3 through 16 depict the layout of word line connection regions where word line couplings can be fabricated and joined to corresponding word lines of the fabricated 3D memory cell array.

[0031] Figure 3 is a flowchart of an exemplary process 300 for fabricating word lines and coupling them to a memory cell array. The exemplary process 300 can be performed using one or more different semiconductor fabrication components and may include wet etching, dry etching, and deposition operations.

[0032] Process 300 includes integrating the fabricated 3D memory cell array with word line connection regions (302). For example, the 3D memory cell array may be positioned on a substrate adjacent to multilayer word line connection regions. The 3D memory cell array is positioned such that the word lines of the 3D memory cell array terminate adjacent to the surface of the word line connection regions. One or more outer surfaces of the 3D memory cell array (including the surface at the end of the word lines) are coated with an oxide layer called a "gate oxide," which may be formed by thermal oxidation of silicon to form silicon dioxide. Within the 3D memory cell array, each memory cell may be partially or completely surrounded by the gate oxide layer. Furthermore, columns of memory cells may be separated from upper and lower columns by an oxide layer (e.g., silicon dioxide SiO2).

[0033] Figure 4 is a diagram of an exemplary layout 400 of the memory cell array and word line connection area. Figure 5 is an isometric view 500 of the memory cell array 502 integrated with the word line connection area 504. Layout 400 may represent a top view of a portion of the memory cell array 502 and word line connection area 504 of Figure 5. Layout 400 includes a single column of memory cells 402 from the memory cell array and an area representing the word line connection area 404. Specifically, the memory cell 402 specifically illustrates four individual memory cells, each memory cell having a capacitor portion 406a and a transistor gate and a memory cell word line portion 406b. Therefore, in the layout illustration, there are four individual memory cells in this column of memory cells 402.

[0034] As shown in Figure 5, memory cell 402 is part of a larger 3D memory cell array 502. The memory cell array 502 is located adjacent to a word line connection region 504. The word line connection region 504 consists of multiple stacked layers. In some embodiments, the multiple stacked layers consist of alternating layers of silicon and silicon alloys (such as silicon-germanium, SiGe), as described in more detail below.

[0035] To provide access to the word line connection region and multiple layers within each row of memory cells, slits can be formed within the word line connection region 504 to expose multiple layers. As shown in Figure 4, the slits 410 are illustrated as being aligned with the capacitor portions of each memory cell, which allows operations to be performed on the layers of the word line connection region coupled to the word lines of the memory cell array. In some embodiments, additional isolation structures 412 may be added to the word line connection region and extend through the multiple layers of the word line connection region 504. For example, the word line connection region may be an insulating region fabricated to have separate areas of the word line connection region coupled to the rows of memory cells in the memory cell array.

[0036] As shown in Figure 3, process 300 includes opening slits (304) in the word line interconnect region. For example, an etching operation can be performed on the word line interconnect region to form channels or trenches extending through multiple layers across the word line interconnect region. The etching process can be selective, for example, such that alternating etching operations are performed to remove layers of different materials. In some embodiments, since SiGe is not selectable in dry etching operations, a wet etching operation is performed to remove layers in the word line interconnect region to form slits. Wet etching is a process used, for example, to selectively remove material from layers deposited onto a wafer substrate. Wet etching uses a liquid chemical etchant to remove material. A mask can be applied to a surface to define the surface to be etched. For example, a mask can be applied that exposes only the area corresponding to the slit to be opened within the word line interconnect region. The liquid etchant dissolves the material to be etched. In some embodiments, the etchant is selective for a particular material, such that the etchant may need to be switched to etch layers of different materials. In other embodiments, a single etchant can be used to remove material from both the silicon layer and the SiGe layer in the word line interconnect region. Wet etching can be isotropic to some extent, which means that the slits formed in the word line connection area are not completely uniform.

[0037] Figure 6 is Figure 600 of the memory cell array 602 integrated with the word line connection region 604 having an open slit 606, and includes a cross-sectional view of an enlarged region 608 that includes a portion of the memory cell array 602 and multiple layers of the word line connection region 604. As shown in the layout with respect to Figure 4, the open slit 602 extends through multiple layers of the word line connection region 604 and is aligned with the capacitor portions of each row of memory cells.

[0038] The enlarged area 608 illustrates the memory cell layer and material layer in the word line connecting area. Specifically, the enlarged area illustrates eight memory cells 609 arranged in four columns of two memory cells each. Each column of memory cells is separated by an oxide layer 610 (e.g., SiO2). The memory cells 609 are positioned and cross-sectionally cut such that the memory cell represents the transistor gate and the cell word line 612 portion of the memory cell. The capacitor portion (not shown) of each memory cell is positioned behind the illustrated memory cell, i.e., perpendicular to the cross-section.

[0039] The memory cells 609 shown in the given column are coupled to the same memory cell word lines 612. Additionally, as formed during the manufacturing process, the word lines of all columns are coupled together because the oxide layer 610 does not extend to the edge facing the word line connection region 604. The memory cell word lines 612 are formed of a conductive material, which can be a metal or other conductive / semiconductor material; for example, the memory cell word lines 612 can be formed of titanium nitride (TiN), tungsten (W), molybdenum (Mo), or ruthenium (Ru). The gate oxide layer 614 separates a portion of the memory cell array 602 from the word line connection region 604.

[0040] The word line connection region 604 is composed of multiple alternating layers of materials. In particular, the word line connection region 604 includes multiple alternating layers of silicon 616 and SiGe 618. Due to the slits etched in the word line connection region 604, each of the alternating layers is adjacent to the slit channel and is accessible, for example, via an etching or deposition operation described in more detail below.

[0041] As shown in Figure 3, process 300 includes recessing the SiGe layer in the word connection region (306). Specifically, a wet etching composition selected for SiGe can be introduced into the slots formed in the word connection region. Selective wet etching aimed at dissolving only SiGe recesses the SiGe layer on each side of the slot while leaving the silicon layer unaffected.

[0042] Figure 700 shows a memory cell array 602 integrated with word line connection region 604, including a cross-sectional view of an enlarged region 708 with a recessed SiGe layer. In Figure 700, word connection region 604 includes a recessed layer 702 illustrated in both word line connection region 604 and enlarged region 708. Gate oxide layer 614 and silicon layer 616 remain unchanged.

[0043] As shown in Figure 3, process 300 includes recessing a portion of the gate oxide layer (308). Specifically, a portion of the gate oxide layer of the memory cell array is now exposed by the recess of the SiGe layer. The exposed portion of the gate oxide layer can then be selectively etched, for example, using a wet etching process having a composition selectively etched to etch the exposed gate oxide layer without etching the silicon layer of the word line interconnect regions.

[0044] Figure 800 shows a cross-sectional view of a memory cell array 602 integrated with word line connection region 604, including an enlarged region 808 with gate oxide recesses 802. In Figure 800, the enlarged region 808 illustrates openings formed in the gate oxide layer 614, which are aligned with the recessed layer 702 previously filled by the SiGe layer in the word line connection region 604.

[0045] As shown in Figure 3, process 300 includes recessing (310) a portion of the memory cell word line region in the memory cell array. As described above, the conductive material of the memory cell word line bonds to each of the cell word line columns because the oxide layer does not extend all the way to the gate oxide layer. To electrically separate each column of memory cells in the memory cell array, a portion of the conductive material in the memory cell array is recessed. An opening in the gate oxide layer recessed at step 308 provides access to the region to be recessed. In some embodiments, a wet etching operation may be performed that selectively removes conductive material from the exposed portion of the memory cell word line without removing different materials from other layers.

[0046] Figure 900 shows a cross-sectional view of a memory cell array 602 integrated with the word line connection region 604, including an enlarged region 908 with cell word line recesses 902. The enlarged region 908 illustrates the recesses 902 corresponding to portions of the memory cell word lines, which are aligned with openings 802 formed in the gate oxide layer 614 and further aligned with recessed layers 702 previously filled by SiGe layers in the word line connection region 604. Additionally, the cell word line recesses 902 isolate individual cell word lines 904 from cell word lines above or below adjacent oxide layers 610.

[0047] As shown in Figure 3, process 300 includes reducing the thickness of the silicon layer in the word connection region (312). As shown in Figure 6, the original SiGe layer is substantially thinner than the silicon layer in the illustrated cross-section. The silicon layer is thinned to provide additional space for the new material to be deposited. A selective wet etching operation can be performed to remove the exposed silicon layer in the word connection region applied via a slot. The composition and application time of the wet etching determine the amount of silicon removed from each side of the silicon layer to obtain a specified final thickness. In some embodiments, the silicon layer has an original height (e.g., layer thickness) in a cross-section in the range of 30-100 nanometers (nm) and a height after thickness reduction in the range of 10-50 nm. In contrast, in some embodiments, the original SiGe layer in the word connection region has a height of 10-60 nm in the cross-section. In some embodiments, the surface area of ​​the silicon layer in the vertical direction (e.g., in the plane entering the cross-section of Figure 9 and facing the slot) is also reduced to a certain extent by the etching operation.

[0048] Figure 1000 shows a memory cell array 602 integrated with word line connection region 604, including a cross-sectional view of an enlarged region 1008 of the reduced silicon layer 1002. Compared to the silicon layer 616 shown in Figure 9, the reduced silicon layer 1002 is illustrated to have a reduced thickness. Specifically, the silicon layer 616 has a thickness extending into the width of the gate oxide recess 802. In contrast, in Figure 10, the thickness of the silicon layer 1002 is now less than the thickness of the gate oxide layer 614 between the gate oxide recesses 802.

[0049] As shown in Figure 3, process 300 includes depositing oxide material to fill exposed recesses and slits (314) in the letter-connected region. In some embodiments, the oxide material is silicon dioxide (SiO2). However, in some other embodiments, different dielectric oxide materials may be used, such as silicon oxynitride (SiON), a composite of silicon dioxide, silicon carbide and carbon nitride (SiCON), silicon carbon nitride (SiCN), or silicon nitride (SiNx).

[0050] Therefore, the previous SiGe layer was replaced by an oxide layer. Furthermore, the oxide layer filled the recesses formed in the word lines of the memory cells between columns, resulting in an oxide layer extending through the word connection regions between the columns of memory cells.

[0051] In some embodiments, chemical vapor deposition (CVD) is used to deposit oxide materials. CVD is a deposition technique that uses gaseous precursors to fabricate thin films on a substrate surface. Specifically, in some embodiments, a particular variant of CVD called atomic layer deposition (ALD) may be used. In ALD, the precursor is alternatively provided such that the film can be deposited in successive layers to a desired layer thickness. In some embodiments, the deposited oxide material substantially replaces the previous SiGe layer, for example, to a thickness in cross-section within the same 10-60 nm range as the SiGe layer.

[0052] Figure 1100 shows a cross-sectional view of the memory cell array 602 integrated with the word line connection region 604, including an enlarged region 1108 with an added oxide layer 1102. As shown in Figure 1100, the previously recessed area has been filled with oxide 1102. Additionally, the slits formed in the word line connection region have been filled with oxide 1104. In some embodiments, the top surface of the slit filling is smooth. For example, the top surface of the word line connection region can be polished, for example, using chemical mechanical polishing, to ensure a smooth top surface of the word line connection region.

[0053] As shown in Figure 3, process 300 includes forming a stepped structure (316) for generating word lines layer by layer within the word line interconnect region. After the introduction of the oxide layer, the word interconnect region consists of alternating layers of silicon and oxide. The combination of materials can have dry etching selectivity, thereby allowing the use of dry etching operations to form precise vertical holes or slits for specific layers of the word interconnect region. These slits can provide layer-by-layer vertical portions of multiple word lines for external electrical connections. Thus, there are slits etched to the level of the word interconnect region corresponding to each column of memory cells in the memory cell array.

[0054] For example, dry etching, also known as plasma etching, can be performed by positioning the word connection area within a plasma processing chamber. During the plasma processing operation, a specific etching gas chemical substance, selected to provide etching for specific materials, is ignited to form a plasma. Ions generated from the plasma are accelerated to the substrate. Specifically, a voltage is applied to control the energy and directionality of the ions, for example, guiding ions of specific energy vertically toward the substrate surface to perform etching of layers on the substrate to form various structures. For example, the etching gas chemical substance can be switched for each layer to selectively etch the silicon and SiO2 layers in the word connection area. Dry etching can have greater anisotropy than wet etching, thus allowing for the etching of precise vertical channels.

[0055] Figure 12 is an association with Figure 1200 of a memory cell array 602, which includes a word line connection region 604 integrated with etched word line stepped openings 1202. The word line stepped openings 1202 are vertical holes of varying depths for alignment with each column of memory cells in the memory cell array 602. The depth of each stepped slit may depend on the number of layers in the word line connection region, and therefore on the number of layers, the thickness of each layer, and the thickness of any top coating. The slits may be rectangular, square, or other geometric cross-sections. In some embodiments, rectangular cross-section slits may have cross-sectional dimensions in the range of 50-200 nm along each side.

[0056] For example, in some embodiments, each step opening is formed to a correspondingly reduced depth of silicon layer 1002 having a word line connection region 604.

[0057] As shown in Figure 3, process 300 includes reforming the slits (318) in the word connection region. Specifically, oxides that have been deposited to fill the slit channels and the recessed SiGe layers can be etched to reform the slits in the word connection region. Wet or dry etching processes can be used to reform the slits because the oxides filling the original slits have dry etching selectivity, for example, depending on one or more other parameters, such as duration and precision constraints. The reformed slits again provide access to each layer of the word connection region on each side of the slit.

[0058] Figure 1300 shows the memory cell array 602 integrated with the word line connection region 604, including a cross-sectional view of the enlarged region 1308. In particular, Figure 1300 illustrates the reformed slit 1302 and the stepped opening 1202 in the word line connection region 604.

[0059] As shown in Figure 3, process 300 includes recessing the silicon layer in the word connection region (320). Specifically, a wet etching composition for Si can be introduced into the slots formed in the word connection region. Selective wet etching recesses the Si layer on each side of the slot while leaving the oxide layer unaffected.

[0060] Figure 1400 shows a memory cell array 602 integrated with word line connection region 604, including a cross-sectional view of an enlarged region 1408 with a recessed silicon layer 1402. In Figure 1400, word connection region 604 includes the recessed layer 1402 illustrated in both word line connection region 604 and enlarged view 1408. The remaining portions of oxide layer 1102 and gate oxide layer 614 remain unchanged.

[0061] As shown in Figure 3, process 300 includes recessing a portion of the gate oxide layer (322). Specifically, a portion of the gate oxide layer of the memory cell array is exposed by the recess in the silicon layer. The portion of the oxide layer can then be selectively etched, for example, using a wet etching process having a composition selectively etching the gate oxide layer without etching the oxide layer of the word line interconnect regions.

[0062] Figure 1500 shows a cross-sectional view of the memory cell array 602 integrated with the word line connection region 604, including an enlarged region 1508 with gate oxide recesses 1502. In Figure 1500, the enlarged region 1508 illustrates openings formed in the gate oxide layer 1502, which are aligned with recesses 1402 previously filled by the silicon layer of the word line connection region 604. As a result, there are corresponding open paths extending from the stepped opening 1202 to the recesses 1402 and through the gate oxide layer 1502 to the corresponding rows of the individual memory cell word lines 904.

[0063] As shown in Figure 3, process 300 includes depositing conductive material to form word lines (324) within the word line connection regions. For example, slot channels can be used to deposit metals or other conductive materials, such as TiN, W, Mo, or Ru, to fill the recessed layers and gate oxide layers in the word connection regions. As a result, memory cell word lines are coupled to each column via the deposited conductive material to form word lines extending through the word line connection regions. As described above, atomic layer deposition can be used to deposit conductive material into open spaces between layers to form word lines and connect the corresponding word lines to memory cell word lines.

[0064] Figure 1600 shows a memory cell array 602 integrated with word line connection region 604, including a cross-sectional view of an enlarged region 1608 with conductive word line deposition. In Figure 1600, the conductive word line deposition electrically couples individual memory cell word lines 904 to new word lines 1602 formed within word line connection region 604. Once externally coupled, electrical signals can be selectively sensed or applied to word lines and aligned with bit lines (not shown) to read or write specific memory cells in the memory cell array.

[0065] In some implementations, the stepped slits (also known as word line connection slits) are filled with a conductive material to electrically couple the corresponding word lines to an external electrical path. The stepped slits may be filled with the same material used in the word line formation, such as TiN, W, Mo, or Ru. The conductive material may be deposited simultaneously with the deposition of the conductive material within the stepped slits to form the word lines, or it may be performed in a later processing stage.

[0066] In some implementations, an additional oxide deposition step is performed at a point in the process following the formation of the stepped slits. Specifically, since some of the stepped slits pass through multiple layers in the word line connection region, an oxide layer is added to the sidewalls of the stepped slits to prevent multiple word lines from simultaneously contacting a single stepped slit. A subsequent etching process can be applied to remove the deepest oxide layer adjacent to the word line (before or after depositing conductive material to form the word line). As a result, each vertical stepped slit is in direct contact with a single word line to provide layer-by-layer word line coupling with the stepped slits.

[0067] In some implementations, after depositing conductive material to form word lines, the reformed slits in the word line connection regions are filled with oxide. The top surface of the word line connection regions can be polished, for example, by chemical mechanical polishing to ensure a smooth top surface.

[0068] In addition to the embodiments described in the appended patent application and the embodiments described above, the following embodiments are also innovative:

[0069] Example 1 is a method comprising: positioning a memory cell array substrate adjacent to a word line connection region, the word line connection region comprising a plurality of layers alternating between a first material and a second material; replacing at least a portion of the layers of the first material with a third material; and replacing at least a portion of the layers of the second material with a fourth material, wherein the fourth material forms word lines in the word line connection region and is electrically coupled to memory cell word lines within the memory cell array.

[0070] Example 2 is the method as described in Example 1, which further includes: forming one or more slits through the layers in the word line connection area, wherein each of the one or more slits exposes the surface of each of the layers in the word line connection area.

[0071] Example 3 is the method described in any one of Examples 1 to 2, wherein replacing at least a portion of the layers of the first material with the third material comprises: using selective etching to recess at least a portion of the layers of the first material; reducing the size of at least a portion of the layers of the second material; and depositing the layer of the third material in the recessed space of the first material.

[0072] Example 4 is the method as described in any one of Examples 1 to 3, wherein the memory cell array further includes a surface coated with a gate oxide layer, and the method further includes: recessing a portion of the gate oxide layer adjacent to recessed portions of the first material, wherein the recessed portions of the gate oxide layer expose the surface of the memory cell word line region in the memory cell array.

[0073] Example 5 is the method described in any one of Examples 1 to 4, the method further comprising: partially recessing the word line region of the memory cell in the memory cell array; and depositing the third material layer comprising depositing the third material in the recessed portions of the memory cell word line region and in the recessed space of the first material.

[0074] Example 6 is the method described in any one of Examples 1 to 5, wherein the layer deposited in the word line connection region forms a layer-by-layer stack of the first material and the third material.

[0075] Example 7 is the method described in any one of Examples 1 to 6, and the method further includes: forming a layer-by-layer approach path to a plurality of layers to the word line connection area using dry etching.

[0076] Example 8 is the method described in any one of Examples 1 to 7, wherein replacing at least a portion of the layers of the second material with the fourth material comprises: recessing at least a portion of each layer of the second material; recessing a portion of the gate oxide layer of the memory cell array adjacent to the second material and the corresponding memory cell word line of the memory cell array; and depositing a layer of the fourth material in the recessed space of the second material to form word lines in the word line connection region, the word lines being electrically coupled to the corresponding memory cell word lines.

[0077] Example 9 is the method as described in any one of Examples 1 to 8, wherein the first material is silicon-germanium and the second material is silicon.

[0078] Example 10 is the method described in any one of Examples 1 to 9, wherein the third material is a dielectric oxide material that is susceptible to dry etching.

[0079] Example 11 is the method as described in any one of Examples 1 to 10, wherein the third material comprises one of SiO2, SiON, SiCON, SiCN or SiN.

[0080] Example 12 is the method as described in any one of Examples 1 to 11, wherein the fourth material is a conductive material.

[0081] Example 13 is the method as described in any one of Examples 1 to 12, wherein the fourth material comprises one of titanium nitride, tungsten, molybdenum or ruthenium.

[0082] Example 14 is a layout structure for manufacturing memory elements, the layout structure comprising: a substrate base; a word line connection region formed on a first portion of the substrate, the word line connection region comprising a plurality of layers alternating between a first material and a second material, the word line connection region further comprising one or more slits passing through the layers, wherein each of the one or more slits exposes the surface of each of the layers; and a 3D memory cell array comprising a plurality of memory cells arranged along the x, y, and z axes, the 3D memory cell array being positioned on a second portion of the substrate adjacent to the word line connection region.

[0083] Example 15 is a layout structure as described in Example 14, wherein each slit in the one or more slits is aligned with the capacitor region of the memory cell in the corresponding row.

[0084] Example 16 is a layout structure as described in any one of Examples 14 to 15, wherein the number of slits corresponds to the number of memory cells in a column of this memory cell array.

[0085] Example 17 is a layout structure as described in any one of Examples 14 to 16, the layout structure further including one or more isolation structures formed in the word line connection area, the isolation structures isolating the area of ​​the word line connection area corresponding to the memory cells of the individual rows of the memory cell array.

[0086] Example 18 is a layout structure as described in any one of Examples 14 to 17, wherein the first material is silicon and the second material is silicon-germanium.

[0087] Example 19 is a layout structure as described in any one of Examples 14 to 18, wherein the memory cell array further includes a gate oxide layer coated on at least one first surface of the memory cell array.

[0088] Example 20 is a layout structure as described in any one of Examples 14 to 19, wherein the memory cell array includes a plurality of word lines, wherein each word line has an end face adjacent to the word line connection region.

[0089] Example 21 is a method comprising: positioning a memory cell array on a substrate adjacent to a word line connection region, the word line connection region comprising a plurality of layers alternating between a first material and a second material; forming one or more slits through the layers in the word line connection region, wherein each of the one or more slits exposes the surface of each of the layers in the word line connection region; selectively etching at least a portion of each layer of the first material to recess, wherein the one or more slits are used to approach the layers; and recessing a portion of a gate oxide layer adjacent to the recessed portions of the layers of the first material, wherein the recessed portions of the gate oxide layer expose the memory cell array. The surface of the word line region of the memory cell in the memory cell array; partially recessing the word line region of the memory cell in the memory cell array; reducing the size of at least a portion of the second material layer; depositing a layer of third material in the recessed portions of the memory cell word line region and in the recessed space of the first material; recessing at least a portion of each layer of the second material; recessing the portion of the gate oxide layer of the memory cell array adjacent to the second material and the corresponding memory cell word line of the memory cell array; and depositing a layer of fourth material in the recessed space of the second material to form word lines in the word line connection region, each word line being electrically coupled to the corresponding memory cell word line.

[0090] Although this specification contains numerous specific implementation details, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features specific to particular embodiments of a particular invention. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, even initially claimed, in some cases one or more features from the claimed combination may be removed from this combination, and this claim may be directed to a sub-combination or a variation thereof.

[0091] Similarly, although operations are described in the accompanying drawings and in a specific order within the scope of the invention claims, this should not be construed as requiring such operations to be performed in the specific order or sequence shown, or requiring all of the shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program elements and systems can generally be integrated into a single software product or packaged into multiple software products.

[0092] Specific embodiments of the subject matter have been described. Other embodiments fall within the scope of the following claims. For example, the actions described in the claims can be performed in different orders and still achieve the desired result. As an example, the processes described in the accompanying drawings do not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0093] 100: DRAM memory cell, memory cell 102: Transistor 104: Capacitor 106: Bit line 108: Character Line 200: Three-dimensional (3D) memory cell array, 3D memory cell array 202: Memory Unit 202a: Memory Unit 202b: Memory Unit 204a: Word Line 204b: Word Line 204c: Word line 206a: Bitline 206b: Bitline 206c: Bit line 206d: Bitline 300: Process 302: Steps 304: Steps 306: Steps 308: Steps 310: Steps 312: Steps 314: Steps 316: Steps 318: Steps 320: Steps 322: Steps 324: Steps 400: Layout 402: Memory Unit 404: Word line connection area 406a: Capacitor section 406b: Transistor gate and memory cell word line section 410: Slit 412: Isolation Structure 500: Isometric View 502: Memory Cell Array 504: Word line connection area 600: Figure 602: Memory Cell Array, Open Slit 604: Word line connection area, word connection area 606: Open Slit 608: Zoom in 609: Memory Unit 610: Oxide layer 612: Transistor gate and cell word line, memory cell word line 614: Gate oxide layer 616: Silicon, silicon layer 618:SiGe 700: Figure 702: Depression layer 708: Zoom in 800: Figure 802: Gate oxide recess, opening 808: Zoom in 900: Image 902: Cell word line recess, recess 904: Unit word line, memory unit word line 908: Zoom in 1000: Figure 1002: Silicon layer, reduced silicon layer 1008: Zoom in area 1100: Image 1102: Oxide layer, oxide 1104: Oxide 1108: Zoom in 1200: Figure 1202: Etched letter line stepped opening, letter line stepped opening, stepped opening 1300: Figure 1302: Slit 1308: Zoom in 1400: Figure 1402: Depressed silicon layer, depressed layer, pre-silicon 1408: Zoom in on the area, zoom in on the view 1500: Figure 1502: Gate oxide recess, gate oxide layer 1508: Zoom in 1600: Figure 1602: New character line 1608: Zoom in

[0094] Domestic storage information (please note in order of storage institution, date, and number) none

[0095] Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing word lines and coupling them to a memory cell array, comprising the steps of: positioning a memory cell array on a substrate and adjacent to a word line connection region, the word line connection region comprising a plurality of layers alternating between a first material and a second material; replacing at least a portion of the layers of the first material with a third material; and replacing at least a portion of the layers of the second material with a fourth material, wherein the fourth material forms word lines in the word line connection region and is electrically coupled to memory cell word lines within the memory cell array.

2. The method as described in claim 1 further comprises the following steps: forming one or more slits through the plurality of layers in the word line connection region, wherein each slit in the one or more slits exposes a surface of each of the plurality of layers in the word line connection region.

3. The method as described in claim 2, wherein the step of replacing at least a portion of the layers of the first material with the third material comprises the following steps: using a selective etching to recess at least a portion of each layer of the first material; reducing a size of at least a portion of the layers of the second material; and depositing the layer of the third material in the recessed space of the first material.

4. The method as described in claim 3, wherein the memory cell array further includes a surface coated with a gate oxide layer, the method further comprising the step of: recessing a portion of the gate oxide layer adjacent to recessed portions of the layers of the first material, wherein the recessed portions of the gate oxide layer expose a surface of a memory cell word line region in the memory cell array.

5. The method as described in claim 4 further includes the steps of: recessing a portion of the word line region of the memory cell in the memory cell array; and the step of depositing the layer of the third material includes the steps of: depositing the third material in the recessed portions of the word line region of the memory cell and in the recessed space of the first material.

6. The method as described in claim 5, wherein the step of depositing the layer of the word line connection region forms a layer-by-layer stack of the first material and the third material.

7. The method as described in claim 5 further comprises the step of: forming a layer-by-layer approach path to a plurality of layers of the word line connection region using dry etching.

8. The method as described in claim 2, wherein the step of replacing at least a portion of the layers of the second material with the fourth material comprises the following steps: recessing at least a portion of each layer of the second material; recessing a portion of a gate oxide layer of the memory cell array adjacent to the second material and the corresponding memory cell word line of the memory cell array; and depositing a layer of the fourth material in the recessed space of the second material to form word lines electrically coupled to the corresponding memory cell word lines in the word line connection region.

9. The method as described in claim 1, wherein the first material is silicon-germanium and the second material is silicon.

10. The method as described in claim 1, wherein the third material is a dielectric oxide material susceptible to dry etching.

11. The method as described in claim 10, wherein the third material comprises one of SiO2, SiON, SiCON, SiCN, or SiN.

12. The method as described in claim 1, wherein the fourth material is a conductive material.

13. The method as described in claim 12, wherein the fourth material comprises one of titanium nitride, tungsten, molybdenum or ruthenium.

14. A method for manufacturing word lines and coupling them to a memory cell array, comprising the steps of: positioning a memory cell array on a substrate and adjacent to a word line connection region, the word line connection region comprising a plurality of layers alternating between a first material and a second material; forming one or more slits through the plurality of layers in the word line connection region, wherein each slit in the one or more slits exposes a surface of each of the plurality of layers in the word line connection region; using a selective etching to recess at least a portion of each layer of the first material, wherein the one or more slits are used to approach each layer; recessing a portion of a gate oxide layer adjacent to the recessed portions of the layers of the first material, wherein the recessed portions of the gate oxide layer expose a surface of a memory cell word line region in the memory cell array; recessing a portion of the memory cell word line region in the memory cell array; and reducing a size of at least a portion of a layer of the second material. A layer of a third material is deposited in the recessed portions of the word line region of the memory cell and in the recessed space of the first material. This causes at least a portion of each layer of the second material to be recessed; The gate oxide layer of the memory cell array is recessed in the portion adjacent to the second material and the corresponding memory cell word line of the memory cell array; and a layer of a fourth material is deposited in the recessed space of the second material to form a word line in the word line connection area, and each word line is electrically coupled to a corresponding memory cell word line.

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