Memory device and memory system

Abstract

The memory device includes a memory string. The memory string is used to store first stored data and to compare the first stored data with first input data to generate a first current signal. The memory string includes a plurality of switching elements coupled in series with each other. The switching elements include: a first switching element for having a first threshold voltage level when the first stored data has a first value and a second threshold voltage level when the first stored data has a first encoding range; and a second switching element for having a second threshold voltage level when the first stored data has a first value and a second threshold voltage level when the first stored data has a first encoding range, wherein the first encoding range includes at least the first value and a second value different from the first value.

Description

Technical Field

[0001] This disclosure relates to a memory technology, and more particularly to a memory device and memory system. Prior Technology

[0002] With the rise of big data and artificial intelligence hardware accelerators, data comparison / search has become an indispensable function in these two fields. Existing ternary content-addressable memory (TCAM) can achieve highly parallel search functionality. However, traditional TCAMs are typically composed of SRAM, thus facing the problems of low memory density (16 transistors per TCAM storage cell) and high access power. To reduce power consumption while maintaining high memory density, TCAM array architectures based on non-volatile memory (such as 2T2R, 2FeFET, etc.) have been proposed in recent years. A 3D NAND flash memory in-cell search architecture has been proposed to achieve high-performance search capabilities. This architecture can be applied to various fields, such as: big data search, AI hardware accelerators / classifiers, approximate computation, analog computation, associative memory, few-shot learning, SSD data management, DNA alignment, data filtering, high-dimensional computation, etc. Summary of the Invention

[0003] This disclosure includes a memory device. The memory device includes a memory string. The memory string is used to store first stored data and to compare the first stored data with first input data to generate a first current signal. The memory string includes a plurality of switching elements connected in series with each other. The switching elements include: a first switching element for having a first threshold voltage level when the first stored data has a first value and a second threshold voltage level when the first stored data has a first encoding range; and a second switching element for having a second threshold voltage level when the first stored data has a first value and a second threshold voltage level when the first stored data has a first encoding range, wherein an encoding range includes at least the first value and a second value different from the first value.

[0004] In some embodiments, the memory string is further used to receive a plurality of character line signals, the character line signals being used to carry first input data, and when the first input data has a first value and the first stored data has a first encoding range, the first current signal has a first current level.

[0005] In some embodiments, when the first input data has a third value and the first stored data has a first encoding range, the first current signal has a second current level.

[0006] In some embodiments, the third value is outside the first encoding range, and the second current level is less than the first current level.

[0007] In some embodiments, the control terminal of the first switching element is used to receive the first character line signal in the character line signal, and the control terminal of the second switching element is used to receive the second character line signal in the character line signal. When the first input data has a first value, the first character line signal and the second character line signal have a first voltage level and a second voltage level, respectively. When the first input data has a first encoding range, each of the first character line signal and the second character line signal has a first voltage level.

[0008] In some embodiments, when the first input data has a first encoding range, the third character line signal in the character line signal has a second voltage level; when the first input data has a second encoding range, the third character line signal has a first voltage level; and the second encoding range is greater than the first encoding range.

[0009] In some embodiments, the first voltage level is greater than the second voltage level.

[0010] In some embodiments, when the first input data has a third encoding range, the first character line signal and the second character line signal have a third voltage level and a fourth voltage level, respectively, and the first voltage level, the second voltage level, the third voltage level and the fourth voltage level are different from each other.

[0011] In some embodiments, each of the third voltage level and the fourth voltage level is located between the first voltage level and the second voltage level.

[0012] In some embodiments, when the first input data has a third encoding range and the first stored data has a first value, the first current signal has a second current level.

[0013] In some embodiments, the first value is outside the third encoding range, and the second current level is less than the first current level.

[0014] In some embodiments, when the first input data has a third encoding range and the first stored data has a first value, the first switching element is turned off.

[0015] This disclosure includes a memory device. The memory device includes a memory string. The memory string is used to store first stored data and to compare the first stored data with first input data to generate a first current signal. The memory string includes a plurality of switching elements connected in series with each other. The switching elements include: a first switching element for receiving a first character line signal, having a first threshold voltage level when the first stored data has a first value, and having a second threshold voltage level when the first stored data has a first encoding range; and a second switching element for receiving a second character line signal, having a second threshold voltage level when the first stored data has a first value, and having a second threshold voltage level when the first stored data has a first encoding range, wherein the first encoding range includes at least the first value and a second value different from the first value.

[0016] In some embodiments, when the first input data has a first value, the first character line signal and the second character line signal have a first voltage level and a second voltage level, respectively, and when the first input data has a first encoding range, each of the first character line signal and the second character line signal has a first voltage level.

[0017] In some embodiments, when the first input data has a third value, the first character line signal and the second character line signal have a third voltage level and a fourth voltage level, respectively, and the first voltage level, the second voltage level, the third voltage level and the fourth voltage level are different from each other.

[0018] In some embodiments, when the first input data has a third value and the first stored data has a first encoding range, the third switching element in the switching element is turned off, and the third value is outside the first encoding range.

[0019] In some embodiments, when the first input data has a first encoding range, each of the first character line signal and the second character line signal has a first voltage level.

[0020] This disclosure includes a memory system. The memory system includes a plurality of text chunks, each text chunk being used to generate a plurality of bit-line signals, and a plurality of memory strings. Each memory string includes: a first memory string for storing first stored data, for receiving a plurality of bit-line signals carrying first input data, and for comparing the first stored data and the first input data to generate a first current signal, wherein in response to the first stored data having a first encoding range and the first input data having a first value, the first current signal has a first current level, and the first encoding range includes the first value.

[0021] In some embodiments, the first encoding range further includes a second value that is different from the first value.

[0022] In some embodiments, in response to the first stored data having a first encoding range, each of at least two switching elements in the first memory string having a first critical voltage level, and the at least two switching elements being arranged sequentially. Simple Explanation of the Diagram

[0023] Figure 1 is a schematic diagram of a portion of a memory device according to some embodiments of the present disclosure. Figure 2 is a table of thermometer codes with ranges for stored data, illustrated according to some embodiments of this case. Figures 3A to 3E are schematic diagrams illustrating a memory device performing a search operation according to some embodiments of this case. Figure 4 is a schematic diagram illustrating various values ​​and encoding ranges of stored data according to some embodiments of this case. Figure 5A is a schematic diagram of a memory system according to some embodiments of the present invention. Figure 5B is a schematic diagram illustrating further details of a memory system according to some embodiments of the present invention. Figure 5C is a schematic diagram illustrating further details of the query information according to some embodiments of this case. Figure 5D is a schematic diagram illustrating further details of a memory string according to some embodiments of this case. Implementation

[0024] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as "first," "second," etc., are used herein to describe different elements, these terms are only used to distinguish elements or operations described using the same technical terminology. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply order or sequence, nor are they intended to limit the content of this disclosure.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant technical context and this disclosure, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0027] The following drawings disclose several embodiments of this disclosure. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the disclosure. That is, in some embodiments of this disclosure, these practical details are not necessary. In addition, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner.

[0028] This disclosure provides a 3D NAND artificial intelligence (AI) engine with thermometer range encoding in both single-cell (SLC) and multi-cell (MLC) architectures. Multi-cell thermometer range encoding can reduce the number of NAND cells used for the designed quantization layers in the memory string and can also extend the quantization layers of eigenvalues ​​to enhance matching capabilities for high-performance AI accelerators. Additionally, multi-cell thermometer range encoding can also improve the efficiency of NAND arrays used for large database storage.

[0029] Figure 1 is a schematic diagram of a portion of a memory device 100 according to some embodiments of the present disclosure. In some embodiments, the memory device 100 may include a plurality of memory strings, such as memory string MS1. Memory string MS1 is used to store stored data SDT1 and to compare input data IDT1 and stored data SDT1 to generate a string current signal IS1. In some embodiments, stored data SDT1 may be implemented by storing feature data, and input data IDT1 may be implemented by input feature data.

[0030] As shown in Figure 1, the memory string MS1 includes multiple switching elements, such as switching elements T1 to T192. In some embodiments, switching elements T1 to T192 are connected in series and arranged sequentially. In some embodiments, switching elements T1 to T192 are respectively located in a memory layer of layer 192 and can be implemented by an MLC. In other words, the memory string MS1 can be implemented by an MLC of layer 192. The control terminals of switching elements T1 to T192 are respectively used to receive character line signals WL1 to WL192. However, the embodiments disclosed herein are not limited to this. In various embodiments, the memory device 100 may include various numbers of memory layers. In other words, 192 may be replaced by other positive integers.

[0031] In some embodiments, two adjacent switching elements can operate as a memory unit. Specifically, switching elements T1 and T2 can operate as memory unit MC1. Switching elements T3 and T4 can operate as memory unit MC2. Switching elements T5 and T6 can operate as memory unit MC3. Switching elements T7 and T8 can operate as memory unit MC4, and so on. Switching elements T187 and T188 can operate as memory unit MC94. Switching elements T189 and T190 can operate as memory unit MC95. Switching elements T191 and T192 can operate as memory unit MC96.

[0032] In summary, the memory string MS1 comprises 96 memory units MC1 to MC96 that are connected in series and arranged sequentially. In some embodiments, the stored data SDT1 comprises 96 stored data bits SDB1 to SDB96. The memory units MC1 to MC96 are used to store the stored data bits SDB1 to SDB96, respectively.

[0033] In the embodiment where the memory string MS1 is implemented using MLC, each of the stored data bits SDB1 to SDB96 can have a logic value of 0, 1, 2, or 3. When the stored data bit has a logic value of 0, the two switching elements in the corresponding memory cell have threshold voltage levels VT4 and VT1, respectively. When the stored data bit has a logic value of 1, the two switching elements in the corresponding memory cell have threshold voltage levels VT3 and VT2, respectively. When the stored data bit has a logic value of 2, the two switching elements in the corresponding memory cell have threshold voltage levels VT2 and VT3, respectively. When the stored data bit has a logic value of 3, the two switching elements in the corresponding memory cell have threshold voltage levels VT1 and VT4, respectively. When the stored data bit has a negligible logic value X, each of the two switching elements in the corresponding memory cell has a threshold voltage level VT1.

[0034] For example, for memory cell MC1, when the stored data bit SDB1 has a logic value of 0, switching elements T1 and T2 have threshold voltage levels VT4 and VT1, respectively. When the stored data bit SDB1 has a logic value of 1, switching elements T1 and T2 have threshold voltage levels VT3 and VT2, respectively. When the stored data bit SDB1 has a logic value of 2, switching elements T1 and T2 have threshold voltage levels VT2 and VT3, respectively. When the stored data bit SDB1 has a logic value of 3, switching elements T1 and T2 have threshold voltage levels VT1 and VT4, respectively. When the stored data bit SDB1 has a negligible logic value X, each of switching elements T1 and T2 has a threshold voltage level VT1. The configuration of each of memory cells MC2 to MC96 can be similar to the configuration of memory cell MC1 described above.

[0035] In some embodiments, the negligible logic value X refers to any logic value stored. The negligible logic value X can represent different logic values. In the embodiment shown in Figure 1, the negligible logic value X can represent any logic value from 0 to 3. In some embodiments, the critical voltage level VT1 is less than the critical voltage level VT2. The critical voltage level VT2 is less than the critical voltage level VT3. The critical voltage level VT3 is less than the critical voltage level VT4.

[0036] On the other hand, the input data IDT1 contains 96 input data bits IDB1 to IDB96. Two character line signals from character line signals WL1 to WL192 are used to carry one of the corresponding input data bits IDB1 to IDB96. Specifically, character line signals WL1 and WL2 carry input data bit IDB1. Character line signals WL3 and WL4 carry input data bit IDB2, and so on. Character line signals WL191 and WL192 carry input data bit IDB96.

[0037] In some embodiments, each of the input data bits IDB1 to IDB96 can have a logic value of 0, 1, 2, or 3. When an input data bit has a logic value of 0, the corresponding two word line signals have voltage levels VS1 and VS4, respectively. When an input data bit has a logic value of 1, the corresponding two word line signals have voltage levels VS2 and VS3, respectively. When an input data bit has a logic value of 2, the corresponding two word line signals have voltage levels VS3 and VS2, respectively. When an input data bit has a logic value of 3, the corresponding two word line signals have voltage levels VS4 and VS1, respectively. When an input data bit has a wildcard logic value W, each of the corresponding two word line signals has a voltage level VS4.

[0038] For example, when the input data bit IDB1 has a logic value of 0, the two word line signals WL1 and WL2 have voltage levels VS1 and VS4, respectively. When the input data bit IDB1 has a logic value of 1, the word line signals WL1 and WL2 have voltage levels VS2 and VS3, respectively. When the input data bit IDB1 has a logic value of 2, the word line signals WL1 and WL2 have voltage levels VS3 and VS2, respectively. When the input data bit IDB1 has a logic value of 3, the word line signals WL1 and WL2 have voltage levels VS4 and VS1, respectively. When the input data bit IDB1 has a wildcard logic value W, each of the word line signals WL1 and WL2 has a voltage level VS4. The configuration of each of the word line signals WL3 to WL192 can be similar to the configuration of the word line signals WL1 and WL2 described above.

[0039] In some embodiments, the wildcard logic value W refers to any logic value at input. The wildcard logic value W can represent different logic values. In the embodiment shown in Figure 1, the wildcard logic value W can represent any logic value from 0 to 3.

[0040] In some embodiments, voltage level VS1 is between critical voltage levels VT1 and VT2. Voltage level VS2 is between critical voltage levels VT2 and VT3. Voltage level VS3 is between critical voltage levels VT3 and VT4. Voltage level VS4 is greater than critical voltage level VT4.

[0041] In other words, when the switching element has a critical voltage level VT1, the switching element is turned on in response to any of the voltage levels VS1 to VS4 at its control terminal. When the switching element has a critical voltage level VT2, the switching element is turned on in response to any of the voltage levels VS2 to VS4 at its control terminal, and turned off in response to any of the voltage levels VS1 at its control terminal. When the switching element has a critical voltage level VT3, the switching element is turned on in response to any of the voltage levels VS3 to VS4 at its control terminal, and turned off in response to any of the voltage levels VS1 to VS2 at its control terminal. When the switching element has a critical voltage level VT4, the switching element is turned on in response to any of the voltage levels VS4 at its control terminal, and turned off in response to any of the voltage levels VS1 to VS3 at its control terminal.

[0042] Figure 2 is a table 200 illustrating a range of thermometer codes for stored data according to some embodiments of this invention. The thermometer codes shown in Table 200 can be used for SLC and MLC. In various embodiments, the stored data described in this disclosure can be implemented by various types of stored data, such as image-type or voice-type stored data.

[0043] Please refer to Figures 1 and 2. Table 200 illustrates the relationship between the various encoding ranges of stored data SDT1 and the corresponding logical values ​​of stored data bits SDB1 to SDB96. For each encoding range, stored data SDT1 can have various values. In some embodiments, the values ​​of the aforementioned stored data SDT1 can be referred to as the quantized values ​​of stored data SDT1.

[0044] As shown in Table 200, when the value of stored data SDT1 is equal to 0, each of the stored data bits SDB1 to SDB96 has a logic value of 0. When stored data SDT1 has an encoding range of 1 to 3, the value of stored data SDT1 can be equal to any value in the encoding range of 1 to 3. Correspondingly, stored data bit SDB96 has a logic value of 1, each of stored data bits SDB95 and SDB94 has a negligible logic value X, and each of stored data bits SDB1 to SDB93 has a logic value of 0.

[0045] When the stored data SDT1 has an encoding range of 2 to 6, the value of the stored data SDT1 can be equal to any value in the encoding range of 2 to 6. Correspondingly, each of the stored data bits SDB95 and SDB96 has a logic value of 1, each of the stored data bits SDB91 to SDB94 has a negligible logic value X, and each of the stored data bits SDB1 to SDB90 has a logic value of 0.

[0046] When the stored data SDT1 has an encoding range of 3 to 8, the value of the stored data SDT1 can be equal to any value in the encoding range of 3 to 8. Correspondingly, each of the stored data bits SDB94 to SDB96 has a logic value of 1, each of the stored data bits SDB89 to SDB93 has a negligible logic value X, and each of the stored data bits SDB1 to SDB88 has a logic value of 0.

[0047] When the stored data SDT1 has an encoding range of 93 to 95, the value of the stored data SDT1 can be equal to any value in the encoding range of 93 to 95. Correspondingly, each of the stored data bits SDB4 to SDB96 has a logic value of 1, each of the stored data bits SDB2 to SDB3 has a negligible logic value X, and the stored data bit SDB1 has a logic value of 0.

[0048] When the stored data SDT1 has an encoding range of 88 to 96, the value of the stored data SDT1 can be equal to any value in the encoding range of 88 to 96. Correspondingly, each of the stored data bits SDB9 to SDB96 has a logic value of 1, and each of the stored data bits SDB1 to SDB8 has a negligible logic value X.

[0049] In summary, for stored data SDT1 with a value less than 96, the minimum value within the encoding range equals the number of stored data bits with a logic value of 1. For example, when stored data SDT1 has an encoding range of 3 to 8, the minimum value within this range is 3, where 3 equals the number of stored data bits SDB94 to SDB96 with a logic value of 1. Similarly, when stored data SDT1 has an encoding range of 88 to 96, the minimum value within this range is 88, where 88 equals the number of stored data bits SDB9 to SDB96 with a logic value of 1.

[0050] Furthermore, the size of the encoding range is equal to the number of stored data bits with negligible logical values ​​X. In some embodiments, the size of the encoding range refers to the difference between the maximum and minimum values ​​within the encoding range. For example, when stored data SDT1 has an encoding range of 3 to 8, the difference between the maximum value 8 and the minimum value 3 within the encoding range of 3 to 8 is equal to 5, where 5 is equal to the number of stored data bits SDB89 to SDB93 with negligible logical values ​​X. As another example, when stored data SDT1 has an encoding range of 88 to 96, the difference between the maximum value 96 and the minimum value 88 within the encoding range of 88 to 96 is equal to 8, where 8 is equal to the number of stored data bits SDB1 to SDB8 with negligible logical values ​​X.

[0051] Next, referring again to Table 200, when the stored data SDT1 has an encoding range of 88~99, the value of the stored data SDT1 can be equal to any value in the encoding range of 88~99. Correspondingly, each of the stored data bits SDB9~SDB93 has a logic value of 1, and each of the stored data bits SDB94~SDB96 and SDB1~SDB8 has a negligible logic value X.

[0052] When the stored data SDT1 has an encoding range of 98 to 100, the value of the stored data SDT1 can be equal to any value in the encoding range of 98 to 100. Correspondingly, each of the stored data bits SDB95 to SDB96 has a logic value of 2, each of the stored data bits SDB93 to SDB94 has a negligible logic value X, and each of the stored data bits SDB1 to SDB92 has a logic value of 1.

[0053] When the stored data SDT1 has an encoding range of 99 to 108, the value of the stored data SDT1 can be equal to any value in the encoding range of 99 to 108. Correspondingly, each of the stored data bits SDB94 to SDB96 has a logic value of 2, each of the stored data bits SDB85 to SDB93 has a negligible logic value X, and each of the stored data bits SDB1 to SDB84 has a logic value of 1.

[0054] When the stored data SDT1 has an encoding range of 184~191, the value of the stored data SDT1 can be equal to any value in the encoding range of 184~191. Correspondingly, each of the stored data bits SDB9~SDB96 has a logic value of 2, each of the stored data bits SDB2~SDB8 has a negligible logic value X, and the stored data bit SDB1 has a logic value of 1.

[0055] When the stored data SDT1 has an encoding range of 190 to 192, the value of the stored data SDT1 can be equal to any value in the encoding range of 190 to 192. Correspondingly, each of the stored data bits SDB3 to SDB96 has a logic value of 2, and each of the stored data bits SDB1 to SDB2 has a negligible logic value X.

[0056] In summary, for stored data SDT1 with a value less than 192, the more stored data bits with logical values ​​of 2, the larger the minimum value in the encoding range. For example, when stored data SDT1 has an encoding range of 99~108, the minimum value in the encoding range of 99~108 is 99, and the number of stored data bits SDB94~SDB96 with logical values ​​of 2 is equal to 3. When stored data SDT1 has an encoding range of 184~191, the minimum value in the encoding range of 184~191 is 184, and the number of stored data bits SDB9~SDB96 with logical values ​​of 2 is equal to 88.

[0057] When the stored data SDT1 has an encoding range of 193 to 196, the value of the stored data SDT1 can be equal to any value in the encoding range of 193 to 196. Correspondingly, the stored data bit SDB96 has a logic value of 3, each of the stored data bits SDB93 to SDB95 has a negligible logic value X, and each of the stored data bits SDB1 to SDB92 has a logic value of 2.

[0058] When the stored data SDT1 has an encoding range of 181 to 200, the value of the stored data SDT1 can be equal to any value in the encoding range of 181 to 200. Correspondingly, each of the stored data bits SDB89 to SDB96 and SDB1 to SDB11 has a negligible logical value X, and each of the stored data bits SDB12 to SDB88 has a logical value 2.

[0059] When the stored data SDT1 has an encoding range of 194~286, the value of the stored data SDT1 can be equal to any value in the encoding range of 194~286. Correspondingly, each of the stored data bits SDB95~SDB96 has a logic value of 3, each of the stored data bits SDB3~SDB94 has a negligible logic value X, and each of the stored data bits SDB1~SDB2 has a logic value of 2.

[0060] When the stored data SDT1 has an encoding range of 285 to 287, the value of the stored data SDT1 can be equal to any value in the encoding range of 285 to 287. Correspondingly, each of the stored data bits SDB4 to SDB96 has a logic value of 3, each of the stored data bits SDB2 to SDB3 has a negligible logic value X, and the stored data bit SDB1 has a logic value of 2.

[0061] When the stored data SDT1 has an encoding range of 286 to 288, the value of the stored data SDT1 can be equal to any value in the encoding range of 286 to 288. Correspondingly, each of the stored data bits SDB3 to SDB96 has a logic value of 3, and each of the stored data bits SDB1 to SDB2 has a negligible logic value X.

[0062] In summary, for stored data SDT1 with a value less than 288, the more stored data bits with logic 3, the larger the minimum value in the encoding range. For example, when stored data SDT1 has an encoding range of 194~286, the minimum value in the encoding range of 194~286 is 194, and the number of stored data bits SDB95~SDB96 with logic 3 is equal to 2. When stored data SDT1 has an encoding range of 286~288, the minimum value in the encoding range of 286~288 is 286, and the number of stored data bits SDB3~SDB96 with logic 3 is equal to 94.

[0063] Referring to Figures 1 and 2, in various embodiments, the memory device 100 can be implemented using a variety of memory layers, and the stored data SDT1 can have corresponding quantization values. For example, when the memory device 100 is implemented using a 48-layer MLC 3D cubic IMS, the stored data SDT1 can have quantization values ​​from 0 to 72. When the memory device 100 is implemented using a 96-layer MLC 3D cubic IMS, the stored data SDT1 can have quantization values ​​from 0 to 144. When the memory device 100 is implemented using a 192-layer MLC 3D cubic IMS, the stored data SDT1 can have quantization values ​​from 0 to 288. In summary, as the number of layers in the memory device 100 increases, the range of quantization values ​​increases, resulting in a corresponding increase in bit resolution.

[0064] In some embodiments, the input data IDT1 also has a thermometer code. Similar to the stored data SDT1, the input data IDT1 may also have an encoding range. The size of the encoding range of the input data IDT1 is equal to the number of input data bits with a wildcard logic value W. For various encoding ranges, the input data IDT1 may have various values. In some embodiments, the value of the input data IDT1 described above may be referred to as the quantized value of the input data IDT1.

[0065] In an embodiment where the memory string MS1 is implemented using a 192-layer MLC, the value of the input data IDT1 can be from 0 to 288. When the value of the input data IDT1 is less than or equal to 96, the value of the input data IDT1 is equal to the number of input data bits with a logic value of 1 in IDB1~IDB96. When the value of the input data IDT1 is less than or equal to 192, the value of the input data IDT1 is proportional to the number of input data bits with a logic value of 2 in IDB1~IDB96. When the value of the input data IDT1 is less than or equal to 288, the value of the input data IDT1 is proportional to the number of input data bits with a logic value of 3 in IDB1~IDB96.

[0066] Figure 3A is a schematic diagram illustrating a search operation of a memory device 100 according to some embodiments of this invention. In the embodiment shown in Figure 3A, the value of input data IDT1 is equal to 288. In other words, each of the input data bits IDB1 to IDB96 has a logic value of 3. Correspondingly, the word line signals WL1 to WL192 have voltage levels VS1, VS4, VS1, VS4, ..., VS1, VS4, VS1 and VS4, respectively.

[0067] On the other hand, the stored data SDT1 has an encoding range of 286 to 288. In other words, each of the stored data bits SDB3 to SDB96 has a logic value of 3, and each of the stored data bits SDB1 to SDB2 has a negligible logic value X. Correspondingly, each of the switching elements T1 to T4 has a critical voltage level VT1, and the switching elements T5 to T192 have critical voltage levels VT1, VT4, VT1, VT4, ..., VT1, VT4, VT1, and VT4, respectively.

[0068] In response to the aforementioned distribution of voltage levels of the character line signal and critical voltage levels of the switching elements, each of the switching elements T1 to T192 is turned on. Correspondingly, the character string current signal IS1 has a current level ISL1, wherein the current level ISL1 is greater than the zero current level.

[0069] In some embodiments, when the string current signal IS1 has a current level ISL1, the memory device 100 can determine that the stored data SDT1 matches the input data IDT1. In other words, in response to the value 288 of the input data IDT1 being included in the encoding range 286 to 288 of the stored data SDT1, the memory string MS1 generates a string current signal IS1 with a current level ISL1, so that the memory device 100 can determine that the stored data SDT1 matches the input data IDT1.

[0070] Figure 3B is a schematic diagram illustrating a search operation of the memory device 100 according to some embodiments of this case. Please refer to Figures 3B and 3A. The scenario shown in Figure 3B is a variation of the scenario shown in Figure 3A. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0071] Compared to the scenario shown in Figure 3A, in the embodiment shown in Figure 3B, the value of input data IDT1 is equal to 285. In other words, each of the input data bits IDB4~IDB96 has a logic value of 3, and each of the input data bits IDB1~IDB3 has a logic value of 2. Correspondingly, the word line signals WL7~WL192 have voltage levels VS1, VS4, VS1, VS4, ..., VS1, VS4, VS1 and VS4, respectively, and the word line signals WL1~WL6 have voltage levels VS2, VS3, VS2, VS3, VS2 and VS3, respectively.

[0072] At this time, in response to the word line signal WL6 having a voltage level VS3 and the switching element T6 having a critical voltage level VT4, the switching element T6 is turned off. Correspondingly, the word string current signal IS1 has a current level ISL0 that is less than the current level ISL1. In some embodiments, the current level ISL0 is equal to the zero current level.

[0073] In some embodiments, when the string current signal IS1 has a current level ISL0, the memory device 100 can determine that the stored data SDT1 does not match the input data IDT1. In other words, in response to the value 285 of the input data IDT1 being outside the encoding range 286-288 of the stored data SDT1, the memory string MS1 generates a string current signal IS1 with a current level ISL0, so that the memory device 100 can determine that the stored data SDT1 does not match the input data IDT1.

[0074] Figure 3C is a schematic diagram illustrating a search operation of a memory device 100 according to some embodiments of this invention. In the embodiment shown in Figure 3C, input data IDT1 has an encoding range of 286 to 288. In other words, each of the input data bits IDB3 to IDB96 has a logic value of 3, and each of the input data bits IDB1 to IDB2 has a wildcard logic value W. Correspondingly, each of the word line signals WL1 to WL4 has a voltage level VS4, and the word line signals WL5 to WL192 have voltage levels VS1, VS4, VS1, VS4, ..., VS1, VS4, VS1 and VS4, respectively.

[0075] On the other hand, the value of stored data SDT1 is equal to 288. In other words, each of the stored data bits SDB1 to SDB96 has a logic value of 3. Correspondingly, the switching elements T1 to T192 have threshold voltage levels VT1, VT4, VT1, VT4, ..., VT1, VT4, VT1 and VT4, respectively.

[0076] In response to the aforementioned distribution of voltage levels of the character line signal and critical voltage levels of the switching elements, each of the switching elements T1 to T192 is turned on. Correspondingly, the character string current signal IS1 has a current level ISL1. In other words, in response to the value 288 of the stored data SDT1 being contained within the encoding range 286 to 288 of the input data IDT1, the memory character string MS1 generates a character string current signal IS1 with a current level ISL1, enabling the memory device 100 to determine that the stored data SDT1 matches the input data IDT1.

[0077] Figure 3D is a schematic diagram illustrating a search operation of the memory device 100 according to some embodiments of this case. Please refer to Figures 3D and 3C. The scenario shown in Figure 3D is a variation of the scenario shown in Figure 3C. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0078] Compared to the scenario shown in Figure 3C, in the embodiment shown in Figure 3D, the input data IDT1 has an encoding range of 285~288. In other words, each of the input data bits IDB4~IDB96 has a logic value of 3, and each of the input data bits IDB1~IDB3 has a wildcard logic value W. Correspondingly, each of the word line signals WL1~WL6 has a voltage level VS4, and the word line signals WL7~WL192 have voltage levels VS1, VS4, VS1, VS4, ..., VS1, VS4, VS1 and VS4, respectively.

[0079] In response to the aforementioned distribution of voltage levels of the character line signal and critical voltage levels of the switching elements, each of the switching elements T1 to T192 is turned on. Correspondingly, the character string current signal IS1 has a current level ISL1. In other words, in response to the value 288 of the stored data SDT1 being contained within the encoding range 285 to 288 of the input data IDT1, the memory character string MS1 generates a character string current signal IS1 with a current level ISL1, enabling the memory device 100 to determine that the stored data SDT1 matches the input data IDT1.

[0080] Figure 3E is a schematic diagram illustrating a search operation of the memory device 100 according to some embodiments of this case. Please refer to Figures 3E and 3C. The scenario shown in Figure 3E is a variation of the scenario shown in Figure 3C. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0081] Compared to the scenario shown in Figure 3C, in the embodiment shown in Figure 3E, the input data IDT1 has an encoding range of 285~287. In other words, each of the input data bits IDB4~IDB96 has a logic value of 3, each of the input data bits IDB2~IDB3 has a wildcard logic value W, and the input data bit IDB1 has a logic value of 2. Correspondingly, each of the character line signals WL3~WL6 has a voltage level VS4, the character line signals WL1~WL2 have voltage levels VS2 and VS3 respectively, and the character line signals WL7~WL192 have voltage levels VS1, VS4, VS1, VS4, ..., VS1, VS4, VS1 and VS4 respectively.

[0082] At this time, in response to the word line signal WL2 having a voltage level VS3 and the switching element T2 having a critical voltage level VT4, the switching element T2 is turned off. Correspondingly, the string current signal IS1 has a current level ISL0. In other words, in response to the stored data SDT1 value 288 being outside the encoding range 285~287 of the input data IDT1, the memory string MS1 generates a string current signal IS1 with a current level ISL0, so that the memory device 100 can determine that the stored data SDT1 does not match the input data IDT1.

[0083] Figure 4 is a schematic diagram 400 illustrating various values ​​and encoding ranges of stored data SDT1 according to some embodiments of this invention. In the embodiment shown in Figure 4, the memory device 100 is implemented using a 48-layer three-level cell (TLC). Correspondingly, the stored data SDT1 includes stored data bits SDB1 to SDB24. Each of the stored data bits SDB1 to SDB24 can have any logic value from 0 to 7. The stored data bits SDB1 to SDB24 can also have a negligible logic value X, wherein the negligible logic value X can represent any logic value from 0 to 7.

[0084] As shown in Figure 4, when the value of stored data SDT1 is equal to 0, each of the stored data bits SDB1 to SDB24 has a logic value of 0. When stored data SDT1 has an encoding range of 1 to 3, each of the stored data bits SDB1 to SDB21 has a logic value of 0, each of the stored data bits SDB22 to SDB23 has a negligible logic value X, and the stored data bit SDB24 has a logic value of 1.

[0085] When the stored data SDT1 has an encoding range of 22 to 24, each of the stored data bits SDB1 to SDB2 has a negligible logical value X, and each of the stored data bits SDB3 to SDB24 has a logical value 1. When the value of the stored data SDT1 is equal to 25, each of the stored data bits SDB1 to SDB23 has a logical value 1, and the stored data bit SDB24 has a logical value 2.

[0086] When the value of stored data SDT1 is equal to 26, each of the stored data bits SDB1~SDB22 has a logic value of 1, and each of the stored data bits SDB23~SDB24 has a logic value of 2. When stored data SDT1 has an encoding range of 45~48, each of the stored data bits SDB1~SDB3 has a negligible logic value X, and each of the stored data bits SDB4~SDB24 has a logic value of 1.

[0087] When the value of stored data SDT1 is equal to 142, each of the stored data bits SDB1~SDB2 has a logic value of 5, and each of the stored data bits SDB3~SDB24 has a logic value of 6. When the value of stored data SDT1 is equal to 143, the stored data bit SDB1 has a logic value of 5, and each of the stored data bits SDB2~SDB24 has a logic value of 6.

[0088] When the value of stored data SDT1 is equal to 144, each of the stored data bits SDB1 to SDB24 has a logic value of 6. When the value of stored data SDT1 is equal to 145, the stored data bit SDB24 has a logic value of 7, and each of the stored data bits SDB1 to SDB23 has a logic value of 6.

[0089] When the stored data SDT1 has an encoding range of 143~146, each of the stored data bits SDB1 and SDB23~SDB24 has a negligible logical value X, and each of the stored data bits SDB2~SDB22 has a logical value 6. When the value of stored data SDT1 is equal to 147, each of the stored data bits SDB22~SDB24 has a logical value 7, and each of the stored data bits SDB1~SDB21 has a logical value 6. When the value of stored data SDT1 is equal to 168, each of the stored data bits SDB1~SDB24 has a logical value 7.

[0090] Figure 5A is a schematic diagram of a memory system 500 according to some embodiments of the present invention. As shown in Figure 5A, the memory system 500 includes a memory device 510, a sensing device 520, a temporary storage device 530, and an output device 540.

[0091] In some embodiments, memory device 510 is used to generate bit line signals BL1~BL128K, where K equals one thousand. Sensing device 520 may include a page buffer and a sensing amplifier, and is used to sense the search results corresponding to the bit line signals BL1~BL128K. Temporary storage device 530 may include a cache and a priority encoder. Output device 540 is used to output the pairing results of memory device 510.

[0092] In some embodiments, the processing of bit line signals by the temporary storage device 530 includes AND logic, OR logic, and counting logic processing, and may also include a combination of the above three logics. Referring to Figures 1 to 5A, the temporary storage device 530 can receive sensing results from memory devices 100 and / or 510, and control the sorting (which may be serial or parallel) and combine the sensing results to generate an overall search result as the pairing result output by the output device 540.

[0093] In some embodiments, the temporary storage device 530 is further used to perform priority encoding on the search results corresponding to the bit line signals BL1 to BL128K. For example, the temporary storage device 530 integrates the search results corresponding to the bit line signals BL1 to BL128K and preferentially selects the address of the bit line signal corresponding to the best search result (that is, the value of the input data and the value of the stored data are closest to each other).

[0094] Figure 5B is a schematic diagram illustrating further details of a memory system 500 according to some embodiments of the present invention. As shown in Figure 5B, the memory device 510 includes a plurality of text chunks TC1 to TC128K. The text chunks TC1 to TC128K are used to generate bit line signals BL1 to BL128K and transmit the bit line signals BL1 to BL128K to the sensing device 520. However, the embodiments disclosed herein are not limited thereto. In various embodiments, the memory device 510 may include a variety of numbers of text chunks. In other words, 128K may be replaced with other positive integers.

[0095] In some embodiments, each of the text blocks TC1 to TC128K contains multiple memory strings. For example, text block TC1 contains memory strings MS1_1 to MS1_384. Text block TC2 contains memory strings MS2_1 to MS2_384, and so on. Text block TC128K contains memory strings MS128K_1 to MS128K_384. However, the embodiments disclosed herein are not limited to this. In various embodiments, the text blocks may contain various numbers of memory strings. In other words, 384 may be replaced with other positive integers.

[0096] Please refer to Figures 1 and 5B. The configuration of each memory string MS1_1 to MS128K_384 is similar to that of memory string MS1. For example, the encoding method of each memory string MS1_1 to MS128K_384 can be similar to the encoding methods shown in Figures 3A to 3E. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0097] As shown in Figure 5B, each of the memory strings MS1_1 to MS128K_384 is used to receive the ground select line signal GSL. Each of the memory strings MS1_1 to MS128K_1 is used to receive the string select line signal SSL1. Each of the memory strings MS1_2 to MS128K_2 is used to receive the string select line signal SSL2, and so on. Each of the memory strings MS1_383 to MS128K_383 is used to receive the string select line signal SSL383. Each of the memory strings MS1_384 to MS128K_384 is used to receive the string select line signal SSL384.

[0098] In some embodiments, memory strings MS1_1 to MS1_384 are used to store stored data SDT1_1 to SDT1_384, respectively. Memory strings MS2_1 to MS2_384 are used to store stored data SDT2_1 to SDT2_384, and so on. Memory strings MS128K_1 to MS128K_384 are used to store stored data SDT128K_1 to SDT128K_384, respectively. Details regarding the stored data and memory strings are further explained in the following embodiments relating to Figure 5D.

[0099] On the other hand, each of the text blocks TC1~TC128K is used to receive the query data QDT to compare the query data QDT with the corresponding stored data. Specifically, the query data QDT includes the input data IDT1~IDT384. Details regarding the query data QDT are further explained in the following embodiment relating to Figure 5C.

[0100] In some embodiments, memory strings MS1_1 to MS128K_1 are used to compare input data IDT1 and stored data SDT1_1 to SDT128K_1 to generate corresponding string current signals. Memory strings MS1_2 to MS128K_2 are used to compare input data IDT2 and stored data SDT1_2 to SDT128K_2 to generate corresponding string current signals, and so on. Memory strings MS1_383 to MS128K_383 are used to compare input data IDT383 and stored data SDT1_383 to SDT128K_383 to generate corresponding string current signals. Memory strings MS1_384 to MS128K_384 are used to compare input data IDT384 and stored data SDT1_384 to SDT128K_384 to generate corresponding string current signals.

[0101] Next, memory strings MS1_1~MS1_384 are used to sum the corresponding string current signals to generate bit line signal BL1. Memory strings MS2_1~MS2_384 are used to sum the corresponding string current signals to generate bit line signal BL2, and so on. Memory strings MS128K_1~MS128K_384 are used to sum the corresponding string current signals to generate bit line signal BL128K.

[0102] Figure 5C is a schematic diagram illustrating further details of a query data QDT according to some embodiments of the present invention. As shown in Figure 5C, the query data QDT can be carried by character line signals.

[0103] Specifically, character line signals WL1_1 to WL192_1 are used to carry input data IDT1. Character line signals WL1_2 to WL192_2 are used to carry input data IDT2, and so on. Character line signals WL1_200 to WL192_200 are used to carry input data IDT200. Character line signals WL1_384 to WL192_384 are used to carry input data IDT384.

[0104] Please refer to Figures 3A to 3E and Figure 5C. The relationships between character line signals WL1_1~WL192_1 and input data IDT1, the relationships between character line signals WL1_200~WL192_200 and input data IDT200, and the relationships between character line signals WL1_384~WL192_384 and input data IDT384 are similar to the relationships between character line signals WL1~WL192 and input data IDT1. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0105] In the embodiment shown in Figure 5C, the input data IDT1 includes input data bits IDB1_1 to IDB1_96. Character line signals WL1_1 and WL2_1 are used to carry input data bit IDB1_1. Character line signals WL3_1 and WL4_1 are used to carry input data bit IDB1_2, and so on. Character line signals WL185_1 and WL186_1 are used to carry input data bit IDB1_93. Character line signals WL187_1 and WL188_1 are used to carry input data bit IDB1_94. Character line signals WL189_1 and WL190_1 are used to carry input data bit IDB1_95. Character line signals WL191_1 and WL192_1 are used to carry input data bit IDB1_96.

[0106] Similarly, the input data IDT200 includes input data bits IDB200_1 to IDB200_96. Character line signals WL1_200 and WL2_200 are used to carry input data bit IDB200_1. Character line signals WL3_200 and WL4_200 are used to carry input data bit IDB200_2, and so on. Character line signals WL185_200 and WL186_200 are used to carry input data bit IDB200_93. Character line signals WL187_200 and WL188_200 are used to carry input data bit IDB200_94. Character line signals WL189_200 and WL190_200 are used to carry input data bit IDB200_95. The character line signals WL191_200 and WL192_200 are used to carry the input data bits IDB200_96.

[0107] Similarly, the input data IDT384 includes input data bits IDB384_1 to IDB384_96. Character line signals WL1_384 and WL2_384 are used to carry input data bit IDB384_1. Character line signals WL3_384 and WL4_384 are used to carry input data bit IDB384_2, and so on. Character line signals WL185_384 and WL186_384 are used to carry input data bit IDB384_93. Character line signals WL187_384 and WL188_384 are used to carry input data bit IDB384_94. Character line signals WL189_384 and WL190_384 are used to carry input data bit IDB384_95. The character line signals WL191_384 and WL192_384 are used to carry the input data bits IDB384_96.

[0108] In the embodiment shown in Figure 5C, the value of input data IDT1 is equal to 3. In other words, each of the input data bits IDB1_1 to IDB1_3 has a logic value of 0, and each of the input data bits IDB1_4 to IDB1_96 has a logic value of 1. Correspondingly, the word line signals WL1_1 to WL188_1 have voltage levels VS4, VS1, VS4, VS1, ..., VS4, VS1, VS4 and VS1, respectively, and the word line signals WL189_1 to WL192_1 have voltage levels VS3, VS2, VS3 and VS2, respectively.

[0109] Additionally, the value of input data IDT200 is equal to 288. In other words, each of the input data bits IDB200_1 to IDB200_96 has a logic value of 3. Correspondingly, the word line signals WL1_200 to WL192_200 have voltage levels VS1, VS4, VS1, VS4, ..., VS1, VS4, VS1 and VS4, respectively.

[0110] Additionally, the value of input data IDT384 is equal to 191. In other words, input data bit IDB384_1 has a logic value of 1, and each of input data bits IDB384_2 to IDB384_96 has a logic value of 2. Correspondingly, word line signals WL3_384 to WL192_384 have voltage levels VS2, VS3, VS2, VS3, ..., VS2, VS3, VS2 and VS3 respectively, and word line signals WL1_384 and WL2_384 have voltage levels VS3 and VS2 respectively.

[0111] Figure 5D is a schematic diagram illustrating further details of memory strings MS1_1 to MS128K_1 according to some embodiments of the present invention. As shown in Figure 5D, memory string MS1_1 includes switching elements TG1, T1_1 to T1_192 and TS1 that are connected in series and arranged sequentially. Memory string MS2_1 includes switching elements TG2, T2_1 to T2_192 and TS2 that are connected in series and arranged sequentially, and so on. Memory string MS128K_1 includes switching elements TG128K, T128K_1 to T128K_192 and TS128K that are connected in series and arranged sequentially.

[0112] In some embodiments, each of the control terminals of switching elements TG1~TG128K is used to receive the ground selection line signal GSL. Each of the control terminals of switching elements T1_1~T128K_1 is used to receive the character line signal WL1_1. Each of the control terminals of switching elements T1_2~T128K_2 is used to receive the character line signal WL2_1. Each of the control terminals of switching elements T1_191~T128K_191 is used to receive the character line signal WL191_1. Each of the control terminals of switching elements T1_192~T128K_192 is used to receive the character line signal WL192_1.

[0113] Please refer to Figure 1 and Figure 5D. The configurations of switching elements T1_1~T1_192, T2_1~T2_192, and T128K_1~T128K_192 are similar to those of switching elements T1~T192. The configurations of character line signals WL1_1~WL192_1 are similar to those of character line signals WL1~WL192. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0114] In some embodiments, stored data SDT1_1 includes stored data bits SDB1_1_1 to SDB1_1_96. Stored data SDT2_1 includes stored data bits SDB2_1_1 to SDB2_1_96, and so on. Stored data SDT128K_1 includes stored data bits SDB128K_1_1 to SDB128K_1_96.

[0115] Correspondingly, switching elements T1_1 and T1_2 are used to store the data bit SDB1_1_1. Switching elements T1_3 and T1_4 are used to store the data bit SDB1_1_2, and so on. Switching elements T1_189 and T1_190 are used to store the data bit SDB1_1_95. Switching elements T1_191 and T1_192 are used to store the data bit SDB1_1_96.

[0116] Similarly, switching elements T2_1 and T2_2 are used to store data bit SDB2_1_1. Switching elements T2_3 and T2_4 are used to store data bit SDB2_1_2, and so on. Switching elements T2_189 and T2_190 are used to store data bit SDB2_1_95. Switching elements T2_191 and T2_192 are used to store data bit SDB2_1_96.

[0117] Similarly, switching elements T128K_1 and T128K_2 are used to store the data bit SDB128K_1_1. Switching elements T128K_3 and T128K_4 are used to store the data bit SDB128K_1_2, and so on. Switching elements T128K_189 and T128K_190 are used to store the data bit SDB128K_1_95. Switching elements T128K_191 and T128K_192 are used to store the data bit SDB128K_1_96.

[0118] In the embodiment shown in Figure 5D, the value of the stored data SDT1_1 stored in the memory string MS1_1 is equal to 3. In other words, each of the stored data bits SDB1_1_1 to SDB1_1_93 has a logic value of 0, and each of the stored data bits SDB1_1_94 to SDB1_1_96 has a logic value of 1. Correspondingly, the switching elements T1_1 to T1_186 have critical voltage levels VT4, VT1, VT4, VT1, ..., VT4, VT1, VT4 and VT1, respectively, and the switching elements T1_187 to T1_192 have critical voltage levels VT3, VT2, VT3, VT2, VT3 and VT2, respectively.

[0119] Furthermore, the value of the stored data SDT2_1 stored in the memory string MS2_1 is equal to 288. In other words, each of the stored data bits SDB2_1_1 to SDB2_1_96 has a logic value of 3. Correspondingly, the switching elements T2_1 to T2_192 have threshold voltage levels VT1, VT4, VT1, VT4, ..., VT1, VT4, VT1 and VT4, respectively.

[0120] Furthermore, the stored data SDT128K_1 stored in the memory string MS128K_1 has an encoding range of 1 to 3. In other words, each of the stored data bits SDB128K_1_1 to SDB128K_1_93 has a logic value of 0, each of the stored data bits SDB128K_1_94 to SDB128K_1_95 has a negligible logic value X, and the stored data bit SDB128K_1_96 has a logic value of 1. Correspondingly, switching elements T128K_1 to T128K_186 have critical voltage levels VT4, VT1, VT4, VT1, ..., VT4, VT1, VT4 and VT1 respectively, switching elements T128K_187 to T128K_190 each have a critical voltage level VT1, and switching elements T128K_191 to T128K_192 have critical voltage levels VT3 and VT2 respectively.

[0121] Please refer to Figures 5C and 5D. The memory string MS1_1 can compare the stored data SDT1_1 and the input data IDT1 to generate a string current signal IS1. In response to the value of the stored data SDT1_1 being equal to 3 and the value of the input data IDT1 also being equal to 3, each of the switching elements T1_1 to T1_192 is turned on, so that the string current signal IS1 has a current level ISL1.

[0122] Similarly, the memory string MS2_1 can compare the stored data SDT2_1 and the input data IDT1 to generate a string current signal IS2. In response to the stored data SDT2_1 being equal to 288 and the input data IDT1 being equal to 3, the switching element with the critical voltage level VT4 and its control terminal having the voltage level VS1 is turned off. In other words, the turn-off of each of the switching elements T2_2, T2_4, ..., T2_190 and T2_192 causes the string current signal IS2 to have a current level ISL0.

[0123] Similarly, the memory string MS128K_1 can compare the stored data SDT128K_1 and the input data IDT1 to generate a string current signal IS128K. In response to the stored data SDT128K_1 having an encoding range of 1 to 3 and the input data IDT1 having a value of 3 (that is, the value of the input data IDT1 is within the encoding range of the stored data SDT128K_1), each of the switching elements T128K_1 to T128K_192 is turned on, causing the string current signal IS128K to have a current level ISL1.

[0124] In some embodiments, the memory cell in this disclosure is referred to as an in-memory searching (IMS) cell. In various embodiments, the IMS cell may be implemented using floating gate memory, split-gate memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, floating dot memory, dynamic random-access memory (DRAM), and / or ferroelectric field-effect transistor (FeFET).

[0125] In various embodiments, the memory device in this disclosure may be implemented by various structures, such as a two-dimensional (2D) cache structure or a three-dimensional (3D) cache structure.

[0126] Although the present disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of the present disclosure. Anyone skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0127] 100, 510: Memory devices MS1: Memory string IS1: String current signal ISL1, ISL0: Current Levels T1~T192: Switching elements WL1~WL192: Character line signals MC1~MC96: Memory Units SDT1: Store data SDB1~SDB96: Storage data bits VT1~VT4: Critical voltage levels IDT1: Input Data IDB1~IDB96: Input data bits VS1~VS4: Voltage Levels X: Ignore logical value W: Wildcard logical value 400: Schematic diagram 500: Memory System 520: Sensing Device 530: Temporary storage device 540: Output device BL1~BL128K: Bit line signals TC1~TC128K: Text Blocking MS1_1~MS128K_384: Memory string SSL1~SSL384: String Select Line Signals GSL: Ground Select Line Signal QDT: Search for information IDT1~IDT384: Input Data WL1_1~WL192_384: Character line signals IDB1_1~IDB384_96: Input data bits SDT1_1~ SDT128K_1: Stored Data TG1~TG128K, T1_1~T128K_192, TS1~TS128K: Switching elements

Claims

1. A memory device comprising a memory string for storing first stored data and for comparing the first stored data with the first input data to generate a first current signal, the memory string comprising a plurality of switching elements connected in series, the switching elements comprising: a first switching element for having a first threshold voltage level when the first stored data has a first value and a second threshold voltage level when the first stored data has a first encoding range; and a second switching element for having the second threshold voltage level when the first stored data has the first value and the second threshold voltage level when the first stored data has the first encoding range, wherein the first encoding range includes at least the first value and a second value different from the first value, wherein in response to the first stored data having a second encoding range and the first input data having a third value, the first current signal has a first current level, and the second encoding range includes the third value. In response to the first stored data having the second encoding range, each of at least two switching elements in the memory string having the second critical voltage level, and the at least two switching elements being arranged sequentially.

2. The memory device as claimed in claim 1, wherein the memory string is further configured to receive a plurality of character line signals, the character line signals being configured to carry the first input data, and the first current signal having a first current level when the first input data has the first value and the first stored data has the first encoding range.

3. The memory device as claimed in claim 2, wherein when the first input data has a fourth value and the first stored data has the first encoding range, the first current signal has a second current level.

4. The memory device as claimed in claim 3, wherein the fourth value is outside the first encoding range and the second current level is less than the first current level.

5. The memory device as claimed in claim 2, wherein the control terminal of the first switching element is configured to receive a first character line signal among the character line signals, the control terminal of the second switching element is configured to receive a second character line signal among the character line signals, the first character line signal and the second character line signal respectively have a first voltage level and a second voltage level when the first input data has the first value, and each of the first character line signal and the second character line signal has the first voltage level when the first input data has the first encoding range.

6. The memory device as claimed in claim 5, wherein when the first input data has the first encoding range, a third character line signal of the character line signals has the second voltage level, when the first input data has a third encoding range, the third character line signal has the first voltage level, and the third encoding range is greater than the first encoding range.

7. The memory device as claimed in claim 6, wherein the first voltage level is greater than the second voltage level.

8. The memory device as claimed in claim 6, wherein when the first input data has a fourth encoding range, the first character line signal and the second character line signal each have a third voltage level and a fourth voltage level, and the first voltage level, the second voltage level, the third voltage level and the fourth voltage level are different from each other.

9. The memory device as claimed in claim 8, wherein each of the third voltage level and the fourth voltage level is between the first voltage level and the second voltage level.

10. The memory device as claimed in claim 8, wherein when the first input data has the fourth encoding range and the first stored data has the first value, the first current signal has a second current level.

11. The memory device as claimed in claim 10, wherein the first value is outside the fourth encoding range and the second current level is less than the first current level.

12. The memory device as claimed in claim 10, wherein the first switching element is turned off when the first input data has the fourth encoding range and the first stored data has the first value.

13. A memory device comprising a memory string for storing first stored data and for comparing the first stored data with the first input data to generate a first current signal, the memory string comprising a plurality of switching elements connected in series, the switching elements comprising: a first switching element for receiving a first word line signal, having a first threshold voltage level when the first stored data has a first value, and having a second threshold voltage level when the first stored data has a first encoding range; and a second switching element for receiving a second word line signal, having the second threshold voltage level when the first stored data has the first value, and having the second threshold voltage level when the first stored data has the first encoding range, wherein the first encoding range includes at least the first value and a second value different from the first value, wherein in response to the first stored data having a second encoding range and the first input data having a third value, the first current signal has a first current level, and the second encoding range includes the third value. In response to the first stored data having the second encoding range, each of at least two switching elements in the memory string having the second critical voltage level, and the at least two switching elements being arranged sequentially.

14. The memory device as claimed in claim 13, wherein when the first input data has the first value, the first character line signal and the second character line signal each have a first voltage level and a second voltage level, and when the first input data has the first encoding range, each of the first character line signal and the second character line signal has the first voltage level.

15. The memory device as claimed in claim 14, wherein when the first input data has a fourth value, the first word line signal and the second word line signal each have a third voltage level and a fourth voltage level, and the first voltage level, the second voltage level, the third voltage level and the fourth voltage level are different from each other.

16. The memory device as claimed in claim 15, wherein when the first input data has the fourth value and the first stored data has the first encoding range, a third switching element of the switching elements is turned off, and the fourth value is outside the first encoding range.

17. The memory device as claimed in claim 14, wherein each of the first character line signal and the second character line signal has the first voltage level when the first input data has the first encoding range.

18. A memory system comprising a plurality of text blocks, each text block being used to generate a plurality of bit-line signals, and comprising a plurality of memory strings, the memory strings comprising: a first memory string for storing first stored data, for receiving a plurality of bit-line signals carrying first input data, and for comparing the first stored data and the first input data to generate a first current signal, wherein in response to the first stored data having a first encoding range and the first input data having a first value, the first current signal has a first current level, and the first encoding range includes the first value, in response to the first stored data having the first encoding range, each of at least two switching elements in the first memory string having a first threshold voltage level, and the at least two switching elements being sequentially arranged.

19. The memory system as described in claim 18, wherein the first encoding range further includes a second value different from the first value.

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