Low power millimeter wave multi-phase inductor-coupled ring oscillator

Abstract

Multi-phase oscillator circuits are disclosed. According to one aspect, a multi-phase oscillator circuit for a millimeter wave (mmW), transceiver is provided. The multi-phase oscillator circuit includes a plurality of inductor-coupled ring oscillators, each inductor-coupled ring oscillator comprising a plurality of single stage active delay cells, an output of each of the plurality of inductor-coupled ring oscillators being inductively coupled to an output of another one of the plurality of inductor-coupled ring oscillators.

Description

[0001] LOW POWER MILLIMETER WAVE MULTI-PHASE INDUCTOR-COUPLED

[0002] RING OSCILLATOR

[0003] TECHNICAL FIELD

[0004] The present disclosure relates to wireless communications, and in particular, to low power millimeter wave (mmWave) multi-phase inductor-coupled ring oscillators.

[0005] BACKGROUND

[0006] The Third Generation Partnership Project (3GPP) has developed and is developing standards for Fourth Generation (4G) (also referred to as Long Term Evolution (LTE)) and Fifth Generation (5G) (also referred to as New Radio (NR)) wireless communication systems. Such systems provide, among other features, broadband communication between network nodes, such as base stations, and mobile wireless devices (WD), as well as communication between network nodes and between WDs. The 3GPP is also developing standards for Sixth Generation (6G) wireless communication networks.

[0007] In addition to these standards, the Institute of Electrical and Electronic Engineers (IEEE) has developed and continues to develop standards for other types of wireless communication networks, including Wireless Local Area Networks (WLANs), including Wireless Fidelity (Wi-Fi) networks and Bluetooth networks. WLANS include wireless communication between access points (APs) and non-access point stations (STAs). Such IEEE standards include IEEE 802.1 la / b / g / n / ac / ax and IEEE 802.15.

[0008] There is a trend towards using higher frequencies in wireless and cellular communications, driven by increased demands for data-rate. Large bandwidth is available in the millimeter wave frequency range and is currently being deployed in 5G cellular communication systems. While high data-rates result, the power consumption levels in the user devices becomes too high for some applications, where batteries become too large or must be re-charged more frequently than what is convenient. Therefore, there is a need for techniques for reduced power consumption in mm-wave devices. A difficulty in obtaining low power consumption in mm-wave receivers, especially in auxiliary receivers and transmitters performing tasks to aid the main transceiver, is the generation of a mm- wave multiphase local oscillator signal. To be generally useful in receivers, transmitters, and compatible with other parts of the frequency generation circuitry, the signal should preferably have an even number of phases, i.e., a differential signal property of the multiple phases, so that each generated signal has a phase that is opposite to the phase of another generated signal.

[0009] Two known solutions for a multi-phase oscillator are discussed. In one known method, a Varactor-Less Interpolative-Phase-Tuning Millimeter-Wave LC Oscillator with Multiphase Outputs is presented. Its architecture is shown in FIGS. 1 and 2 and exhibit an example of a differential ring oscillator topology, with differential LC tanks in-between each differential delay cells stage. Each differential delay cells stage includes two parallel differential stages (transistors Ml and M2 in differential stage 1) and (M3 and M4 in stage 2). The signals to differential stage 2 are phase shifted by an LC loaded differential stage (M5 and M6). By adjusting the tail current ratio of differential stage 1 and 2, their combined output current may be shifted in phase between not being phase shifted by the LC loaded differential stage, i.e., only differential stage 1 has a tail current and stage 2 has none, and the output current being fully phase shifted by the LC loaded differential stage, i.e., only differential stage 2 has a tail current and stage 1 has none. Different tail current ratios will provide phase shifts in between these extremes. By tuning the phase shift of the transconductance in this way, the phase between voltage and current in the differential LC tanks located between stages must change accordingly, corresponding to the oscillation frequency changing. As shown in FIG. 1, through the impedance Z which relates voltage to current, the phase between current and voltage of the LC-tanks is zero at the resonance frequency, and it shifts as the frequency departs from resonance. It is thus possible to tune the frequency of oscillation by tuning the ratio of the differential pair tail currents, so no variable capacitors or inductors are needed.

[0010] Scaling this design leads to high complexity: for a 6-phase oscillator as shown in FIGS. 1 and 2, for example it would contain three Gm delay cells, each with three differential active stages and two LC tanks.

[0011] Another known circuit is a Dual-Band Six-Phase Voltage-Control Oscillator, operating between 890MHz and 1080MHz and implemented in 0.18um CMOS technology. It includes two single-ended ring oscillators, each featuring three delay cells, with corresponding nodes in the two oscillators connected to each other through a phase shift cell, as depicted in FIG. 3 The corresponding nodes will then provide signals in opposite phases, and the combined oscillator may provide six symmetrical phase outputs.

[0012] Each single-ended delay cell includes a main transconductance stage, an active frequency tuning circuit and an active band switch circuit, as shown in FIG. 4 Each delay cell introduces a 120-degree phase shift from input to output. The unitary phase-shift block includes a cross-coupled pair circuit, which has two nodes with a phase difference of 180 degrees as shown in FIG. 5

[0013] The known multi-phase even-order oscillators do not exhibit performance compatible with the targeted application: sub-mW power consumption, low complexity and mmW operation.

[0014] Numerous active stages result in high power consumption (35 mW).

[0015] In some known methods, all frequency tuning, band selection and phase shift operations are implemented using active components. This increases the complexity and the power consumption. The use of active components to create the phase shift block also creates noise that may lead to unwanted jitter.

[0016] SUMMARY

[0017] A multi-phase inductor-coupled ring oscillator for a mmW beamforming circuit of a radio transceiver is disclosed. Some embodiments advantageously provide low power millimeter wave (mmWave) multi-phase inductor-coupled ring oscillators. In some embodiments, a multi-phase inductor-coupled ring oscillator includes two inductor- coupled ring oscillators. Each of the two coupled ring oscillators includes a series of simple, single-ended, single-stage active delay cells.

[0018] Some embodiments provide 6 phases separated by 60 degrees, or substantially 60 degrees, with the same oscillation amplitude, or substantially the same oscillation amplitude, at mmW frequencies. In some embodiments, a first of two inductor-coupled ring oscillators output three signals separated in phase by 120 degrees, and a second of the two inductor-coupled ring oscillators also output three signals separated by 120 degrees. In some embodiments, corresponding ones of the three output signals of the first and second inductor-coupled ring oscillators are out of phase by 180 degrees.

[0019] In some embodiments, the topology is of low complexity with a single differential inductor and 2 single stage active delay cells, per stage. This low complexity results in a sub-mW power consumption that is lower than known oscillators, enabling embodiments to be implemented in low-power systems (e.g., Wake-Up Receivers, low power sensors).

[0020] Moreover, the use of passive components to create the phase differences between the signals of the multi-phase inductor-coupled oscillators reduces the noise that would otherwise be introduced using active components to introduce the phase differences.

[0021] Some embodiments provide for dynamic coarse frequency tuning using a variable capacitor, and provide for fine-tuning using the supply voltage. The supply voltage may be dynamically reconfigured for power consumption and oscillation amplitude adjustment, enabling additional energy savings depending on performance requirements.

[0022] Having differential signals, the oscillator may be connected to differential buffers, complementary mixers, differential frequency dividers (including injection locked frequency dividers), double-balanced mixers, mixers converting single ended to differential signals, to differential power amplifiers, and parts in low power transceivers.

[0023] Having multiple phases allows the use of multiphase mixers converting to and from baseband signals in receivers and transmitters, the baseband having differential signals with different phase relations. The multiple phases may also be used in frequency generation circuitry such as in the feedback path of a phase-locked loop (PLL), or in the modulated signal generation circuitry in a transmitter.

[0024] According to one aspect, a multi-phase oscillator circuit for a millimeter wave, mmW, transceiver is provided. The multi-phase oscillator circuit includes a plurality of inductor-coupled ring oscillators, each inductor-coupled ring oscillator comprising a plurality of single stage active delay cells, an output of each of the plurality of inductor- coupled ring oscillators being inductively coupled to an output of another one of the plurality of inductor-coupled ring oscillators .

[0025] According to this aspect, in some embodiments, the multi-phase oscillator circuit includes a center tapped differential inductor configured to inductively couple outputs of a pair of inductor-coupled ring oscillators . In some embodiments, the center tap of the center tapped differential inductor is connected to a signal ground via a first capacitor. In some embodiments, the multi-phase oscillator circuit includes a second capacitor for each of the plurality of outputs, the second capacitor being configured to set a frequency of operation of the multi-phase oscillator circuit. In some embodiments, a capacitance of the second capacitor is variable. In some embodiments, the plurality of inductor-coupled ring oscillators are configured to produce signals separated by a same phase difference, or substantially a same phase difference. In some embodiments, a number of stages of each inductor-coupled ring oscillators of the plurality of inductor-coupled ring oscillators is three and the same phase difference is 60 degrees, or substantially 60 degrees. In some embodiments, the number of inductor-coupled ring oscillators is two. In some embodiments, each inductor-coupled ring oscillator includes two single-ended, single- stage active delay cells. In some embodiments, the inductively coupled outputs of two inductor-coupled ring oscillators are separated in phase by substantially 180 degrees, the phase separation being obtained using passive components. In some embodiments, the multi-phase oscillator circuit includes a variable supply voltage configured to enable tuning of the plurality of inductor-coupled ring oscillators .

[0026] According to another aspect, a multi-phase oscillator circuit includes three differential inductors and three pairs of active inverters, each active inverter of a pair having an output, the outputs of the pair of active inverters being inductively coupled by one of the three differential inductors.

[0027] According to this aspect, in some embodiments, each differential inductor is center tapped, the center tap being connected to a signal ground via a first capacitor. In some embodiments, the multi-phase oscillator circuit has, in addition to the active inverters, only passive components. In some embodiments, each active inverter is configured to have an input and output voltage operating point that is one-half of a supply voltage of the multiphase oscillator circuit. In some embodiments, each differential inductor is electrically in parallel with a corresponding resistance. In some embodiments, each differential inductor is center-tapped and each center tap is connected to a common mode resistance. In some embodiments, an output of each active inverter is coupled to a differential inductor and a variable shunt capacitance. In some embodiments, each active inverter is configured to introduce a 120 degree phase shift between an input of the active inverter and an output of the active inverter. In some embodiments, each differential inductor is configured to introduce a 180 degree phase shift between outputs of a pair of the active inverters. In some embodiments, the active inverters and differential inductors are configured in three stages, each stage being configured to provide a 60 degree phase difference between adjacent phase signals of the three stages.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] A more complete understanding of the present embodiments, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

[0030] FIG. 1 illustrates a known oscillator circuit topology;

[0031] FIG. 2 illustrates a Gm cell included in the known oscillator circuit of FIG. 1;

[0032] FIG. 3 is a known 6-phase oscillator architecture;

[0033] FIG. 4 is a known unitary single-ended delay cell;

[0034] FIG. 5 is a known unitary active phase shift cell; FIG. 6 is a schematic diagram of an example network architecture illustrating a communication system according to principles disclosed herein;

[0035] FIG. 7 is a block diagram of a network node in communication with a wireless device over a wireless connection according to some embodiments of the present disclosure;

[0036] FIG. 8 is a low power millimeter wave (mmWave) multi-phase inductor-coupled ring oscillator circuit constructed according to principles disclosed herein;

[0037] FIG. 9 is a Gm delay cell for use in a multi-phase inductor-coupled ring oscillator circuitry constructed according to principles disclosed herein;

[0038] FIG. 10 illustrates voltage waveforms at 6 different outputs of an example inductor-coupled ring oscillator circuit according to principles disclosed herein;

[0039] FIG. 11 illustrates frequency tuning using the capacitor Cm of an example inductor-coupled ring oscillator circuit constructed according to principles disclosed herein;

[0040] FIG. 12 illustrates an oscillation amplitude versus Cm of an example inductor- coupled ring oscillator circuit constructed according to principles disclosed herein;

[0041] FIG. 13 illustrates oscillator frequency versus supply voltage Vsup of an example inductor-coupled ring oscillator circuit constructed according to principles disclosed herein;

[0042] FIG. 14 illustrates oscillation amplitude versus supply voltage Vsup of an example inductor-coupled ring oscillator circuit constructed according to principles disclosed herein;

[0043] FIG. 15 illustrates combined power consumption of oscillators and buffers versus supply voltage Vsup of an example inductor-coupled ring oscillator circuit constructed according to principles disclosed herein;

[0044] FIG. 16 is an example inductor-coupled ring oscillator circuit used for simulating the common mode loop gain of a circuit disclosed herein;

[0045] FIG. 17 is another example inductor-coupled ring oscillator circuit used for simulating the differential mode loop gain of a circuit disclosed herein;

[0046] FIG. 18 illustrates the simulated common mode loop gain and differential mode loop gain versus frequency for the simulated inductor-coupled ring oscillator circuits of FIGS. 21 and 22, respectively;

[0047] FIG. 19 is an example inductor-coupled ring oscillator circuit configured with common mode resistors Rem to signal ground according to principles disclosed herein; FIG. 20 illustrates an impact of common mode resistors Rem on phase noise;

[0048] FIG. 21 is a diagram illustrating an example inductor orientation;

[0049] FIG. 22 illustrates phase differences between successive nodes versus position of inductors of an example inductor-coupled ring oscillator circuit according to principles disclosed herein;

[0050] FIG. 23 is a fixed Cm capacitor topology of an example inductor-coupled ring oscillator circuit according to principles disclosed herein;

[0051] FIG. 24 is an example inductor-coupled ring oscillator circuit configured with a number 2*N of phases and with an odd number of inverters per ring according to principles disclosed herein; and

[0052] FIG. 25 is another example inductor-coupled ring oscillator circuit configured with a number 2*N of phases and with an even number of inverters per ring according to principles disclosed herein.

[0053] DETAILED DESCRIPTION

[0054] Before describing in detail exemplary embodiments, it is noted that the embodiments reside primarily in combinations of apparatus components and processing steps related to low power millimeter wave (mmWave) multi -phase inductor-coupled ring oscillators. Accordingly, components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Like numbers refer to like elements throughout the description.

[0055] As used herein, relational terms, such as “first” and “second,” “top” and “bottom,” and the like, may be used solely to distinguish one entity or element from another entity or element without necessarily requiring or implying any physical or logical relationship or order between such entities or elements. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts described herein. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and / or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0056] In embodiments described herein, the joining term, “in communication with” and the like, may be used to indicate electrical or data communication, which may be accomplished by physical contact, induction, electromagnetic radiation, radio signaling, infrared signaling or optical signaling, for example. One having ordinary skill in the art will appreciate that multiple components may interoperate and modifications and variations are possible of achieving the electrical and data communication.

[0057] In some embodiments described herein, the term “coupled,” “connected,” and the like, may be used herein to indicate a connection, although not necessarily directly, and may include wired and / or wireless connections.

[0058] The term “network node” used herein may be any kind of network node comprised in a radio network which may further comprise any of base station (BS), radio base station, base transceiver station (BTS), base station controller (BSC), radio network controller (RNC), g Node B (gNB), evolved Node B (eNB or eNodeB), Node B, multistandard radio (MSR) radio node such as MSR BS, multi-cell / multicast coordination entity (MCE), integrated access and backhaul (IAB) node, relay node, donor node controlling relay, radio access point (AP), transmission points, transmission nodes, Remote Radio Unit (RRU) Remote Radio Head (RRH), a core network node (e.g., mobile management entity (MME), self-organizing network (SON) node, a coordinating node, positioning node, MDT node, etc.), an external node (e.g., 3rd party node, a node external to the current network), nodes in distributed antenna system (DAS), a spectrum access system (SAS) node, an element management system (EMS), etc. The network node may also comprise test equipment. The term “radio node” used herein may be used to also denote a wireless device (WD) such as a wireless device (WD) or a radio network node.

[0059] In some embodiments, the non-limiting terms wireless device (WD) or a user equipment (UE) are used interchangeably. The WD herein may be any type of wireless device capable of communicating with a network node or another WD over radio signals, such as wireless device (WD). The WD may also be a radio communication device, target device, device to device (D2D) WD, machine type WD or WD capable of machine to machine communication (M2M), low-cost and / or low-complexity WD, a sensor equipped with WD, Tablet, mobile terminals, smart phone, laptop embedded equipped (LEE), laptop mounted equipment (LME), USB dongles, Customer Premises Equipment (CPE), an Internet of Things (loT) device, or a Narrowband loT (NB-IOT) device, etc. Also, in some embodiments the generic term “radio network node” is used. It may be any kind of a radio network node which may comprise any of base station, radio base station, base transceiver station, base station controller, network controller, RNC, evolved Node B (eNB), Node B, gNB, Multi-cell / multicast Coordination Entity (MCE), IAB node, relay node, access point, radio access point, Remote Radio Unit (RRU) Remote Radio Head (RRH).

[0060] Note that although terminology from one particular wireless system, such as, for example, 3GPP LTE and / or New Radio (NR), may be used in this disclosure, this should not be seen as limiting the scope of the disclosure to only the aforementioned system. Other wireless systems, including without limitation Wide Band Code Division Multiple Access (WCDMA), Worldwide Interoperability for Microwave Access (WiMax), Ultra Mobile Broadband (UMB) and Global System for Mobile Communications (GSM), may also benefit from exploiting the ideas covered within this disclosure.

[0061] Note further, that functions described herein as being performed by a wireless device or a network node may be distributed over a plurality of wireless devices and / or network nodes. In other words, it is contemplated that the functions of the network node and wireless device described herein are not limited to performance by a single physical device and, in fact, may be distributed among several physical devices.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0063] Some embodiments include low power millimeter wave (mmWave) multi -phase inductor-coupled ring oscillators.

[0064] Referring to the drawing figures, in which like elements are referred to by like reference numerals, there is shown in FIG. 6 a schematic diagram of a communication system 10, according to an embodiment, such as a 3 GPP -type cellular network that may support standards such as LTE and / or NR (5G), which comprises an access network 12, such as a radio access network, and a core network 14. The access network 12 comprises a plurality of network nodes 16a, 16b, 16c (referred to collectively as network nodes 16), such as NBs, eNBs, gNBs or other types of wireless access points, each defining a corresponding coverage area 18a, 18b, 18c (referred to collectively as coverage areas 18). Each network node 16a, 16b, 16c is connectable to the core network 14 over a wired or wireless connection 20. A first wireless device (WD) 22a located in coverage area 18a is configured to wirelessly connect to, or be paged by, the corresponding network node 16a. A second WD 22b in coverage area 18b is wirelessly connectable to the corresponding network node 16b. While a plurality of WDs 22a, 22b (collectively referred to as wireless devices 22) are illustrated in this example, the disclosed embodiments are equally applicable to a situation where a sole WD is in the coverage area or where a sole WD is connecting to the corresponding network node 16. Note that although only two WDs 22 and three network nodes 16 are shown for convenience, the communication system may include many more WDs 22 and network nodes 16.

[0065] Also, it is contemplated that a WD 22 can be in simultaneous communication and / or configured to separately communicate with more than one network node 16 and more than one type of network node 16. For example, a WD 22 can have dual connectivity with a network node 16 that supports LTE and the same or a different network node 16 that supports NR. As an example, WD 22 can be in communication with an eNB for LTE / E-UTRAN and a gNB for NR / NG-RAN.

[0066] A network node 16 may be configured to include a network node oscillator 24 which is configured to provide multi-phase oscillations for a mmWave transceiver. The network node oscillator 24 may be configured to include a plurality of inductor-coupled ring oscillators each inductor-coupled ring oscillator comprising a plurality of single stage active delay cells, an output of each of the plurality of inductor-coupled ring oscillators being inductively coupled to an output of another one of the plurality of inductor-coupled ring oscillators. A wireless device 22 may be configured to include a WD oscillator 26 which is also configured to provide multi-phase oscillations in the same manner as the network node oscillator 24 as disclosed herein.

[0067] Example implementations, in accordance with an embodiment, of the WD 22 and network node 16 discussed in the preceding paragraphs will now be described with reference to FIG. 7 The communication system 10 includes a network node 16 provided in a communication system 10 and including hardware 28 enabling it to communicate with the WD 22. The hardware 28 may include a radio interface 30 for setting up and maintaining at least a wireless connection 32 with a WD 22 located in a coverage area 18 served by the network node 16. The radio interface 30 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and / or one or more RF transceivers. The radio interface 30 includes an array of antennas 34 to radiate and receive signal(s) carrying electromagnetic waves. Radio interface 30 of the network node 16 may include a network node oscillator 24 which is configured to provide multi -phase oscillations for a mmWave transceiver. The network node oscillator 24 may be configured to include a plurality of inductor-coupled ring oscillators each inductor- coupled ring oscillator comprising a plurality of single stage active delay cells, an output of each of the plurality of inductor-coupled ring oscillators being inductively coupled to an output of another one of the plurality of inductor-coupled ring oscillators.

[0068] In the embodiment shown, the hardware 28 of the network node 16 further includes processing circuitry 36. The processing circuitry 36 may include a processor 38 and a memory 40. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 36 may comprise integrated circuitry for processing and / or control, e.g., one or more processors and / or processor cores and / or FPGAs (Field Programmable Gate Array) and / or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processor 38 may be configured to access (e.g., write to and / or read from) the memory 40, which may comprise any kind of volatile and / or nonvolatile memory, e.g., cache and / or buffer memory and / or RAM (Random Access Memory) and / or ROM (Read-Only Memory) and / or optical memory and / or EPROM (Erasable Programmable Read-Only Memory).

[0069] Thus, the network node 16 further has software 42 stored internally in, for example, memory 40, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the network node 16 via an external connection. The software 42 may be executable by the processing circuitry 36. The processing circuitry 36 may be configured to control any of the methods and / or processes described herein and / or to cause such methods, and / or processes to be performed, e.g., by network node 16. Processor 38 corresponds to one or more processors 38 for performing network node 16 functions described herein. The memory 40 is configured to store data, programmatic software code and / or other information described herein. In some embodiments, the software 42 may include instructions that, when executed by the processor 38 and / or processing circuitry 36, causes the processor 38 and / or processing circuitry 36 to perform the processes described herein with respect to network node 16.

[0070] The communication system 10 further includes the WD 22 already referred to. The WD 22 may have hardware 44 that may include a radio interface 46 configured to set up and maintain a wireless connection 32 with a network node 16 serving a coverage area 18 in which the WD 22 is currently located. The radio interface 46 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and / or one or more RF transceivers. The radio interface 46 includes an array of antennas 48 to radiate and receive signal(s) carrying electromagnetic waves. For example, the radio interface 46 of the wireless device 22 may be configured to include a WD oscillator 26 which is also configured to provide multi-phase oscillations in the same manner as the network node oscillator 24 as disclosed herein.

[0071] The hardware 44 of the WD 22 further includes processing circuitry 50. The processing circuitry 50 may include a processor 52 and memory 54. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 50 may comprise integrated circuitry for processing and / or control, e.g., one or more processors and / or processor cores and / or FPGAs (Field Programmable Gate Array) and / or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processor 52 may be configured to access (e.g., write to and / or read from) memory 54, which may comprise any kind of volatile and / or nonvolatile memory, e.g., cache and / or buffer memory and / or RAM (Random Access Memory) and / or ROM (Read-Only Memory) and / or optical memory and / or EPROM (Erasable Programmable Read-Only Memory).

[0072] Thus, the WD 22 may further comprise software 56, which is stored in, for example, memory 54 at the WD 22, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the WD 22. The software 56 may be executable by the processing circuitry 50. The software 56 may include a client application 58. The client application 58 may be operable to provide a service to a human or non-human user via the WD 22.

[0073] The processing circuitry 50 may be configured to control any of the methods and / or processes described herein and / or to cause such methods, and / or processes to be performed, e.g., by WD 22. The processor 52 corresponds to one or more processors 52 for performing WD 22 functions described herein. The WD 22 includes memory 54 that is configured to store data, programmatic software code and / or other information described herein. In some embodiments, the software 56 and / or the client application 58 may include instructions that, when executed by the processor 52 and / or processing circuitry 50, causes the processor 52 and / or processing circuitry 50 to perform the processes described herein with respect to WD 22. In some embodiments, the inner workings of the network node 16 and WD 22 may be as shown in FIG. 7 and independently, the surrounding network topology may be that of FIG. 6.

[0074] The wireless connection 32 between the WD 22 and the network node 16 is in accordance with the teachings of the embodiments described throughout this disclosure. More precisely, the teachings of some of these embodiments may improve the data rate, latency, and / or power consumption and thereby provide benefits such as reduced user waiting time, relaxed restriction on file size, better responsiveness, extended battery lifetime, etc. In some embodiments, a measurement procedure may be provided for the purpose of monitoring data rate, latency and other factors on which the one or more embodiments improve.

[0075] Although FIGS. 6 and 7 show various “units” such as NN oscillator 24 and WD oscillator unit 26 as being within a respective radio interface, it is contemplated that these units may be implemented such that a portion of the unit is implemented within processing circuitry 36 and 50, respectively. In other words, the units may be implemented in hardware or in a combination of hardware and software within the processing circuitry and / or radio interface.

[0076] Having described the general process flow of arrangements of the disclosure and having provided examples of hardware and software arrangements for implementing the processes and functions of the disclosure, the sections below provide details and examples of arrangements for low power millimeter wave (mmWave) multi-phase inductor-coupled ring oscillators.

[0077] Proposed 6-phases inductor-coupled ring oscillator architecture

[0078] Overall architecture

[0079] In some embodiments, a multi-phase inductor-coupled ring oscillator with low complexity and sub-mW power consumption is presented. An example multi-phase inductor-coupled ring oscillator 100 configured according to principles disclosed herein is shown in FIG. 8. The example multi -phase inductor-coupled ring oscillator 100 may be implemented in the network node oscillator 24 and the WD oscillator 26. Although a 6- phase inductor-coupled ring oscillator is shown in FIG. 8, other numbers of phases may be implemented.

[0080] The multi -phase inductor-coupled ring oscillator 100 includes two single-ended ring oscillators 102 and 104, each featuring three active stages acting as delay cells 106. As shown in the example of FIG. 8, some embodiments are of low complexity and low power consumption by using as few active elements as possible.

[0081] The delay cells 106 introduce a 120-degree phase shift between their respective input and output and thus, three phases are available at the three outputs of the delay cells 106 for each ring oscillator 102 and 104.

[0082] The output node of each delay cell 106 of the ring oscillator 102 is coupled to an output of a corresponding delay cell 106 of the ring oscillator 104 using a differential inductor 108, which is a passive element. The differential inductor 108 creates a 180- degree phase shift between the output nodes of the corresponding delay cells 106 of each ring oscillator 102, 104. The use of passive elements to induce this phase shift has no impact on the power consumption and does not add significant complexity to the circuit. This is in contrast to known methods where active elements are used, which adds complexity and increases overall oscillator power consumption. By using passive inductors to tune the oscillator nodes, as disclosed herein, the multi-phase inductor- coupled ring oscillator 100 may operate at higher frequency with low power. The phase noise is also reduced compared to known ring oscillators without inductive tuning. A benefits, is that the differential inductors improve performance over a frequency band, reduce power consumption and reduce phase noise. This is achieved without significant additional circuit complexity or power consumption.

[0083] The multi -phase inductor-coupled ring oscillator 100 has six different phases available, one phase for each delay cell output of the six delay cells 106. The differential inductors 108 may have the same size and a same coupling factor k, or substantially the same size and substantially the same coupling factor k, between their primary and secondary windings. Each differential inductor 108 may have their center taps connected to the AC ground through a fixed capacitor Cmid 110.

[0084] A variable capacitor Cm 112 is placed between each active delay cell 106. The value of variable capacitor Cm 112, together with the supply voltage, may be used to set the oscillation frequency of the delay cell 106.

[0085] The resonant frequency of each LC tank is: where Cinvis the sum of the input capacitance of the loading inverter 114 and the output capacitance of the driving inverter 114, where each inverter 114 may be a loading inverter for a previous delay cell 106, and each inverter 114 may be the driving inverter for a subsequent delay cell 106. Active elements

[0086] In some embodiments, the only active elements used in this oscillator are the Gm delay cells 106 (inverters 114) shown on the left in FIG. 9. An example topology of a delay cell 106 is shown on the right in FIG. 9.

[0087] Voltage waveforms at outputs

[0088] FIG. 10 is a diagram of six different outputs of the multi -phase inductor-coupled ring oscillator 100 shown in FIG. 8. Each waveform in FIG. 10 is an output of a different delay cell 106. The delay cells 106 of the ring oscillator 102 output signals are separated by 120 degrees. The delay cells 106 of the ring oscillator 104 output signals are separated by 120 degrees. The output signals of the delay cells 106 of the ring oscillator 102 are separated from the output signals of the delay cells 106 of the ring oscillator 104 by 60 degrees. The waveforms in the example of FIG. 10 oscillate at a frequency of 29.6 GHz and have the same amplitudes, in some embodiments. Also, as noted above, outputs of corresponding delay cells 106 of ring oscillators 102 and 104 that are inductively coupled by corresponding differential inductors 108 may be separated by 180 degrees.

[0089] Oscillator Loading

[0090] Each phase of the multi -phase inductor-coupled ring oscillator 100 may be loaded with an active inverter 114 acting as a buffer The power consumption of these buffers is included in the numbers presented below.

[0091] Frequency tuning

[0092] Frequency tuning may be achieved by setting the value of the variable capacitors Cm 112.

[0093] FIG. 11 is a graph showing an example of the variation of frequency of oscillation versus capacitance values of variable capacitor Cm 112 in the range of 3fF to 15fF for an example multi-phase inductor-coupled ring oscillator 100. FIG. 12 is a graph showing an example of variation of amplitude of oscillation versus capacitance values of variable capacitor Cm 112 in the range of 3fF to 15fF for the example multi-phase inductor- coupled ring oscillator 100.

[0094] Almost constant oscillation amplitude and power consumption performances may be achievable through the covered frequency range by variation of the variable capacitor Cm 112.

[0095] The multi -phase inductor-coupled ring oscillator circuit 100 together with any buffers (not shown) loading the outputs, may consume a total power of 1.39mW, which is low compared to known solutions. Influence of VDD

[0096] FIGS. 13-15 are example graphs showing the oscillation frequency, amplitude of oscillation and the combined power consumption of the oscillator and the buffers, respectively, with respect to the supply voltage Vsup.

[0097] While Cm values of variable capacitor Cm 112 may offer coarse frequency tuning steps that may depend on a programmable capacitor resolution, the value of VDD 116 may be used to fine tune the oscillation frequency.

[0098] The frequency of operation is only slightly affected by the VDD settings in some embodiments. This means that depending on a desired performance goal, it may be possible to further reduce the power consumption, from 2.1mW to 0.8mW, by reducing VDD from 900mV to 700mV. This power consumption reduction may come at the price of a reduced peak oscillation amplitude, from 290m V to 140mV.

[0099] The VDD 116 may be then set based on performances goals to reduce the average power consumption of the overall system.

[0100] Common-mode oscillation

[0101] Typically, a concern with differential oscillators is the possibility of the oscillator starting up in common mode oscillation. To assess this risk, the following analysis may be performed. A first test bench is used to analyze the common mode loop gain: the two inverter loops are broken, and common mode AC test sources are inserted. In addition, since there should be no voltage across the differential inductors in common mode oscillation, the inductors are then shorted by a very small resistor R 118, as shown in the example schematic diagram of FIG. 16.

[0102] Another test bench may be used to measure the differential loop gain of the circuit as shown in the example schematic diagram of FIG. 17.

[0103] The results of these simulations are shown in FIG. 18. Observe that the differential mode gain is higher than 1, making the multi -phase inductor-coupled ring oscillator 100 disposed to oscillation in differential mode. Also, the common mode loop gain is much less than 1, and the circuit may not be disposed to oscillate in common mode.

[0104] In addition, the effect of introducing common mode resistors Rem 120 placed between the center node each differential inductor 108 and the AC ground may be evaluated, as shown in FIG. 19Error! Reference source not found.. These resistors Rem 120 do not contribute significantly to the phase noise since only a marginal signal current flows through these resistors when the circuit is in its regular differential mode oscillation. The presence of the common mode resistors Rem 120 has a small impact on the phase noise. As seen in FIG. 20, the two curves, one being phase noise without common mode resistors 120 and the other being phase noise with common mode resistors 120, are indistinguishable and thus appear in FIG. 1 as a single curve (e.g., one superimposed on the other).

[0105] Due to the common mode resistors Rem 120, the common mode loop gain may be reduced. Furthermore, there may be a significant reduction of ~7 dB in the 2ndharmonic distortion present in the output signal spectrum of the multi-phase inductor-coupled ring oscillator 100.

[0106] Mutual coupling among the inductors

[0107] Some embodiments may include multiple inductors in proximity to each other. Therefore, the layout of the differential inductors may be implemented so that a differential inductor 108 in one stage is not significantly affected by magnetic fields from the differential inductors 108 of the other stages. When the differential inductors 108 in various stages couple to each other, they may induce currents in affected differential inductors 108 with unwanted phase. This may result in a phase difference in successive stages that deviate from a desired phase difference between successive stages.

[0108] The coupling between the differential inductors 108 between stages depends on the distance between them, their relative orientation, and the relative direction of current flow in them. An optimal layout with differential inductors may be determined by experimentation or by simulation using an electromagnetic simulator.

[0109] The inductors may be arranged, as an example, in a triangular pattern with appropriate orientation and distance to minimize the magnetic coupling between them and create maximum symmetry. See FIG. 21. Since implementing such a layout unfortunately has some practical concerns, square shaped inductors with the center points on the vertices of an isosceles right triangle has been investigated. In the simulation, the origin of the coordinate system was placed at the center point of a long side of a triangle. The center points of the inductors, which are placed at the vertices of the triangle, will then have the same distances to the origin, i.e., lying on a circle, but not at 120 degree angle differences as would be the case for an equilateral triangle with the origin placed in its the center. The outer side of the square inductors was 68um, and the side-length of the triangle was changed (which changes the distance between inductors) to investigate the influence of inductor proximity on the phase accuracy of the oscillator for a non-symmetric layout. A harmonic balance simulation test bench may be used to find the phase difference between signals in successive nodes. This test bench may use simulated inductors that are not ideal.

[0110] As shown in Table 1, the phase error increases as the inductors come close to each other but it is small even in the case where the coils are less than one diameter away from each other. A worst-case error in Table 1 is -3.5°. See FIG. 22.

[0111] Table 1

[0112] When placed at the vertices of an equilateral triangle, the square-shaped differential inductors 108 show less coupling due to the increased symmetry of the layout. For example, in the case of 40pm distance when a coil is moved closer to a vertice of the triangle, the phase differences between nodes may be as shown in Error! Reference source not found.. As expected, the error is even smaller when the symmetry of the layout improves. With improved symmetry, the error is ~1° in the worst case, even for square shaped inductors. Layouts with improved symmetry may include inductors that are shaped with more comers, such as, for example, an octagonal shape.

[0113] Table 2.

[0114] Comparison with Known Methods

[0115] To provide a comparison with a known solution, the classical oscillator figure of merit (FOM), may be derived from the following equation:

[0116] FOM = L(Aco) - 201og(coo / Aco) + 101og(PDc / lmW) Then some embodiments achieve a FOM of -177.7 dBc / Hz. For comparison with known methods, the noise at 1MHz offset is -82.8 dBc / Hz.

[0117] An inductor Q of 10 is assumed for the 1.2nH differential inductor used in one example embodiment. Table 3 provides a comparison between performance of 7 known oscillator circuits and an embodiment of a 6-phase inductor-coupled ring oscillator 100 disclosed herein.

[0118] Table 3

[0119] In Table 3, the reference numbers refer to the following technical references:

[0120] [1], S. Rong and H. C. Luong, "Design and Analysis of Varactor-Less

[0121] Interpolative-Phase-Tuning Millimeter-Wave LC Oscillators with Multiphase Outputs," in IEEE Journal of Solid-State Circuits, vol. 46, no. 8, pp. 1810-1819, Aug. 2011, doi: 10.1109 / JSSC.2011.2155850.

[0122] [2], S.-F. Wang, Y.-W. Chang, and C.-Y. Tang, “A Novel Dual-Band Six- Phase Voltage-Control Oscillator,” Sensors, vol. 18, no. 11, p. 4025, Nov. 2018, doi: 10.3390 / sl8114025. [Online], Available: http: / / dx.doi.org / 10.3390 / sl8114025

[0123] [3], R. Tao and M. Berroth, “Low power 10 GHz ring VCO using source capacitively coupled current amplifier in 0.12 um CMOS technology,” Electron. Lett., vol. 40, no. 23, pp. 1484-1486, Nov. 2004

[0124] [4], K. Scheir, G. Vandersteen, Y. Rolain and P. Wambacq, "A 57-to-66 GHz quadrature PLL in 45 nm digital CMOS", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 494-495, 2009. [5], K. Scheir, S. Bronckers, J. Borremans, P. Wambacq and Y. Rolain, "A 52

[0125] GHz phase-array receiver front-end in 90 nm digital CMOS", IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2651-2659, Dec. 2008. [6], E. Laskin, M. Khanpour, S. T. Nicolson, A. Tomkins, P. Garcia, A.

[0126] Cathelin, et al., "Nanoscale CMOS transceiver design in the 90-170 GHz range", IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 3477-3490, Dec. 2009.

[0127] [7], U. Decanis, A. Ghilioni, E. Monaco, A. Mazzanti and F. Svelto, "A mm- wave quadrature VCO based on magnetically coupled resonators", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 280-2811, 2011.

[0128] From Table 3 above, the FOM of the disclosed multi-phase inductor-coupled ring oscillator 100 is higher than most of the known ring oscillators in Table 3. For oscillators claiming a better FOM, it comes with a significant increase in power consumption.

[0129] Thus, some embodiments disclosed herein achieve a FOM that has a value that compares favorably to other oscillators. Several circuits show a better FOM but all suffer from a higher power consumption (from two to more than 35 times higher). While they are operating at mmW frequencies (with the exception of reference [Error! Reference source not found.]), they are also designed in conventional complementary metal oxide semiconductor (CMOS) technology nodes (250nm, 130nm, 90nm CMOS) and have a high complexity.

[0130] Some oscillators in Table 3 have a better phase noise at the 1MHz offset. However, the advantages of improved power consumption and simplicity of design are features of some embodiments that outweigh any disadvantage disclosed herein. Thus, embodiments may be employed as simple connectable devices in a mmWave transceiver.

[0131] Some multi-phase oscillators disclosed herein are capable of operating at mmW frequencies with a sub-mW power consumption, while exhibiting a good FOM, and keeping a low level of complexity.

[0132] Fixed Cm topology

[0133] It is possible to use a fixed capacitor Cm 122 in place of a variable capacitor Cm 112, as illustrated in FIG. 23. In this case, the complexity is even further reduced but the oscillation frequency may remain fixed because Cm remains fixed. 2*N-Phases topology

[0134] Embodiments are not limited to a 6-phase topology and may be extended up to 2*N-phases and odd number of inverters per ring, as illustrated in FIG. 24. In this case the different active and passive elements may be set up in a way to achieve the desired phase difference between the different outputs.

[0135] Additional Embodiment FIG. 25 is an example schematic diagram of another embodiment of a multi-phase inductor-coupled ring oscillator 100. The topology of FIG. 25 includes an even number of inverters per ring and the output of the last delay cell 106 of one ring oscillator 102 is cross-coupled to the input of the first delay cell 106 of the other ring oscillator 104, and vice versa.

[0136] Some embodiments may include one or more of the following:

[0137] Al. A 6-phase low complexity and low power oscillator comprising at least: a. Two single-ended ring oscillators include three single-ended, single-stage, custom-tailored inverter-based active delay cells; b. Each three outputs of each ring oscillator coupled to its counterpart through a differential inductor, introducing a phase shift, for which the center tap is connected to the AC ground through a capacitor; and c. Each three output of each ring oscillator connected to a shunt variable capacitor to set the frequency of operation.

[0138] A2. Al in which the variable capacitor in c is replaced by a fixed capacitor for the circuit to operates at a fixed frequency.

[0139] A3. Al and / or A2 for which the topology is extended to 2*N-phases.

[0140] As will be appreciated by one of skill in the art, the concepts described herein may be embodied as a method, data processing system, computer program product and / or computer storage media storing an executable computer program. Accordingly, the concepts described herein may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects all generally referred to herein as a “circuit” or “module.” Any process, step, action and / or functionality described herein may be performed by, and / or associated to, a corresponding module, which may be implemented in software and / or firmware and / or hardware. Furthermore, the disclosure may take the form of a computer program product on a tangible computer usable storage medium having computer program code embodied in the medium that may be executed by a computer. Any suitable tangible computer readable medium may be utilized including hard disks, CD-ROMs, electronic storage devices, optical storage devices, or magnetic storage devices.

[0141] Some embodiments are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems and computer program products. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer (to thereby create a special purpose computer), special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0142] These computer program instructions may also be stored in a computer readable memory or storage medium that may direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instruction means which implement the function / act specified in the flowchart and / or block diagram block or blocks.

[0143] The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0144] It is to be understood that the functions / acts noted in the blocks may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality / acts involved. Although some of the diagrams include arrows on communication paths to show a primary direction of communication, it is to be understood that communication may occur in the opposite direction to the depicted arrows.

[0145] Computer program code for carrying out operations of the concepts described herein may be written in an object oriented programming language such as Python, Java® or C++. However, the computer program code for carrying out operations of the disclosure may also be written in conventional procedural programming languages, such as the "C" programming language. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer. In the latter scenario, the remote computer may be connected to the user's computer through a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0146] Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, all embodiments may be combined in any way and / or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

[0147] It will be appreciated by persons skilled in the art that the embodiments described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings without departing from the scope of the following claims.

Claims

Claims:

1. A multi -phase oscillator circuit (100) for a millimeter wave, mmW, transceiver, the multi-phase oscillator circuit (100) comprising: a plurality of inductor-coupled ring oscillators (102, 104), each inductor-coupled ring oscillator (102, 104) comprising a plurality of single stage active delay cells (106), an output of each of the plurality of inductor-coupled ring oscillators (102, 104) being inductively coupled to an output of another one of the plurality of inductor-coupled ring oscillators (102, 104).

2. The multi-phase oscillator circuit (100) of Claim 1, further comprising a center tapped differential inductor (108) configured to inductively couple outputs of a pair of inductor-coupled ring oscillators (102, 104).

3. The multi -phase oscillator circuit (100) of Claim 2, wherein the center tap of the center tapped differential inductor (108) is connected to a signal ground via a first capacitor (110).

4. The multi-phase oscillator circuit (100) of any of Claims 1-3, further comprising a second capacitor (112, 122) for each of the plurality of outputs, the second capacitor (112, 122) being configured to set a frequency of operation of the multi -phase oscillator circuit (100).

5. The multi -phase oscillator circuit (100) of Claim 4, wherein a capacitance of the second capacitor (112, 122) is variable.

6. The multi-phase oscillator circuit (100) of any of Claims 1-5, wherein the plurality of inductor-coupled ring oscillators (102, 104) are configured to produce signals separated by a same phase difference.

7. The multi-phase oscillator circuit (100) of Claim 6, wherein a number of stages of each inductor-coupled ring oscillators (102, 104) of the plurality of inductor- coupled ring oscillators (102, 104) is three and the same phase difference is 60 degrees.

8. The multi -phase oscillator of any of Claims 1-7, wherein the number of inductor-coupled ring oscillators (102, 104) is two.

9. The multi-phase oscillator circuit (100) of any of Claims 1-8, wherein each inductor-coupled ring oscillator (102, 104) includes two single-ended, single-stage active delay cells (106).

10. The multi-phase oscillator circuit (100) of any of Claims 1-9, wherein the inductively coupled outputs of two inductor-coupled ring oscillators (102, 104) are separated in phase by substantially 180 degrees, the phase separation being obtained using passive components.

11. The multi -phase oscillator circuit (100) of any of Claims 1-10, further comprising a variable supply voltage configured to enable tuning of the plurality of inductor-coupled ring oscillators (102, 104).

12. A multi-phase oscillator circuit (100), comprising: three differential inductors (108); and three pairs of active inverters (114), each active inverter (114) of a pair having an output, the outputs of the pair of active inverters (114) being inductively coupled by one of the three differential inductors (108).

13. The multi-phase oscillator circuit (100) of Claim 12, wherein each differential inductor (108) is center tapped, the center tap being connected to a signal ground via a first capacitor (110).

14. The multi-phase oscillator circuit (100) of any of Claims 12 and 13, wherein the multi -phase oscillator circuit (100) has, in addition to the active inverters (114), only passive components.

15. The multi -phase oscillator circuit (100) of any of Claims 12-14, wherein each active inverter (114) is configured to have an input and output voltage operating point that is one-half of a supply voltage of the multi-phase oscillator circuit (100).

16. The multi-phase oscillator circuit (100) of any of Claims 12-15, wherein each differential inductor (108) is electrically in parallel with a corresponding resistance.

17. The multi-phase oscillator circuit (100) of any of Claims 12-16, wherein each differential coupled inductor (108) is center-tapped and each center tap is connected to a common mode resistance.

18. The multi -phase oscillator circuit (100) of any of Claims 12-17, wherein an output of each active inverter (114) is coupled to a differential inductor and a variable shunt capacitance.

19. The multi-phase oscillator circuit (100) of any of Claims 12-18, wherein each active inverter (114) is configured to introduce a 120 degree phase shift between an input of the active inverter (114) and an output of the active inverter (114).

20. The multi-phase oscillator circuit (100) of any of Claims 12-19, wherein each differential inductor (108) is configured to introduce a 180 degree phase shift between outputs of a pair of the active inverters (114).

21. The multi-phase oscillator circuit (100) of any of Claims 12-20, wherein the active inverters (114) and differential inductors (108) are configured in three stages, each stage being configured to provide a 60 degree phase difference between adjacent phase signals of the three stages.

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