Light reception element

Abstract

The present disclosure relates to a light reception element with which it is possible to perform inspection in a shorter time. Provided is a light reception element comprising a pixel array unit in which pixels are arranged in an array form, each of the pixels comprising an avalanche photodiode element, a waveform shaping circuit that shapes the output of the avalanche photodiode element into a pulse, and a counter circuit that counts a detection pulse outputted by the waveform shaping circuit or an inspection pulse outputted by an inspection pulse generation circuit, wherein the pixel has a determination circuit that determines whether the counter circuit is normal or not on the basis of a count value outputted from the counter circuit. The present disclosure can be applied, for example, to a light reception element in which a counter circuit for counting the number of photons is provided for each pixel.

Description

Light receiving element

[0001] The present disclosure relates to a light receiving element, and more particularly to a light receiving element that enables inspection to be performed in a shorter time.

[0002] A light receiving element is known in which a SPAD (Single Photon Avalanche Diode) element for detecting the presence or absence of photons and a counter circuit for counting the number of photons are provided for each pixel (see, for example, Patent Document 1).

[0003] Japanese Patent Application Publication No. 2023-111734

[0004] In this type of light receiving element, there is a possibility that the counter circuit may contain circuits with poor characteristics, and therefore inspection is necessary, but it is required to perform the inspection in a shorter time.

[0005] The present disclosure has been made in view of these circumstances, and aims to enable inspection to be performed in a shorter time.

[0006] A light receiving element according to one aspect of the present disclosure includes a pixel array section in which pixels are arranged in an array, each pixel having an avalanche photodiode element, a waveform shaping circuit that shapes the output of the avalanche photodiode element into a pulse, and a counter circuit that counts detection pulses output by the waveform shaping circuit or inspection pulses output by an inspection pulse generation circuit, and the pixel is a light receiving element having a determination circuit that determines whether the counter circuit is normal or not based on the count value output from the counter circuit.

[0007] In a light-receiving element according to one aspect of the present disclosure, a pixel array section has pixels arranged in an array, each pixel having an avalanche photodiode element, a waveform shaping circuit that shapes the output of the avalanche photodiode element into a pulse, and a counter circuit that counts the detection pulses output by the waveform shaping circuit or the inspection pulses output by the inspection pulse generation circuit. Each pixel in the pixel array section determines whether the counter circuit is normal or not based on the count value output by the counter circuit.

[0008] A light-receiving element according to one aspect of the present disclosure includes a pixel array section in which pixels are arranged in an array, each pixel having an avalanche photodiode element, a waveform shaping circuit that shapes the output of the avalanche photodiode element into a pulse, and a counter circuit composed of a first counter circuit and a second counter circuit, and the pixels have a first selection circuit connected to the input side of the first counter circuit and that selects either a detection pulse output by the waveform shaping circuit or an inspection pulse output by an inspection pulse generation circuit, and a second selection circuit connected to the input side of the second counter circuit and that selects either a carry-out output by the first counter circuit or the inspection pulse.

[0009] In a light-receiving element according to one aspect of the present disclosure, a pixel array section has pixels arranged in an array, each pixel having an avalanche photodiode element, a waveform shaping circuit that shapes the output of the avalanche photodiode element into a pulse, and a counter circuit composed of a first counter circuit and a second counter circuit. Each pixel in the pixel array section selects either a detection pulse output by the waveform shaping circuit or an inspection pulse output by an inspection pulse generation circuit, and selects either a carry-out output by the first counter circuit or the inspection pulse.

[0010] The light receiving element according to one aspect of the present disclosure may be an independent device or an internal block constituting a single device.

[0011] 1 is a diagram showing an example of the configuration of an embodiment of an electronic device to which the present disclosure is applied. FIG. 1 is a diagram showing an example of the configuration of a pixel array unit in the light receiving element of FIG. 1. FIG. 2 is a diagram showing an example of the configuration of a pixel. FIG. 3 is a timing chart illustrating a determination by the determination circuit of FIG. 3. FIG. 4 is a diagram showing an example of the connection between the counter circuit and the determination circuit of FIG. 3. FIG. 5 is a diagram showing an example of the configuration of the determination circuit when the counter circuit is configured as a binary counter. FIG. 6 is a diagram showing an example of the configuration of a determination circuit when the counter circuit is configured as a Johnson counter. FIG. 7 is a diagram showing an example of the configuration of the determination circuit of FIG. 3. FIG. 9 is a timing chart illustrating a determination by the determination circuit of FIG. 9. FIG. 9 is a timing chart illustrating a determination by the determination circuit of FIG. 3. FIG. 10 is a diagram showing an example of the configuration of the pixel of FIG. 2. FIG. 11 is a diagram showing an example of the configuration of the counter circuit of FIG. 13. FIG. 14 is a diagram showing an example of the configuration of the pixel of FIG. 2. FIG. 15 is a diagram showing an example of the operation sequence during normal counting. FIG. 16 is a diagram showing an example of an inspection sequence during inspection. FIG. 17 is a diagram showing an example of the configuration of the pixel of FIG. 2. FIG. 18 is a diagram showing an example of the inspection sequence during inspection. FIG. 19 is a diagram showing an example of the configuration of the pixel of FIG. 2. FIG. 20 is a diagram showing an example of the configuration of the pixel of FIG. 2. FIG. 27 is a diagram showing an example of a structure in which two layers of substrates are stacked in the light receiving element of FIG. 1. FIG. 28 is a diagram showing an example of a circuit layout on the substrate of FIG. 25. FIG. 29 is a diagram showing an example of a structure in which three layers of substrates are stacked in the light receiving element of FIG. 1. FIG. 29 is a diagram showing an example of a circuit layout on the substrate of FIG. 27. FIG. 29 is a diagram explaining an example of an inspection method when inspecting before bonding the substrates. FIG. 30 is a diagram explaining an example of an inspection method when inspecting a pixel array portion. FIG. 31 is a diagram showing an example of a configuration for performing signal processing using the judgment results of each pixel. FIG. 32 is a diagram showing an example of defect correction for defective pixels.

[0012] <Device Configuration> Fig. 1 is a diagram showing an example configuration of an embodiment of an electronic device to which the present disclosure is applied. The electronic device 1 in Fig. 1 is a device having an imaging function. For example, the electronic device 1 is a device such as a smartphone, a digital camera, a PC (Personal Computer), an in-vehicle camera, or an IoT (Internet of Things) camera. In Fig. 1, the electronic device 1 is composed of an optical system 11, a light receiving element 12, a control unit 13, and a storage unit 14.

[0013] The optical system 11 is composed of lenses and the like that collect incident light from a subject and guide it to the light receiving element 12. The light receiving element 12 is a photoelectric conversion device that includes a pixel array unit in which pixels, each having a photoelectric conversion unit, are arranged in an array. The light receiving element 12 captures an image of the subject, generates image data, and outputs the image data to the memory unit 14 under the control of the control unit 13. The memory unit 14 records the image data output from the light receiving element 12. The control unit 13 is composed of a processor such as a CPU (Central Processing Unit). The memory unit 14 is composed of a storage device such as a non-volatile memory.

[0014] 1 may include a display unit such as a display to display an image corresponding to image data. Also, the electronic device 1 may include a communication unit such as a communication device compatible with a predetermined communication method to transmit image data to an external device via a network.

[0015] FIG. 2 is a diagram showing an example of the configuration of a pixel array section in the photodetector 12 of FIG. 1. As shown in FIG. 2, the photodetector 12 includes a pixel array section 41 in which pixels 51 are arranged in an array (matrix). In FIG. 2, the optical axis of incident light is defined as the Z axis, the axis perpendicular to the Z axis is defined as the X axis, and the axis perpendicular to the Z and X axes is defined as the Y axis. The pixels 51 arranged in the pixel array section 41 are arranged along the X and Y axes. Each pixel 51 includes a single photon avalanche diode (SPAD) element. When a voltage greater than the breakdown voltage is applied to a SPAD element, avalanche amplification occurs when a single photon enters a PN junction region with a high electric field. The photodetector 12 is a photon-counting photodetector, with each pixel equipped with a SPAD element that detects the presence or absence of photons and a counter circuit that counts the number of photons. A SPAD element is a type of avalanche photodiode (APD).

[0016] <<First Embodiment>> Fig. 3 is a diagram showing an example of the configuration of the pixel 51 in Fig. 2. In Fig. 3, the pixel 51 is composed of a SPAD element 61, a waveform shaping circuit 62, a transistor 63, a selection circuit 64, a counter circuit 65, and a determination circuit 66.

[0017] The cathode terminal of the SPAD element 61 is connected to a waveform shaping circuit 62 formed by an inverter circuit and a transistor 63 that performs quenching and recharging (resetting) operations for the SPAD element 61. The waveform shaping circuit 62 amplifies the voltage at the connection point between the SPAD element 61 and the transistor 63 and then detects the edge, thereby generating a voltage pulse (hereinafter also referred to as a detection pulse) from the voltage change caused by the incidence of a photon. In this way, the SPAD element 61, waveform shaping circuit 62, and transistor 63 form a photon detection circuit that can detect the incidence of a single photon.

[0018] During normal imaging (normal counting), the selection circuit 64 receives detection pulses from the waveform shaping circuit 62. During normal counting, the counter circuit 65 counts (photon counts) the (number of) detection pulses received from the selection circuit 64 and outputs a count value. On the other hand, during inspection, the selection circuit 64 receives inspection pulses from the inspection pulse generation circuit 42. During inspection, the counter circuit 65 counts (the number of) inspection pulses received from the selection circuit 64 and outputs a count value. The selection circuit 64 is connected to the input side of the counter circuit 65 and selects detection pulses or inspection pulses in accordance with a selection signal received from a control circuit such as the control unit 13. For example, the counter circuit 65 may be configured with an n-bit counter, where n is an integer greater than or equal to 2, and may also be considered a multi-bit counter.

[0019] The inspection pulse generating circuit 42 is used, for example, for inspection of the light receiving elements 12 during manufacturing, generates inspection pulses according to input values ​​specified by the control circuit, and inputs the inspection pulses to the selection circuits 64 of the pixels 51. The inspection pulse generating circuit 42 is configured to be connectable to the light receiving elements 12, and is connected, for example, when inspection is performed during manufacturing. Alternatively, the inspection pulse generating circuit 42 may be configured within the control unit 13. The inspection pulse may be common to each pixel.

[0020] The determination circuit 66 receives the count value output from the counter circuit 65. Based on the count value from the counter circuit 65, the determination circuit 66 determines whether the counter circuit 65 is normal and outputs the determination result. In each pixel arranged in the pixel array unit 41, the counter circuit 65 may include a circuit with poor characteristics. During testing, the determination circuit 66 determines whether the counter circuit 65 is normal (whether there is a fault). FIG. 4 is a timing chart illustrating the determination operation by the determination circuit 66 of FIG. 3. FIG. 4 shows the determination result by the determination circuit 66 when a test pulse is input to the binary counter when the counter circuit 65 is configured as a binary counter. A binary counter counts binary numbers, and when a clock pulse is input, the binary number increases by one for each cycle of the clock pulse. The binary counter is configured with a plurality of flip-flop circuits, etc.

[0021] 4, it is assumed that the binary counter is a 2-bit counter that can count from 0 (00) to 3 (11). In this case, when the binary counter is normal, the value increases by one each time a test pulse is input, as shown by the solid line in FIG. 4. When the value exceeds 3 depending on the number of test pulses input, the value overflows and returns to 0. At this time, the determination circuit 66 outputs a determination result indicating normal (1), as shown by the solid line in FIG. 4, because the count value matches the expected value. On the other hand, when the binary counter is faulty, the value does not increase by one each time a test pulse is input, as shown by the dashed line in FIG. 4, and the count value does not match the expected value, so the determination circuit 66 outputs a determination result indicating fault (0).

[0022] <<Second Embodiment>> Fig. 5 is a diagram showing an example of the connection between the counter circuit 65 and the determination circuit 66 in Fig. 3. In Fig. 5, when the counter circuit 65 is an n-bit counter, the counter circuit 65 and the determination circuit 66 are connected by n signal lines, and the values ​​of each bit (Q1, Q2, ..., Q n-1 , Q n) is input from the counter circuit 65 to the decision circuit 66. In FIG. 5, the counter circuit 65 is an n-bit counter, and n By inputting the test pulse 10 times, the determination circuit 66 determines whether the value of each bit output from the counter circuit 65 is 0 or not. That is, the n-bit counter is overflowed and the determination circuit 66 determines whether the counter circuit 65 is normal or not by determining whether all bits are 0 or not. Here, the determination circuit 66 makes the determination using the values ​​of all bits of the counter circuit 65.

[0023] 6 is a diagram showing an example of the configuration of the decision circuit 66 in FIG. 6. In FIG. 6, the decision circuit 66 has a plurality of NOR gate circuits 71 and a register circuit 73. As shown in FIG. 6, the NOR gate circuits 71 １ The NOR gate circuit 71 calculates the negative OR of Q1 and Q2 input thereto. ２ The NOR gate circuit 71 calculates the NOR of Q2 and Q3 input thereto. ３ to NOR gate circuit 71 ｎ－２ The same applies to the NOR gate circuit 71. ｎ－１ is the Q that is input there n-1 and Q n Furthermore, although not shown, a NOR gate circuit 71 １ and NOR gate circuit 71 ２ The operation results of the NOR gate circuits 71 are input to the subsequent NOR gate circuit 71, and the NOR of these operation results is further calculated. Similarly, by repeating the operation of the NOR of the operation results of two adjacent NOR gate circuits 71 for each row (stage) of the NOR gate circuits 71, the number of NOR gate circuits 71 per row decreases, and finally, one NOR gate circuit 71 ｍ (1<n<m) performs a negative OR operation. NOR gate circuit 71 ｍ is the NOR gate circuit 71 in the previous row. ｍ－２ The calculation result and the NOR gate circuit 71 ｍ－１ The NOR of the calculation results of the above is calculated, and the calculation result is output to the register circuit 73.

[0024] 5 , a plurality of NOR gate circuits 71 connected in an inverted pyramid shape perform a NOR operation on all bits of the output of the counter circuit 65 to determine whether all bits output from the counter circuit 65 are 0. The register circuit 73 is composed of a 1-bit register and holds the calculation results from the NOR gate circuits 71 connected in an inverted pyramid shape. For example, if it is determined that all bits output from the counter circuit 65 are 0, the register circuit 73 outputs a determination result indicating normal (1). On the other hand, if it is determined that all bits output from the counter circuit 65 are not 0, the register circuit 73 outputs a determination result indicating fault (0).

[0025] <<Third Embodiment>> The counter circuit 65 can be configured as a binary counter or a Johnson counter. When this configuration is used, the counter circuit 65 is an n-bit counter. n By inputting a check pulse once, the decision circuit 66 determines whether the value of each bit output from the counter circuit 65 is 1, i.e., whether all bits are 1. A Johnson counter is a type of shift register counter, which inverts the output of the final stage of the shift register and returns it to the input of the first stage.

[0026] 7 is a diagram showing an example of the configuration of the determination circuit 66 when the counter circuit 65 is configured as a binary counter. In FIG. 7, the determination circuit 66 has a plurality of AND gate circuits 81 and a register circuit 83. As shown in FIG. 7, the AND gate circuits 81 １performs a logical AND operation on Q1 and Q2 input thereto. Although not shown, the AND gate circuit 81 in FIG. 7 is connected in an inverted pyramid shape, similar to the NOR gate circuit 71 in FIG. 6. In the determination circuit 66 in FIG. 7, the AND gate circuit 81 connected in an inverted pyramid shape performs a logical AND operation on all bits to determine whether all bits output from the counter circuit 65 are 1. For example, the register circuit 83 outputs a determination result indicating normal (1) if it is determined that all bits are 1, and outputs a determination result indicating fault (0) if it is determined that all bits are not 1.

[0027] 8 is a diagram showing an example of the configuration of the decision circuit 66 when the counter circuit 65 is configured as a Johnson counter (a quaternary counter consisting of a Johnson counter). In FIG. 8, the decision circuit 66 has a plurality of AND gate circuits 81 and a register circuit 83. Since the Johnson counter is configured as a ring with output inversion, an inverter circuit 84 is provided for the input of odd-numbered bits. As shown in FIG. 8, the AND gate circuit 81 １ Q1 and Q2 are input to the inverter circuit 84. １ is provided, and outputs the inverted value of the input value (Q1). １ The AND gate circuit 81 calculates the logical product of the inverted Q1 and Q2 input thereto. ｎ－１ Even in n-1 ) to inverter circuit 84 ｎ－１ is provided, and the inverted Q n-1 and Q n 8 is connected in an inverted pyramid shape, similar to the AND gate circuit 81 in FIG. 7. In the determination circuit 66 in FIG. 8, the AND gate circuits 81 connected in an inverted pyramid shape (however, odd-numbered bit inputs go through inverter circuits) perform a logical AND of all bits to determine whether all bits output from the counter circuit 65 are 1 or not.

[0028] <<Fourth Embodiment>> Fig. 9 is a diagram showing an example of the configuration of the determination circuit 66 of Fig. 3. In Fig. 9, the determination circuit 66 has a falling edge detection circuit 91. As shown in Fig. 9, the falling edge detection circuit 91 is connected to the counter circuit 65 via one signal line, and detects the value of the most significant bit (MSB) (Q n ) is input to the counter circuit 65. n When the falling edge detection circuit 91 detects the falling edge of the most significant bit at the timing when the first check pulse is input, it is determined that the counting is normal. The value of the most significant bit can also be said to be the value of a specific bit in the counter circuit 65, which is composed of an n-bit counter.

[0029] FIG. 10 is a timing chart illustrating the determination operation by the determination circuit 66 of FIG. 9 . FIG. 10 shows the determination result by the determination circuit 66 when a check pulse is input to the binary counter in the case where the counter circuit 65 is configured as a binary counter. That is, when the binary counter is normal, its value increases by one for each check pulse input, as shown by the solid line in FIG. 10 . When the value exceeds three depending on the number of check pulse inputs, it overflows and returns to zero. At this time, the falling edge detection circuit 91 monitors only the most significant bit and detects the falling edge of the most significant bit to determine whether an overflow has occurred. Therefore, when the falling edge is detected, the circuit outputs a determination result indicating normal (1), as shown by the solid line in FIG. 10 . On the other hand, when the falling edge detection circuit 91 does not detect a falling edge, it outputs a determination result indicating failure (0), as shown by the dashed line in FIG. 10 .

[0030] Fig. 11 is a timing chart illustrating the determination operation by the determination circuit 66 of Fig. 9. Fig. 11 shows the determination result by the determination circuit 66 when an inspection pulse is input to the Johnson counter in the case where the counter circuit 65 is configured with a Johnson counter. That is, as shown by the solid line in Fig. 11, when the Johnson counter is normal, it detects the falling edge of the most significant bit and outputs a determination result indicating normal (1). On the other hand, as shown by the dashed line in Fig. 11, when it cannot detect the falling edge, it outputs a determination result indicating failure (0).

[0031] <<Fifth Embodiment>> Fig. 12 is a diagram showing an example of the configuration of the determination circuit 66 of Fig. 3. In Fig. 12, the determination circuit 66 has a selection circuit 101 and a falling edge detection circuit 102. As shown in Fig. 12, the selection circuit 101 is connected to the counter circuit 65 via n signal lines, and the values ​​of each bit (Q1, Q2, ..., Q n-1 , Q n ) is input. The selection circuit 101 selects a specific bit value for edge detection from the bit values ​​input from the counter circuit 65 in accordance with a selection signal input from a control circuit such as the control unit 13, and outputs the selected bit value to the falling edge detection circuit 102. When a specified number of inspection pulses have been input to the counter circuit 65 and the falling edge of the specific bit input from the selection circuit 101 is detected by the falling edge detection circuit 102, the determination circuit 66 in FIG. 12 determines that counting is being performed normally and outputs a determination result indicating normal (1).

[0032] In this way, by selecting and determining a specific bit to monitor, if the value at which the counter transition fails is known, for example, detection is possible by inputting a test pulse up to that value, thereby speeding up the test.

[0033] <<Sixth Embodiment>> Fig. 13 is a diagram showing an example of the configuration of the pixel 51 in Fig. 2. In Fig. 13, parts corresponding to those in Fig. 3 are assigned the same reference numerals, and their description will be omitted as appropriate. Compared to the pixel 51 in Fig. 3, the pixel 51 in Fig. 13 is provided with a counter circuit 111 instead of the counter circuit 65. The counter circuit 111 is configured with an n-bit counter or the like. During normal counting, the counter circuit 111 counts detection pulses input from the selection circuit 64 and outputs a count value. Furthermore, during inspection, the counter circuit 111 counts inspection pulses input from the selection circuit 64 and outputs a count value.

[0034] An initial value is input to the counter circuit 111 from a control circuit such as the control unit 13. The counter circuit 111 can set an initial value and count test pulses at the start of the test sequence (before the test starts). The counter circuit 111 is configured to input a test pulse (clock pulse) for each bit, and an initial value can be set for each bit. FIG. 14 is a diagram showing an example configuration of the counter circuit 111 shown in FIG. 13. In FIG. 14, the counter circuit 111 is configured as a Johnson counter, and the selection circuit 121 and shift register 122 of an n-bit Johnson counter are illustrated as one stage. The Johnson counter is configured as a ring with output inversion, and the Q signal from the shift register 122 is fed back to the D input. In the counter circuit 111 shown in FIG. 14, a selection circuit 121 that selects the initial value and the D input for the shift register 122 is provided, allowing the initial value to be set at the start of the test sequence.

[0035] The test time can be reduced by setting an initial value in the counter circuit 111. For example, if a value at which a transition fails in the counter circuit 111 is known, the test time can be reduced by setting a value close to the value at which the transition fails as the initial value of the counter circuit 111.

[0036] <<Seventh Embodiment>> Fig. 15 is a diagram showing an example of the configuration of the pixel 51 in Fig. 2. In Fig. 15, the pixel 51 is composed of a SPAD element 61, a waveform shaping circuit 62, a transistor 63, selection circuits 131, selection circuits 132, counter circuits 141, and counter circuits 142. In Fig. 15, parts corresponding to those in Fig. 3 are given the same reference numerals, and their description will be omitted as appropriate. In Fig. 15, the counter circuit 140 is divided into counter circuits 141 and 142, and the counter circuits 141 and 142 constitute the counter circuit 140.

[0037] For example, the counter circuit 140 may be configured with an n-bit counter or the like, with the counter circuit 141 being a counter corresponding to the least significant bit (LSB) side bits and the counter circuit 142 being a counter corresponding to the most significant bit (MSB) side bits. More specifically, if the counter circuit 140 is a 14-bit counter and is divided into lower and upper bits, each of the counter circuits 141 and 142 may be a 7-bit counter.

[0038] The selection circuit 131 is connected to the input side of the counter circuit 141, and selects either the detection pulse input from the waveform shaping circuit 62 or the inspection pulse input from the inspection pulse generation circuit 42 in accordance with a selection signal input from a control circuit such as the control unit 13, and outputs the selected pulse to the counter circuit 141. During normal counting, the counter circuit 141 counts (photon counts) the detection pulse input from the selection circuit 131 and outputs a count value. During inspection, the counter circuit 141 counts the inspection pulse input from the selection circuit 131 and outputs a count value.

[0039] The selection circuit 132 is connected to the input side of the counter circuit 142 and to the carry input of the counter circuit 141. In accordance with a selection signal input from a control circuit such as the control unit 13, the selection circuit 132 selects either the carry-out (carry output) input from the counter circuit 141 or the check pulse input from the check pulse generation circuit 42, and outputs the selected signal to the counter circuit 142. During normal counting, the counter circuit 142 counts (photon counts) the carry-out pulse input from the selection circuit 132 and outputs a count value. During inspection, the counter circuit 142 counts the check pulse input from the selection circuit 132 and outputs a count value.

[0040] Fig. 16 is a diagram showing an example of an operation sequence during normal counting in the pixel 51 of Fig. 15. As shown in Fig. 16, during normal counting, the selection circuit 131 selects the detection pulse and the selection circuit 132 selects the carry-out, thereby causing the counter circuits 141 and 142 to count (CNT) the detection pulse. That is, during normal counting, the counter circuit 140 of Fig. 15 can operate as a 2n-bit counter by the counter circuit 141, which is an n-bit counter, and the counter circuit 142, which is also an n-bit counter.

[0041] FIG. 17 is a diagram showing an example of a test sequence during testing of pixel 51 in FIG. 15 . As shown in FIG. 17 , during testing, selection circuit 131 selects a test pulse, and selection circuit 132 selects a test pulse, respectively, and counter circuits 141 and 142 count the test pulses (CNT1, CNT2), respectively. That is, by simultaneously inputting test pulses to counter circuits 141 and 142, it is possible to test the n-bit counter in parallel. In this way, by dividing the counter circuit in counter circuit 140 in FIG. 15 , it is possible to input a test pulse to each of the divided counter circuits during testing, thereby shortening the time required to test all bits of the counter circuit. For example, when a counter circuit operating as a 2n-bit counter is divided, the input time for the test pulse is reduced by 2 times compared to a configuration in which the counter circuit is not divided. n It can be twice as fast.

[0042] Eighth Embodiment Fig. 18 is a diagram showing an example of the configuration of the pixel 51 in Fig. 2. In Fig. 18, parts corresponding to those in Fig. 15 are assigned the same reference numerals, and their description will be omitted as appropriate. Compared to the pixel 51 in Fig. 15, the pixel 51 in Fig. 18 is additionally provided with a determination circuit 151. The determination circuit 151 is a circuit that determines whether the counter circuit 140 in Fig. 18 is normal. The counter circuit 140 in Fig. 18 is composed of a counter circuit 141 and a counter circuit 142, similar to the counter circuit 140 in Fig. 15. The determination circuit 151 includes a determination circuit 161, a determination circuit 162, and an AND gate circuit 163.

[0043] The determination circuit 161 receives an input of a count value (CNT1) from the counter circuit 141. The determination circuit 161 determines whether the counter circuit 141 is normal or not based on the count value (CNT1) received from the counter circuit 141, and outputs the determination result (RSLT1) to the AND gate circuit 163. The determination circuit 162 receives an input of a count value (CNT2) from the counter circuit 142. The determination circuit 162 determines whether the counter circuit 142 is normal or not based on the count value (CNT2) received from the counter circuit 142, and outputs the determination result (RSLT2) to the AND gate circuit 163. The determination circuits 161 and 162 in FIG. 18 can perform the determination using any of the configurations of the determination circuits described above (e.g., the determination circuits 66 in FIGS. 3, 5, 9, and 12).

[0044] The AND gate circuit 163 receives the judgment result (RSLT1) from the judgment circuit 161 and the judgment result (RSLT2) from the judgment circuit 162. The AND gate circuit 163 takes the logical product (AND) of the judgment result (RSLT1) and the judgment result (RSLT2) and outputs a judgment result indicating normal (1) only when both the counter circuits 141 and 142 are normal. The AND gate circuit 163 outputs a judgment result indicating fault (0) when at least one of the counter circuits 141 and 142 is faulty.

[0045] 19 is a diagram showing an example of an inspection sequence during inspection of pixel 51 in FIG. 19 illustrates a case in which judgment circuit 161 outputs a judgment result (RSLT1) indicating failure (0) from the count value (CNT1) of counter circuit 141, and judgment circuit 162 outputs a judgment result (RSLT2) indicating normal (1) from the count value (CNT2) of counter circuit 142. In this case, AND gate circuit 163 performs a logical AND operation on the judgment result (RSLT1) indicating failure (0) and the judgment result (RSLT2) indicating normal (1), and judgment circuit 151 outputs a judgment result indicating failure (0) as a final result output.

[0046] <<Ninth Embodiment>> Fig. 20 is a diagram showing an example of the configuration of the pixel 51 in Fig. 2. In Fig. 20, parts corresponding to those in Figs. 15 and 18 are assigned the same reference numerals, and their description will be omitted as appropriate. Compared to the pixel 51 in Fig. 15, the pixel 51 in Fig. 20 is additionally provided with a selection circuit 133 and a determination circuit 151. The selection circuit 133 selects either the selection circuit 131 or the selection circuit 132 in accordance with a selection signal input from a control circuit such as the control unit 13, and outputs the check pulse input from the check pulse generation circuit 42. The counter circuit 140 in Fig. 20 is composed of a counter circuit 141 and a counter circuit 142, similar to the counter circuit 140 in Fig. 15.

[0047] 20 , during testing, the test sequences for the counter circuits 141 and 142 are not performed simultaneously, but are performed sequentially according to the selection by the selection circuit 133. That is, the selection circuit 133 outputs a test pulse to the selection circuit 131 to perform a first test sequence for testing the counter circuit 141 on the least significant bit (LSB) side, and then the selection circuit 133 outputs a test pulse to the selection circuit 132 to perform a second test sequence for testing the counter circuit 142 on the most significant bit (MSB) side. In the first test sequence, the selection circuit 131 selects the test pulse input from the selection circuit 133 and inputs it to the counter circuit 141, and the selection circuit 132 selects the carry-out of the counter circuit 141. In the second test sequence, the selection circuit 132 selects the test pulse input from the selection circuit 133 and inputs it to the counter circuit 142.

[0048] 21 is a diagram showing examples of a first test sequence and a second test sequence during testing of pixel 51 in FIG. 20. As shown in FIG. 21, first, in the first test sequence, selection circuit 131 inputs test pulses from selection circuit 133 until counter circuit 141 on the least significant bit (LSB) side overflows, causing counter circuit 142 on the most significant bit (MSB) side to increment by 1 due to a carry. After achieving this state, selection circuit 133 switches the output destination of the test pulses, so that in the second test sequence, selection circuit 132 inputs test pulses from selection circuit 133 until counter circuit 142 overflows.

[0049] The judgment circuit 151 receives the count value (CNT1) from the least significant bit (LSB) counter circuit 141 and the count value (CNT2) from the most significant bit (MSB) counter circuit 142 as inputs, and outputs a judgment result based on these count values ​​(CNT1, CNT2). For example, as shown in FIG. 21 , if the counter circuits 141 and 142 operate normally through a series of test sequences, the count values ​​(CNT1) and (CNT2) will all be 0. If the count values ​​(CNT1) and (CNT2) are all 0, the judgment circuit 151 outputs a judgment result indicating normal (1). If the count values ​​(CNT1) and (CNT2) are not all 0, the judgment circuit 151 outputs a judgment result indicating defective (0).

[0050] <<Tenth Embodiment>> Fig. 22 is a diagram showing an example of the configuration of the pixel 51 in Fig. 2. In Fig. 22, parts corresponding to those in Figs. 15, 18, and 20 are given the same reference numerals, and their description will be omitted as appropriate. Compared to the pixel 51 in Fig. 20, the pixel 51 in Fig. 22 has initial values ​​set for the counter circuits 141 and 142. The counter circuit 140 in Fig. 22 is composed of the counter circuits 141 and 142, similar to the counter circuit 140 in Fig. 15.

[0051] An initial value is input to the counter circuit 141 and the counter circuit 142 from a control circuit such as the control unit 13. The counter circuit 141 is configured to be able to input a test pulse for each bit, and at the start of a test sequence, an initial value is set for each bit and the test pulses can be counted. The same applies to the counter circuit 142. For example, the counter circuits 141 and 142 may be configured similarly to the configuration shown in FIG. 14. Setting an initial value in each of the divided counter circuits makes it possible to quickly check the transition, for example, from the counter circuit 141 on the least significant bit (LSB) side to the counter circuit 142 on the most significant bit (MSB) side.

[0052] <<Eleventh Embodiment>> Fig. 23 is a diagram showing an example of the configuration of the pixel 51 in Fig. 2. In Fig. 23, parts corresponding to those in Fig. 3 are assigned the same reference numerals, and their description will be omitted as appropriate. Compared to the pixel 51 in Fig. 3, the pixel 51 in Fig. 23 is provided with a determination circuit 171 instead of the determination circuit 66. The determination circuit 171 can perform determination using the configuration of any of the determination circuits described above (for example, the determination circuit 66 in Figs. 3, 5, 9, and 12).

[0053] In FIG. 23 , the determination circuit 171 is configured to output the determination result in parallel with the count value output by the counter circuit 65. In this way, by separately outputting the determination result and the count value from the pixel 51, both the determination result and the count value, or either one of them, can be selected and read during readout. For example, by providing a dedicated 1-bit signal line for the determination circuit 171 and using it for reading the determination result, the inspection time can be shortened. Note that while FIG. 23 shows a configuration corresponding to the case where the counter circuit is not divided, as shown in FIG. 3 etc., a similar configuration can also be adopted when the counter circuit is divided, as shown in FIG. 18 etc. For example, in FIG. 18 , the determination circuit 151 may output the determination result in parallel with the count values ​​output by the counter circuits 141 and 142.

[0054] <<Twelfth Embodiment>> Figure 24 is a diagram showing an example of the configuration of the pixel 51 in Figure 2. Components corresponding to those in Figures 3 and 23 are assigned the same reference numerals, and their description will be omitted as appropriate. Compared to the pixel 51 in Figure 3, the pixel 51 in Figure 24 is provided with a determination circuit 171 and a selection circuit 172 instead of the determination circuit 66. The determination circuit 171 is the same as that in Figure 23, and can perform determination using the configuration of any of the determination circuits described above (for example, the determination circuit 66 in Figures 3, 5, 9, and 12).

[0055] The selection circuit 172 receives the count value from the counter circuit 65 and the determination result from the determination circuit 171. The selection circuit 172 selects and outputs either the count value or the determination result in accordance with a selection signal input from a control circuit such as the control unit 13. By selecting and outputting the determination result from the pixel 51 and the count value in this manner, it is possible to, for example, standardize the normal counting process and the readout process, thereby reducing design costs. While FIG. 24 illustrates a configuration corresponding to the case where the counter circuit is not divided, as shown in FIG. 3 and the like, a similar configuration can also be adopted when the counter circuit is divided, as shown in FIG. 18 and the like. For example, in FIG. 18, a selection circuit may be provided downstream of the counter circuits 141, 142, and the determination circuit 151 to select and output the count value or the determination result.

[0056] <<Thirteenth Embodiment>> Fig. 25 is a diagram showing an example of a structure in which substrates in the light-receiving element 12 of Fig. 1 are stacked. As shown in Fig. 25, the light-receiving element 12 has a two-layer stacked structure in which a substrate 21 and a substrate 22 are bonded together. The substrate 21 is a substrate on which the SPAD element 61 and the like are formed. The substrate 22 is a substrate on which a logic circuit is formed. A signal line for transmitting a signal is provided between the substrate 21 and the substrate 22.

[0057] Fig. 26 is a diagram showing an example of circuit layout on the substrate 22 of Fig. 25. As shown in Fig. 26, a waveform shaping circuit 62, a transistor 63, a selection circuit 64, a counter circuit 65, and a determination circuit 66 are formed on the substrate 22. As such, the light receiving element 12 has a two-layer structure in which a first layer including the SPAD element 61 and a second layer including a logic circuit are stacked, and the determination circuit 66 is arranged on the same layer (logic layer) as the counter circuit 65. By arranging the counter circuit 65 and the determination circuit 66 on the same layer, the circuit area can be reduced.

[0058] <<Fourteenth Embodiment>> Fig. 27 is a diagram showing an example of a structure in which substrates in the light-receiving element 12 of Fig. 1 are stacked. As shown in Fig. 27, the light-receiving element 12 has a three-layer stacked structure in which a substrate 21, a substrate 22, and a substrate 23 are bonded together. The substrate 21 is a substrate on which the SPAD element 61 and the like are formed. The substrates 22 and 23 are substrates on which logic circuits are formed. Signal lines for transmitting signals are provided between the substrates 21 and 22, and between the substrates 22 and 23.

[0059] 28 is a diagram showing an example of circuit layout on the substrate 22 and the substrate 23 of FIG. 27. As shown in FIG. 28, a waveform shaping circuit 62 and a transistor 63 are formed on the substrate 22. A selection circuit 64, a counter circuit 65, and a determination circuit 66 are formed on the substrate 23. In this way, the light receiving element 12 has a three-layer laminated structure, and the determination circuit 66 is arranged on the same layer (second logic layer) as the counter circuit 65. By arranging the counter circuit 65 and the determination circuit 66 on the same layer, the circuit area can be reduced.

[0060] <<Fifteenth Embodiment>> Fig. 29 is a diagram illustrating an example of an inspection method when an inspection is performed before bonding substrates in a light-receiving element 12. Fig. 29 illustrates an example in which, in a two-layer stacked structure as shown in Fig. 25, an inspection (pre-shipment inspection) is performed on a substrate 22 (logic layer) on which a logic circuit is formed, before bonding the substrates 21 and 22 together.

[0061] 29 , during inspection, an inspection pulse generation circuit 42 is connected via signal lines 46 to the terminals of each pixel formed on the substrate 22 before bonding. The inspection pulse generation circuit 42 generates inspection pulses and inputs them to each pixel formed on the substrate 22 via the signal lines 46. A control circuit 43 is connected via signal lines 47 to the gates of the transistors 63 of each pixel formed on the substrate 22. The control circuit 43 generates drive signals and inputs them to the gates of the transistors 63 of each pixel to control the driving of the transistors 63. A memory 44 is connected via signal lines 48 to each pixel formed on the substrate 22 and stores the count values ​​and determination results output from each pixel.

[0062] When inspecting the substrate 22 before bonding it to the substrate 21, the SPAD element 61 is not connected to the connection point between the waveform shaping circuit 62 and the transistor 63 in each pixel, and therefore each pixel is configured as a circuit (hereinafter also referred to as a CLK-DET circuit) that controls the count of the SPAD with an external periodic signal. In this case, the period of the inspection pulse generated by the inspection pulse generation circuit 42 is shorter than the recharge period corresponding to the drive of the transistor 63. In other words, the period of the inspection pulse must be regular and shorter than the shortest recharge period in the operation of the CLK-DET circuit during inspection.

[0063] The counter circuit 65 counts the inspection pulses input via the waveform shaping circuit 62 and outputs a count value. The judgment circuit 66 judges whether the counter circuit 65 is normal or not based on the count value from the counter circuit 65 and outputs the judgment result. The counter circuit 65 and the judgment circuit 66 are the same as those shown in FIG. 3 and the like. The count value output from the counter circuit 65 and the judgment result output from the judgment circuit 66 are stored in the memory 44 via the signal line 48. This allows the memory 44 to store the count value and the judgment result for each pixel formed on the substrate 22 before bonding, so that the counter circuit 65 can identify defective pixels from among the pixels.

[0064] Thus, in the present disclosure, when the light receiving element 12 has a laminated structure formed by bonding substrates, a test sequence can be employed in which the test pulse generation circuit 42 is connected to the terminals of each pixel in the logic layer before bonding, with only the logic layer remaining. When testing is performed using this test sequence, there is no need to provide a selection circuit 64 upstream of the counter circuit 65 in each pixel, thereby reducing the area required. Furthermore, the photon detection circuit (waveform shaping circuit 62, transistor 63) upstream of the counter circuit 65 can also be simultaneously tested. Note that in FIG. 29 , the control circuit 43 and memory 44 may be included in the light receiving element 12, or may be provided in an external device and connected during testing. While FIG. 29 illustrates a configuration corresponding to the case where the counter circuit shown in FIG. 3 is not divided, a similar configuration can also be employed when the counter circuit shown in FIG. 18 is divided. For example, the logic circuit formed on the substrate 22 may include a counter circuit 140 (see FIG. 18, etc.) consisting of a counter circuit 141 and a counter circuit 142 instead of the counter circuit 65, and a judgment circuit 151 (see FIG. 18, etc.) instead of the judgment circuit 66, and the above-mentioned inspection sequence may be performed before the substrates are bonded together.

[0065] <<Sixteenth Embodiment>> Fig. 30 is a diagram for explaining an example of an inspection method when inspecting the pixel array section 41. Fig. 30 illustrates an example in which inspection is performed on each pixel formed in the pixel array section 41 after the substrates are bonded together in the two-layer stacked structure shown in Fig. 25 or the three-layer stacked structure shown in Fig. 27 .

[0066] 30 , during testing, the pixels 51 arranged in the pixel array unit 41 of the light-receiving element 12 are connected to the test pulse generation circuit 42, and a test sequence is performed. The test pulse generation circuit 42 generates test pulses and inputs them to each of the pixels 51 arranged in the pixel array unit 41 via a signal line 46. In each pixel 51, a selection circuit 64 selects the test pulse input from the test pulse generation circuit 42 and inputs it to a counter circuit 65. Here, the test pulse generation circuit 42 inputs the same test pulse to the pixel array unit 41, so that the test pulse input to each pixel can be common.

[0067] The counter circuit 65 counts the inspection pulses input from the selection circuit 64 and outputs a count value. The judgment circuit 66 judges whether the counter circuit 65 is normal or not based on the count value from the counter circuit 65 and outputs the judgment result. The counter circuit 65 and the judgment circuit 66 are the same as those shown in FIG. 3 and other figures. The count value output from the counter circuit 65 and the judgment result output from the judgment circuit 66 are stored in the memory 44 via the signal line 48. This allows the memory 44 to store the count value and the judgment result for each pixel 51 arranged in the pixel array unit 41, thereby making it possible to identify pixels 51 for which the counter circuit 65 is defective from among the pixels 51 arranged in the pixel array unit 41. Note that while FIG. 30 shows a configuration corresponding to the case where the counter circuit shown in FIG. 3 and other figures is not divided, a similar configuration can also be adopted when the counter circuit shown in FIG. 18 and other figures is divided. For example, instead of the pixel 51 in FIG. 30, the pixel 51 in FIG. 18 may be formed, and the inspection pulse from the inspection pulse generation circuit 42 in FIG. 30 may be input to the selection circuits 131 and 132 via the signal line 46.

[0068] 31 is a diagram showing an example of a configuration for performing signal processing using the determination results of each pixel arranged in a pixel array section 41. As shown in Fig. 31 , in the light receiving element 12, a defect correction circuit 52 and a non-volatile memory 53 are provided for a plurality of pixels 51 arranged in the pixel array section 41.

[0069] During inspection, the nonvolatile memory 53 records the judgment results for each pixel output from each of the multiple pixels 51 arranged in the pixel array unit 41. During imaging (normal counting), the nonvolatile memory 53 appropriately supplies the recorded judgment results for each pixel to the defect correction circuit 52. During normal counting, the defect correction circuit 52 is supplied with the count values ​​for each pixel from each of the multiple pixels 51 arranged in the pixel array unit 41 and the judgment results for each pixel from the nonvolatile memory 53. The defect correction circuit 52 corrects the count values ​​of the pixels to be corrected based on the judgment results for each pixel read out from the nonvolatile memory 53, and outputs the corrected values ​​(data).

[0070] For example, in a test sequence during testing, the following steps are repeated a specified number of times: (a) input of a test pulse to the counter circuit 65; (b) execution of a test by the determination circuit 66; (c) output of the determination result by the determination circuit 66; and (d) recording of the determination result in the nonvolatile memory 53 (the processes (a) through (d) are repeated the specified number of times). Note that (a) through (c) are performed for each pixel arranged in the pixel array unit 41. In step (d), the nonvolatile memory 53 records, for example, the coordinates of each pixel and the number of times it has been determined to be defective, according to the determination result of each pixel. The coordinates can be expressed as coordinates on an XY plane with a predetermined specific position as the origin, representing the positions of the pixels 51 arranged along the X-axis and Y-axis in the pixel array unit 41. A pixel in the pixel array unit 41 that has experienced a defect a certain number of times or more is considered a defective pixel, and the defect correction circuit 52 performs defect correction using the coordinates of the defective pixel.

[0071] The defect correction circuit 52 can perform the following defect correction process, for example. That is, the defect correction circuit 52 can replace the value (count value) output from a defective pixel with a representative value, such as a median or average value, obtained from the values ​​(count values) of pixels neighboring the defective pixel. For example, as shown in FIG. 32A, if a 3×3 square represents the pixels 51 arranged in the pixel array unit 41 and the central black square pixel is deemed to be a defective pixel, the circuit calculates the median of the values ​​of the eight pixels (neighboring pixels) arranged around the central black square pixel. Then, as shown in FIG. 32B, the defective pixel can be corrected by replacing the value of the central defective pixel with the median calculated from the neighboring pixels. Note that in FIGS. 32A and 32B, the different values ​​of each pixel are indicated by patterns applied to the squares corresponding to each pixel.

[0072] In this way, by recording the judgment results for each pixel arranged in the pixel array section 41 (for example, the coordinates of a defective pixel judged to be defective by the counter circuit 65) in the non-volatile memory 53 during inspection, the defect correction circuit 52 can perform correction only on defective pixels based on the judgment results for each pixel (for example, the coordinates of the defective pixel) during normal counting, thereby reducing degradation in resolution compared to when a filter (for example, a median filter) is applied to the values ​​of all pixels arranged in the pixel array section 41.

[0073] The correction processes shown in Figures 31 and 32 merely illustrate examples of recording and using the determination results for each pixel, and may be used in other signal processing. In the correction processes described above, the condition for determining a defective pixel is whether the pixel has experienced a certain number of defects, but other conditions may also be used. In the above description, the light-receiving element 12 includes the defect correction circuit 52 and the nonvolatile memory 53. However, an external signal processing device connected to the light-receiving element 12 may also include the defect correction circuit 52 and the nonvolatile memory 53. While Figure 31 illustrates a configuration corresponding to the case where the counter circuit is not divided, as shown in Figure 3, a similar configuration can also be used when the counter circuit is divided, as shown in Figure 18. For example, in Figure 18, the determination results by the determination circuit 151 may be output and recorded in the nonvolatile memory 53 during inspection, and the count values ​​by the counter circuits 141 and 142 may be output to the defect correction circuit 52 during normal counting. This allows the defect correction circuit 52 to correct the count value based on the determination result recorded in the nonvolatile memory 53 during normal counting.

[0074] <<Effects>> In the present disclosure, as shown in FIG. 3 and other figures, in the light receiving element 12, each pixel (pixel 51) arranged in the pixel array section 41 has a determination circuit 66 that determines whether the counter circuit 65 is normal based on the count value output from the counter circuit 65. During testing, after a predetermined number of test pulses are input, the determination circuit 66 in the pixel determines whether each bit of the counter circuit 65 is at the expected value, and outputs the determination result as a one-bit value indicating normal or defective. As a result, while in the past it took a readout time equal to the number of bits in the counter circuit, in the present disclosure, it only takes a readout time for one bit. Therefore, testing can be performed in a shorter time.

[0075] For example, the technology disclosed in the aforementioned Patent Document 1 includes a test input before the counter circuit, allowing the input to the counter circuit to be selected between a test pulse and a detection pulse from a SPAD element. Furthermore, a circuit that compares the count value with an expected value is provided outside the pixel, allowing the count value after the test pulse is input to be determined to be normal or not. Here, if the occurrence of a counter circuit defect is deterministic, a single test is sufficient. However, if probabilistic defects are to be detected, the test must be repeated multiple times. In the aforementioned Patent Document 1, the count value is read outside the pixel and compared with the expected value in an external judgment circuit. This can take a long time to read each time a test is performed, and therefore a proposal for a shorter test time has been sought. The present disclosure enables a shorter test time when probabilistic defects are to be detected.

[0076] In addition, in the present disclosure, as shown in FIG. 15 and other figures, in the light receiving element 12, when each pixel (pixel 51) arranged in the pixel array unit 41 has a counter circuit composed of a counter circuit 141 (e.g., a counter for the least significant bit) and a counter circuit 142 (e.g., a counter for the most significant bit), the pixel 51 includes a selection circuit 131 that selects either the detection pulse output by the waveform shaping circuit 62 or the check pulse output by the check pulse generation circuit 42, and a selection circuit 132 that selects either the carry-out output by the counter circuit 141 or the check pulse output by the check pulse generation circuit 42. During testing, multiple check pulses can be input to the counter circuit of each pixel (multiple test inputs can be provided), thereby shortening the time required to test all bits of the counter circuit. For example, by allowing test pulses to be input to both the upper and lower bits of the counter, the number of test pulses required to test each of the upper and lower bits can be significantly reduced, thereby significantly reducing the time required for the test inputs.

[0077] For example, in the technology disclosed in the aforementioned Patent Document 1, test pulses are input up to the counter's upper limit, which can increase the test time depending on the counter size. Therefore, proposals for shortening the test time are needed. In the present disclosure, by providing multiple test inputs to the counter circuit of each pixel, the time required to test all bits of the counter circuit can be reduced. In the present disclosure, when detecting probabilistic defects, the test can be performed in a shorter time. For example, in the present disclosure, when the counter circuit is a 14-bit counter, if counter circuits 141 and 142 are divided into upper and lower counters, only 7 test inputs for each counter are required, resulting in a 1 / 128 reduction in the test inputs compared to the conventional technology.

[0078] <<Modifications>> In the above explanation, the control unit 13 (FIG. 1) inputs a selection signal to a selection circuit such as the selection circuit 64 (FIG. 3) to control the selection of the selection circuit, but a control circuit included in the light-receiving element 12 (for example, the control circuit 43 in FIGS. 29 and 30) may control the selection circuit. That is, a selection circuit such as the selection circuit 64 may be controlled by a control circuit inside the light-receiving element 12, or may be controlled by an external control unit 13. Similarly, while the control unit 13 (FIG. 1) inputs and sets an initial value to a counter circuit such as the counter circuit 111 (FIG. 13), a control circuit included in the light-receiving element 12 may input and set an initial value to the counter circuit.

[0079] It should be noted that the embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. For example, each of the above-described embodiments may be implemented alone, or multiple embodiments may be combined and implemented. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0080] The present disclosure can also be configured as follows.

[0081] (1) A photodetector comprising a pixel array section in which pixels each having an avalanche photodiode element, a waveform shaping circuit that shapes the output of the avalanche photodiode element into a pulse, and a counter circuit that counts detection pulses output by the waveform shaping circuit or test pulses output by a test pulse generating circuit are arranged in an array, and the pixel has a determination circuit that determines whether the counter circuit is normal or not based on the count value output from the counter circuit. (2) The photodetector according to (1), wherein the counter circuit is a multi-bit counter, and the determination circuit makes a determination using the values ​​of all bits of the counter circuit. (3) The photodetector according to (2), wherein the determination circuit has a plurality of NOR gate circuits connected in an inverted pyramid shape with respect to the output of the counter circuit. (4) The photodetector according to (2), wherein the counter circuit is formed by a binary counter, and the determination circuit has a plurality of AND gate circuits connected in an inverted pyramid shape with respect to the output of the counter circuit. (5) The photodetector according to (2), wherein the counter circuit is a quaternary counter made up of a Johnson counter, and the decision circuit has an AND gate circuit connected in an inverted pyramid shape to the output of the counter circuit, and an inverter circuit for odd-numbered bit inputs of the output of the counter circuit. (6) The photodetector according to (1), wherein the counter circuit is a multi-bit counter, and the decision circuit makes a decision using the value of a specific bit of the counter circuit. (7) The photodetector according to (6), wherein the decision circuit has a falling edge detection circuit that detects the falling edge of a specific bit. (8) The photodetector according to (7), wherein the decision circuit further has a selection circuit that selects a specific bit from the output of the counter circuit for edge detection, and the falling edge detection circuit detects the falling edge of the specific bit selected by the selection circuit. (9) The photodetector according to any one of (1) to (8), wherein the pixel further has a selection circuit connected to the input side of the counter circuit and that selects either the detection pulse or the check pulse.(10) The photodetector according to any one of (1) to (9), wherein the counter circuit is a multi-bit counter, and an initial value is set for each bit before testing begins. (11) The photodetector according to any one of (1) to (10), wherein the pixel outputs the determination result of the determination circuit in parallel with the count value of the counter circuit. (12) The photodetector according to any one of (1) to (10), wherein the pixel further includes a selection circuit connected to the counter circuit and an output side of the determination circuit, and which selects and outputs either the count value of the counter circuit or the determination result of the determination circuit. (13) The photodetector according to any one of (1) to (12), wherein the photodetector has a layered structure in which a first layer including the avalanche photodiode element and a second layer including a logic circuit are layered. (14) The photodetector according to (13), having a two-layer laminated structure in which a first substrate on which the avalanche photodiode element is formed and a second substrate on which the logic circuit is formed are bonded together, wherein the waveform shaping circuit, the counter circuit, and the determination circuit are formed on the second substrate. (15) The photodetector according to (13), having a three-layer laminated structure in which a first substrate on which the avalanche photodiode element is formed, a second substrate on which a part of the logic circuit is formed, and a third substrate on which the remaining part of the logic circuit is formed are laminated together, wherein the waveform shaping circuit is formed on the second substrate, and the counter circuit and the determination circuit are formed on the third substrate. (16) The photodetector according to (1), having the inspection pulse generating circuit connected to the pixel and receiving the inspection pulse generated by the inspection pulse generating circuit. (17) The photodetector according to (16), wherein the inspection pulse is common to each pixel. (18) The light receiving element according to (16), wherein the pixel further includes a selection circuit connected to an input side of the counter circuit and selecting either the detection pulse or the inspection pulse, and during inspection, the selection circuit selects the inspection pulse to inspect the counter circuit.(19) The photodetector according to (16), having a two-layer structure in which a first substrate on which the avalanche photodiode element is formed and a second substrate on which the waveform shaping circuit, the counter circuit, and the determination circuit are formed are bonded together, and the inspection pulse generating circuit is connected to the second substrate before the first substrate and the second substrate are bonded together to inspect the counter circuit. (20) The photodetector according to (19), in which the count of the avalanche photodiode element of the pixel is controlled by an external periodic signal, and the period of the inspection pulse is shorter than a recharge period. (21) The photodetector according to any of (1) to (12) and (16) to (18), further comprising: a memory that records a determination result of the determination circuit; and a correction circuit that corrects the count value of the counter circuit based on the recorded determination result. (22) A photodetector comprising: a pixel array unit in which pixels each having an avalanche photodiode element, a waveform shaping circuit that shapes the output of the avalanche photodiode element into a pulse, and a counter circuit composed of a first counter circuit and a second counter circuit are arranged in an array, wherein the pixels each have: a first selection circuit connected to an input side of the first counter circuit and that selects either a detection pulse output by the waveform shaping circuit or an inspection pulse output by an inspection pulse generation circuit, and a second selection circuit connected to an input side of the second counter circuit and that selects either a carry-out output by the first counter circuit or the inspection pulse. (23) The photodetector according to (22), wherein, during imaging, the detection pulse is selected by the first selection circuit, the carry-out is selected by the second selection circuit, and counting is performed by the first counter circuit and the second counter circuit. (24) The light receiving element according to (22), wherein during inspection, the inspection pulse is selected by the first selection circuit, and the inspection pulse is selected by the second selection circuit, and inspection of the first counter circuit and the second counter circuit is performed.(25) The photodetector according to (22), wherein, during testing, the first selection circuit selects the test pulse, the second selection circuit selects a carry-out, and the second selection circuit selects the test pulse, thereby testing the first counter circuit and the second counter circuit. (26) The photodetector according to any of (22) to (25), wherein the counter circuit is a multi-bit counter, and an initial value is set for each bit of the first counter circuit and the second counter circuit before testing begins. (27) The photodetector according to any of (22) to (26), wherein the pixel has a determination circuit that determines whether the counter circuit is normal or not based on count values ​​output from the first counter circuit and the second counter circuit. (28) The photodetector according to any of (22) to (27), wherein the counter circuit is a multi-bit counter, and the first counter circuit is a counter corresponding to the least significant bit, and the second counter circuit is a counter corresponding to the most significant bit. (29) The photodetector according to (27), wherein the pixel is connected to the inspection pulse generating circuit and receives the inspection pulse generated by the inspection pulse generating circuit. (30) The photodetector according to (29), wherein the inspection pulse is common to each pixel. (31) The photodetector according to (29), wherein the photodetector has a two-layer structure in which a first substrate on which the avalanche photodiode element is formed and a second substrate on which the waveform shaping circuit, the counter circuit, and the determination circuit are formed are bonded together, and the inspection pulse generating circuit is connected to the second substrate before bonding the first substrate and the second substrate together to inspect the counter circuit. (32) The photodetector according to (31), wherein the count of the avalanche photodiode element in the pixel is controlled by an external periodic signal, and the period of the inspection pulse is shorter than a recharge period.(33) The light receiving element according to any one of (22) to (30), further comprising: a memory that records a determination result of the determination circuit; and a correction circuit that corrects the count value of the counter circuit based on the recorded determination result.

[0082] 1 Electronic device, 11 Optical system, 12 Light receiving element, 13 Control unit, 14 Memory unit, 21 Substrate, 22 Substrate, 23 Substrate, 41 Pixel array unit, 42 Inspection pulse generation circuit, 43 Control circuit, 44 Memory, 51 Pixel, 52 Defect correction circuit, 53 Non-volatile memory, 61 SPAD element, 62 Waveform shaping circuit, 63 Transistor, 64 Selection circuit, 65 Counter circuit, 66 Judgment circuit, 71 NOR gate circuit, 73 Register circuit, 81 AND gate circuit, 83 Register circuit, 84 Inverter circuit, 91 Falling edge detection circuit, 101 Selection circuit, 102 Falling edge detection circuit, 111 Counter circuit, 121 Selection circuit, 122 Shift register, 131 Selection circuit, 132 Selection circuit, 133 Selection circuit, 140 Counter circuit, 141 Counter circuit, 142 Counter circuit, 151 Decision circuit, 161 Decision circuit, 162 Decision circuit, 163 AND gate circuit, 171 Decision circuit, 172 Selection circuit

Claims

1. A light receiving element comprising: a pixel array section in which pixels each having an avalanche photodiode element; a waveform shaping circuit which shapes the output of the avalanche photodiode element into a pulse; and a counter circuit which counts detection pulses output by the waveform shaping circuit or inspection pulses output by an inspection pulse generating circuit are arranged in an array, and each of the pixels has a determination circuit which determines whether or not the counter circuit is normal based on the count value output by the counter circuit.

2. The light receiving element according to claim 1, wherein the counter circuit is a multi-bit counter, and the decision circuit makes a decision using the values ​​of all the bits of the counter circuit.

3. The light receiving element according to claim 2, wherein the decision circuit has a plurality of NOR gate circuits connected in an inverted pyramid shape to the output of the counter circuit.

4. The light receiving element according to claim 2, wherein the counter circuit is constituted by a binary counter, and the decision circuit has a plurality of AND gate circuits connected in an inverted pyramid shape to the output of the counter circuit.

5. The photodetector according to claim 2, wherein the counter circuit is composed of a quaternary counter consisting of a Johnson counter, and the decision circuit has an AND gate circuit connected in an inverted pyramid shape to the output of the counter circuit, and has an inverter circuit for odd-numbered bit inputs of the output of the counter circuit.

6. The light receiving element according to claim 1, wherein the counter circuit is a multi-bit counter, and the determination circuit makes a determination using a value of a specific bit of the counter circuit.

7. The light receiving element according to claim 6, wherein the determination circuit has a falling edge detection circuit for detecting the falling edge of a specific bit.

8. The light receiving element according to claim 7, wherein the determination circuit further comprises a selection circuit that selects a specific bit for edge detection from the output of the counter circuit, and the falling edge detection circuit detects the falling edge of the specific bit selected by the selection circuit.

9. The light receiving element according to claim 1, wherein the pixel further comprises a selection circuit connected to an input side of the counter circuit and configured to select either the detection pulse or the inspection pulse.

10. The light receiving element according to claim 1, wherein the counter circuit is a multi-bit counter, and an initial value is set for each bit before the start of testing.

11. The light receiving element according to claim 1, wherein the pixel outputs the determination result of the determination circuit in parallel with the count value of the counter circuit.

12. The photodetector according to claim 1, wherein the pixel further comprises a selection circuit connected to the output side of the counter circuit and the judgment circuit, for selecting and outputting either the count value of the counter circuit or the judgment result of the judgment circuit.

13. The photodetector according to claim 1, which has a laminated structure in which a first layer including the avalanche photodiode element and a second layer including a logic circuit are laminated.

14. The photodetector according to claim 13, which has a two-layer structure formed by bonding together a first substrate on which the avalanche photodiode element is formed and a second substrate on which the logic circuit is formed, and the waveform shaping circuit, the counter circuit, and the determination circuit are formed on the second substrate.

15. A photodetector as described in claim 13, comprising a three-layer structure in which a first substrate on which the avalanche photodiode element is formed, a second substrate on which a part of the logic circuit is formed, and a third substrate on which the remaining part of the logic circuit is formed, the waveform shaping circuit being formed on the second substrate, and the counter circuit and the determination circuit being formed on the third substrate.

16. The light receiving element according to claim 1, wherein the pixel is connected to the inspection pulse generating circuit and receives the inspection pulse generated by the inspection pulse generating circuit.

17. The light receiving element according to claim 16, wherein the inspection pulse is common to each pixel.

18. The photodetector according to claim 16, wherein the pixel further comprises a selection circuit connected to an input side of the counter circuit and configured to select either the detection pulse or the inspection pulse, and during inspection, the selection circuit selects the inspection pulse to inspect the counter circuit.

19. The photodetector according to claim 16, comprising a two-layer laminated structure in which a first substrate on which the avalanche photodiode element is formed and a second substrate on which the waveform shaping circuit, the counter circuit and the judgment circuit are formed are bonded together, and the inspection pulse generating circuit is connected to the second substrate before bonding the first substrate and the second substrate together to inspect the counter circuit.

20. The light receiving element according to claim 19, wherein the pixel has a count of the avalanche photodiode element controlled by an external periodic signal, and the period of the inspection pulse is shorter than a recharge period.

21. The light receiving element according to claim 16, further comprising: a memory for recording a determination result of said determination circuit; and a correction circuit for correcting the count value of said counter circuit based on said recorded determination result.

22. A light receiving element comprising: a pixel array section in which pixels having: an avalanche photodiode element; a waveform shaping circuit that shapes the output of the avalanche photodiode element into a pulse; and a counter circuit composed of a first counter circuit and a second counter circuit, are arranged in an array, wherein the pixels have: a first selection circuit connected to the input side of the first counter circuit and selecting either a detection pulse output by the waveform shaping circuit or an inspection pulse output by an inspection pulse generation circuit; and a second selection circuit connected to the input side of the second counter circuit and selecting either a carry out output by the first counter circuit or the inspection pulse.

23. The light receiving element according to claim 22, wherein, during imaging, the detection pulse is selected by the first selection circuit, a carry-out is selected by the second selection circuit, and counting is performed by the first counter circuit and the second counter circuit.

24. The light receiving element according to claim 22, wherein during inspection, the inspection pulse is selected by the first selection circuit, and the inspection pulse is selected by the second selection circuit to inspect the first counter circuit and the second counter circuit.

25. The photodetector according to claim 22, wherein during testing, the first counter circuit and the second counter circuit are tested by selecting the test pulse with the first selection circuit, selecting a carry-out with the second selection circuit, and then selecting the test pulse with the second selection circuit.

26. The light receiving element according to claim 22, wherein the counter circuit is a multi-bit counter, and an initial value is set in each bit of the first counter circuit and the second counter circuit before the start of testing.

27. The light receiving element according to claim 22, wherein the pixel has a determination circuit that determines whether the counter circuit is normal or not based on the count values ​​output from the first counter circuit and the second counter circuit.

28. The light receiving element according to claim 22, wherein the counter circuit is a multi-bit counter, the first counter circuit is a counter corresponding to the least significant bit, and the second counter circuit is a counter corresponding to the most significant bit.

29. The light receiving element according to claim 27, wherein the pixel is connected to the inspection pulse generating circuit and receives the inspection pulse generated by the inspection pulse generating circuit.

30. The light receiving element according to claim 29, wherein the inspection pulse is common to each pixel.

31. The photodetector according to claim 29, comprising a two-layer laminated structure in which a first substrate on which the avalanche photodiode element is formed and a second substrate on which the waveform shaping circuit, the counter circuit and the judgment circuit are formed are bonded together, and the inspection pulse generating circuit is connected to the second substrate before bonding the first substrate and the second substrate together to inspect the counter circuit.

32. The light receiving element according to claim 31, wherein the pixel has a count of the avalanche photodiode element controlled by an external periodic signal, and the period of the inspection pulse is shorter than a recharge period.

33. The light receiving element according to claim 29, further comprising: a memory for recording a determination result of said determination circuit; and a correction circuit for correcting the count value of said counter circuit based on said recorded determination result.

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