Bridging packaging structure and forming method therefor

Abstract

The present invention relates to the technical field of semiconductor packaging, and disclosed are a bridging packaging structure and a forming method therefor. The bridging packaging structure comprises: a plurality of chips; a silicon bridge structure in bridge connection with the plurality of chips; metal columns located beside the silicon bridge structure; a first interconnection structure electrically connected to the silicon bridge structure and the metal columns; and a second interconnection structure electrically connected to the plurality of chips, the silicon bridge structure, and the metal columns. By using the silicon bridge structure based on TSV interposer technology, vertical and horizontal interconnection can be realized, and the interconnection density is high.

Description

A bridge package structure and its forming method Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a bridge packaging structure and a forming method thereof. Background Art

[0002] 2.5D packaging is the primary packaging format for high-computing and high-performance applications, as it enables the shortest vertical interconnects and planar submicron interconnects. However, high process costs limit its application in other products. Silicon bridge technology combines the advantages of 2.5D packaging's high-density interconnects with its relatively small size, effectively reducing interconnect costs. This provides a more flexible packaging solution for products with high interconnect density and performance requirements.

[0003] The current main silicon bridge technology is to produce high-density wiring and fine-pitch micro-bumps on a silicon substrate, and achieve horizontal high-density interconnection between chips through substrate embedment or fan-out packaging integration. It cannot achieve horizontal + three-dimensional integrated interconnection.

[0004] Summary of the Invention

[0005] To solve at least some of the above problems in the prior art, the present invention provides a bridge packaging structure, comprising:

[0006] Multiple chips;

[0007] a silicon bridge structure bridging the plurality of chips;

[0008] a metal pillar located next to the silicon bridge structure;

[0009] a first interconnect structure electrically connected to the silicon bridge structure and the metal pillar; and

[0010] A second interconnection structure is electrically connected to the plurality of chips, the silicon bridge structure and the metal pillar.

[0011] Furthermore, the silicon bridge structure includes:

[0012] An adapter plate comprising:

[0013] substrate;

[0014] a conductive through-silicon via extending through the substrate; and

[0015] a first interconnection layer, which is located on the first surface of the adapter plate and is electrically connected to the conductive silicon via;

[0016] a first bump, which is provided on a side of the first interconnect layer facing away from the substrate and is electrically connected to the first interconnect layer;

[0017] a first plastic encapsulation layer, which encapsulates the first bump, with ends of the first bump exposed from the first plastic encapsulation layer;

[0018] a second interconnect layer disposed on a second side of the interposer, the second side of the interposer being opposite to the first side; and

[0019] The second bump is arranged on a side of the second interconnect layer facing away from the transfer board.

[0020] Further, the first bump is electrically connected to the second interconnect structure; and the second bump is electrically connected to the first interconnect structure.

[0021] Furthermore, an IPD capacitor and a DTC capacitor are integrated in the substrate of the adapter board.

[0022] Furthermore, it also includes:

[0023] a second plastic encapsulation layer, which plastic encapsulates the silicon bridge structure and the metal pillar, with both ends of the metal pillar and the first surface and the opposite second surface of the silicon bridge structure exposed;

[0024] a third plastic encapsulation layer, which plastic encapsulates the plurality of chips; and

[0025] An underfill is filled between the chip and the second interconnect structure.

[0026] Furthermore, the first interconnection structure is located on the second surface of the second plastic packaging layer;

[0027] The second interconnect structure is located on the first surface of the second plastic packaging layer; and

[0028] The plurality of chips are arranged on a side of the second interconnect structure away from the second plastic packaging layer.

[0029] The present invention also provides a method for forming a bridge package structure, comprising:

[0030] Arranging a first bump on a first side of an interposer, wherein the interposer includes a substrate; a conductive through-silicon via (TSV) located in the substrate, with one end of the conductive through-silicon via exposed and the other end located in the substrate; and a first interconnect layer located on the first side of the interposer and electrically connected to the conductive through-silicon via;

[0031] Plastic-sealing the first bumps to form a first plastic-sealing layer that wraps the first bumps;

[0032] thinning the second surface of the adapter plate to expose the conductive through silicon via;

[0033] Arranging a second interconnect layer on a second surface of the adapter board, and arranging second bumps on a surface of the second interconnect layer facing away from the adapter board, wherein the second surface of the adapter board is opposite to the first surface; and

[0034] Cut the adapter plate to obtain the silicon bridge structure.

[0035] Furthermore, it also includes:

[0036] Arranging a first interconnect structure on the second carrier wafer, and arranging a metal pillar on a side of the first interconnect structure facing away from the second carrier wafer;

[0037] Arranging the silicon bridge structure on a side of the first interconnect structure facing away from the second carrier;

[0038] Plastic-sealing the silicon bridge structure and the metal pillar to form a second plastic-sealing layer surrounding the silicon bridge structure and the metal pillar;

[0039] thinning the first surface of the second plastic packaging layer to expose the silicon bridge structure and the metal pillar;

[0040] Arranging the second interconnect structure on the first surface of the second plastic packaging layer;

[0041] Flip-chipping a plurality of chips on a side of the second interconnect structure facing away from the second plastic packaging layer, and filling underfill between the chips and the second interconnect structure;

[0042] Plastic-sealing the chip to obtain a third plastic-sealing layer; and

[0043] The second carrier is removed, and solder balls are arranged on a surface of the first interconnect structure facing away from the third plastic packaging layer.

[0044] Further, the first interconnect structure is electrically connected to the second bump of the silicon bridge structure and the metal pillar;

[0045] The second interconnect structure is electrically connected to the first bump of the silicon bridge structure and the metal pillar;

[0046] The substrate of the adapter board is integrated with IPD capacitors and DTC capacitors.

[0047] Furthermore, before the second surface of the adapter plate is thinned, the first plastic packaging layer and the first carrier are bonded together by a temporary bonding adhesive; and

[0048] Cutting the transfer plate also includes removing the first carrier and temporary bonding glue.

[0049] The present invention has at least the following beneficial effects: the present invention discloses a bridge packaging structure and a method for forming the same, which adopts a silicon bridge structure of TSV adapter board technology, can realize vertical and horizontal interconnection with high interconnection density; copper bumps and plastic encapsulation protection are used on one side of the adapter board, which is conducive to subsequent integration; IPD and DTC capacitors can be integrated inside the TSV adapter board to improve system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding parts will be represented by the same or similar reference numerals.

[0051] FIG1 is a cross-sectional view of a bridge package structure according to an embodiment of the present invention;

[0052] FIG2 shows a cross-sectional schematic diagram of an adapter plate having a first bump according to an embodiment of the present invention;

[0053] FIG3 is a schematic diagram showing a first bump plastic package according to an embodiment of the present invention;

[0054] FIG4 shows a schematic diagram of a plastic layer bonded to a carrier according to an embodiment of the present invention;

[0055] FIG5 is a schematic diagram showing a thinned adapter plate according to an embodiment of the present invention;

[0056] FIG6 is a schematic diagram showing an embodiment of the present invention after the second interconnect layer and the second bumps are arranged on the interposer;

[0057] FIG7 shows a cross-sectional schematic diagram of a silicon bridge structure according to an embodiment of the present invention;

[0058] FIG8 is a schematic diagram showing a metal column arranged on a slide surface according to an embodiment of the present invention;

[0059] FIG9 is a schematic diagram showing a silicon bridge structure arranged on a wafer surface according to an embodiment of the present invention;

[0060] FIG10 shows a schematic diagram of a silicon bridge structure and metal pillars after plastic packaging according to an embodiment of the present invention;

[0061] FIG11 is a schematic diagram showing a thinned plastic layer according to an embodiment of the present invention;

[0062] FIG12 is a schematic diagram showing a second interconnect structure disposed on a first surface of a second plastic encapsulation layer according to an embodiment of the present invention;

[0063] FIG13 is a schematic diagram showing a flip-chip arrangement according to an embodiment of the present invention;

[0064] FIG14 shows a schematic diagram of a plastic-encapsulated chip according to an embodiment of the present invention; and

[0065] FIG. 15 is a schematic diagram showing a first interconnect structure after solder balls are arranged according to an embodiment of the present invention.

[0066] Reference numerals: 101 adapter board; 1011 substrate; 1012 conductive silicon via; 1013 first dielectric layer; 1014 first redistribution layer; 102 first bump; 103 first plastic layer; 104 second dielectric layer; 105 second redistribution layer; 106 second bump; 107 second plastic layer; 108 metal pillar; 109 first interconnect structure; 1091 first insulating layer; 1092 first wiring layer; 110 solder ball; 111 second interconnect structure; 1111 second insulating layer; 1112 second wiring layer; 112 chip; 113 underfill; 114 third plastic layer; 201 adapter board; 20 11 substrate; 2012 conductive silicon via; 2013 first dielectric layer; 2014 first redistribution layer; 202 first bump; 203 first plastic layer; 204 first carrier; 205 second bump; 206 second dielectric layer; 207 second redistribution layer; 200 silicon bridge structure; 301 second carrier; 302 first interconnect structure; 3021 first insulating layer; 3022 first wiring layer; 303 metal pillar; 304 second plastic layer; 305 second interconnect structure; 3051 second insulating layer; 3052 second wiring layer; 306 chip; 307 underfill; 308 third plastic layer; 309 solder ball. DETAILED DESCRIPTION

[0067] It should be noted that components in the drawings may be shown exaggerated for illustrative purposes and are not necessarily true to scale.

[0068] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0069] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the presence of multiple elements.

[0070] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person skilled in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario.

[0071] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the two values ​​are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0072] It should also be noted that in the description of the present invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the present invention. They do not explicitly or implicitly state that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0073] In addition, the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0074] FIG1 shows a cross-sectional schematic diagram of a silicon bridge package structure according to an embodiment of the present invention.

[0075] As shown in FIG1 , a silicon bridge package structure includes a silicon bridge structure, a second plastic layer 107 , metal pillars 108 , a first interconnect structure 109 , solder balls 110 , a second interconnect structure 111 , a chip 112 , an underfill 113 and a third plastic layer 114 .

[0076] The silicon bridge structure bridges the plurality of chips 112 and includes an adapter plate 101 , first bumps 102 , a first plastic layer 103 , a second interconnect layer and second bumps 106 .

[0077] The adapter board 101 includes a substrate 1011, conductive through-silicon vias 1012, and a first interconnect layer. The conductive through-silicon vias 1012 extend through the substrate 1011. The first interconnect layer is located on the first side of the adapter board 101. The first interconnect layer includes a first dielectric layer 1013 and a first redistribution layer 1014. The first redistribution layer 1014 is located within the first dielectric layer 1013, with the first dielectric layer 1013 exposed on the surface. The adapter board substrate 1011 integrates IPD capacitors and DTC capacitors.

[0078] The first bump 102 is disposed on a side of the first interconnect layer facing away from the substrate 1011 . The first bump 102 is electrically connected to the first redistribution layer 1014 .

[0079] The first plastic encapsulation layer 103 encapsulates the first bump 102 , and ends of the first bump 102 are exposed from the first plastic encapsulation layer 103 .

[0080] The second interconnect layer is disposed on the second side of the adapter board 101, which faces the first side. The second interconnect layer includes a second dielectric layer 104 and a second redistribution layer 105. The second redistribution layer 105 is disposed within the second dielectric layer 104, with the second dielectric layer 104 exposed on its surface. The second redistribution layer 105 is electrically connected to the conductive through-silicon vias 1012.

[0081] The second bumps 106 are disposed on a side of the second interconnect layer facing away from the transfer board 101 , and the second bumps 106 are electrically connected to the second redistribution layer 105 .

[0082] The second plastic encapsulation layer 107 encapsulates the silicon bridge structure, and a portion of the silicon bridge structure is exposed from the second plastic encapsulation layer 107 .

[0083] The metal pillar 108 passes through the second plastic encapsulation layer 107 and is located next to the silicon bridge structure. Both ends of the metal pillar 108 are not covered by the second plastic encapsulation layer 107.

[0084] First interconnect structure 109 is disposed on the second surface of second plastic layer 107. First interconnect structure 109 is electrically connected to metal pillars 108 and the silicon bridge structure. First interconnect structure 109 includes multiple first insulating layers 1091 and multiple first wiring layers 1092. First wiring layers 1092 are disposed within first insulating layer 1091 and are electrically connected to each other. First wiring layers 1092 are electrically connected to metal pillars 108 and second bumps 106.

[0085] The solder balls 110 are disposed on a side of the first interconnect structure 109 facing away from the second plastic layer 107 .

[0086] Second interconnect structure 111 is disposed on the first surface of second plastic encapsulation layer 107, with the first surface and second surface of second plastic encapsulation layer 107 facing each other. Second interconnect structure 111 is electrically connected to metal pillars 108 and the silicon bridge structure. Second interconnect structure 111 includes a second insulating layer 1111 and a second wiring layer 1112. Second wiring layer 1112 is located within second insulating layer 1111, with the second insulating layer 1111 exposed on its surface. Second wiring layer 1112 is electrically connected to metal pillars 108 and first bumps 102.

[0087] A plurality of chips 112 are flip-chip mounted on a side of the second interconnect structure 111 facing away from the second plastic encapsulation layer 107. The front side of the chips 112 has bumps, and the bumps of the chips 112 are connected to the second wiring layer 1112.

[0088] The underfill 113 is filled between the chip 112 and the second interconnect structure 111 .

[0089] The third plastic encapsulation layer 114 encapsulates the chip 112 .

[0090] A method for forming a silicon bridge package structure includes:

[0091] Step 1, as shown in FIG2 , arranges first bumps 202 on the first side of adapter board 201. Adapter board 201 includes a substrate 2011, conductive through-silicon vias 2012, and a first interconnect layer. The conductive through-silicon vias 2012 are located in substrate 2011 but do not penetrate through it. One end of the conductive through-silicon vias 2012 is exposed, while the other end is located in substrate 2011. The first interconnect layer, located on the first side of adapter board 201, includes a first dielectric layer 2013 and a first redistribution layer 2014. The first redistribution layer 2014 is located in the first dielectric layer 2013 and has an exposed surface. The first redistribution layer 2014 is electrically connected to the conductive through-silicon vias 2012.

[0092] A photoresist is applied to the first surface of the adapter board 201. A portion of the photoresist covering the first redistribution layer 2014 is removed through a photolithography process to form a bump pattern. Metal is then filled to form the first bumps 202. Finally, the photoresist is removed. The first bumps 202 are copper bumps electrically connected to the first redistribution layer 2014.

[0093] IPD and DTC capacitors may be integrated inside the substrate 2011 of the adapter board 201 .

[0094] In step 2, as shown in FIG. 3 , the first bumps 202 are plastic-encapsulated to form a first plastic-encapsulation layer 203 that encapsulates the first bumps 202 .

[0095] Step 3, as shown in FIG4 , the first plastic encapsulation layer 203 is bonded to the first carrier sheet 204 by using a temporary bonding adhesive.

[0096] In step 4, as shown in FIG5 , the second surface of the adapter plate 201 is thinned to expose the conductive through silicon vias 2012. The second surface of the adapter plate 201 is opposite to the first surface.

[0097] In step 5, as shown in FIG6 , a second interconnect layer is arranged on the second surface of the interposer 201, and second bumps 205 are arranged on the side of the second interconnect layer facing away from the interposer. The second interconnect layer includes a second dielectric layer 206 and a second redistribution layer 207. The second redistribution layer 207 is located within the second dielectric layer 206 and has an exposed surface. The second redistribution layer 207 is electrically connected to the conductive through-silicon vias 2012.

[0098] A second dielectric layer 206 is coated on the second side of the adapter board 201, and a circuit pattern is etched. The circuit pattern is then filled with metal to form a second redistribution layer 207. A photoresist is applied to the side of the second interconnect layer facing away from the adapter board 201. A portion of the photoresist covering the second redistribution layer 207 is removed through a photolithography process to form a bump pattern. The pattern is then filled with metal to form second bumps 205, and the photoresist is finally removed. The second bumps 205 are electrically connected to the second redistribution layer 207.

[0099] In step 6, as shown in FIG. 7 , the first carrier 204 and the temporary bonding adhesive are removed, and the adapter plate 201 is cut to obtain a single silicon bridge structure 200 .

[0100] Step 7, as shown in Figure 8, applies a temporary bonding glue on the second carrier 301, and arranges the first interconnection structure 302 on the surface of the temporary bonding glue, and arranges the metal pillar 303 on the side of the first interconnection structure 302 facing away from the second carrier 301. Specifically, the first interconnection structure 302 includes a multi-layer first insulating layer 3021 and a multi-layer first wiring layer 3022. The first insulating layer 3021 is coated on the surface of the temporary bonding glue, and a circuit pattern is formed by etching. The circuit pattern is filled with metal to obtain the first wiring layer 3022. Repeating this process multiple times can obtain a multi-layer first wiring layer. The multi-layer first wiring layers 3022 are electrically connected. The metal pillars 303 can be arranged on the surface of the first wiring layer 3022 by welding, and the first interconnection structure 302 is electrically connected to the metal pillars 303. The metal pillars 303 are located at the edge of the second carrier 301.

[0101] In step 8, as shown in FIG9 , a silicon bridge structure 200 is placed on the side of the first interconnect structure 302 facing away from the second carrier 301. The silicon bridge structure 200 is placed in the middle, between the plurality of metal pillars 303. The second bump 205 of the silicon bridge structure 200 is connected to the first wiring layer 3022.

[0102] In step 9, as shown in FIG. 10 , the silicon bridge structure 200 and the metal pillar 303 are plastic-encapsulated to form a second plastic-encapsulation layer 304 surrounding the silicon bridge structure 200 and the metal pillar 303 .

[0103] In step 10, as shown in FIG11 , the first surface of the second plastic encapsulation layer 304 is thinned to expose the silicon bridge structure 200 and the metal pillar 303. The first surface of the second plastic encapsulation layer 304 is the surface facing away from the second carrier 301.

[0104] In step 11, as shown in FIG12 , a second interconnect structure 305 is arranged on the first surface of the second plastic encapsulation layer 304. Specifically, the second interconnect structure 305 includes a second insulating layer 3051 and a second wiring layer 3052. The second insulating layer 3051 is coated on the first surface of the second plastic encapsulation layer 304, and then etched to form a circuit pattern. The circuit pattern is then filled with metal to obtain the second wiring layer 3052. The second wiring layer 3052 is electrically connected to the first bump 202 and the metal pillar 303 of the silicon bridge structure 200.

[0105] In step 12, as shown in FIG13 , multiple chips 306 are flip-chipped and arranged on the side of the second interconnect structure 305 facing away from the second plastic layer 304, and underfill 307 is filled between the chips 306 and the second interconnect structure 305. The front side of the chips 306 has bumps, which are connected to the second wiring layer 3052.

[0106] In step 13 , as shown in FIG. 14 , the chip 306 is plastic-encapsulated to obtain a third plastic-encapsulation layer 308 .

[0107] In step 14 , as shown in FIG. 15 , the second carrier 301 and the temporary bonding adhesive are removed, and solder balls 309 are arranged on the surface of the first interconnect structure 302 facing away from the second molding layer 304 .

[0108] Although certain embodiments of the present invention have been described in this application, those skilled in the art will appreciate that these embodiments are provided by way of example only. Numerous variations, alternatives, and modifications will be contemplated by those skilled in the art in light of the teachings of this disclosure without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and are intended to encompass methods and structures within the scope of these claims and their equivalents.

Claims

1. A bridge package structure, characterized in that: include: Multiple chips; A silicon bridge structure, which bridges the plurality of chips, the silicon bridge structure comprising: The adapter plate comprises: substrate; a conductive through silicon via extending through the substrate; and A first interconnect layer is located on the first surface of the adapter plate and is electrically connected to the conductive silicon via. A first bump, which is arranged on a side of the first interconnect layer away from the substrate and is electrically connected to the first interconnect layer; a first plastic encapsulation layer, which encapsulates the first bump, and an end of the first bump is exposed from the first plastic encapsulation layer; A second interconnect layer is disposed on a second side of the interposer, the second side of the interposer being opposite to the first side; and A second bump is arranged on a side of the second interconnect layer away from the transfer board; a metal column is located beside the silicon bridge structure; A first interconnect structure electrically connected to the silicon bridge structure and the metal pillar; and The second interconnection structure is electrically connected to the plurality of chips, the silicon bridge structure and the metal pillar.

2. The bridge package structure according to claim 1, characterized in that: The first bump is electrically connected to the second interconnect structure; and the second bump is electrically connected to the first interconnect structure.

3. The bridge package structure according to claim 1, characterized in that: The substrate of the adapter board is integrated with IPD capacitors and DTC capacitors.

4. The bridge package structure according to claim 1, characterized in that: Also includes: A second plastic sealing layer, which plastic seals the silicon bridge structure and the metal column, and both ends of the metal column and the first surface and the opposite second surface of the silicon bridge structure are exposed; A third plastic sealing layer, which plastic seals the plurality of chips; as well as An underfill is filled between the chip and the second interconnect structure.

5. The bridge package structure according to claim 4, characterized in that: The first interconnection structure is located on the second surface of the second plastic packaging layer; The second interconnect structure is located on the first surface of the second plastic packaging layer; as well as The plurality of chips are arranged on a side of the second interconnect structure away from the second plastic packaging layer.

6. A method for forming a bridge package structure, characterized in that: include: The first bump is arranged on the first surface of the transfer board, wherein the transfer board includes a substrate; a conductive silicon through hole, which is located in the substrate, and one end of the conductive silicon through hole is exposed and the other end is located in the substrate; and a first interconnect layer, which is located on the transfer board a first side of the board and electrically connected to the conductive through silicon via; Plastic-sealing the first bumps to form a first plastic-sealing layer that wraps the first bumps; Thinning the second surface of the adapter plate to expose the conductive through silicon via; Arranging a second interconnection layer on the second surface of the adapter board, and arranging second bumps on a surface of the second interconnection layer facing away from the adapter board, the second surface of the adapter board being opposite to the first surface; as well as Cut the adapter plate to obtain the silicon bridge structure.

7. The method for forming a bridge package structure according to claim 6, characterized in that: Also includes: Arranging a first interconnection structure on the second carrier wafer, and arranging a metal column on a side of the first interconnection structure facing away from the second carrier wafer; Arranging the silicon bridge structure on a side of the first interconnect structure facing away from the second carrier; Plastic-encapsulating the silicon bridge structure and the metal column to form a second plastic-encapsulation layer surrounding the silicon bridge structure and the metal column; Thinning the first surface of the second plastic packaging layer to expose the silicon bridge structure and the metal column; Arranging the second interconnect structure on the first surface of the second plastic packaging layer; Arrange multiple chips flip-chip on a side of the second interconnect structure away from the second plastic packaging layer, and fill underfill between the chips and the second interconnect structure; Plastic-sealing the chip to obtain a third plastic-sealing layer; as well as The second carrier is removed, and solder balls are arranged on a surface of the first interconnect structure facing away from the third plastic packaging layer.

8. The method for forming a bridge package structure according to claim 7, characterized in that: The first interconnect structure is electrically connected to the second bump of the silicon bridge structure and the metal pillar; The second interconnect structure is electrically connected to the first bump of the silicon bridge structure and the metal pillar; The substrate of the adapter board is integrated with IPD capacitors and DTC capacitors.

9. The method for forming a bridge package structure according to claim 6, characterized in that: Before the second surface of the adapter plate is thinned, the first plastic encapsulation layer and the first carrier are bonded by a temporary bonding adhesive; and The first carrier and temporary bonding glue are removed before cutting the transfer plate.

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