Row hammer event tracking

Abstract

A random access memory device includes memory cells associated with each row for storing metadata related to accesses to that row. Events that may cause row hammer may be tracked on a row-by-row basis by counter values in the metadata dedicated cells. The counter values are stored in a subset of rows of the metadata dedicated memory array. Multiple counter values (e.g., those associated with multiple victim and / or aggressor rows) may be read and / or written with a single activation of the metadata dedicated row. The metadata dedicated row stores the counter values for both the accessed data row and nearby data rows, the metadata counter value(s) associated with both the accessed data some nearby data rows may be updated using the single access to the metadata dedicated row.

Description

ROW HAMMER EVENT TRACKING BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figures 1 A-1H are diagrams illustrating a memory system and memory system operation.

[0002] Figures 2A-2B are diagrams illustrating a memory array tile (MAT) stripe and an example MAT data storage configuration.

[0003] Figure 3 is a diagram illustrating a multiple MAT stripe data storage configuration.

[0004] Figure 4 is a diagram illustrating a MAT stripe configuration.

[0005] Figure 5A is a diagram illustrating the relationship between a suspected aggressor row and victim row levels.

[0006] Figure 5B is a diagram illustrating victim row levels across different row groups.

[0007] Figure 6 is a flowchart illustrating a method of operating a memory component.

[0008] Figure 7 is a flowchart illustrating a method of operating a memory system.

[0009] Figure 8 is a flowchart illustrating a method of reducing power consumption.

[0010] Figure 9 is a flowchart illustrating a method of updating event counts.

[0011] Figure 10 is a block diagram of a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] Repeated row activations and / or refreshes of the same row (a.k.a., “aggressor row”) in a dynamic random access memory (DRAM) device (whether malicious or accidental) can cause cells of rows (a.k.a., “victim rows”) in the neighborhood of the aggressor row to lose a stored value. This effect on DRAM storage reliability has been termed “row hammer.” Row hammer, when applied to the multiple, parallel, DRAM device accesses that may occur with memory modules, can cause multiple errors across multiple DRAM devices on the module that are possibly uncorrectable and / or undetectable.

[0013] In an embodiment, a random access memory device includes memory cells associated with each row for storing metadata related to accesses to that row. For example, these metadata dedicated memory cells may store counter values to be updated (e.g., increment or decremented) when certain events occur (e.g., activate row - ACT, column read — CAS, error detected, etc.). In particular, events that may cause row hammer may be tracked on a row-by-row basis by counter values in the metadata dedicated cells.

[0014] In an embodiment, the counter values are stored in a subset of rows of the metadata dedicated memory array. For example, one row of metadata dedicated cells maystore the counter values associated with four (4) or eight (8) data rows in the neighborhood of that metadata dedicated row. In this manner, multiple counter values (e.g., those associated with multiple victim and / or aggressor rows) may be read and / or written with a single activation of the metadata dedicated row. In other words, when a data row is accessed, the metadata dedicated row associated with that data row is also accessed — even though the metadata dedicated row may have a different internal row address than the data row. Since the metadata dedicated row stores the counter values for both the accessed data row and nearby data rows, the metadata counter value(s) associated with both the accessed data some nearby data rows may be updated using the single access to the metadata dedicated row.

[0015] Figures 1 A-1H are diagrams illustrating a memory system and memory system operation. In Figures 1 A-1H In Figure 1, memory system 100 comprises memory device 110 and memory controller 120. Memory device 110 includes command / address (CA) interface 111, data (DQ) interface 112, memory array 130, row circuitry 131, column circuitry 132, metadata / counter operations circuitry 141, and control circuitry 145. Metadata / counter operations circuitry 141 includes configuration circuitry 141a, control circuitry 141b, function circuitry 141c, and update circuitry 14 Id. The rows and columns of memory array 130 may be organized into rows and columns of memory array tiles (MATs). Memory controller 120 includes CA interface 121, DQ interface 122, and metadata / counter operation configuration control circuitry 125.

[0016] CA interface 121 of controller 120 is operatively coupled to CA interface 111 of memory device 110. CA interface 121 of controller 120 is operatively coupled to CA interface 111 of memory device 110 to at least communicate, from controller 120, commands, addresses, and configuration information to memory device 110. DQ interface 122 of controller 120 is operatively coupled to DQ interface 112 of memory device 110. DQ interface 122 of controller 120 is operatively coupled to DQ interface 112 of memory device 110 to communicate data between controller 120 and memory device 110.

[0017] Memory controller 120 and memory device 110 may be integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as memory controller 120, manages the flow of data going to and from memory devices and / or memory modules. Memory device 110 may be a standalone device, or may be a component of a memory module such as a DIMM module used in servers. Memory device 110 may be, or be part of, a component having a “stack” of memory devices. Memory device 110 may be a device that adheres to, or is compatible with, a dynamic random access memory (DRAM) specification. A memory controller can be a separate, standalone chip, or integrated intoanother chip. For example, a memory controller 120 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect.

[0018] CA interface 111 of memory device 110 is operatively coupled to row circuitry 131, column circuitry 132, and metadata / counter operations circuitry 141. CA interface 111 is operatively coupled to row circuitry 131 to at least to activate rows in memory array 130. CA interface 111 is operatively coupled to column circuitry 132 to at least sense values from activated rows, and to decode and provide the values of selected columns to other circuitry of memory device 110 (e.g., metadata / counter operations circuitry 141, DQ interface 112, etc.)

[0019] Memory array 130 of memory device 110 is logically subdivided into column groups 130a-130b (or MAT groups, columns ofMATs, sections, assignments, and / or associations). Row data column group 130a is to store data provided by controller 120. Metadata / counter information field 130b is to store metadata associated with the rows in memory array 130. Metadata / counter information field 130b Thus, it should be understood that each row of memory array 130 may be viewed as comprising two “fields” - a data field and a metadata field. In an embodiment, the metadata / counter field of a row may be confined to a single MAT (a.k.a., metadata MAT) that has fewer columns than the MATs of the data field. This single metadata / counter MAT may be operated at a different (e.g., faster) access timing.

[0020] In an embodiment, a subset of rows of the metadata MAT are configured to store a plurality of counter values or other information related to a plurality of rows that these rows are respectively associated with (e.g., nearby and / or commonly addressed) In other words, for example, a respective one of the subset of rows in a metadata MAT is / will be activated in response to in response to the row addresses of the rows that metadata MAT row is associated with (a.k.a., row group) . At least how and when the metadata values associated with the rows of this metadata MAT are used and / or updated may be based on the configuration (e.g., stored by configuration circuitry 141a) of metadata / counter operations circuitry 141 provided by controller 120.

[0021] Figure IB is an illustration of information fields in a memory array row. In Figure IB, rows 150-154 (a.k.a., row information entries 150-154, respectively) include respective row data fields 150a- 154a and respective metadata fields 150b-154b. Metadata field #1 151b stores metadata associated with the data fields 151a-153a of row #1 151 through row #N 153,respectively. Metadata field #1 151b does not store metadata based on operations performed on non-associated row data field 150a and non-associated row data field 154b. Because metadata field #1 151b does not store metadata associated with row 150 or row 154, it should be understood that metadata field #1 151b is not associated with row 150 (and row data field 150a, in particular) or row information entry 154 (and row data field 154a, in particular). Also because metadata field #1 151b does not store metadata associated with non-associated row data field 150a and non-associated row data field 154b, metadata field #1 151b is not accessed in response to either of non-associated row data field 150a and non-associated row data field 154a being accessed or otherwise operated on.

[0022] Conversely, because metadata field #1 151b stores metadata associated with associated row data fields 151a-153a, it should be understood that metadata field #1 151b is associated with row information entries 151-153 (and row data fields 151a-153a, in particular) Also because metadata field #1 151b stores metadata associated with row data fields 151a-153a, metadata field #1 151b is accessed in response to any of associated row data fields 151a-153a being accessed.

[0023] The row data information stored by row data fields 150a- 154a is from the cells of row information entries 150-154 that are part of row data column group 130a. The metadata / counter information stored by metadata field 15 lb is from the cells of row information entry 151 that are part of metadata / counter information field 130b.

[0024] In an embodiment, when row data fields 151a-153a are accessed, the data in respective row data fields 150a- 154a is provided to, or comes from, row data processing circuitry of memory device 110 (e.g., DQ interface 112, etc.). When row data fields 151a- 153a are accessed, at least a portion of the data in row metadata field 15 lb is provided to, or comes from, metadata / counter operations circuitry 141.

[0025] Returning now to Figure 1 A, column circuitry 132 is subdivided into column circuitry groups 132a-132b that may have different access timing requirements. For example, metadata / counter information field 130b, which is activated and written by row circuitry 131 and column circuitry group 132b, respectively, may comprise a smaller MAT(s), and / or column circuitry group 132b may have reduced (or none) column decoding logic. For example, for each access operation (e.g., activation, read, write) the data from / to addressed portions (e.g., 10 bits) of column circuitry group 132b (rather than the whole) may be communicated with metadata / counter operations circuitry 141. This may allow these addressed portions of metadata / counter information field 130b to be accessed (e.g., activation, read, written, refreshed, etc.) in less time than row data column group 130a. In anembodiment, one or more portions of metadata / counter information field 130b (e.g., one or more counter values) may be read, the read data processed by metadata / counter operations circuitry 141, and the results of processing by metadata / counter operations circuitry 141 written back to (i.e., updated) metadata / counter information field 130b before the wordline of the row in memory array 130 being accessed is deactivated thereby storing a new (updated) metadata value in the metadata / counter information field of the activated row.

[0026] In an embodiment, metadata / counter operations circuitry 141 comprises configuration circuitry 141a, control circuitry 141b, function circuitry 141c, and update circuitry 14 Id. Configuration circuitry 141a may be configured to control the functions and / or operations of one or more of control circuitry 141b, function circuitry 141c, and update circuitry 14 Id. Configuration circuitry 141a may be configured by controller 120 (and metadata / counter operation configuration control circuitry 125, in particular) to configure metadata / counter operations circuitry 141 to perform various functions on, or based on, the metadata / counter value(s) stored in the metadata / counter information fields 130b.

[0027] Control circuitry 141b may be configured (e.g., in response to configuration circuitry 141a) to control the operations, functions and / or sequence of operations, data flows, etc. of function circuitry 141c, and metadata / counter update circuitry 141d. Function circuitry 141c may be configured and / or controlled, for example, to perform various functions on values stored in the metadata / counter information field 130b associated with the row data column group 130a being accessed. For example, function circuitry 141c may be configured to increment, decrement, advance (e.g., +2, -2), set to value (e.g., ‘0’), reset, etc. the value(s) read from one or more portions of metadata / counter information field 130b (which may then be stored back to memory array 130 — e.g., by update circuitry 141 d).

[0028] Update circuitry 141 d may be configured and / or controlled to perform updates of value(s) stored in the metadata / counter information field 130b of the metadata / counter information field 130b associated with the row data column group 130a being accessed. Update circuitry 141 d may be configured and / or controlled, for example, to perform updates of values stored in the metadata / counter information field 130b associated with the row data column group 130a being accessed based on one or more results and / or indicators produced by function circuitry 141c. In various embodiments, metadata / counter operations circuitry 141 may be configured to use counter values stored by the in-DRAM metadata / counter information fields 130b associated with groups of rows to, for example, update the counter values in the metadata / counter information fields 130b to count the number of activations of respective ones of the rows associated with a respective group.

[0029] Figure 1C illustrates a group of rows associated with a metadata / counter information field. In Figure 1C, row data fields 130aaa-130aac are illustrated as being associated with row group “A”. Similarly, at least one (or one) of metadata fields (e.g., metadata field 130baa) is associated with the row data fields 130aaa-130aac. The at least one (or one) of metadata fields (e.g., metadata field 130baa) may be associated with the row data fields 130aaa-130aac to store counter values (e.g., 8-bit, 10-bit, 16-bit, etc. counter values) respectively associated with row data fields 130aaa-130aac.

[0030] In an embodiment, when any one of the row data fields 130aaa-130aac associated with group “A” are accessed (e.g., activated), the metadata field (e.g., metadata field 130baa) associated with group “A” is also accessed (e.g., activated). This is illustrated in Figure ID and Figure IE. In Figure ID, an access to row data field 130aaa of row group “A” is illustrated by arrow 181 running from controller 120 to row circuitry 131, arrow 182 running from row circuitry 131 to row data field 130aaa (symbolizing an access to row data field 130aaa), and arrow 183 running from row circuitry 131 to metadata field 130baa (symbolizing an access to metadata field 130baa). In Figure IE, an access to row data field 130aac of row group “A” is illustrated by arrow 184 running from controller 120 to row circuitry 131, arrow 185 running from row circuitry 131 to row data field 130aac (symbolizing an access to row data field 130aac), and arrow 186 running from row circuitry 131 to metadata field 130baa (symbolizing an access to metadata field 130baa). Note that metadata field 130baa is accessed based on accesses to any one of row data fields 130aa- 130aac of row data group “A” - even though the row data field 130aa-130aac accessed may not be in the same row as metadata field 130baa. In Figures 1D-1E, metadata field 130baa is illustrated as being accessed in response to accesses to any of row data fields 130aaa-130aac. However, this is merely an example for illustration purposes. In an embodiment, any of metadata fields 130baa-130bac may be selected (e.g., by row circuitry 131 or control circuitry 145) to be accessed when a row of a row group is accessed.

[0031] Figure IF is an illustration of information fields in a memory array row. In Figure IF, metadata field 151b includes counter fields 151ba-151bc and (optionally) other metadata field(s) 15 Ibd. The row data information stored by metadata field 151b is from the cells of row that are part of row data column group 130a. In an embodiment, when metadata field 151b is accessed, portion of the data (e.g., one or more of counter values in counter fields 151ba-151bc) in metadata field 151b are provided to, or comes from, metadata / counter operations circuitry 141. Thus, for example, counter value “A” stored by counter field 151ba may be associated with a count (e.g., of activations, victim count, etc.) associated with rowdata field 130aaa of row data group “A”. Counter value “B” stored by counter field 15 Ibb may be associated with a count (e.g., of activations, victim count, etc.) associated with row data field 130aab of row data group “A”, and so on.

[0032] Figure 1G illustrates two group of rows associated. In Figure 1G, row data fields 130aaa-130aac are illustrated as being associated with row group “A”. Row data fields 130aba-130abc are illustrated as being associated with row group “B”. In an embodiment, at least one (or one) of metadata fields (e.g., metadata field 130bba) is associated with the row data fields 130aaa-130aac are in a different row group. Thus, for example, at least one (or one) of row data fields addressed by group “A” addresses (e.g., row data field 130aab) may be associated with a metadata fields (e.g., metadata field 130bbb) stored by a group “B” addressed row. In an embodiment, the metadata fields associated with these different row groups may be accessed concurrently. For example, the group “A” row data fields 130aaa- 130aac, the group “A” metadata field (e.g., metadata field 130baa) associated with the ingroup metadata field, and the cross-group metadata field may be accessed concurrently. This is illustrated in Figure H by arrow 191 running from controller 120 to row circuitry 131, arrow 192 running from row circuitry 131 to row data field 130aab (symbolizing an access to row data field 130aab), arrow 193 running from row circuitry 131 to metadata field 130baa (symbolizing an access to metadata field 130baa), and arrow 194 running from row circuitry 131 to metadata field 130bbb (symbolizing an access to metadata field 130bb). Being able to access metadata associated with a row data field in a first group (e.g., group “A”) that is stored in a metadata field of a second group (e.g., group “B”) concurrently with also accessing the metadata for the remaining row data fields in the first group (e.g., group “A”) allows reading and writing of the metadata associated with neighboring row data fields that are on or near the boundary between two groups.

[0033] Figures 2A-2B are diagrams illustrating an example memory array tile (MAT) stripe and an example MAT data storage configuration. In Figures 2A-2B, MAT stripe (e.g., row of MATs) 201 is illustrated. MAT stripe 201 comprises data field MATs 260a-260b and metadata MAT 270. In an embodiment, data field MATs 260a-260b (and additional MATs not illustrated in Figures 2A-2B) correspond to row data column group 130a and metadata MAT 270 corresponds to metadata / counter information field 130b. Data field MATs 260a- 260b of MAT stripe 201 are respectively illustrated including row data subwordline decoders 261a-261b, rows 265a-266a 266a-266b, and bit line sense amplifiers 262a-262b. Metadata MAT 270 is illustrated including row data sub wordline decoder 271, rows 275-276, and bitline sense amplifiers 272. Each of data field MAT’s 260a-260b bit line sense amplifiers262a-262b is operatively coupled with a respective column select line (CSL) and a global input / output (GIO) line. Metadata field MAT’s 270 bit line sense amplifiers 272 are operatively coupled with a column select line (CSL) and a global input / output (GIO) line.

[0034] In an embodiment, row data subwordline decoders 261a-261b of data field MATs 260a-260b decode subwordline addresses (e.g., from row circuitry 131) in a one-hot (i.e., one active rest inactive) manner in order to select a single row of data field MATs 260a-260b in response to a single subwordline address. Row data subwordline decoder 271 of metadata MAT 270, however, decodes sub wordline addresses in a many-to-one manner in order to select a single row of metadata MAT 265 in response to any of a group (plurality) of row addresses. This is illustrated in Figure 2B by rows 266a-266b of data field MATs 260a-260b (which are vertically aligned) being shaded to indicate activation / access, and row 275 of metadata MAT 270, which is not vertically aligned with rows 266a-266b also being shaded to indicate activation / access.

[0035] Figure 3 is a diagram illustrating a multiple MAT stripe data storage configuration. In Figure 3, two adjacent MAT stripes are illustrated running horizontally with a first MAT stripe (a.k.a., MAT stripe #2) above a second MAT stripe (a.k.a., MAT stripe #3). MAT stripe #2 comprises data field MAT 2A 362a and metadata MAT 2 372. MAT stripe #2 may include additional data field MAT(s) not shown in Figure 3. MAT stripe #3 comprises data field MAT 3 A 363a and metadata MAT 3 373. MAT stripe #3 may include additional data field MAT(s) not shown in Figure 3. Metadata MAT 2 372 includes metadata fields 375a-374c each in separate rows of metadata MAT 2 372. Metadata MAT3 373 includes metadata fields 376a-376c each in separate rows of metadata MAT 3 373.

[0036] In an embodiment, the MATs of the memory device including MAT stripe #2 and MAT stripe #3 are configured into contiguous row groups (i.e., all of the rows of a group have no physically intervening or interleaved rows from other groups between or among them). In Figure 3, MAT stripe #2 is illustrated with at least three row groups (group #1, group #2, and group #3 in Figure 3). Row group #1 is vertically adjacent row-wise to group #2 and row group #2 is vertically adjacent row-wise to group #3. Thus, group #1, group #2, and group #3 form a contiguous block of rows where the bottom row 365a of group #1 is physically immediately next to the top row 365b of group #2 and the bottom row 365c of group #2 is physically immediately next to the top row 365d of group #3.

[0037] MAT stripe #3 is also illustrated with at least three row groups (group #4, group #5, and group #6 in Figure 3). Row group #4 is vertically adjacent row-wise to group #5 and row group #5 is vertically adjacent row- wise to group #6. Thus, group #4, group #5, andgroup #6 form a contiguous block of rows where the bottom row of group #4 is physically immediately next to the top row of group #5 and the bottom row of group #5 is physically immediately next to the top row of group #6.

[0038] In an embodiment, the rows in group #1 (illustrated with angled hashing) are associated with row 375a in metadata MAT 2 372 and the rows in group #3 (illustrated with no hashing) are associated with row 375c in metadata MAT 2 372. Thus, accesses to any row in group #1 also cause an access to row 375a. Likewise, accesses to any row in group #3 also cause an access to row 375c. Data accessed to / from row 375a or row 375c may be routed to / from the bit line sense amplifiers of metadata MAT 2 372 to / from other circuitry (e.g., metadata / counter operations circuitry 141) via global I / O switching circuitry 385 and a plurality (e.g., 10, 12, 16) of metadata MAT GIO[] signal lines.

[0039] The rows in group #2 (illustrated with cross-hashing), however, are associated with row 376b in metadata MAT 3 373. Thus, accesses to any row in group #2 also cause an access to row 376b. Data accessed to / from row 375a or row 375c may be routed to / from the bit line sense amplifiers of metadata MAT 3 373 to / from other circuitry (e.g., metadata / counter operations circuitry 141) via global I / O switching circuitry 386 and a plurality (e.g., 10, 12, 16) of metadata MAT GIO[] signal lines.

[0040] In an embodiment, accesses to row in a first group (e.g., group #1) in the vicinity (e.g., immediately adjacent, 1 row intervening, 2 rows intervening, etc., or all the way to the next boundary) of a boundary between groups (e.g., boundary between group #1 and group #2) also cause an access to the metadata row associated with the group that is across that boundary. For example, an access to row 365a (which is on the boundary between group #1 and #2) will cause an access to metadata row 375a and may also, based on row 365a being in the vicinity of row 365b of group #2, cause an access to metadata row 375b. The data from metadata row 375a and metadata row 376a may then be sequentially read and / or written via metadata MAT GIO[] signal lines. In another example, an access to row 3653 (which is in the vicinity of the boundary between group #3 and #2, but is not on the boundary) will cause an access to metadata row 375c and may also, based on row 365e being in the vicinity of row 365c of group #2, cause an access to metadata row 376b. The data from metadata row 375a and metadata row 376a may then be sequentially read and / or written via metadata MAT GIO[] signal lines.

[0041] Thus, for example, if the memory device is configured whereby an access to a row of a group (e.g., row in the vicinity of a group boundary) should update metadata and / or counters associated with a row in a different group (e.g., immediately adjacent row that is in adifferent group), the concurrent activation of adjacent MATs (because adjacent groups are associated with metadata stored in different MATs) enables the metadata for adjacent / nearby groups / rows to be read / written from the columns of two different MATs without having to cycle the metadata MAT through a row-to-row access cycle in order to access two rows in the same metadata MAT. In an embodiment, the number of rows (e.g., 0, 1, 2, etc.) in the vicinity of a row being accessed that are to be updated (and thus how close to a boundary a row needs to be to cause the activation of an adjacent metadata MAT) is configurable (e.g., by control circuitry 145 and / or configuration circuitry 141a).

[0042] Figure 4 is a diagram illustrating a MAT stripe configuration. In Figure 4, two adjacent MAT stripes are illustrated running horizontally with a first MAT stripe (a.k.a., MAT stripe #2) above a second MAT stripe (a.k.a., MAT stripe #3). MAT stripe #2 comprises data field MAT 2A 462a and metadata MAT 2 472. MAT stripe #2 may include additional data field MAT(s) not shown in Figure 4. MAT stripe #3 comprises data field MAT 3 A 463a and metadata MAT 3 473. MAT stripe #3 may include additional data field MAT(s) not shown in Figure 4.

[0043] In an embodiment, the MATs of the memory device including MAT stripe #2 and MAT stripe #3 are configured into contiguous row groups (i.e., all of the rows of a group have no physically intervening or interleaved rows from other groups between or among them). In Figure 4, MAT stripe #2 is illustrated with at least three row groups (group #1, group #2, and group #3 in Figure 3). Row group #1 is vertically adjacent row-wise to group #2 and row group #2 is vertically adjacent row-wise to group #3. Thus, group #1, group #2, and group #3 form a contiguous block of rows where the bottom row of group #1 is physically immediately next to the top row of group #2 and the bottom row of group #2 is physically immediately next to the top row 365d of group #3.

[0044] MAT stripe #3 is also illustrated with at least three row groups (group #4, group #5, and group #6 in Figure 3). Row group #4 is vertically adjacent row-wise to group #5 and row group #5 is vertically adjacent row- wise to group #6. Thus, group #4, group #5, and group #6 form a contiguous block of rows where the bottom row of group #4 is physically immediately next to the top row of group #5 and the bottom row of group #5 is physically immediately next to the top row of group #6.

[0045] In an embodiment, similar to the MAT stripes illustrated in Figure 3, accesses to row in a first group (e.g., group #1) in the vicinity (e.g., immediately adjacent, 1 row intervening, 2 rows intervening, etc., or all the way to the next boundary) of a boundary between groups (e.g., boundary between group #1 and group #2) also cause an access to themetadata row associated with the group that is across that boundary. Thus, for the sake of brevity, the discussion of concurrent accessing of multiple adjacent metadata MATs will not be repeated herein.

[0046] The embodiment illustrated in Figure 4, however, includes additional global I / O lines to access the bit line sense amplifiers of metadata MATs 472-472. GIO1[] global I / O lines are operatively coupled with the bit line sense amplifiers of metadata MAT 2 472 via global I / O switching circuitry 485. GIO2[] global I / O lines are operatively coupled with the bit line sense amplifiers of metadata MAT 3 473 via global I / O switching circuitry 486. Thus, rather than the data from metadata rows in different metadata MATs having to be read and / or written via sequentially via a single set of global I / O lines, the bit line sense amplifiers of metadata MAT 2 472 may be read / written via global I / O switching circuitry 485 and GIO1[] concurrently with the bit line sense amplifiers of metadata MAT 3 473 may be read / written via global I / O switching circuitry 486 and GIO2[],

[0047] Figure 5A is a diagram illustrating the relationship between a suspected aggressor row and victim row levels. In Figure 5, row circuitry 531 (e.g., row circuitry 131) and a partial DRAM array 530 (e.g., memory array 130) are illustrated. The rows of array 530 are illustrated running from left to right with rows being adjacent to each other in the up and down directions. A suspected aggressor row 540 is illustrated near the middle of array.Immediately adjacent to suspected aggressor row 540 (i.e., without any intervening rows) are victim level 1 rows 54 la-54 lb (one above and one below, respectively).

[0048] Immediately above victim level 1 row 541a is victim level 2 row 542a. Likewise, immediately below victim level 1 row 541b is victim level 2 row 542b. Thus, it should be noted that each victim level 2 row 542a-542b has one intervening row (level 1 rows 54 la- 54 lb, respectively) between themselves and suspected aggressor row 540. Immediately above victim level 2 row 542a is victim level 3 row 543a. Likewise, immediately below victim level 2 row 542b is victim level 3 row 543b. Thus, it should be noted that each victim level 3 row 543a-543b have two intervening rows between themselves and suspected aggressor row 540, and so on for additional victim levels (e.g., level 4, level 5, etc.).

[0049] Figure 5B is a diagram illustrating victim row levels across different row groups. In Figure 5B, suspected aggressor row 540 and victim rows 541a-543a are associated with row group #1 (and are thus associated with a first metadata field). Victim rows 541b-543b are associated with row group #1 (and are thus associated with a second metadata field).

[0050] In an embodiment, the memory device that includes DRAM array 530 is configured to update the counter associated with rows when those rows are accessed(activated). The memory device may also check the counter values in the metadata field(s) associated with the accessed row and zero or more nearby (i.e., victim level 1, victim level 2, etc. — configurable) rows to determine whether any of those rows meet a threshold number that would trigger a refresh of one or more of the nearby rows. For example, if the victim level that is to be checked is configured to be greater than zero, when suspected aggressor row 540 is accessed, the memory device accesses the metadata field associated with row group #1, and (because row 540 is adjacent to the boundary between row group #1 and row group #2) the memory device also accesses the metadata field associated with row group #2. Thus, for example, if the victim level to be checked is equal to one (i.e., check victim level 1 rows), the memory device performs three read column operations (one for suspected aggressor row 540 counter, one for victim level 1 541a counter, and one for victim level 1 541b counter), and one write column operation (to update suspected aggressor row 540 counter with a new value - e.g., incremented or decremented).

[0051] In another embodiment, the memory device that includes DRAM array 530 is configured to update the counters associated with nearby victim rows when a given row is accessed (activated). The memory device checks the counter values in the metadata field(s) associated with t nearby (i.e., victim level 1, victim level 2, etc.— configurable) rows to determine whether any of those rows meet a threshold number that would trigger a refresh of one or more of these nearby rows. For example, when suspected aggressor row 540 is accessed, the memory device accesses the metadata field associated with row group #1 (to get the counter value for at least victim level 1 541a), and the memory device also accesses the metadata field associated with row group #2 (to get the counter value for at least victim level 1 541b). Thus, for example, if the victim level to be checked is equal to one (i.e., check victim level 1 rows), the memory device performs two read column operations (one for the victim level 1 541a counter, and one for victim level 1 541b counter), and three write column operation (to update victim level 1 54 la-54 lb counter values (e.g., increment or decrement), and to set suspected aggressor row 540 counter to an initial value - e.g., zero).

[0052] Figure 6 is a flowchart illustrating a method of operating a memory component. One or more steps illustrated in Figure 6 may be performed by, for example, memory system 100, and / or its components. By a memory component, a first command that includes an activation of a first row of a random access memory array and does not include an activation of a second row of the random access memory array is received (602). For example, memory device 110 may receive, from controller 120, a first command (e.g., activate, refresh) thatinstructs memory device 110 to activate row 152 and but does not include instructions to activate row 153.

[0053] Based on the first command and by the memory device, a first portion of the first row is activated (604). For example, based on receiving the first command, memory device 110 may activate row #2 data field 152a. Based on the first command and by the memory device, a first plurality of row metadata values from the random access memory array that are not stored in the first row are accessed (606). For example, also based on receiving the first command, memory device 110 may access metadata field #1 151b that contains metadata / counters for rows 151-153.

[0054] Based on the first command and a first row indicator associated with a first row location of the first row, a first row metadata value of the first plurality of row metadata values is updated (608). For example, based on receiving the first command and based on the address of row #2 152, memory device 110 may update a metadata / counter value (e.g., read from metadata field #1 151b or set an initial value) that corresponds to row #2 data field 152a (e.g., counter B 15 Ibb). Based on the first command and in the random access memory array, an updated value of a first row metadata value is stored (610). For example, based on receiving the first command the updated metadata / counter value (e.g., updated or initialized) that corresponds to row #2 data field 152a may be stored, by memory device 110, in the field of metadata field #1 151b that corresponds to row #2 data field 152a (e.g., counter B 15 Ibb).

[0055] Figure 7 is a flowchart illustrating a method of operating a memory system. One or more steps illustrated in Figure 7 may be performed by, for example, memory system 100, and / or its components. By a controller, a memory component if configured to perform a function on stored metadata values that are each associated with respective rows of a random access memory array (702). For example, memory controller 120 may configure memory device 110 to count, using metadata field 151b, each occurrence where a given row is a configured victim level within a row being activated.

[0056] By the controller and to the memory component, a first command that includes an activation of a first row of a random access memory array and does not include an activation of a second row of the random access memory array is received (704). For example, memory device 110 may receive, from controller 120, a first command (e.g., activate, refresh) that instructs memory device 110 to activate row 152 and but does not include instructions to activate row 153. Based on the first command and by the memory device, a first portion of the first row is activated (706). For example, based on receiving the first command, memory device 110 may activate row #2 data field 152a.

[0057] Based on the first command and by the memory device, a first plurality of row metadata values from the random access memory array that are not stored in the first row are accessed (708). For example, also based on receiving the first command, memory device 110 may access metadata field #1 151b that contains metadata / counters for rows 151-153. Based on the first command and a first row indicator associated with a first row location of the first row, a first row metadata value of the first plurality of row metadata values is updated (710). For example, based on receiving the first command and based on the address of row #2 152, memory device 110 may update a metadata / counter value (e.g., read from metadata field #1 151b or set an initial value) that corresponds to row #1 data field 151a (e.g., counter A 151ba).

[0058] Based on the first command and in the random access memory array, an updated value of a first row metadata value is stored (712). For example, based on receiving the first command, the updated metadata / counter value (e.g., updated or initialized) that corresponds to row #1 data field 151a may be stored, by memory device 110, in the field of metadata field #1 151b that corresponds to row #1 data field 151a (e.g., counter A 151ba).

[0059] Figure 8 is a flowchart illustrating a method of reducing power consumption. One or more steps illustrated in Figure 8 may be performed by, for example, memory system 100, and / or its components. From a controller and by a memory component, a command to configure the memory component to, based on meeting a threshold condition associated with a row in a dynamic random access memory array, not refresh the row in response to a row hammer mitigation command (802). For example, controller 120 may configure memory device 110 to, before refreshing a row in response to a row hammer mitigation command (e.g., directed refresh management - DRFM —command), check a counter value in metadata / counter information field 130b associated with that row to determine whether that row has needs to be refreshed in order to reduce the likelihood of row hammer caused data corruption. For example, if the row has been refreshed recently (where what constitutes recently may be configurable by memory controller 120 - e.g., threshold number of nearby activations, clock time, etc.), memory device 110 may not refresh the row that was a target of the row hammer mitigation command. This may reduce the power consumption of memory device 110 by reducing the number of unnecessary refresh operations that are performed by memory device 110.

[0060] By the memory component, a first row hammer mitigation command that includes an activation of a first row of the random access memory array is received (804). For example, memory device 110 may receive, from controller 120, a row hammer mitigationcommand directed to row 152. Based on a first metadata value not stored in the first row not meeting the threshold condition, activating the first row in response to the row hammer mitigation command (806). For example, based on a counter value stored in metadata field #1 of row 151 not meeting a threshold condition (e.g., victim count associated with row 152 is greater than a configured number) for skipping a row hammer mitigation refresh, memory device 110 may activate row 152 in response to the row hammer mitigation command.

[0061] By the memory component, a second row hammer mitigation command that includes an activation of a second row of the random access memory array is received (808). For example, memory device 110 may receive, from controller 120, a row hammer mitigation command directed to row 153. Based on a second metadata value not stored in the first row not meeting the threshold condition, not activating the first row in response to the row hammer mitigation command (810). For example, based on a counter value stored in metadata field #1 of row 151 meeting the threshold condition (e.g., victim count associated with row 153 is less than the configured number) for skipping a row hammer mitigation refresh, memory device 110 may not activate row 153 in response to the row hammer mitigation command.

[0062] Figure 9 is a flowchart illustrating a method of updating event counts. One or more steps illustrated in Figure 9 may be performed by, for example, memory system 100, and / or its components. By a memory controller, a memory component is configured to update stored metadata values for a first number of victim row levels (902). For example, memory controller 120 may configure memory device 110 to, in response to an activation of a suspected aggressor row (e.g., row 540), update the metadata values for victim level 1 54 la-54 lb and victim level 2 542a-542b rows.

[0063] By the controller and to the memory component, a first command that includes an activation of a first row of the random access memory array and does not include an activation of a second row of the random access memory array (904). For example, controller 120 may transmit, to memory device 110, a command that includes an activation of suspected aggressor row 152 and does not include an activation of row 151. Based on the first command and by the memory component, a first portion of the first row is activated (906). For example, based on the command from controller 120, memory device 110 may activate the row data column group 130a portion of row 152 (i.e., row #2 data field 152a).

[0064] Based on the first command and by the memory component, a first plurality of row metadata values are accessed from the random access memory array that are stored in the second row (908). For example, based on the command from controller 120, memory device110 may access a first plurality of counter values (e.g., two or more of counter A 151ba- 151bc) from the metadata / counter information field 130b portion of row 151 (i.e., metadata field #1 151b).

[0065] Based on the first command and a first row indicator associated with a first row location of the first row, and using a first function, row metadata values associated with the first number of victim row levels relative to the first row are updated (910). For example, based on the command from controller 120, memory device 110 may update counter values associated with the configured number of victim row levels (e.g., 1, 2, etc.) that are physically neighboring row 152. Based on the first command and in the random access memory array, an updated value of a first metadata value is stored (912). For example, based on the command from controller 120, memory device 110 may store at least one updated value of the first plurality of counter values (e.g., one or more of counter A 151ba-151bc) in the metadata / counter information field 130b portion of row 151 (i.e., metadata field #1 151b).

[0066] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of memory system 100, and its components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry -level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0067] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0068] Figure 10 is a block diagram illustrating one embodiment of a processing system 1000 for including, processing, or generating, a representation of a circuit component 1020. Processing system 1000 includes one or more processors 1002, a memory 1004, and one or more communications devices 1006. Processors 1002, memory 1004, and communicationsdevices 1006 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1008.

[0069] Processors 1002 execute instructions of one or more processes 1012 stored in a memory 1004 to process and / or generate circuit component 1020 responsive to user inputs 1014 and parameters 1016. Processes 1012 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1020 includes data that describes all or portions of memory system 100, and its components, as shown in the Figures.

[0070] Representation 1020 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1020 may be stored on storage media or communicated by carrier waves.

[0071] Data formats in which representation 1020 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email

[0072] User inputs 1014 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1016 may include specifications and / or characteristics that are input to help define representation 1020. For example, parameters 1016 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0073] Memory 1004 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1012, user inputs 1014, parameters 1016, and circuit component 1020.

[0074] Communications devices 1006 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1000 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communicationsdevices 1006 may transmit circuit component 1020 to another system. Communications devices 1006 may receive processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 and cause processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 to be stored in memory 1004.

[0075] Implementations discussed herein include, but are not limited to, the following examples:

[0076] Example 1: A memory component, comprising: a command / address interface;

[0077] a first random access memory array having memory element rows and memory element columns; a first plurality of memory element columns to store row data associated with a first plurality of memory element rows; a second plurality of memory element columns of a first memory element row of the first plurality of memory element rows to store a first plurality of row metadata values respectively associated with each of the first plurality of memory element rows; and metadata access circuitry to, based on a first activation of a first one of the first plurality of memory element rows, access memory elements in the second plurality of memory element columns of the first memory element row to access a second plurality of row metadata values that is a proper subset of the first plurality of row metadata values.

[0078] Example 2: The memory component of claim 1, wherein the first plurality of memory element rows and a second plurality of memory element rows are part of a first memory array tile stripe.

[0079] Example 3: The memory component of claim 2, wherein a second memory element row is part of a second memory array tile stripe, the second plurality of memory element columns of the second memory element row is to store a third plurality of row metadata values respectively associated with each of the second plurality of memory element rows, and the metadata access circuitry is to, based on a second activation of a one of the second plurality of memory element rows, access memory elements in the second plurality of memory element columns of the second memory element row to access a fourth plurality of row metadata values that is a proper subset of the third plurality of row metadata values.

[0080] Example 4: The memory component of claim 1, further comprising: metadata value processing circuitry to determine the first plurality of row metadata values.

[0081] Example 5: The memory component of claim 4, wherein the metadata value processing circuitry is configurable, using the command / address interface, to determine, based on the first activation of the first one of the first plurality of memory element rows,which of the first plurality of row metadata values are to be included in the second plurality of row metadata values in response to the first activation.

[0082] Example 6: The memory component of claim 5, wherein the metadata value processing circuitry is configurable, using the command / address interface, to use a one of at least a first update scheme and a second update scheme to update at least one of the second plurality of row metadata values.

[0083] Example 7: The memory component of claim 6, wherein the first update scheme includes counting row hammer events that affect a second one of the first plurality of memory element rows.

[0084] Example 8: A memory component, comprising: a random access memory array, organized into row segments that each store a plurality of row data entries and an associated row metadata information entry, the row metadata information entry comprising a first plurality of row metadata values respectively associated with each of the row data entries; a command / address interface to receive a first access command to access a first row data entry of the plurality of row data entries and a first subset of the first plurality of row metadata values, the first subset to be based on a first row location indicator of the first row data entry; and metadata value processing circuitry to, based on the first access command, perform a first operation on a first row metadata value of the first subset to produce a first result row metadata value and to store the first result row metadata value in the row metadata information entry.

[0085] Example 9: The memory component of claim 8, wherein the metadata value processing circuitry is configurable, using the command / address interface, to determine, based on first row location indicator, whether the first operation is to produce the first result row metadata value from the first row metadata value.

[0086] Example 10: The memory component of claim 8, wherein the metadata value processing circuitry is configurable, using the command / address interface, to use a one of at least a first function and a second function to produce the first result row metadata value from the first row metadata value.

[0087] Example 11: The memory component of claim 10, wherein the first function includes counting row hammer events that affect the first row data entry.

[0088] Example 12: The memory component of claim 10, wherein the first function includes counting activation events of a row storing the first row data entry.

[0089] Example 13: The memory component of claim 10, the first function includes counting row hammer events that affect the first row data entry and the second function includes counting activation events of a row storing the first row data entry.

[0090] Example 14: The memory component of claim 8, wherein the metadata value processing circuitry is to, based on the first access command, perform a second operation on a second row metadata value of the first subset to produce a second result row metadata value and to store the second result row metadata value in the row metadata information entry, where the first operation and the second operation are not the same operations.

[0091] Example 15: The memory component of claim 14, wherein the first operation comprises advancing a counter value and the second operation comprises setting an initial value.

[0092] Example 16: A method of operating a memory component, comprising: receiving, by the memory component, a first command that includes an activation of a first row of a random access memory array and does not include an activation of a second row of the random access memory array; based on the first command, activating, by the memory component, a first portion of the first row; based on the first command, accessing, by the memory component, a first plurality of row metadata values from the random access memory array that are not stored in the first row; based on the first command, and a first row indicator associated with a first row location of the first row, updating a first row metadata value of the first plurality of row metadata values; and based on the first command, storing, in the random access memory array, an updated value of a first row metadata value.

[0093] Example 17: The method of claim 16, further comprising: receiving, by the memory component, a first indicator to configure first circuitry to update the first plurality of row metadata values using a first function; and configuring the first circuitry to perform the first function on values of the first plurality of row metadata values.

[0094] Example 18: The method of claim 17, further comprising: receiving, by the memory component, a second indicator to configure second circuitry to update the first plurality of row metadata values using a second function; and configuring the second circuitry to perform the second function on values of the first plurality of row metadata values.

[0095] Example 19: The method of claim 16, further comprising: receiving, by the memory component, a second command that includes an activation of a second row of the random access memory array; based on the second command, activating, by the memory component, the first portion of the second row; based on the second command, accessing, bythe memory component, the first plurality of row metadata values; based on the second command, and a second row indicator associated with a second row location of the second row, updating a second row metadata value of the first plurality of row metadata values; and based on the second command, storing, in the random access memory array, an updated value of a second row metadata value.

[0096] Example 20: The method of claim 16, further comprising: based on the first command, not activating, by the memory component, the first portion of the second row; based on the first command, accessing, by the memory component, a second plurality of row metadata values from the random access memory array that are not stored in the first row; based on the first command, and a second row indicator associated with a second row location of the second row, updating a second row metadata value of the second plurality of row metadata values; and based on the first command, storing, in the random access memory array, an updated value of a second row metadata value.

[0097] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. A memory component, comprising: a command / address interface; a first random access memory array having memory element rows and memory element columns; a first plurality of memory element columns to store row data associated with a first plurality of memory element rows; a second plurality of memory element columns of a first memory element row of the first plurality of memory element rows to store a first plurality of row metadata values respectively associated with each of the first plurality of memory element rows; and metadata access circuitry to, based on a first activation of a first one of the first plurality of memory element rows, access memory elements in the second plurality of memory element columns of the first memory element row to access a second plurality of row metadata values that is a proper subset of the first plurality of row metadata values.

2. The memory component of claim 1, wherein the first plurality of memory element rows and a second plurality of memory element rows are part of a first memory array tile stripe.

3. The memory component of claim 2, wherein a second memory element row is part of a second memory array tile stripe, the second plurality of memory element columns of the second memory element row is to store a third plurality of row metadata values respectively associated with each of the second plurality of memory element rows, and the metadata access circuitry is to, based on a second activation of a one of the second plurality of memory element rows, access memory elements in the second plurality of memory element columns of the second memory element row to access a fourth plurality of row metadata values that is a proper subset of the third plurality of row metadata values.

4. The memory component of claim 1, further comprising: metadata value processing circuitry to determine the first plurality of row metadata values.

5. The memory component of claim 4, wherein the metadata value processing circuitry is configurable, using the command / address interface, to determine, based on the first activation of the first one of the first plurality of memory element rows, which of the first plurality of row metadata values are to be included in the second plurality of row metadata values in response to the first activation.

6. The memory component of claim 5, wherein the metadata value processing circuitry is configurable, using the command / address interface, to use a one of at least a first update scheme and a second update scheme to update at least one of the second plurality of row metadata values.

7. The memory component of claim 6, wherein the first update scheme includes counting row hammer events that affect a second one of the first plurality of memory element rows.

8. A memory component, comprising: a random access memory array, organized into row segments that each store a plurality of row data entries and an associated row metadata information entry, the row metadata information entry comprising a first plurality of row metadata values respectively associated with each of the row data entries; a command / address interface to receive a first access command to access a first row data entry of the plurality of row data entries and a first subset of the first plurality of row metadata values, the first subset to be based on a first row location indicator of the first row data entry; and metadata value processing circuitry to, based on the first access command, perform a first operation on a first row metadata value of the first subset to produce a first result row metadata value and to store the first result row metadata value in the row metadata information entry.

9. The memory component of claim 8, wherein the metadata value processing circuitry is configurable, using the command / address interface, to determine, based on first row location indicator, whether the first operation is to produce the first result row metadata value from the first row metadata value.

10. The memory component of claim 8, wherein the metadata value processing circuitry is configurable, using the command / address interface, to use a one of at least a first function and a second function to produce the first result row metadata value from the first row metadata value.

11. The memory component of claim 10, wherein the first function includes counting row hammer events that affect the first row data entry.

12. The memory component of claim 10, wherein the first function includes counting activation events of a row storing the first row data entry.

13. The memory component of claim 10, the first function includes counting row hammer events that affect the first row data entry and the second function includes counting activation events of a row storing the first row data entry.

14. The memory component of claim 8, wherein the metadata value processing circuitry is to, based on the first access command, perform a second operation on a second row metadata value of the first subset to produce a second result row metadata value and to store the second result row metadata value in the row metadata information entry, where the first operation and the second operation are not the same operations.

15. The memory component of claim 14, wherein the first operation comprises advancing a counter value and the second operation comprises setting an initial value.

16. A method of operating a memory component, comprising: receiving, by the memory component, a first command that includes an activation of a first row of a random access memory array and does not include an activation of a second row of the random access memory array; based on the first command, activating, by the memory component, a first portion of the first row; based on the first command, accessing, by the memory component, a first plurality of row metadata values from the random access memory array that are not stored in the first row;based on the first command, and a first row indicator associated with a first row location of the first row, updating a first row metadata value of the first plurality of row metadata values; and based on the first command, storing, in the random access memory array, an updated value of a first row metadata value.

17. The method of claim 16, further comprising: receiving, by the memory component, a first indicator to configure first circuitry to update the first plurality of row metadata values using a first function; and configuring the first circuitry to perform the first function on values of the first plurality of row metadata values.

18. The method of claim 17, further comprising: receiving, by the memory component, a second indicator to configure second circuitry to update the first plurality of row metadata values using a second function; and configuring the second circuitry to perform the second function on values of the first plurality of row metadata values.

19. The method of claim 16, further comprising: receiving, by the memory component, a second command that includes an activation of a second row of the random access memory array; based on the second command, activating, by the memory component, the first portion of the second row; based on the second command, accessing, by the memory component, the first plurality of row metadata values; based on the second command, and a second row indicator associated with a second row location of the second row, updating a second row metadata value of the first plurality of row metadata values; and based on the second command, storing, in the random access memory array, an updated value of a second row metadata value.

20. The method of claim 16, further comprising:based on the first command, not activating, by the memory component, the first portion of the second row; based on the first command, accessing, by the memory component, a second plurality of row metadata values from the random access memory array that are not stored in the first row; based on the first command, and a second row indicator associated with a second row location of the second row, updating a second row metadata value of the second plurality of row metadata values; and based on the first command, storing, in the random access memory array, an updated value of a second row metadata value.

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