Software and hardware collaborative simulation verification platform for accelerating verification and positioning of smart network interface card chip

Abstract

The present application relates to the technical field of chip verification, and relates to a software and hardware collaborative simulation verification platform for accelerating verification and positioning of a smart network interface card chip. The platform comprises: a host side QEMU virtual machine, which simulates a hardware device, sends an IO request, responds to the IO request, and calls a device driving program to implement driving execution of a host side hardware device; a host side thread adapter, which converts a multi-thread processing program of the host side QEMU virtual machine into a single-thread processing program; an UVM verification platform, which performs simulation reproduction of FPGA prototype verification of the smart network interface card chip to generate a simulation waveform and a simulation log; a network side data stream adapter, which performs data type conversion on an Ethernet message; and a network side data packet transceiver, which performs message legitimacy check on the Ethernet message returned by the network side data stream adapter. The platform of the present application can improve the problem positioning speed and the chip verification efficiency, shorten the overall chip development period, and improve the chip quality.

Description

A hardware-software co-simulation verification platform that accelerates smart network card chip verification and positioning

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 12, 2023, with application number 202311704639.3 and invention name “Software and hardware collaborative simulation and verification platform for accelerating verification and positioning of smart network card chips”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application belongs to the field of chip verification technology, and in particular relates to a hardware and software collaborative simulation verification platform for accelerating the verification and positioning of smart network card chips. Background Art

[0004] Smart NIC chips integrate Ethernet interfaces, PCIe (Peripheral Component Interconnect Express) bus interfaces, multi-core processors (CPUs), and optional field-programmable gate arrays (FPGAs). They are primarily used to assist host servers with virtual switching acceleration, network offload acceleration, storage acceleration, and security acceleration, and are used in cloud computing network virtualization solutions. The chip development cycle includes multiple stages, including functional requirements specification, architecture design, code design, UVM (Universal Verification Methodology) functional simulation verification, FPGA prototype verification, software development and testing, and post-silicon product application testing.

[0005] UVM functional simulation verification and FPGA prototype verification take up most of the development cycle. Therefore, accelerating chip verification convergence means shortening the chip development cycle and improving chip product quality.

[0006] (1) UVM functional simulation verification

[0007] The advantages of UVM functional simulation verification are:

[0008] 1. Fast compilation and simulation speed, especially for module-level functional verification. Functional simulation tools have fast compilation and simulation speeds, which will, to a certain extent, speed up the verification of the entire application project.

[0009] 2. Problem location is convenient. The verification environment platform can enter any part of the DUT (Design Under Test) that needs to be verified, generate sufficiently accurate data packets at a specific moment, and perform simulation verification. The operation of the verification tool can be paused or interrupted at any time. The simulation waveform can also be opened through the graphical interface. Combined with the simulation log, the problem can be quickly located, which improves the efficiency of problem location.

[0010] The disadvantages of UVM functional simulation verification are:

[0011] 1. When the DUT scale is large, the simulation performance drops rapidly. When the DUT design scale is relatively large, the system-level functional simulation speed will become very slow, and the verification speed will be greatly reduced, which in turn affects the verification speed of the entire project;

[0012] 2. The stimulus source simulation is limited. Constrained-based random simulation helps cover lower abstraction layers, including extreme cases of designed system-level behavior. However, in terms of simulating software transaction drivers, especially smart network cards, it involves business functions such as network acceleration, storage acceleration, and security acceleration. Among them, network acceleration mainly includes OVS (Open vSwitch, open source virtual switch) acceleration, TCP offload, Vxlan / GRE tunnel message offload, reliable UDP (User Datagram Protocol), NAT / PAT, RDMA (Remote Direct Memory Access), etc.; storage acceleration includes NVMe-OF (NVMe Over Fabrics), support for local PCIe SSD disks, support for remote NVMe arrays, etc.; security acceleration includes IPSec (Internet Protocol Security) decryption offload, message filtering, firewall, DPI, DDoS, etc. The software drivers used by these services include OVS virtual switching, SDN / NFV virtualization standard software, TCP / UDP offload, SR-IOV (Single Root I / O Virtualization), LinuxNet / DPDK (Intel Data Plane Development Kit), Express Virtio (XVIO), vPDA, etc. Such complex functional services and software drivers still have a gap between functional simulation and actual software operation. Due to insufficient application scenario simulation, bugs may be missed and verification quality cannot be guaranteed.

[0013] The main advantages of FPGA prototyping are:

[0014] 1. Hardware simulation speed is very fast. Using FPGA hardware simulation can improve the verification speed and shorten the verification time;

[0015] 2. Carry out software development and testing in advance. Software engineers can develop software drivers and applications on the FPGA prototype platform in advance. When the chip comes back, it only takes a few weeks to port the software and hardware, thereby accelerating the release of the product.

[0016] The main disadvantages of FPGA prototyping:

[0017] 1. The compilation time is relatively long. Hardware simulation requires logic synthesis of the design file and the mapping of the synthesis results to the real hardware circuit for simulation acceleration. However, software-based functional simulation does not require logic synthesis to generate physical circuits. This makes its compilation time much longer than that of functional simulation.

[0018] 2. Problem location is inconvenient. FPGAs are also chip products, so internal signals cannot be directly observed. You need to use FPGA debug tools to select the signals to observe before generating the bit file. Furthermore, due to the limited capacity of block RAM (block random access memory), only a subset of signals can be observed. Each time you reselect the observed signals and trigger conditions, you must recompile and generate the bit file, which is very inefficient and affects verification efficiency. This means that reproducing, locating, and resolving the problem requires a significant investment of time, extending the development cycle, and compiling the overall chip quality.

[0019] In summary, traditional chip verification and UVM functional simulation are equivalent to software simulation verification platforms, while FPGA prototype verification is equivalent to hardware simulation verification platforms. These are two completely independent verification platforms. In the verification of complex services such as SmartNIC chips, UVM functional simulation cannot fully simulate all SmartNIC services. Problems discovered during FPGA prototype verification are also difficult to replicate on the UVM functional simulation verification platform. Problems can only be located by continuously adding positioning logic and signals and continuously releasing FPGA versions. This verification method of locating problems on the FPGA prototype verification platform is difficult, time-consuming, and labor-intensive, with extremely low efficiency, ultimately impacting the entire project development cycle.

[0020] Therefore, how to reproduce the problems found in FPGA prototype verification on the UVM functional simulation platform, quickly locate the errors in the DUT design through simulation waveforms and simulation logs, and repair and solve them, thereby accelerating chip verification convergence, improving verification quality, and shortening the overall chip development cycle, is the pain point that needs to be solved in the verification of smart network card chips. Summary of the Invention

[0021] In view of the above shortcomings of the existing technology, the purpose of this application is to provide a hardware and software collaborative simulation verification platform that accelerates the verification and positioning of smart network card chips, improves the problem location speed, improves the chip verification efficiency, shortens the overall chip development cycle, and improves chip quality.

[0022] This application proposes a hardware-software co-simulation verification platform for accelerating the verification and positioning of smart network card chips, including: a host-side QEMU virtual machine, a host-side thread adapter, a UVM verification platform, a network-side data flow adapter, and a network-side data packet transceiver, wherein:

[0023] The host-side QEMU virtual machine is used to simulate hardware devices, issue IO requests, respond to IO requests, and call device drivers to implement driver execution of the host-side hardware devices;

[0024] The host-side thread adapter is used for inter-process communication, converting the multi-threaded processing program of the host-side QEMU virtual machine into a single-threaded processing program suitable for processing by the UVM verification platform, thereby realizing interactive communication between the host-side QEMU virtual machine and the UVM verification platform;

[0025] The UVM verification platform is used to perform simulation reproduction of the FPGA prototype verification of the smart network card chip according to the Ethernet message sent from the network side data stream adapter, generate simulation waveforms and simulation logs, and send them to the network side data stream adapter in the form of Ethernet messages;

[0026] The network side data stream adapter performs data type conversion on the Ethernet message received from the network side data packet transceiver, and sends the converted data to the UVM verification platform; and performs data type conversion on the Ethernet message returned by the UVM verification platform, and sends the converted data to the network side data packet transceiver;

[0027] The network-side data packet transceiver is used to simulate and generate Ethernet messages, send the Ethernet messages to the network-side data stream adapter in the message format and data structure specified by the TCP / IP protocol, and perform message legitimacy checks on the Ethernet messages returned by the network-side data stream adapter; based on the simulation waveforms and simulation logs generated by dynamic simulation of the EDA simulation tool, scenario problems in FPGA prototype verification are reproduced and located, and corrections and regression tests are performed, and regression testing is performed on the FPGA prototype verification.

[0028] Optionally, the host-side QEMU virtual machine simulates an IO request issued to a front-end driver of a hardware device, and the host-side QEMU virtual machine implements back-end processing to respond to the IO request.

[0029] Optionally, the host-side thread adapter implements interaction between the UVM SystemVerilog program and the C program of the host-side QEMU virtual machine through a DPI-C interface.

[0030] Optionally, the host-side QEMU virtual machine calls the device driver to initialize the host system and the design under test DUT, including host-side system memory management and allocation, PCIe driver, Virtio driver and OVS driver, and initially configures the design under test DUT by calling the smart network card related drivers.

[0031] Optionally, the UVM verification platform includes a global environment configuration, an APP component, a MAC simulation model, a DDR simulation model, a reference model, a scoreboard, and an instantiated design under test (DUT).

[0032] Optionally, the network-side data stream adapter performs data type conversion on Ethernet messages received and sent to the UVM verification platform through a DPI-C interface.

[0033] Optionally, the network-side data packet transceiver is further configured to encapsulate the Ethernet message according to the control address, payload, data packet length and data packet type.

[0034] Optionally, the network-side data packet transceiver is further configured to inject various abnormal Ethernet messages to generate damaged Ethernet data messages, and perform a network abnormal message sending and receiving test.

[0035] Optionally, the network-side data packet transceiver performs a message legitimacy check on the Ethernet message returned by the network-side data flow adapter, and performs the following processing according to the check result: message reception, discarding, or replying.

[0036] Optionally, the simulation waveforms and simulation logs generated by the host-side QEMU virtual machine, UVM verification platform and network-side data packet transceiver are used to open the waveforms and the design code of the design DUT to be tested through a graphical interface tool, and combined with the simulation logs, the scenario problems in the FPGA prototype verification are located.

[0037] The beneficial effects of this application are as follows:

[0038] (1) Solve the problem of insufficient UVM functional simulation stimulus source, and the driver software can run directly on the hardware and software co-simulation platform. The software driver can be used directly on the UVM functional simulation verification platform, reducing the repeated development of the driver software. At the same time, the simulation stimulus source is not limited to the traditional UVM verification platform, and more realistically simulates various network, storage, and security acceleration scenarios, which not only reduces repeated driver development but also improves the test scenario coverage, thereby improving the verification quality.

[0039] (2) Problems found in FPGA prototype verification can be reproduced on the software-hardware co-simulation platform. Through the software-hardware co-simulation verification platform, software drivers and application test programs can be run directly on the UVM functional simulation platform. Problems found in FPGA prototype verification can be directly reproduced on the software-hardware co-simulation verification platform. Through simulation waveforms and simulation logs, problems can be quickly located and DUT design defects can be repaired. At the same time, regression testing can be performed on the software-hardware co-simulation platform and the FPGA prototype verification platform, thereby accelerating the problem location of smart network card chip verification and accelerating the verification convergence of the chip.

[0040] (3) By introducing the host-side QEMU virtual machine, the simulation of various hardware devices and the execution of host-side hardware device drivers are realized.

[0041] (4) Through software and hardware collaborative simulation verification, the problem location speed is improved, the chip verification efficiency is improved, the overall chip development cycle is shortened, and the chip quality is improved.

[0042] (5) By introducing a host-side thread adapter, inter-process communication between multi-threaded programs and single-threaded processing programs is realized. The UVM SystemVerilog program and the QEMU virtual machine C program are interacted through the DPI-C interface, and communication between multiple processes and single threads is realized, thereby realizing interactive communication between the QEMU virtual machine and the UVM verification environment.

[0043] (6) By introducing a network-side data stream adapter, the data type conversion of network message transmission and reception is realized, thereby realizing the interactive communication between the network message transceiver and the UVM verification environment.

[0044] (7) By introducing a network-side data packet transceiver, the simulation generation and reception processing of Ethernet messages can be realized.

[0045] (8) Software drivers can be used directly in the UVM functional simulation verification platform, reducing the repeated development of driver software. At the same time, the simulation stimulus source is not limited to the traditional UVM verification platform, and can more realistically simulate various network, storage, and security acceleration scenarios, which not only reduces repeated driver development but also improves the test scenario coverage, thereby improving the verification quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are only for the purpose of illustrating specific embodiments and are not to be considered as limiting the present application. Throughout the drawings, the same reference numerals represent the same components. Obviously, the drawings described below are only some of the embodiments described in the present application. Those skilled in the art can also obtain other drawings based on these drawings.

[0047] FIG1 is a structural diagram of a hardware and software co-simulation verification platform for accelerating smart network card chip verification and positioning according to an embodiment of the present application;

[0048] FIG2 is a schematic diagram of a hardware and software co-simulation verification platform for accelerating verification and positioning of a smart network card chip according to an embodiment of the present application;

[0049] FIG3 is a data flow diagram of a hardware-software co-simulation platform in a problem reproduction process of a network message sending scenario for verifying a smart network card chip system according to an embodiment of the present application;

[0050] FIG4 is a data flow diagram of a hardware-software collaborative simulation platform in a problem reproduction process of a network message receiving scenario for verification of a smart network card chip system according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work should fall within the scope of protection of this application.

[0052] Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts disclosed in this application.

[0053] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. The terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be a communication between the internal parts of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0054] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of methods and systems consistent with certain aspects of the present application, as detailed in the appended claims.

[0055] The embodiments of the present application propose a hardware-software co-simulation verification platform and testing method for accelerating the location of verification problems of smart network card chips. By introducing the host-side QEMU virtual machine, the host-side thread adapter, the network-side data packet transceiver, and the network-side data stream adapter, combined with the UVM verification platform, a hardware-software co-simulation platform is constructed. Problems found in FPGA prototype verification are reproduced on the hardware-software co-simulation platform. Through simulation waveforms and simulation logs, various behaviors of DUT internal signals are viewed, and DUT design defects are quickly located and repaired, thereby improving the problem location speed, improving chip verification efficiency, shortening the overall chip development cycle, and improving chip quality.

[0056] The following is an explanation of the technical terms involved in the embodiments of this application:

[0057] UVM: It is a verification platform development framework based on the SystemVerilog class library. Its reusable components can be used to build a functional verification environment with standardized hierarchical structures and interfaces.

[0058] QEMU (Quick EMUlator), a set of simulated processor software, QEMU uses a virtualization simulator implemented purely by software and can simulate almost any hardware device.

[0059] PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard. It is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging and quality of service (QOS) and other functions.

[0060] DDR (Double Data Rate SDRAM), double data rate synchronous dynamic random access memory, transmits data twice in one clock cycle, and it can transmit data once during the rising and falling phases of the clock.

[0061] The MAC (Media Access Control) layer defines how data frames are transmitted over the media. Within links sharing the same bandwidth, access to the connection medium is on a first-come, first-served basis. Physical addressing is defined here, as is the logical topology (the path that signals follow through the physical topology). Line control, error notification (uncorrected), frame delivery ordering, and optional flow control are also implemented at this sublayer.

[0062] As shown in Figures 1 and 2, the present application proposes a hardware-software co-simulation verification platform for accelerating the verification and positioning of smart network card chips, including: a host-side QEMU virtual machine 100, a host-side thread adapter 200, a UVM verification platform 300, a network-side data flow adapter 400 and a network-side data packet transceiver 500.

[0063] The host-side QEMU virtual machine 100 is used to simulate hardware devices, issue IO requests, respond to IO requests, and call device drivers to implement driver execution of the host-side hardware devices.

[0064] First, determine the test scenarios for FPGA prototype verification. For example, consider hot-swap storage with streaming, the number of attached disks, I / O size, plug-in and plug-out cycles, and error detection. Then, start the host-side QEMU virtual machine 100. Using QEMU software, the host-side QEMU virtual machine 100 simulates various hardware devices. It simulates I / O requests to the hardware device's front-end driver and implements back-end processing to respond to I / O requests.

[0065] Hardware devices include virtio-blk, virtio-net and other devices. The host-side QEMU virtual machine 100 sends IO requests to the front-end drivers of the virtio-blk and virtio-net devices, and QEMU implements a back-end processing program to respond to the IO requests.

[0066] The host-side QEMU virtual machine 100 can also start by directly calling a device driver through the QEMU virtual machine to implement driver execution of the host-side hardware device, such as a Virtio device.

[0067] The host-side thread adapter 200 (Thread Adapter is used for inter-process communication and converts the multi-threaded processing program of the host-side QEMU virtual machine 100 into a single-threaded processing program suitable for processing by the UVM verification platform 300, thereby realizing interactive communication between the host-side QEMU virtual machine 100 and the UVM verification platform 300.

[0068] Specifically, the host-side thread adapter 200 implements the interaction between the UVM SystemVerilog program and the QEMU virtual machine C program through the DPI-C (Direct Programming Interface) interface, thereby realizing the interactive communication between the host-side QEMU virtual machine 100 and the UVM verification platform 300.

[0069] The UVM verification platform 300 is used to simulate and reproduce the FPGA prototype verification of the smart network card chip based on the Ethernet message sent from the network side data stream adapter 400, generate simulation waveforms and simulation logs, and send them to the network side data stream adapter 400 in the form of Ethernet messages.

[0070] In the embodiment of the present application, the UVM verification platform 300 includes a global environment configuration, an APP component, a MAC simulation model, a DDR simulation model, a reference model, a scoreboard, and an instantiated design under test (DUT).

[0071] The network-side data stream adapter 400 (Data Streaming Adapter) converts the data type of the Ethernet message received from the network-side data packet transceiver 500 through the DPI-C interface and sends the converted data to the UVM verification platform 300; and converts the data type of the Ethernet message returned by the UVM verification platform 300 through the DPI-C interface and sends the converted data to the network-side data packet transceiver 500.

[0072] The network-side packet transceiver 500 (Packet Generator) is used to simulate and generate Ethernet packets. It encapsulates Ethernet data packets by controlling the address, payload, packet length, packet type, etc., and sends Ethernet packets to the network-side data stream adapter 400 in the packet format and data structure specified by the TCP / IP (Transmission Control Protocol / Internet Protocol) protocol. It also performs a message legitimacy check on the Ethernet packets returned by the network-side data stream adapter 400. Based on the simulation waveforms and simulation logs generated by dynamic simulation using EDA (Electronic Design Automation) simulation tools, it reproduces and locates scenario problems in FPGA prototype verification, and performs corrections and regression testing. Regression testing is also performed on the FPGA prototype verification.

[0073] In addition, the network-side data packet transceiver 500 is also used to inject various abnormal Ethernet messages to generate damaged Ethernet data messages and perform network abnormal message sending and receiving tests.

[0074] In the embodiment of the present application, the network-side data packet transceiver 500 performs a message validity check on the Ethernet message returned by the network-side data stream adapter 400 according to the data format specified by the TCP / IP protocol, and performs the following processing based on the check result: message reception, discarding, or replying.

[0075] The host-side QEMU virtual machine 100, UVM verification platform 300 and network-side data packet transceiver 500 generate simulation waveforms and simulation logs. The waveforms and the design code of the design under test (DUT) are opened through a graphical interface tool, and combined with the simulation logs, the scenario problems in the FPGA prototype verification are located.

[0076] The hardware and software collaborative simulation verification platform for accelerating the verification and positioning of the smart network card chip in the embodiment of the present application performs problem reproduction testing, and the main process is: first start QEMU and wait for the connection on its remote port (RP); start the emulator, which can be a mainstream emulator such as VCS, IRUN / Xcelium, ModelSim / QuestaSim, etc. The emulator will start compiling the DUT design code and UVM verification environment code, and prepare to start simulation after compilation; connect the QEMU virtual machine to the emulator, QEMU starts and loads the Linux kernel; QEMU calls system-related drivers and applications; the network message transceiver receives or sends network messages; the emulator runs the simulation and generates simulation waveforms and simulation logs; end the simulation, open the waveforms and design code through the graphical interface tool (Verdi), and combine them with the simulation log to locate the problem.

[0077] The following describes the problem reproduction process of the intelligent network card chip system verification network message sending scenario in an embodiment of the present application with reference to Figure 3.

[0078] a) First start QEMU and wait for a connection on its remote port (RP).

[0079] b) Start the simulator. Here, we take the VCS simulator as an example. The VCS simulator will start compiling the DUT design code and UVM verification environment code, and then prepare to start simulation.

[0080] c) Connect the QEMU virtual machine to the emulator, and QEMU starts and loads the Linux kernel.

[0081] d) The simulator starts running the simulation and generates simulation waveforms and simulation logs.

[0082] e) QEMU first calls system-related drivers to initialize the host system and DUT, including host-side system memory management and allocation, PCIe driver, Virtio driver, OVS driver, etc., and initially configures the DUT by calling smart network card-related drivers.

[0083] f) After initializing the DUT, QEMU calls the iperf application to send TCP or UDP network packets.

[0084] g) The thread adapter converts the DUT initialization configuration and network message multi-threaded processing request sent by QEMU into a single-threaded processing request that can be processed by the UVM verification environment and sends it to the app driver.

[0085] h) The App driver converts the request sent by the thread adapter into an interface timing that the DUT can recognize.

[0086] i) The DUT performs a series of related operations based on the driver configuration and application issued by QEMU, including mode initialization, reading various initialized descriptors in the host side memory, reading the data to be sent according to the descriptors, updating the descriptors, writing back the relevant status to the host side, reporting interrupts, etc., and finally sending the network message to the MAC agent through the MAC port.

[0087] j) The monitor in the mac agent sends the received network message to the network side data stream adapter 400. The data stream adapter converts the data type of the received network message through the DPI-C interface and passes it to the network message transceiver after processing.

[0088] k) The network message transceiver will check the legitimacy of the received network messages and perform corresponding processing, including message reception, discarding, replying, etc.

[0089] l) After the simulation is finished, use the graphical interface tool (Verdi) to open the waveform and DUT design code, and combine them with the simulation log to locate the problem.

[0090] The following describes the problem reproduction process of the intelligent network card chip system verifying the network message receiving scenario in an embodiment of the present application with reference to Figure 4.

[0091] a) First start QEMU and wait for a connection on its remote port (RP).

[0092] b) Start the simulator. Here, we take the VCS simulator as an example. The VCS simulator will start compiling the DUT design code and UVM verification environment code, and then prepare to start simulation.

[0093] c) Connect the QEMU virtual machine to the emulator, and QEMU starts and loads the Linux kernel.

[0094] d) The simulator starts running the simulation and generates simulation waveforms and simulation logs.

[0095] e) QEMU first calls system-related drivers to initialize the host system and DUT, including host-side system memory management and allocation, PCIe driver, Virtio driver, OVS driver, etc., and initially configures the DUT by calling smart network card-related drivers.

[0096] f) The thread adapter converts the DUT initialization configuration multi-threaded processing request issued by QEMU into a single-threaded processing request that can be processed by the UVM verification environment and sends it to the app driver.

[0097] g) The App driver converts the request sent by the thread adapter into an interface timing that the DUT can recognize.

[0098] h) The DUT performs a series of related operations based on the driver configuration and application sent by QEMU, including mode initialization, reading various initialized descriptors in the host side memory, prefetching descriptors, updating descriptors, writing back related status to the host side, reporting interrupts, etc.

[0099] i) The network-side data packet transceiver 500 simulates and generates Ethernet packets, defines Ethernet data packets by controlling the address, payload, packet length, packet type, etc., and sends them to the network-side data stream adapter 400 in a fixed format and data structure.

[0100] j) The data stream adapter converts the data type of the received network message through the DPI-C interface and sends it to the mac driver after processing.

[0101] k) The mac driver converts the request sent by the data stream adapter into an interface timing that the DUT can recognize.

[0102] l) The DUT will receive the network message, process it, and send it to the app agent.

[0103] m) The monitor in the app agent sends the received network message to the thread adapter. The thread adapter converts the data type of the received network message through the DPI-C interface and passes it to QEMU after processing.

[0104] n) QEMU will check the legitimacy of the received network messages and perform corresponding processing, including message reception, discarding, and replying.

[0105] o) After the simulation is finished, use the graphical interface tool (Verdi) to open the waveform and DUT design code, and combine them with the simulation log to locate the problem.

[0106] The embodiment of the present application accelerates the verification and positioning of intelligent network card chips through software and hardware co-simulation verification platform and test method. The software driver is directly run on the UVM functional verification platform. The software and hardware co-simulation method is used to quickly reproduce the problems found in the FPGA prototype verification. By introducing the host-side QEMU virtual machine, the host-side thread adapter, the network-side data packet transceiver, and the network-side data stream adapter, combined with the UVM verification platform, a software and hardware co-simulation verification platform is constructed. In addition to being directly applied to the intelligent network card chip verification project, this application can also be used in different chip verification projects, including the verification of GPUs and intelligent AI chips. It can significantly accelerate the problem location of chip verification, thereby accelerating the verification convergence of the chip.

[0107] The hardware and software co-simulation verification platform for accelerating smart network card chip verification and positioning according to the embodiment of the present application has the following beneficial effects:

[0108] (1) Solve the problem of insufficient UVM functional simulation stimulus source, and the driver software can run directly on the hardware and software co-simulation platform. The software driver can be used directly on the UVM functional simulation verification platform, reducing the repeated development of the driver software. At the same time, the simulation stimulus source is not limited to the traditional UVM verification platform, and more realistically simulates various network, storage, and security acceleration scenarios, which not only reduces repeated driver development but also improves the test scenario coverage, thereby improving the verification quality.

[0109] (2) Problems found in FPGA prototype verification can be reproduced on the software-hardware co-simulation platform. Through the software-hardware co-simulation verification platform, software drivers and application test programs can be run directly on the UVM functional simulation platform. Problems found in FPGA prototype verification can be directly reproduced on the software-hardware co-simulation verification platform. Through simulation waveforms and simulation logs, problems can be quickly located and DUT design defects can be repaired. At the same time, regression testing can be performed on the software-hardware co-simulation platform and the FPGA prototype verification platform, thereby accelerating the problem location of smart network card chip verification and accelerating the verification convergence of the chip.

[0110] (3) By introducing the host-side QEMU virtual machine, the simulation of various hardware devices and the execution of host-side hardware device drivers are realized.

[0111] (4) Through software and hardware collaborative simulation verification, the problem location speed is improved, the chip verification efficiency is improved, the overall chip development cycle is shortened, and the chip quality is improved.

[0112] (5) By introducing a host-side thread adapter, inter-process communication between multi-threaded programs and single-threaded processing programs is realized. The UVM SystemVerilog program and the QEMU virtual machine C program are interacted through the DPI-C interface, and communication between multiple processes and single threads is realized, thereby realizing interactive communication between the QEMU virtual machine and the UVM verification environment.

[0113] (6) By introducing a network-side data stream adapter, the data type conversion of network message transmission and reception is realized, thereby realizing the interactive communication between the network message transceiver and the UVM verification environment.

[0114] (7) By introducing a network-side data packet transceiver, the simulation generation and reception processing of Ethernet messages can be realized.

[0115] (8) Software drivers can be used directly in the UVM functional simulation verification platform, reducing the repeated development of driver software. At the same time, the simulation stimulus source is not limited to the traditional UVM verification platform, and can more realistically simulate various network, storage, and security acceleration scenarios, which not only reduces repeated driver development but also improves the test scenario coverage, thereby improving the verification quality.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them. Although this application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of this application. Any changes or replacements that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be covered by the scope of protection of this application.

Claims

1. A hardware-software co-simulation verification platform for accelerating the verification and positioning of smart network card chips, characterized in that: include: Host-side QEMU virtual machine, host-side thread adapter, UVM verification platform, network-side data stream adapter and network-side data packet transceiver, wherein: The host-side QEMU virtual machine is used to simulate hardware devices, issue IO requests, respond to IO requests, and call device drivers to implement driver execution of the host-side hardware devices; The host-side thread adapter is used for inter-process communication, converting the multi-threaded processing program of the host-side QEMU virtual machine into a single-threaded processing program suitable for processing by the UVM verification platform, so as to realize interactive communication between the host-side QEMU virtual machine and the UVM verification platform; The UVM verification platform is used to perform simulation reproduction of FPGA prototype verification of the smart network card chip according to the Ethernet message sent from the network side data stream adapter, generate simulation waveforms and simulation logs, and send them to the network side data stream adapter in the form of Ethernet messages; The network-side data stream adapter performs data type conversion on the Ethernet message received from the network-side data packet transceiver, and sends the converted data to the UVM verification platform; and performs data type conversion on the Ethernet message returned by the UVM verification platform, and sends the converted data to the network-side data packet transceiver; The network side data packet transceiver is used to simulate and generate Ethernet messages, send the Ethernet messages to the network side data stream adapter in the message format and data structure specified by the TCP / IP protocol, and perform message legitimacy check on the Ethernet messages returned by the network side data stream adapter. According to the simulation waveforms and simulation logs generated by dynamic simulation of the EDA simulation tool, the scenario problems in the FPGA prototype verification are reproduced and located, and corrections and regression tests are performed, and regression tests are performed on the FPGA prototype verification.

2. The hardware-software co-simulation verification platform for accelerating smart network card chip verification and positioning according to claim 1 is characterized in that: The host-side QEMU virtual machine simulates the IO request issued to the front-end driver of the hardware device, and the host-side QEMU virtual machine implements back-end processing and responds to the IO request.

3. The hardware-software co-simulation verification platform for accelerating smart network card chip verification and positioning according to claim 1, characterized in that: The host-side thread adapter realizes the interaction between the UVM SystemVerilog program and the C program of the host-side QEMU virtual machine through the DPI-C interface.

4. The hardware-software co-simulation verification platform for accelerating smart network card chip verification and positioning according to claim 1, characterized in that: The host-side QEMU virtual machine calls the device driver to initialize the host system and the design under test DUT, including host-side system memory management and allocation, PCIe driver, Virtio driver and OVS driver, and initially configures the design under test DUT by calling the smart network card related drivers.

5. The hardware-software co-simulation verification platform for accelerating smart network card chip verification and positioning according to claim 1, characterized in that: The UVM verification platform includes global environment configuration, APP components, MAC simulation model, DDR simulation model, reference model, scoreboard and instantiated design under test (DUT).

6. The hardware-software co-simulation verification platform for accelerating smart network card chip verification and positioning according to claim 1, characterized in that: The network-side data stream adapter implements data type conversion of Ethernet messages received and sent by the UVM verification platform through a DPI-C interface.

7. The hardware-software co-simulation verification platform for accelerating intelligent network card chip verification and positioning according to claim 1, characterized in that: The network side data packet transceiver is also used to encapsulate the Ethernet message according to the control address, effective load, data packet length and data packet type.

8. The hardware-software co-simulation verification platform for accelerating smart network card chip verification and positioning according to claim 1, characterized in that: The network side data packet transceiver is also used to inject various abnormal Ethernet messages, generate damaged Ethernet data messages, and perform network abnormal message sending and receiving tests.

9. The hardware-software co-simulation verification platform for accelerating intelligent network card chip verification and positioning according to claim 1, characterized in that: The network-side data packet transceiver performs a message legitimacy check on the Ethernet message returned by the network-side data stream adapter, and performs the following processing according to the check result: message reception, discarding or replying.

10. The hardware-software co-simulation verification platform for accelerating smart network card chip verification and positioning according to claim 1, characterized in that: The host-side QEMU virtual machine, UVM verification platform and network-side data packet transceiver generate simulation waveforms and simulation logs, open the waveforms and the design code of the design DUT to be tested through a graphical interface tool, and locate the scenario problems in FPGA prototype verification in combination with the simulation logs.

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