Receiving device, laser radar, imaging system, and related method

Abstract

Embodiments of the present application provide a receiving device, a laser radar, an imaging system, and a related method. The receiving device is connected to a receiving array, the receiving array comprises N receiving units, and each receiving unit is used for detecting a photon signal and outputting a pulse signal; and the receiving device comprises a combiner and a speed limiter. The combiner is connected to the receiving array and is used for performing signal combination processing on N received pulse signals respectively output by the N receiving units, and outputting a first combined pulse signal, the first combined pulse signal comprising K pulse signals among the N pulse signals. The speed limiter is used for performing pulse deletion processing on the received first combined pulse signal on the basis of a signal processing rate or a preset time interval, and outputting a second combined pulse signal, wherein the second combined pulse signal comprises M pulse signals among the K pulse signals. By implementing the embodiments of the present application, the hardware volume can be reduced and the resource consumption can be reduced without limiting the photon event processing scale.

Description

A receiving device, laser radar, imaging system and related methods Technical Field

[0001] The present application relates to the field of radar technology, and in particular to a receiving device, a laser radar, an imaging system and related methods. Background Art

[0002] In the prior art, a laser radar or imaging system can often first send a light signal to an object, and after a period of time, receive the light signal reflected by the object. The laser radar or imaging system can then perform imaging and / or ranging processing on the object based on the reflected light signal. As is well known, the amount of received photon signals is much greater than the transmission speed and processing speed of the signal stream in the processor. Therefore, the receiving end often receives a large number of photon events to be processed in a very short period of time. During the subsequent processor processing, when processing the photon events received at the previous moment, a large number of photon events at the current moment may be lost, thereby causing the laser radar or imaging system to be unable to obtain high-quality imaging and / or ranging information. In order to ensure the collection of static information of photons, a memory is often set at the receiving end of the laser radar or imaging system in the prior art. Each receiving unit that receives photons at the receiving end can correspond to one or more storage bits in the memory, and the memory can be used to store the photon information received by the corresponding receiving unit to ensure the collection of static information of photons.

[0003] However, the memory size in this scheme is often determined by the size of the receiving units at the receiving end, resulting in a large area of ​​memory devices on the chip. Furthermore, the photon information received by each receiving unit must be stored in the memory before being read out for processing, further limiting the scale of photon event processing. Furthermore, additional resources are required to drive the memory for writing, reading, and resetting.

[0004] Therefore, how to reduce the hardware size and save resource consumption without limiting the scale of photon event processing is a technical problem that needs to be solved urgently.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a receiving device, a laser radar, an imaging system and related methods to reduce the hardware size and save resource consumption without limiting the scale of photon event processing.

[0007] In a first aspect, an embodiment of the present application provides a receiving device, which is connected to a receiving array, wherein the receiving array includes N receiving units, each of which is used to detect a photon signal and output a pulse signal, and N is a positive integer greater than or equal to 2; the receiving device includes: a combiner and a speed limiter; the combiner is connected to the receiving array, and is used to: receive the pulse signals output by the N receiving units respectively, perform signal merging processing on the received N pulse signals, and output a first combined pulse signal, wherein the first combined pulse signal includes K pulse signals among the N pulse signals, and K is a positive integer less than or equal to N; the speed limiter is used to: receive the first combined pulse signal; perform pulse deletion processing on the first combined pulse signal based on the signal processing rate or a preset time interval, and output a second combined pulse signal; wherein the second combined pulse signal includes M pulse signals among the K pulse signals, and M is a positive integer less than or equal to K.

[0008] In the prior art, in order to avoid missing large-scale photon events, a memory is usually added to the receiving end to store photon events that have not been fully processed. However, this will result in a large area of ​​storage devices on the chip or receiving end, and the size of the memory will also inversely limit the scale of subsequent photon event processing. In addition, the chip or receiving end also requires additional resources to drive the memory to write, read or reset, which wastes resources. In this regard, the embodiment of the present application can efficiently process a large number of photon events without setting up a memory, avoid missing large-scale photon events, and thus reduce resource consumption while reducing the hardware area, thereby improving the processing efficiency of photon events. For example: The embodiment of the present application provides a receiving device that can be applied to the receiving end of a laser radar or imaging system. The receiving device is connected to a receiving array that outputs multiple pulse signals. The receiving device includes a combiner and a speed limiter. The combiner is connected to the receiving array and can be used to combine the N pulse signals output by the receiving array for signal processing, outputting a first combined pulse signal, and the first combined pulse signal includes K pulse signals out of the N pulse signals. The combiner combines multiple pulse signals from parallel transmission into serial transmission, which is conducive to the orderly processing of the back-end processing system. Compared with the solution of directly performing imaging or ranging processing on the first combined pulse signal in the prior art, the first combined pulse signal output after the combiner is combined in the embodiment of the present application also needs to be processed by the pulse deletion of the above-mentioned speed limiter, and then the second combined pulse signal obtained after the pulse deletion is processed is imaged or ranging. Since the speed limiter performs pulse deletion processing on the above-mentioned first combined pulse signal based on the size of the signal processing rate or the preset time interval, the number and time interval of the pulse signals in the output second combined pulse signal can meet the requirements of the subsequent signal processing rate or the preset time interval. Therefore, in the embodiment of the present application, it is possible to avoid missing large-scale photon events without setting up a large-scale storage device. Moreover, the area of ​​the speed limiter is greatly reduced compared to the area of ​​the memory, which greatly reduces the overall area of ​​the receiving device. Moreover, the speed limiter does not require a lot of additional resources to drive operations such as writing, reading or resetting, which greatly reduces resource consumption. Most importantly, since the second combined pulse signal obtained after pulse deletion meets the signal processing rate requirements, the rate limiter does not limit the scale of subsequent photon event processing, greatly improving the processing efficiency of photon events.

[0009] In one possible implementation, the speed limiter is specifically used to: perform pulse deletion processing on the first combined pulse signal based on the drive of the K pulse signals in the first combined pulse signal and the size of the signal processing rate or the preset time interval, and output the second combined pulse signal; the time interval between any two adjacent pulse signals of the M pulse signals in the second combined pulse signal is greater than or equal to a first preset duration, and the first preset duration is determined by the signal processing rate.

[0010] Compared to the global clock used by the memory, the speed limiter in the embodiment of the present application is an asynchronous speed limiter that does not require the drive of a global clock. It can implement pulse deletion processing of the first combined pulse signal based on the drive of the pulse signal in the first combined pulse signal, greatly reducing the cost of the device. Moreover, under the drive of the pulse signal, pulse signals that do not meet the size of the signal processing rate or the preset time interval, that is, pulse signals where the time interval between two adjacent pulse signals is less than the first preset time length, will be deleted so that the subsequent processing system can process all pulse signals in the second combined pulse signal normally and orderly.

[0011] In one possible implementation, the speed limiter includes: a latch, an integrator and a comparator; the input end of the latch and the driving end of the comparator are connected to the output end of the combiner, the reset end of the latch is connected to the output end of the comparator, the output end of the latch is connected to the first input end of the comparator through the integrator, and the second input end of the comparator is connected to a reference voltage; wherein the latch is used to receive the K pulse signals in the first combined pulse signal, and output the M pulse signals in the second combined pulse signal based on the reset signal fed back by the comparator; so the integrator is used to receive the M pulse signals output by the latch, integrate the M pulse signals and output corresponding integrated voltages; the comparator is used to compare the integrated voltage output by the integration circuit with the reference voltage when receiving the drive of the K pulse signals in the first combined pulse, and output the reset signal to the latch based on the comparison result.

[0012] In an embodiment of the present application, only when a valid reset signal is input to the reset terminal is the state of the input terminal of the latch saved to the output terminal until the next valid reset signal is input to the reset terminal. To this end, the integrator integrates the M pulse signals and outputs the corresponding integrated voltage; the comparator can compare the integrated voltage output by the integration circuit with the reference voltage, and output the reset signal to the latch based on the comparison result, and output different reset signals according to different comparison results to filter the pulse signal. This filtering method is simple and efficient, and does not require the drive of a global clock, which helps to further reduce the device size of the receiving device and improve the processing efficiency of photon events.

[0013] In one possible implementation, the integrator includes a current source, a first switch tube, a second switch tube, and a capacitor; one end of the current source is connected to a power supply voltage, one end of the current source is connected to one end of the first switch tube, the other end of the first switch tube and one end of the second switch tube are connected to one end of the capacitor, and the other end of the second switch tube and the other end of the capacitor are grounded; the control end of the first switch tube and the control end of the second switch tube serve as input ends of the integrator, are connected to the output of the latch, and are used to receive the second combined pulse signal.

[0014] In an embodiment of the present application, a simple and efficient integrator circuit structure is provided. The current source and capacitance values ​​in the integrator can determine the speed of the integrator's integration processing. Therefore, the speed of the integrator's integration processing can be controlled by adjusting the current source and capacitance values ​​in the integrator to adapt to the subsequent signal processing rate for the second combined pulse signal. The smaller the capacitance value of the capacitor, the larger the current value of the current source in the integrator, and the faster the integration speed of the integrator.

[0015] In one possible implementation, the smaller the capacitance value of the capacitor in the integrator, the shorter the first preset time length; the larger the current value of the current source in the integrator, the shorter the first preset time length; and the smaller the reference voltage in the comparator, the shorter the first preset time length.

[0016] In an embodiment of the present application, the minimum time interval (i.e., the first preset duration) between any two adjacent pulse signals in the second combined pulse signal can be adjusted based on the current source and capacitance values ​​in the integrator, as well as the reference voltage received by the comparator. For example, when the signal processing rate is slow, the minimum time interval between two adjacent pulse signals can be extended. In this case, the capacitance value can be increased, the current source can be reduced, or the reference voltage can be increased.

[0017] In one possible implementation, the N pulse signals include a first pulse signal and a second pulse signal; and the time when the combiner receives the first pulse signal is earlier than the time when the second pulse signal is received; the combiner is specifically used to: when the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is greater than the second preset time length, the K pulse signals include the first pulse signal and the second pulse signal; when the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is less than or equal to the second preset time length and greater than a third preset time length, the K pulse signals include the first pulse signal and do not include the second pulse signal; when the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is less than or equal to the third preset time length, the K pulse signals do not include the first pulse signal and the second pulse signal.

[0018] In an embodiment of the present application, if the combiner receives two non-overlapping pulse signals (e.g., the time interval is greater than the second preset duration), the two pulse signals can be directly combined for signal processing. If two overlapping pulse signals are received, but the interval between the two overlapping pulse signals is greater than the dead time of the address processing module or other hardware circuits (e.g., the third preset duration), the combiner only retains the pulse signal received first and discards the pulse signal received later. If the interval between the two overlapping pulse signals is very small and is not enough to be distinguished by the address processing module or other hardware circuits, the combiner directly discards the two overlapping pulse signals to avoid signal errors.

[0019] In a possible implementation, the apparatus further includes an address processing module; the address processing module is configured to determine address information of a receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array.

[0020] In an embodiment of the present application, the receiving device further includes an address processing module for determining address information corresponding to each pulse signal in the second combined pulse signal, so as to perform subsequent imaging or ranging processing.

[0021] In one possible implementation, the address processing module includes an address encoder and an address decoder; the address encoder is used to: when the combiner outputs the first combined pulse signal, output the encoded address information corresponding to each pulse signal in the first combined pulse signal to the address decoder; the address decoder is used to: based on the encoded address information corresponding to each pulse signal in the first combined pulse signal, when the speed limiter outputs the second combined pulse signal, output the decoding address information corresponding to each pulse signal in the second combined pulse signal, the decoding address information including the address information of the receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array.

[0022] In the embodiment of the present application, the address information of each pulse signal is synchronously input to the back-end processing system for imaging or ranging processing. Accordingly, the address processing module includes an address encoder and an address decoder to encode and decode the address information, while also preventing errors or omissions in the address information of the pulse signal.

[0023] In one possible implementation, each of the above-mentioned receiving units detects the photon signal through one or more avalanche diodes and outputs the above-mentioned pulse signal; the above-mentioned receiving device also includes an avalanche quenching and reset module; the above-mentioned avalanche reset module is used to: after the receiving unit outputs the above-mentioned pulse signal, quench and reset one or more above-mentioned avalanche diodes of the corresponding receiving unit.

[0024] In embodiments of the present application, the receiving device can be applied to single-photon imaging or ranging, utilizing avalanche diodes to collect photon events, significantly improving the quality of imaging or ranging. To ensure the proper functioning of the avalanche diodes within each time window, the receiving device also includes an avalanche reset module to promptly quench and reset one or more avalanche diodes in the corresponding receiving unit after the receiving unit outputs the aforementioned pulse signal.

[0025] In the second aspect, an embodiment of the present application provides a laser radar, characterized in that the above-mentioned laser radar includes: a receiving array and a receiving device provided by the above-mentioned first aspect or any possible implementation of the first aspect, the above-mentioned receiving device is connected to the above-mentioned receiving array, and the above-mentioned receiving array includes multiple receiving units, each of the above-mentioned receiving units is used to detect photon signals and output pulse signals.

[0026] In a third aspect, an embodiment of the present application provides an imaging system, characterized in that the imaging system includes: a receiving array and a receiving device provided by the first aspect or any possible implementation of the first aspect, the receiving device is connected to the receiving array, and the receiving array includes multiple receiving units, each of the receiving units is used to detect photon signals and output pulse signals.

[0027] In a fourth aspect, an embodiment of the present application provides a receiving method, which is characterized in that it is applied to a receiving device, the receiving device is connected to a receiving array, wherein the receiving array includes N receiving units, each of the receiving units is used to receive an optical signal and output a pulse signal, and N is a positive integer greater than or equal to 2; the receiving device includes a combiner and a speed limiter, and the method includes: receiving the pulse signals respectively output by the N receiving units through the combiner, performing signal merging processing on the received N pulse signals to obtain a first combined pulse signal, the first combined pulse signal includes K pulse signals among the N pulse signals, and K is a positive integer less than or equal to N; performing pulse deletion processing on the first combined pulse signal based on the size of the signal processing rate or a preset time interval through the speed limiter to obtain a second combined pulse signal; wherein the second combined pulse signal includes M pulse signals among the K pulse signals, and M is a positive integer less than or equal to K.

[0028] In one possible implementation, the above-mentioned speed limiter performs pulse deletion processing on the above-mentioned first combined pulse signal based on the size of the signal processing rate or the preset time interval to obtain the second combined pulse signal, including: under the drive of the K pulse signals in the above-mentioned first combined pulse signal, the above-mentioned first combined pulse signal is pulse deleted based on the size of the above-mentioned signal processing rate or the preset time interval to output the above-mentioned second combined pulse signal; the time interval between any two adjacent pulse signals of the above-mentioned M pulse signals in the above-mentioned second combined pulse signal is greater than or equal to the first preset duration, and the above-mentioned first preset duration is determined by the above-mentioned signal processing rate.

[0029] In one possible implementation, the speed limiter includes: a latch, an integrator, and a comparator; the input end of the latch and the driving end of the comparator are connected to the output end of the combiner, the reset end of the latch is connected to the output end of the comparator, the output end of the latch is connected to the first input end of the comparator through the integrator, and the second input end of the comparator is connected to a reference voltage; the speed limiter performs pulse deletion processing on the first combined pulse signal based on the size of the signal processing rate or the preset time interval to obtain the second combined pulse signal, including: The latch receives the above-mentioned K pulse signals in the above-mentioned first combined pulse signal, and outputs the above-mentioned M pulse signals in the above-mentioned second combined pulse signal based on the reset signal fed back by the above-mentioned comparator; the above-mentioned method also includes: receiving the above-mentioned M pulse signals output by the above-mentioned latch through the integrator, integrating the above-mentioned M pulse signals and outputting corresponding integrated voltages; when the above-mentioned comparator receives the drive of the above-mentioned K pulse signals in the first combined pulse, it compares the integrated voltage output by the above-mentioned integration circuit with the above-mentioned reference voltage, and outputs the above-mentioned reset signal to the above-mentioned latch based on the comparison result.

[0030] In one possible implementation, the integrator includes a current source, a first switch tube, a second switch tube, and a capacitor; one end of the current source is connected to a power supply voltage, one end of the current source is connected to one end of the first switch tube, the other end of the first switch tube and one end of the second switch tube are connected to one end of the capacitor, and the other end of the second switch tube and the other end of the capacitor are grounded; the control end of the first switch tube and the control end of the second switch tube serve as input ends of the integrator, are connected to the output of the latch, and are used to receive the second combined pulse signal.

[0031] In one possible implementation, the smaller the capacitance value of the capacitor in the integrator, the shorter the first preset time length; the larger the current value of the current source in the integrator, the shorter the first preset time length; and the smaller the reference voltage in the comparator, the shorter the first preset time length.

[0032] In one possible implementation, the N pulse signals include a first pulse signal and a second pulse signal; and the time when the combiner receives the first pulse signal is earlier than the time when the second pulse signal is received; when the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is greater than the second preset time length, the K pulse signals include the first pulse signal and the second pulse signal; when the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is less than or equal to the second preset time length and greater than a third preset time length, the K pulse signals include the first pulse signal and do not include the second pulse signal; when the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is less than or equal to the third preset time length, the K pulse signals do not include the first pulse signal and the second pulse signal.

[0033] In one possible implementation, the apparatus further includes an address processing module; the method further includes: determining, by the address processing module, address information of a receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array.

[0034] In one possible implementation, the address processing module includes an address encoder and an address decoder; the address processing module determines the address information of the receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array, including: outputting the coded address information corresponding to each pulse signal in the first combined pulse signal to the address decoder through the address encoder when the combiner outputs the first combined pulse signal; outputting the decoding address information corresponding to each pulse signal in the second combined pulse signal through the address decoder based on the coded address information corresponding to each pulse signal in the first combined pulse signal and when the speed limiter outputs the second combined pulse signal, the decoding address information includes the address information of the receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array.

[0035] In one possible implementation, each of the above-mentioned receiving units detects the photon signal through one or more avalanche diodes and outputs the above-mentioned pulse signal; the above-mentioned receiving device also includes an avalanche quenching and reset module; the above-mentioned method also includes: after the receiving unit outputs the above-mentioned pulse signal, the above-mentioned avalanche reset module quenches and resets one or more of the above-mentioned avalanche diodes of the corresponding receiving unit.

[0036] It should be understood that the laser radar provided in the second aspect of this application, the imaging system provided in the third aspect, and the receiving method provided in the fourth aspect are consistent with the technical solution of the first aspect of this application. Their specific contents and beneficial effects can be referred to the receiving device provided in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0038] FIG1 is a schematic structural diagram of a receiving end in the prior art provided by an embodiment of the present application.

[0039] FIG2 is a schematic structural diagram of a receiving device provided in an embodiment of the present application.

[0040] FIG3A is a schematic diagram of a combined pulse signal provided in an embodiment of the present application.

[0041] FIG3B is a schematic diagram of another combined pulse signal provided in an embodiment of the present application.

[0042] FIG4 is a schematic diagram of a deleted pulse signal provided in an embodiment of the present application.

[0043] FIG5 is a schematic structural diagram of another receiving device provided in an embodiment of the present application.

[0044] FIG6 is a schematic diagram of the working principle of a speed limiter provided in an embodiment of the present application.

[0045] FIG7 and FIG8 are comparative schematic diagrams of a group of second combined pulse signals corresponding to different integration speeds provided in an embodiment of the present application.

[0046] FIG9 is a schematic diagram of the circuit structure of a speed limiter provided in an embodiment of the present application.

[0047] FIG10 is a schematic diagram showing a comparison of second combined pulse signals corresponding to different reference voltages provided in an embodiment of the present application.

[0048] FIG11 is a schematic structural diagram of another receiving device provided in an embodiment of the present application.

[0049] FIG12 is a flow chart of a receiving method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0051] The terms "first," "second," "third," and "fourth," etc., in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, rather than to describe a specific order. In addition, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0052] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0053] For ease of description, embodiments of the present application may use spatial relationship terms such as "under", "below", "below", "below", "above", "on", etc. to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation, in addition to the directions depicted in the drawings. For example, if the device in the drawings is turned over, the direction of the element described as "under" or "below" or "below" other elements or features will be changed to "above" the other elements or features. Thus, the exemplary terms "under" and "below" can include both the up and down directions. The device may also have other orientations (rotated 90 degrees or in other directions), so the spatial relationship descriptors used here should be interpreted accordingly. In addition, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more layers between them.

[0054] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0055] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0056] First, in order to facilitate understanding of the embodiments of the present application, the technical problems that need to be solved by the embodiments of the present application are analyzed in detail below.

[0057] In the prior art, a lidar or imaging system may first send a light signal to an object, and then receive a light signal reflected by the object after a period of time. The lidar or imaging system may then image and / or measure the distance of the object based on the reflected light signal.

[0058] As we all know, the amount of received photon signals is far greater than the transmission speed and processing speed of the signal flow in the processor. Therefore, the receiving end often receives a large number of photon events to be processed in a very short period of time. In the subsequent processor processing process, when processing the photon events received at the previous moment, it is very likely that a large number of photon events at the current moment will be lost, which will cause the lidar or imaging system to be unable to obtain high-quality imaging and / or ranging information.

[0059] In order to ensure the collection of static information of photons, please refer to FIG1, which is a structural diagram of a receiving end in a prior art provided by an embodiment of the present application. As shown in FIG1, in the prior art, a memory is often set at the receiving end, and each receiving unit that receives photons at the receiving end can correspond to one or more storage bits in the memory, and then the memory can be used to store the photon information received by the corresponding receiving unit to ensure the collection of static information of photons. For example: after the receiving array receives the photon information, the receiving end will combine the event pulse signal corresponding to the photon information through the combiner and input it into the event sampler. At this time, since the combiner will output a large number of event pulse signals of photon events, the event sampler cannot process them completely in time. At this time, the receiving end will pre-store the photon event in the memory, and then read out the corresponding photon events in sequence following the count of the event sampler for the back-end to process.

[0060] However, the size of the memory in this solution is often determined according to the size of the receiving units at the receiving end. For example, if Y storage bits are arranged for each receiving unit to store the corresponding photon event, then M*N receiving units require a memory with a minimum size of M*N*Y storage bits. This will result in a large-area storage device on the chip. Moreover, the size of the memory will also limit the processing scale of the photon event. For example, if the memory only has storage bits corresponding to M*N receiving units, it will be difficult to store more photon events corresponding to receiving units once it is full. In addition, after the photon event information is stored in the memory, the above-mentioned photon events need to be read out in sequence during the subsequent processing process, and the memory must be reset after all are read out in order to receive the photon events of the next receiving window. Therefore, the receiving end not only requires additional resources to drive the memory for writing, reading or resetting, but also greatly reduces the efficiency of photon event processing.

[0061] In this regard, the present application can efficiently process a large number of photon events without setting up memory and without limiting the scale of photon event processing, thereby reducing hardware area while reducing resource consumption and improving photon event processing efficiency. For example, an embodiment of the present application provides a receiving device that can be applied to the receiving end of a laser radar or imaging system to perform imaging or ranging processing on received photon events. Wherein, the receiving device is connected to a receiving array, which includes a plurality of receiving units, and the receiving device includes a combiner and a speed limiter; the above-mentioned combiner is connected to the above-mentioned receiving array, and the combiner can be used to receive the pulse signals respectively output by the above-mentioned N receiving units, perform signal merging processing on the received N pulse signals, and output a first combined pulse signal, wherein the above-mentioned first combined pulse signal includes K pulse signals among the above-mentioned N pulse signals, K is a positive integer less than or equal to N; the above-mentioned speed limiter is used to: receive the above-mentioned first combined pulse signal; perform pulse deletion processing on the above-mentioned first combined pulse signal based on the size of the signal processing rate or the preset time interval, and output a second combined pulse signal; wherein the above-mentioned second combined pulse signal includes M pulse signals among the above-mentioned K pulse signals, M is a positive integer less than or equal to K. Wherein, the specific structure and related description of the receiving device please refer to the following embodiments, which will not be described in the embodiments of this application.

[0062] Secondly, based on the technical issues raised above and to facilitate understanding of the embodiments of the present application, the hardware architecture on which the embodiments of the present application are based is described below.

[0063] The receiving device in the embodiment of the present application is connected to a receiving array, which includes a combiner and a speed limiter. The receiving array is used to detect photon signals and output pulse signals. It can be understood that the receiving array includes N receiving units arranged in an array, that is, multiple receiving units, and the multiple receiving units can respectively detect photon signals in each time window of multiple time windows and output pulse signals corresponding to the time window, so that the back-end processing system can perform imaging or ranging processing based on the pulse signals output by the multiple time windows. The following related embodiments are illustrative examples of the photon signal detected in a time window.

[0064] The combiner in the receiving device is connected to the above-mentioned receiving array, wherein the receiving array includes N receiving units, each of which is used to detect photon signals and output pulse signals, and N is a positive integer greater than or equal to 2. The combiner can be used to: receive event pulse signals respectively output by the above-mentioned N receiving units, perform signal merging processing on the received N pulse signals, and output a first combined pulse signal, wherein the above-mentioned first combined pulse signal includes K pulse signals among the above-mentioned N pulse signals, and K is a positive integer less than or equal to N; the speed limiter in the receiving device can be used to: receive the first combined pulse signal sent by the combiner; perform pulse deletion processing on the first combined pulse signal based on the size of the signal processing rate or the preset time interval, and output a second combined pulse signal; wherein the above-mentioned second combined pulse signal includes M pulse signals among the above-mentioned K pulse signals, and wherein M is a positive integer less than or equal to K.

[0065] Please refer to FIG2 , which is a schematic structural diagram of a receiving device provided in the embodiment of the present application.

[0066] As shown in FIG2 , the receiving device in the embodiment of the present application includes a combiner and a rate limiter. Compared to setting up a memory at the receiving end, the cooperation between the combiner and the rate limiter in the embodiment of the present application can adjust the number of pulse signals output by the receiving device based on the signal processing rate or preset time interval of the backend. For example, the rate limiter in the receiving device can filter out pulse signals with relatively close time intervals, so that the backend processing system can have sufficient time to pipeline the output of multiple pulse signals. Alternatively, the rate limiter in the receiving device can determine the preset time interval required for the pulse signal when processing the signal corresponding to the algorithm based on the specific algorithm requirements of the backend processing system, and filter out pulse signals that do not meet or meet the preset time interval requirements. The receiving device in the embodiment of the present application can avoid missing large-scale photon events without setting up a large-scale storage device. Moreover, the area of ​​the rate limiter is greatly reduced compared to the area of ​​the memory, greatly reducing the overall area of ​​the receiving device. In addition, the rate limiter does not require a lot of additional resources to drive operations such as writing, reading, or resetting, greatly reducing resource consumption. Crucially, because the second combined pulse signal obtained after pulse pruning meets the signal processing rate requirements and the algorithmic requirements of the back-end processing system, the rate limiter does not restrict the scale of subsequent photon event processing, greatly improving photon event processing efficiency. The rate limiter can also control key signal processing indicators such as signal transfer function and signal-to-noise ratio by controlling the interval between the second combined pulse signals to adapt to various application scenarios.

[0067] For example, as shown in FIG. 2 , the combiner combines N pulse signals outputted by N receiving units, respectively, and performs signal processing to output a first combined pulse signal. Each receiving unit can output a pulse signal corresponding to a photon event, and the pulse corresponding to a pulse signal can include a single pulse or multiple pulses, which is not specifically limited in this embodiment of the present application.

[0068] The first combined pulse signal may include part or all of the N pulse signals. It can be understood that the first combined pulse signal output by the combiner is to combine multiple pulse signals (i.e., the N pulse signals mentioned above) according to the time domain for signal processing, that is, to combine multiple pulse signals sent in parallel into multiple pulse signals sent in series in sequence. In order to avoid conflicts in the time domain between pulse signals sent by different receiving units in the combined signal processing, when the pulse signals sent by any two receiving units do not overlap in the time domain, the combiner can retain all the pulse signals for output; when the pulse signals sent by any two receiving units overlap in the time domain, the combiner can give priority to retaining the first pulse signal received in the time domain. Therefore, the first combined pulse signal output by the combiner can include part or all of the N pulse signals, that is, K pulse signals, where K is a positive integer less than or equal to N.

[0069] For example, please refer to Figure 3A, which is a schematic diagram of a combined pulse signal provided in an embodiment of the present application. As shown in Figure 3A, taking the receiving array including 5 receiving units as an example, the 5 receiving units respectively output 5 pulse signals. The combiner can combine the 5 pulse signals according to the time domain to obtain 1 combined pulse signal (i.e., the first combined pulse signal), which includes 4 pulse signals (1, 2, 4 and 5).

[0070] In some embodiments, the above-mentioned N pulse signals include a first pulse signal and a second pulse signal; and the time when the above-mentioned combiner receives the above-mentioned first pulse signal is earlier than the time when the above-mentioned second pulse signal is received; the above-mentioned combiner is specifically used to: when the time interval between the time when the above-mentioned first pulse signal is received and the time when the above-mentioned second pulse signal is received is greater than the second preset time length, the above-mentioned K pulse signals include the above-mentioned first pulse signal and the above-mentioned second pulse signal; when the time interval between the time when the above-mentioned first pulse signal is received and the time when the above-mentioned second pulse signal is received is less than or equal to the above-mentioned second preset time length and greater than the third preset time length, the above-mentioned K pulse signals include the above-mentioned first pulse signal and do not include the above-mentioned second pulse signal; when the time interval between the time when the above-mentioned first pulse signal is received and the time when the above-mentioned second pulse signal is received is less than or equal to the above-mentioned third preset time length, the above-mentioned K pulse signals do not include the above-mentioned first pulse signal and the above-mentioned second pulse signal.

[0071] It is understandable that when the combiner performs signal merging processing on multiple pulse signals, if the combiner receives two non-overlapping pulse signals (such as: the time interval is greater than the second preset time length), the two pulse signals can be directly merged for signal processing. As shown in Figure 3A above, the five receiving units each output five pulse signals. The combiner can perform signal merging processing on the five pulse signals to obtain one combined pulse signal (i.e., the first combined pulse signal). The first combined pulse signal includes four pulse signals (1, 2, 3, 4, and 5) of the above five pulse signals (1, 2, 3, 4, and 5). Among them, the shortest time interval between pulse signal 2, pulse signal 4, and pulse signal 5 is greater than the second preset time length, then pulse signal 2, pulse signal 4, and pulse signal 5 can be directly merged for signal processing.

[0072] If two overlapping pulse signals are received, but the interval between the two overlapping pulse signals is greater than the dead time of the address processing module or the dead time of other related hardware circuits (such as the third preset duration), the combiner will only retain the pulse signal received first and discard the pulse signal received later. As shown in Figure 3A above, the shortest time interval between pulse signal 1 and pulse signal 3 is less than or equal to the second preset duration, but greater than or equal to the third preset duration, then the first combined pulse signal output by the combiner only includes pulse signal 1, and does not include pulse signal 3. That is, since the third pulse signal (pulse signal 3) overlaps with the first pulse signal (pulse signal 1) in the time domain, according to the priority principle, pulse signal 3 will be discarded or filtered out in the first combined pulse signal.

[0073] If the interval between the two overlapping pulse signals is very small, for example: the two pulse signals completely overlap and are not enough to be distinguished by the address processing module or other hardware circuits, that is, the time interval between any two pulse signals is less than the third preset time length, then the combiner can discard the two overlapping pulse signals to avoid the phenomenon that the pulse signal address cannot be resolved. Please refer to Figure 3B, Figure 3B is a schematic diagram of another pulse signal combination provided by an embodiment of the present application. As shown in Figure 3B, the five receiving units respectively output five pulse signals, and the combiner can combine the five pulse signals according to the time domain for signal processing, wherein the time interval between pulse signal 1 and pulse signal 3 is less than or equal to the third preset time length, that is, the interval between pulse signal 1 and pulse signal 3 is very small and is not enough to be distinguished by the address processing module or other hardware circuits, then the first combined pulse signal output by the combiner directly discards or filters out pulse signal 1 and pulse signal 3, and only includes pulse signal 2, pulse signal 4 and pulse signal 5.

[0074] It should be noted that the second preset time mentioned in the embodiment of the present application can be a pre-set time for determining whether there is photon overlap, and the third preset time can be a pre-set time based on the dead time (deadtime) of the address processing module or other related hardware circuits mentioned in the following embodiments, and generally the second preset time is greater than the third preset time. In this regard, the embodiment of the present application does not make specific restrictions on the specific sizes of the second preset time and the third preset time.

[0075] In other embodiments, in other application scenarios where retaining the address information corresponding to the pulse signals is not required, the combiner may choose to retain the overlapping pulse signals. For example, if the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is less than or equal to a third preset duration, the K pulse signals include the first pulse signal and the second pulse signal. This embodiment of the present application does not impose specific limitations on this.

[0076] After the combiner performs signal processing on multiple pulse signals to obtain a first combined pulse signal, since the first combined pulse signal includes most of the photon events received by the receiving array within a time window, that is, the amount of received photon signals is much greater than the transmission speed and processing speed of the signal stream in the processor, the back-end processing system cannot timely process all the pulse signals (that is, the first combined pulse signal) within the time window. In order to avoid the loss of a large amount of photon information, the speed limiter in the embodiment of the present application can perform pulse deletion processing on part of the pulse signals in the above-mentioned first combined pulse signal based on the size of the signal processing rate of the back-end processing system or a preset time interval, so that the deleted pulse signal (the second combined pulse signal) can be processed completely and in time by the back-end processing system (such as the event sampler shown in Figure 2 above). For example: the speed limiter can receive the first combined pulse signal output by the combiner; and perform pulse deletion processing on the first combined pulse signal based on the size of the signal processing rate, and output a second combined pulse signal; wherein the above-mentioned second combined pulse signal includes M pulse signals among the above-mentioned K pulse signals. For example, if the processing time of each pulse signal of the back-end processing system is at least X nanoseconds; then the speed limiter can delete the pulse signals in the first combined pulse signal that are too close in time domain (for example: the time interval is less than X nanoseconds), to ensure that each pulse signal in the output second combined pulse signal can be processed by the back-end processing system in a timely manner.

[0077] In some embodiments, the speed limiter is specifically used to: perform pulse deletion processing on the first combined pulse signal based on the drive of K pulse signals in the first combined pulse signal and the signal processing cycle, and output the second combined pulse signal; the time interval between any two adjacent pulse signals of the M pulse signals in the second combined pulse signal is greater than or equal to a first preset duration, and the first preset duration is determined by the signal processing rate.

[0078] Please refer to Figure 4, which is a schematic diagram of a pulse signal deletion provided in an embodiment of the present application. As shown in Figure 4, the first combined pulse signal output by the combiner includes pulse signal 1, pulse signal 2, pulse signal 4 and pulse signal 5. Among them, since the time interval between pulse signal 4 and pulse signal 5 is too short, that is, the maximum processing speed of the processor in the back-end processing system or the maximum sampling speed of the event sampler is not enough to complete the processing of pulse signal 4 when pulse signal 5 is received. Therefore, the speed limiter can filter out pulse signal 5 to ensure efficient and smooth processing in the subsequent processing process. For example, as shown in Figure 4 above, the second combined pulse signal includes pulse signal 1, pulse signal 2 and pulse signal 4, and pulse signal 5 is deleted. This method of not requiring a memory to store unprocessed pulse signals can greatly improve the processing efficiency of the entire process while reducing the scale of hardware.

[0079] It is understood that the signal processing rate mentioned in the above embodiment can be the maximum processing rate of the event sampler or event timer for the pulse signal in the subsequent processing process, or it can be the fastest reading rate of the histogram memory. This embodiment of the present application does not specifically limit this. For example, the event sampler shown in Figure 2 can be used to sample and process the received second combined pulse signal. The maximum processing rate of the event sampler can be simply understood as the signal processing rate of the back-end processing system.

[0080] It should be noted that the preset time interval can be a pulse signal time interval according to the algorithm requirements in the back-end processing system. For example, in different application scenarios, due to the different specific requirements of different algorithms for photon pulses (for example: signal-to-noise ratio, the relationship between light wavelength and photon pulse interval, etc.), that is, the time interval requirements of two adjacent pulse signals in the second combined pulse signal of different algorithms are different, the speed limiter can also perform pulse deletion processing on the first combined pulse signal based on different preset time intervals, and output a second combined pulse signal. Exemplarily, in two different application scenarios of lidar ranging and photon imaging, when the maximum signal processing rate of their back-end processing systems is consistent, due to different algorithm requirements, the speed limiters in the different scenarios can perform pulse deletion processing on the first combined pulse signal based on different preset time intervals, and output different second combined pulse signals. The size of the preset time interval can be specifically controlled by the back-end processing system, and this embodiment of the present application does not make specific limitations on this.

[0081] It can also be understood that the pulse signal in the first combined pulse signal can drive the speed limiter to perform deletion processing on the first combined pulse signal, wherein the speed limiter does not delete the first combined pulse signal based on the number of pulse signals, but deletes it based on the length of the time interval between the pulse signals in the time domain. The time interval between any two adjacent pulse signals in the second combined pulse signal obtained after deletion is greater than or equal to the first preset duration.

[0082] Exemplarily, a pulse signal that does not meet the signal processing rate or the preset time interval under the drive of a pulse signal, that is, a pulse signal whose time interval between two adjacent pulse signals is less than the first preset time length will be deleted so that the subsequent processing system can process all the pulse signals in the second combined pulse normally and orderly. For example: as shown in Figure 4 above, the time interval between any two adjacent pulse signals of pulse signal 1, pulse signal 2 and pulse signal 4 is greater than or equal to the first preset time length, and the time interval between pulse signal 4 and pulse signal 5 is less than the first preset time length. Therefore, the second combined pulse signal includes pulse signal 1, pulse signal 2 and pulse signal 4, and pulse signal 5 is deleted.

[0083] Accordingly, the first preset duration can be understood as the minimum time interval between any two adjacent pulse signals in the second combined pulse signal. The first preset duration can be pre-set or can be adaptively adjusted according to the back-end signal processing rate or the preset time interval. This embodiment of the present application does not impose specific limitations on this. For example, when the signal processing rate is slow, the first preset duration is increased; when the signal processing rate is fast, the first preset duration is reduced. This embodiment of the present application does not impose specific limitations on this.

[0084] In addition, it should be noted that the first preset time length needs to be greater than the circuit delay of the speed limiter, otherwise the speed limiter cannot correctly output the second combined pulse signal with a time interval less than the circuit delay.

[0085] It can also be understood that compared with the global clock used by the memory, the speed limiter in the embodiment of the present application is an asynchronous speed limiter, which does not require the drive of the global clock. It can realize pulse deletion processing of the first combined pulse signal based on the drive of the pulse signal in the first combined pulse signal by the present application, thereby greatly reducing the device cost.

[0086] It should be noted that the embodiments of the present application utilize an asynchronous combiner and an asynchronous speed limiter. That is, the combined signal processing and pruning of pulse signals are all asynchronous, without the need for synchronization with a global clock signal. For example, when K pulse signals are input from a first combined pulse signal, the speed limiter is driven to perform pulse pruning on the first combined pulse signal. If the first combined pulse signal is not received, the speed limiter cannot operate normally due to the lack of a driving signal.

[0087] In some embodiments, the speed limiter includes: a latch, an integrator and a comparator; the input end of the latch and the driving end of the comparator are connected to the output end of the combiner, the reset end of the latch is connected to the output end of the comparator, the output end of the latch is connected to the first input end of the comparator through the integrator, and the second input end of the comparator is connected to a reference voltage; wherein, the latch is used to receive the K pulse signals in the first combined pulse signal, and output the M pulse signals in the second combined pulse signal based on the reset signal fed back by the comparator; so the integrator is used to receive the M pulse signals output by the latch, integrate the M pulse signals and output the corresponding integrated voltage; the comparator is used to compare the integrated voltage output by the integration circuit with the reference voltage when receiving the drive of the K pulse signals in the first combined pulse, and output the reset signal to the latch based on the comparison result.

[0088] Wherein, please refer to Figures 5 and 6. Figure 5 is a schematic diagram of the structure of another receiving device provided in an embodiment of the present application, and Figure 6 is a schematic diagram of the working principle of a speed limiter provided in an embodiment of the present application. As shown in Figure 5, the speed limiter includes: a latch, an integrator and a comparator. Wherein, the latch includes an input terminal S, a reset terminal R and an output terminal Q. The input terminal S of the latch is connected to the output terminal of the combiner and the driving terminal of the comparator, the reset terminal R of the latch is connected to the output terminal of the comparator, and the output terminal Q of the latch is connected to the first input terminal of the comparator through the integrator. For example, the input terminal of the integrator is connected to the output terminal Q of the latch, and the output terminal is connected to the first input terminal of the comparator. In addition, the second input terminal of the comparator is connected to the reference voltage VREF.

[0089] It can be understood that, for the latch, only when a valid reset signal is input to the reset terminal, the state of the input terminal of the latch is saved to the output terminal (that is, the output at this time changes with the input). When there is no valid reset signal input to the reset terminal, the latch will be in a latched state until the next valid reset signal is input to the reset terminal. Exemplarily, as shown in Figure 6, taking the reset signal as a low level valid example, that is, when S=1, R=0, the pulse signal 1 and the pulse signal 3 in the first combined pulse signal input to the input terminal of the latch can pass. When R=1, the state of the latch is locked, and the output at this time will not change with the change of the input. Therefore, the pulse signal 2 of the first combined pulse signal input to the latch cannot pass. Therefore, the latch of the receiving device can control the output of M pulse signals (that is, the second combined pulse signal) out of the K pulse signals (that is, the first combined pulse signal) based on the reset signal fed back by the comparator, that is, M is a positive integer less than or equal to K.

[0090] Regarding the comparator, the comparator in the speed limiter is a dynamic comparator that can maintain a high output level in the absence of a pulse signal drive, that is, the reset terminal maintains R = 1 at this time. When the comparator receives the drive of the K pulse signals in the first combined pulse, for example, when the comparator receives the rising edge of the pulse signal, it begins to compare the integrated voltage output by the integrator with the reference voltage, and outputs the reset signal to the latch based on the comparison result. For example, when the integrated voltage is greater than the reference voltage, the level is pulled low so that R = 0, and the latch outputs the corresponding pulse signal. In this way, under the drive of the pulse signal, following the drive of the pulse signal, and the integrator's integration processing of the pulse signal, the comparator can obtain different comparison results in the process of the integrator outputting the integrated voltage, and can thus output different reset signals in different time periods. Correspondingly, the speed limiter can control the time interval between adjacent pulse signals in the output second combined pulse signal by controlling the time that the reset signal maintains a high level state or a low level state (as shown in Figure 6 above). This pulse deletion method is simple and efficient, and does not require the drive of a global clock, which helps to further reduce the device size of the receiving device and improve the processing efficiency of photon events.

[0091] For the integrator, the integrator can receive the M pulse signals output by the latch, integrate the M pulse signals and output a corresponding integrated voltage. It should be noted that when there is no pulse signal driving or after the integration processing of the previous pulse signal is completed, the integrated voltage of the integrator will quickly reset to the power supply voltage (VDD).

[0092] Please refer to FIG7 and FIG8 , which are comparative schematic diagrams of a group of second combined pulse signals corresponding to different integration speeds provided in an embodiment of the present application.

[0093] As shown in FIG7 , when there is no pulse signal input, the integrated voltage Vramp of the integrator remains at or close to the power supply voltage VDD, and the reset signal Vout output by the comparator maintains a high level state.

[0094] When pulse signal 1 in the first combined pulse signal is input into the latch and drives the comparator, the integrator has not yet received the input of pulse signal 1, and its corresponding integrated voltage Vramp still maintains or is close to the power supply voltage VDD; the driving end of the comparator directly receives the drive of pulse signal 1, and can then start to compare the integrated voltage Vramp with the reference voltage VREF. At this time, since the integrated voltage Vramp is greater than the reference voltage VREF, the comparator pulls down the output reset signal Vout, that is, the reset signal Vout changes from a high level to a low level state; after the latch receives the pulled-down reset signal Vout, it can output the first pulse signal in the second combined pulse signal, that is, pulse signal 1.

[0095] In addition, after receiving the driving of the falling edge of the first pulse signal, the comparator pulls up the output reset signal Vout, that is, the reset signal Vout changes from a low level to a high level state.

[0096] At this point, since the latch also outputs pulse signal 1 to the integrator, this pulse signal 1 can be input to the integrator to begin integration, that is, the integrated voltage Vramp output by the integrator begins to ramp up. During the integrator's integration process, if the comparator receives the rising edge drive of the second pulse signal (i.e., pulse signal 2) in the first combined pulse signal again, it can then begin comparing the integrated voltage Vramp with the reference voltage VREF again.

[0097] As shown in Figure 7, the comparator receives the rising edge drive of the second pulse signal (i.e., pulse signal 2) in the first combined pulse signal again, and begins to compare the integrated voltage Vramp with the reference voltage VREF. Since the integration speed of the integrator is relatively fast, the integrated voltage Vramp is greater than the reference voltage VREF at this time. The comparator pulls down the output reset signal Vout again, that is, the reset signal Vout changes from a high level to a low level state; after receiving the reset signal Vout that has been pulled down again, the latch outputs the second pulse signal in the second combined pulse signal, i.e., pulse signal 2. After the integrator completes the integration processing for pulse signal 1, it will perform integration processing on pulse signal 2 again.

[0098] As shown in Figure 8, the comparator receives the rising edge drive of the second pulse signal (i.e., pulse signal 2) in the first combined pulse signal again, and begins to compare the integrated voltage Vramp with the reference voltage VREF. Due to the slow integration speed of the integrator, the integrated voltage Vramp is less than the reference voltage VREF. The comparator maintains the high-level reset signal Vout unchanged, that is, the reset signal Vout remains high, and the latch cannot output pulse signal 2. The integrator will continue to complete the integration process for pulse signal 1.

[0099] After receiving the drive of the falling edge of pulse signal 2, the comparator continues to maintain the high-level reset signal Vout unchanged until it receives the rising edge drive of pulse signal 3, and starts to compare the integral voltage Vramp and the reference voltage VREF. At this time, the integral voltage Vramp is greater than the reference voltage VREF, and the comparator can pull down the output reset signal Vout. After receiving the pulled-down reset signal Vout, the latch outputs the second pulse signal in the second combined pulse signal, that is, pulse signal 3.

[0100] As can be seen from the comparative schematic diagrams of the second combined pulse signal shown in Figures 7 and 8 above, the integrator can control the time interval of the output of the second combined pulse signal for different integration speeds of the pulse signal. When the integration speed is fast enough, that is, within a sufficiently short time, such as before the rising edge of the next pulse signal arrives (e.g., within a time period less than t0), the integrated voltage Vramp output by the integrator can be greater than the reference voltage VREF, then the latch can receive a reset signal to output the next pulse signal. As shown in Figure 7, the second combined pulse signal includes pulse signal 1 and pulse signal 2. Correspondingly, when the integration speed is slow and is not enough to make the integrated voltage Vramp output by the integrator greater than the reference voltage VREF before the rising edge of the next pulse signal arrives, then the latch cannot output the next pulse signal. As shown in Figure 8, the second combined pulse signal does not include pulse signal 2.

[0101] It is understood that the first preset duration mentioned in the above embodiment can be specifically understood as the duration after the integrator begins integration, during which the integrated voltage reaches or exceeds the reference voltage. When the time interval between two adjacent pulse signals in the first combined pulse signal is less than the first preset duration, the second combined pulse signal will be deleted from the latter of the two pulse signals.

[0102] In some embodiments, the integrator includes a current source, a first switch tube, a second switch tube and a capacitor; one end of the current source is connected to the power supply voltage, one end of the current source is connected to one end of the first switch tube, the other end of the first switch tube and one end of the second switch tube are connected to one end of the capacitor, and the other end of the second switch tube and the other end of the capacitor are grounded; the control end of the first switch tube and the control end of the second switch tube serve as the input end of the integrator, connected to the output of the latch, and used to receive the second combined pulse signal.

[0103] Please refer to Figure 9, which is a schematic diagram of the circuit structure of a speed limiter provided in an embodiment of the present application. As shown in Figure 9, the speed limiter includes a latch, an integrator and a comparator. Among them, the integrator includes a current source, a first switch tube T1, a second switch tube T2 and a capacitor C. One end of the current source is connected to the power supply voltage VDD, one end of the current source is connected to one end of the first switch tube T1, the other end of the first switch tube T1 and one end of the second switch tube T2 are connected to one end of the capacitor C, and the other end of the second switch tube T2 and the other end of the capacitor C are grounded; the control end of the first switch tube T1 and the control end of the second switch tube T2 serve as the input end of the integrator, connected to the output of the latch, and used to receive the second combined pulse signal. It can be understood that the pulse signal can control the first switch tube T1 and the second switch tube T2 to turn on to perform integration processing on the pulse signal. In this regard, an embodiment of the present application provides a simple and efficient integrator circuit structure, in which the current source and capacitance value in the integrator can determine the speed of the integration processing of the integrator. Therefore, the speed of the integration processing of the integrator can be controlled by adjusting the size of the current source and capacitance value in the integrator to adapt to the subsequent signal processing rate for the second combined pulse signal.

[0104] In some embodiments, the smaller the capacitance value of the capacitor, the shorter the first preset time length; the larger the current value of the current source, the shorter the first preset time length; the smaller the reference voltage, the shorter the first preset time length.

[0105] It is understandable that, according to the circuit structure of the integrator, and as shown in Figures 7 and 8 above, when the capacitance value of the capacitor is smaller, the integration speed is faster, the integration voltage can reach the size of the reference voltage faster, and the corresponding first preset duration is shorter. When the current value of the current source is larger, the integration speed is faster, the integration voltage can reach the size of the reference voltage faster, and the corresponding first preset duration is shorter. Therefore, the embodiment of the present application can control the speed of the integration processing speed by adjusting the size of the capacitance and current source of the integrator, and then control the length of the first preset duration, thereby controlling the pulse rate of the second combined pulse signal. For example: when the signal processing rate is slow, the minimum time interval (i.e., the first preset duration) between two adjacent pulse signals can be extended. At this time, the capacitance value can be increased, the current source can be reduced, etc.

[0106] It is also understandable that, when the preset reference voltage is constant, the faster the integrator integrates the pulse signal, the shorter the first preset time duration, and the shorter the effective waiting time corresponding to the pulse signal. Correspondingly, when the integrator integrates the pulse signal at a constant speed, the smaller the reference voltage is, the shorter the first preset time duration is, and the shorter the effective waiting time corresponding to the pulse signal is.

[0107] Please refer to Figure 10, which is a comparative schematic diagram of the second combined pulse signal corresponding to different reference voltages provided in an embodiment of the present application. As shown in Figure 10, when the integration processing speed of the integrator is the same, different reference voltages can control the effective waiting time corresponding to the pulse signal to be different. After the integrator outputs the integrated voltage, when the comparator compares the integrated voltage with the reference voltage, the smaller the reference voltage VREF, the earlier the reset signal Vout2 outputs a low-level signal, and the corresponding first preset time length is shorter; the larger the reference voltage VREF, the later the reset signal Vout1 outputs a low-level signal, and the corresponding first preset time length is longer. For example: as shown in Figure 10 above, since the reference voltage VREF1 is greater than the reference voltage VREF2, the time interval corresponding to the second combined pulse signal 1 is greater than the time interval corresponding to the second combined pulse signal 2. The second combined pulse signal 1 only includes pulse signal 1, and the second combined pulse signal 2 includes pulse signal 1 and pulse signal 2.

[0108] In some embodiments, the apparatus further comprises an address processing module; the address processing module is configured to determine address information of a receiving unit in the receiving array corresponding to each pulse signal in the second combined pulse signal.

[0109] Please refer to Figure 11, which is a structural diagram of another receiving device provided in an embodiment of the present application. As shown in Figure 11, the receiving device also includes an address processing module for determining the address information corresponding to each pulse signal in the above-mentioned second combined pulse signal, so as to perform imaging or ranging processing subsequently. It can be understood that when performing imaging or ranging processing on the second combined pulse signal, it is necessary to determine the address information of the receiving unit corresponding to each pulse signal in the second combined pulse signal in the above-mentioned receiving array. The address processing module can synchronously determine the address information of the remaining pulse signals when multiple pulse signals are subjected to signal merging processing or pulse deletion processing, so as to determine the address information corresponding to each pulse signal in the second combined pulse signal when outputting the second combined pulse signal.

[0110] In some embodiments, the address processing module includes an address encoder and an address decoder; the address encoder is used to: when the combiner outputs the first combined pulse signal, output the encoded address information corresponding to each pulse signal in the first combined pulse signal to the address decoder; the address decoder is used to: based on the encoded address information corresponding to each pulse signal in the first combined pulse signal, when the speed limiter outputs the second combined pulse signal, output the decoding address information corresponding to each pulse signal in the second combined pulse signal, and the decoding address information includes the address information of the receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array.

[0111] It is understandable that the address information of each pulse signal will be synchronously input to the back-end processing system for imaging or ranging processing according to the pulse signal. Accordingly, the address processing module includes an address encoder and an address decoder to encode and decode the address information, while also avoiding errors or omissions in the address information of the pulse signal. For example: the address encoder can output the coded address information corresponding to each pulse signal in the first combined pulse signal to the address decoder when the combiner outputs the first combined pulse signal. Exemplarily, the address decoder can decode the address coding information of the M pulse signals based on the coded address information corresponding to each pulse signal in the first combined pulse signal when the speed limiter outputs the second combined pulse signal, that is, after determining the M pulse signals output by the second combined pulse signal, to obtain the address information of the receiving units corresponding to the M pulse signals in the above-mentioned receiving array. It is understandable that the embodiment of the present application does not specifically limit the encoding method and decoding method of the address information.

[0112] In some embodiments, each of the above-mentioned receiving units detects the photon signal through one or more avalanche diodes and outputs the above-mentioned pulse signal; the above-mentioned receiving device also includes an avalanche quenching and reset module; the above-mentioned avalanche reset module is used to: after the receiving unit outputs the above-mentioned pulse signal, quench and reset one or more above-mentioned avalanche diodes of the corresponding receiving unit.

[0113] The receiving device can be applied to the field of single-photon imaging or ranging. For example, an avalanche diode can be used to collect photon events, which can greatly improve the quality of imaging or ranging. In order to ensure the normal use of the avalanche diode within each time window, as shown in Figure 11 above, the receiving device also includes an avalanche reset module. After the receiving unit outputs the above-mentioned pulse signal, the avalanche reset module can quench and reset one or more avalanche diodes of the corresponding receiving unit, so that after the receiving unit outputs the above-mentioned pulse signal, the photon signal can be detected again and the corresponding pulse signal can be output.

[0114] In the prior art, in order to avoid missing large-scale photon events, a memory is usually added to the receiving end to store photon events that have not been fully processed. However, this will result in a large area of ​​storage devices on the chip or receiving end, and the size of the memory will also inversely limit the scale of subsequent photon event processing. In addition, the chip or receiving end also requires additional resources to drive the memory to write, read or reset, which wastes resources. In this regard, the embodiment of the present application can efficiently process a large number of photon events without setting up a memory, avoid missing large-scale photon events, and thus reduce resource consumption while reducing the hardware area, thereby improving the processing efficiency of photon events. For example: The embodiment of the present application provides a receiving device that can be applied to the receiving end of a laser radar or imaging system. The receiving device is connected to a receiving array that outputs multiple pulse signals. The receiving device includes a combiner and a speed limiter. The combiner is connected to the receiving array and can be used to combine the N pulse signals output by the receiving array for signal processing, outputting a first combined pulse signal, and the first combined pulse signal includes K pulse signals out of the N pulse signals. The combiner combines multiple pulse signals from parallel transmission into serial transmission, which is conducive to the orderly processing of the back-end processing system. Compared with the solution of directly performing imaging or ranging processing on the first combined pulse signal in the prior art, the first combined pulse signal output after the combiner is combined in the embodiment of the present application also needs to be processed by the pulse deletion of the above-mentioned speed limiter, and then the second combined pulse signal obtained after the pulse deletion is processed is imaged or ranging. Since the speed limiter performs pulse deletion processing on the above-mentioned first combined pulse signal based on the size of the signal processing rate or the preset time interval, the number and time interval of the pulse signals in the output second combined pulse signal can meet the requirements of the subsequent signal processing rate or the preset time interval. Therefore, in the embodiment of the present application, it is possible to avoid missing large-scale photon events without setting up a large-scale storage device. Moreover, the area of ​​the speed limiter is greatly reduced compared to the area of ​​the memory, which greatly reduces the overall area of ​​the receiving device. Moreover, the speed limiter does not require a lot of additional resources to drive operations such as writing, reading or resetting, which greatly reduces resource consumption. Most importantly, since the second combined pulse signal obtained after pulse deletion meets the signal processing rate requirements, the rate limiter does not limit the scale of subsequent photon event processing, greatly improving the processing efficiency of photon events.

[0115] In addition, based on the hardware structure of the receiving device mentioned above, the technical problems raised in this application are further analyzed and solved in combination with a receiving method provided in this application.

[0116] Please refer to FIG12 , which is a flowchart of a receiving method provided in an embodiment of the present application.

[0117] This receiving method can be applied to the receiving device involved in the embodiments shown in Figures 2 to 11 above. The receiving device is connected to a receiving array, wherein the receiving array includes N receiving units, each of which is configured to receive an optical signal and output a pulse signal, where N is a positive integer greater than or equal to 2. The receiving device includes a combiner and a rate limiter. The specific relevant descriptions of each step of the method are as follows:

[0118] Step S101: receiving pulse signals respectively output by N receiving units through a combiner, performing signal combining processing on the received N pulse signals, and obtaining a first combined pulse signal.

[0119] Specifically, the receiving device can receive the pulse signals output by the above-mentioned N receiving units respectively through the above-mentioned combiner, perform signal merging processing on the received N pulse signals, and obtain a first combined pulse signal, wherein the above-mentioned first combined pulse signal includes K pulse signals among the above-mentioned N pulse signals, and K is a positive integer less than or equal to N.

[0120] In some embodiments, the above-mentioned N pulse signals include a first pulse signal and a second pulse signal; and the time when the above-mentioned combiner receives the above-mentioned first pulse signal is earlier than the time when the above-mentioned second pulse signal is received; when the time interval between the time when the above-mentioned first pulse signal is received and the time when the above-mentioned second pulse signal is received is greater than the second preset time length, the above-mentioned K pulse signals include the above-mentioned first pulse signal and the above-mentioned second pulse signal; when the time interval between the time when the above-mentioned first pulse signal is received and the time when the above-mentioned second pulse signal is received is less than or equal to the above-mentioned second preset time length and greater than the third preset time length, the above-mentioned K pulse signals include the above-mentioned first pulse signal and do not include the above-mentioned second pulse signal; when the time interval between the time when the above-mentioned first pulse signal is received and the time when the above-mentioned second pulse signal is received is less than or equal to the above-mentioned third preset time length, the above-mentioned K pulse signals do not include the above-mentioned first pulse signal and the above-mentioned second pulse signal.

[0121] Step S102: The rate limiter performs pulse deletion processing on the first combined pulse signal based on the signal processing rate or a preset time interval to obtain a second combined pulse signal.

[0122] Specifically, the receiving device may perform pulse pruning processing on the first combined pulse signal based on the signal processing rate or a preset time interval through the rate limiter to obtain a second combined pulse signal. The second combined pulse signal includes M pulse signals from the K pulse signals, where M is a positive integer less than or equal to K.

[0123] In some embodiments, the above-mentioned speed limiter performs pulse deletion processing on the above-mentioned first combined pulse signal based on the size of the signal processing rate or the preset time interval to obtain the second combined pulse signal, including: under the drive of the K pulse signals in the above-mentioned first combined pulse signal, the above-mentioned first combined pulse signal is pulse deleted based on the size of the above-mentioned signal processing rate or the preset time interval to output the above-mentioned second combined pulse signal; the time interval between any two adjacent pulse signals of the above-mentioned M pulse signals in the above-mentioned second combined pulse signal is greater than or equal to the first preset duration, and the above-mentioned first preset duration is determined by the above-mentioned signal processing rate.

[0124] In some embodiments, the speed limiter includes: a latch, an integrator and a comparator; the input end of the latch and the driving end of the comparator are connected to the output end of the combiner, the reset end of the latch is connected to the output end of the comparator, the output end of the latch is connected to the first input end of the comparator through the integrator, and the second input end of the comparator is connected to a reference voltage; the speed limiter performs pulse deletion processing on the first combined pulse signal based on the size of the signal processing rate or the preset time interval to obtain the second combined pulse signal, including: receiving the K pulse signals in the first combined pulse signal through the latch, and outputting the M pulse signals in the second combined pulse signal based on the reset signal fed back by the comparator; the method further includes: receiving the M pulse signals output by the latch through the integrator, integrating the M pulse signals and outputting corresponding integrated voltages; when the comparator receives the drive of the K pulse signals in the first combined pulse, comparing the integrated voltage output by the integration circuit with the reference voltage, and outputting the reset signal to the latch based on the comparison result.

[0125] In some embodiments, the integrator includes a current source, a first switch tube, a second switch tube and a capacitor; one end of the current source is connected to the power supply voltage, one end of the current source is connected to one end of the first switch tube, the other end of the first switch tube and one end of the second switch tube are connected to one end of the capacitor, and the other end of the second switch tube and the other end of the capacitor are grounded; the control end of the first switch tube and the control end of the second switch tube serve as the input end of the integrator, connected to the output of the latch, and used to receive the second combined pulse signal.

[0126] In some embodiments, the smaller the capacitance value of the capacitor in the integrator, the shorter the first preset time length; the larger the current value of the current source in the integrator, the shorter the first preset time length; the smaller the reference voltage in the comparator, the shorter the first preset time length.

[0127] In some embodiments, the above-mentioned device further includes an address processing module; the above-mentioned method further includes: determining, by the above-mentioned address processing module, address information of a receiving unit corresponding to each pulse signal in the above-mentioned second combined pulse signal in the above-mentioned receiving array.

[0128] In some embodiments, the address processing module includes an address encoder and an address decoder; the address processing module determines the address information of the receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array, including: outputting the coded address information corresponding to each pulse signal in the first combined pulse signal to the address decoder through the address encoder when the combiner outputs the first combined pulse signal; outputting the decoding address information corresponding to each pulse signal in the second combined pulse signal through the address decoder based on the coded address information corresponding to each pulse signal in the first combined pulse signal and when the speed limiter outputs the second combined pulse signal, the decoding address information includes the address information of the receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array.

[0129] In some embodiments, each of the above-mentioned receiving units detects the photon signal through one or more avalanche diodes and outputs the above-mentioned pulse signal; the above-mentioned receiving device also includes an avalanche quenching and reset module; the above-mentioned method also includes: after the receiving unit outputs the above-mentioned pulse signal through the above-mentioned avalanche reset module, quenching and resetting one or more of the above-mentioned avalanche diodes of the corresponding receiving unit.

[0130] An embodiment of the present application also provides a laser radar, which includes: a receiving array and a receiving device involved in the relevant embodiments shown in Figures 2 to 11 above, the receiving device is connected to the receiving array, and the receiving array includes multiple receiving units, each of which is used to detect photon signals and output pulse signals.

[0131] The present application also provides an imaging system comprising a receiving array and a receiving device according to the embodiments shown in Figures 2 to 11. The receiving device is connected to the receiving array, which comprises a plurality of receiving units, each of which is configured to detect photon signals and output pulse signals.

[0132] It should be understood that the receiving method, laser radar or imaging system provided in the embodiments of the present application are consistent with the receiving device involved in the relevant embodiments shown in Figures 2 to 11 above. The specific content and beneficial effects can be referred to the receiving device involved in the relevant embodiments shown in Figures 2 to 11 above, and will not be repeated here.

[0133] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0134] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0135] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0136] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0137] In addition, the functional units in the embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0138] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to execute all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0139] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A receiving device, characterized in that: The device is connected to a receiving array, wherein the receiving array includes N receiving units, each of which is used to detect a photon signal and output a pulse signal, and N is a positive integer greater than or equal to 2; the receiving device includes: a combiner and a rate limiter; The combiner is connected to the receiving array and is used to: receive the pulse signals respectively output by the N receiving units, perform signal combining processing on the received N pulse signals, and output a first combined pulse signal, where the first combined pulse signal includes K pulse signals of the N pulse signals, where K is a positive integer less than or equal to N; The speed limiter is used to: receive the first combined pulse signal; perform pulse deletion processing on the first combined pulse signal based on the size of the signal processing rate or a preset time interval, and output a second combined pulse signal; wherein, the second combined pulse signal includes M pulse signals of the K pulse signals, and M is a positive integer less than or equal to K.

2. The device according to claim 1, characterized in that The speed limiter is specifically configured to: under the drive of K pulse signals in the first combined pulse signal, perform pulse deletion processing on the first combined pulse signal based on the size of the signal processing rate or the preset time interval, and output the second combined pulse signal; The time interval between any two adjacent pulse signals in the M pulse signals in the second combined pulse signal is greater than or equal to a first preset duration, and the first preset duration is determined by the signal processing rate or the preset time interval.

3. The device according to claim 2, characterized in that The speed limiter includes: a latch, an integrator and a comparator; The input end of the latch and the driving end of the comparator are connected to the output end of the combiner, the reset end of the latch is connected to the output end of the comparator, the output end of the latch is connected to the first input end of the comparator through the integrator, and the second input end of the comparator is connected to a reference voltage; The latch is configured to receive the K pulse signals in the first combined pulse signal and output the M pulse signals in the second combined pulse signal based on the reset signal fed back by the comparator; Therefore, the integrator is used to receive the M pulse signals output by the latch, integrate the M pulse signals and output a corresponding integrated voltage; The comparator is configured to compare the integrated voltage output by the integration circuit with the reference voltage when receiving the drive of the K pulse signals in the first combined pulse, and output the reset signal to the latch based on the comparison result.

4. The device according to claim 3, characterized in that The integrator includes a current source, a first switch tube, a second switch tube and a capacitor; One end of the current source is connected to the power supply voltage, one end of the current source is connected to one end of the first switch tube, the other end of the first switch tube and one end of the second switch tube are connected to one end of the capacitor, and the other end of the second switch tube and the other end of the capacitor are grounded; The control end of the first switch tube and the control end of the second switch tube serve as input ends of the integrator, are connected to the output of the latch, and are used to receive the second combined pulse signal.

5. The device according to claim 4, characterized in that The smaller the capacitance value of the capacitor in the integrator, the shorter the first preset time length; the larger the current value of the current source in the integrator, the shorter the first preset time length; the smaller the reference voltage in the comparator, the shorter the first preset time length.

6. The device according to any one of claims 1 to 5, characterized in that: The N pulse signals include a first pulse signal and a second pulse signal; and the time when the combiner receives the first pulse signal is earlier than the time when the combiner receives the second pulse signal; The combiner is specifically configured to: when the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is greater than a second preset time length, the K pulse signals include the first pulse signal and the second pulse signal; In the case where the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is less than or equal to the second preset time length and greater than the third preset time length, the K pulse signals include the first pulse signal and do not include the second pulse signal; In a case where the time interval between the time when the first pulse signal is received and the time when the second pulse signal is received is less than or equal to the third preset duration, the K pulse signals do not include the first pulse signal and the second pulse signal.

7. The device according to any one of claims 1 to 6, characterized in that: The device further includes an address processing module; the address processing module is used to determine the address information of the receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array.

8. The device according to claim 7, characterized in that The address processing module includes an address encoder and an address decoder; The address encoder is used to: when the combiner outputs the first combined pulse signal, output the encoded address information corresponding to each pulse signal in the first combined pulse signal to the address decoder; The address decoder is used to: based on the encoded address information corresponding to each pulse signal in the first combined pulse signal, when the speed limiter outputs the second combined pulse signal, output the decoded address information corresponding to each pulse signal in the second combined pulse signal, and the decoded address information includes the address information of the receiving unit corresponding to each pulse signal in the second combined pulse signal in the receiving array.

9. The device according to any one of claims 1 to 8, characterized in that: Each of the receiving units detects the photon signal through one or more avalanche diodes and outputs the pulse signal; the receiving device also includes an avalanche quenching reset module; The avalanche reset module is used to quench and reset one or more avalanche diodes of the corresponding receiving unit after the receiving unit outputs the pulse signal.

10. A laser radar, characterized in that: The laser radar includes: a receiving array and a receiving device as described in any one of claims 1 to 9, the receiving device is connected to the receiving array, the receiving array includes a plurality of receiving units, each of the receiving units is used to detect photon signals and output pulse signals.

11. An imaging system, characterized in that: The imaging system includes: a receiving array and a receiving device according to any one of claims 1 to 9, wherein the receiving device is connected to the receiving array, and the receiving array includes a plurality of receiving units, each of which is used to detect a photon signal and output a pulse signal.

12. A receiving method, characterized in that: The method is applied to a receiving device connected to a receiving array, wherein the receiving array includes N receiving units, each receiving unit is configured to receive an optical signal and output a pulse signal, and N is a positive integer greater than or equal to 2; the receiving device includes a combiner and a rate limiter, and the method includes: Receiving the pulse signals respectively output by the N receiving units through the combiner, combining the received N pulse signals and performing signal processing to obtain a first combined pulse signal, wherein the first combined pulse signal includes K pulse signals of the N pulse signals, where K is a positive integer less than or equal to N; The speed limiter performs pulse deletion processing on the first combined pulse signal based on the size of the signal processing rate or a preset time interval to obtain a second combined pulse signal; wherein, the second combined pulse signal includes M pulse signals of the K pulse signals, and M is a positive integer less than or equal to K.

Images