Data processing method, apparatus and system

Abstract

Disclosed in embodiments of the present application are a data processing method, apparatus and system. Specifically, the method comprises: firstly, acquiring p first data streams having undergone RS encoding; then, respectively performing first data processing, which comprises FEC encoding and first interleaving, on the p first data streams to obtain m second data streams, m being an integer greater than or equal to p; and performing second data processing, which comprises second interleaving, dual-polarization (DP)-16QAM symbol mapping and framing, on the m second data streams to obtain one first DP symbol stream, wherein the first DP symbol stream comprises a symbol stream in a first polarization direction and a symbol stream in a second polarization direction. By means of the method, a concatenated FEC transmission scheme is simple to implement, has low power consumption and relatively high burst tolerance, can be applied to more transmission scenarios, and is particularly applicable to actual coherent transmission scenarios where colored noise exists in a channel.

Description

A data processing method, device and system

[0001] The present application claims priority from the Chinese patent application No. 202410518237.2 filed on April 25, 2024, and entitled "A data processing method, device and system", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, in particular to a data processing method, device and system. BACKGROUND

[0003] Under the continuous promotion of 5G, cloud computing, big data, artificial intelligence and other technologies, high-speed optical transmission networks are developing towards large capacity, packetization and intelligentization. Optical communication systems use the amplitude, phase, polarization or frequency of light waves to carry information. Using forward error correction (FEC) encoding to perform error correction coding on the transmitted data can solve transmission errors, and the receiving end can recover the original data sent by the sending end from the received data. A current cascaded FEC transmission scheme is proposed, in which a sending device and a sending processing module are connected through a connection unit interface. The sending device performs first FEC encoding on the data to be transmitted, and sends the first FEC encoded data to the sending processing module. The sending processing module performs second FEC encoding on the first FEC encoded data, and generates a corresponding modulation symbol sequence by modulating and mapping the second FEC encoded bit sequence. Finally, an optical signal is generated according to the modulation symbol sequence and transmitted to the receiving end through an optical fiber.

[0004] Generally, interleaving can be performed before and / or after the second FEC encoding to disrupt the data order, thereby enhancing the error correction performance of the overall FEC scheme. In addition, in the actual transmission process, the transmission link is affected by burst factors, which can cause a number of consecutive symbols in the modulation symbol sequence to be in error. The receiving end receives the modulation symbol sequence affected by the burst factors. Due to the large number of consecutive errors, it is difficult to accurately correct errors through the second FEC code, resulting in a high bit error rate of information transmission, i.e., the existing cascaded FEC encoding scheme has poor burst resistance. Moreover, the existing cascaded FEC encoding scheme and interleaving scheme for coherent transmission scenarios are mainly applied to 800Gbps scenarios and do not consider the compatibility requirements of the next generation of rates, especially the data structure of the data stream of the next generation of sending devices, which cannot adapt to future scenarios above 800Gbps (such as 1.6Tbps, etc.), and is a problem that needs to be solved urgently in the future. SUMMARY

[0005] The embodiment of the present application provides a data processing method, device and system. The cascaded FEC transmission scheme is simple in implementation, low in power consumption, strong in burst resistance, and applicable to more transmission scenes, especially applicable to actual coherent transmission scenes with colored noise.

[0006] In a first aspect, the embodiment of the present application provides a data processing method. Specifically, first, p pieces of first data streams encoded by Reed-Solomon (RS) are acquired, p is a positive integer multiple of 4, and p is an integer power of 2. Each a RS pieces of adjacent RS symbols in each first data stream come from a RS RS code word, a RS is greater than or equal to 4 and is an integer power of 2. Then, the first data processing including FEC encoding and first interleaving is performed on the p pieces of first data streams respectively to obtain m pieces of second data streams, m is an integer greater than or equal to p. Further, the second data processing including second interleaving, dual-polarization 16-ary quadrature amplitude modulation (DP-16QAM) symbol mapping and framing is performed on the m pieces of second data streams to obtain one piece of first dual-polarization symbol stream. The first dual-polarization symbol stream includes a symbol stream in a first polarization direction and a symbol stream in a second polarization direction.

[0007] In this embodiment, the cascaded FEC transmission scheme is simple in implementation and low in power consumption. Since the second interleaving is introduced before the DP-16QAM symbol mapping and framing, it is beneficial to reduce the influence of polarization dependent loss (PDL) on the X polarization direction and the Y polarization direction, has strong burst resistance, and can be applied to more transmission scenes, especially applicable to actual coherent transmission scenes with colored noise.

[0008] In some possible implementation manners, in the scene of m > p, the first data processing including FEC encoding and first interleaving is performed on the p pieces of first data streams respectively to obtain m pieces of second data streams, including: distributing each of the p pieces of first data streams to obtain m / p pieces of first sub-data streams, obtaining m pieces of first sub-data streams, and performing FEC encoding and first interleaving on the m pieces of first sub-data streams respectively to obtain m pieces of second data streams. In this implementation manner, the data processing method has better scalability through the distribution operation, which enriches the implementation manners of the scheme. In particular, when m = 32, the data processing method can be better compatible with the existing 800G coherent cascaded FEC processing architecture.

[0009] In some possible implementation, each first sub-data stream obtained by distributing the one first data stream comprises K consecutive bits in the one first data stream, K being a positive integer, wherein K is the number of information bits participating in FEC encoding. For example, the FEC encoding mode of N=128 and K=120 is adapted. For another example, the FEC encoding mode of N=176 and K=160 is adapted. Or, each first sub-data stream obtained by distributing the one first data stream comprises K0 consecutive bits in the one first data stream, K0 being an integer multiple of 40. For example, K is not an integer multiple of 40, wherein, represents rounding down. For example, K=110, The FEC encoding mode of N=126 and K=110 can be adapted. Here, multiple granularities of distributing the first data stream are provided, facilitating adaptation of different FEC encoding modes.

[0010] In some possible implementation, the first data processing comprising FEC encoding and first interleaving on the p first data streams to obtain the m second data streams comprises: performing convolution interleaving on the p first data streams, distributing each of the p first data streams after convolution interleaving to obtain m / p first sub-data streams, obtaining m first sub-data streams, and performing FEC encoding and first interleaving on the m first sub-data streams to obtain the m second data streams. It should be understood that performing convolution interleaving is beneficial to improving the performance of the cascaded FEC transmission scheme.

[0011] In some possible implementation, the first data processing comprising FEC encoding and first interleaving on the p first data streams to obtain the m second data streams comprises: performing convolution interleaving on the p first data streams, and performing FEC encoding and first interleaving on the p first data streams after convolution interleaving to obtain the m second data streams. In this implementation, convolution interleaving and distribution are decoupled, enriching the implementation of the present scheme.

[0012] In some possible implementation, the convolution interleaving on the one first data stream comprises: delaying bits from the first data stream according to r delay lines, r being an integer greater than 1, each delay line comprising a different number of storage units, the delay line comprising the smallest number of storage units comprising 0 storage unit, the difference between the number of storage units of each adjacent two delay lines being Q, each storage unit being configured to store d bits, the input bits being input to the r delay lines in sequence according to the sequence number of the r delay lines, d bits being input to each delay line at a time and d bits being output from each delay line at a time, Q and d being integers greater than or equal to 1. It should be understood that the storage unit is also referred to as a delay element.

[0013] In some possible implementation manners, the delay line with the largest serial number among the r delay lines includes 0 memory cells, or the delay line with the smallest serial number among the r delay lines includes 0 memory cells. Different implementation manners of the convolution interleaving are provided herein, so as to adapt to different application scenarios.

[0014] In some possible implementation manners, d = a RS × 10.

[0015] In some possible implementation manners, a RS = 4 or 8.

[0016] In some possible implementation manners, the delay line with the largest serial number among the r delay lines includes 0 memory cells or the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p = 8, r = 3, d = 40, and Q ≥ 23. In order to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 24. Or, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p = 16, r = 3, d = 40, and Q ≥ 11. In order to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 12 or 14 or 16. Or, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p = 16, r = 3, d = 40, and Q ≥ 12. In order to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 12 or 14 or 16. Or, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p = 4, r = 3, d = 40, and Q ≥ 45. In order to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 46 or 48. Or, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p = 4, r = 3, d = 40, and Q ≥ 46. In order to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 46 or 48. For different values of p, appropriate r, d, and Q parameters and implementation manners of the convolution interleaving are selected, so that any 12 consecutive RS symbols in the data stream after the convolution interleaving come from 12 different RS code words, which can be used for N = 128 and K = 120 FEC encoding mode, and can make the FEC cascading scheme including RS encoding and inner code encoding have optimal performance. Or, appropriate r, d, and Q parameters and implementation manners of the convolution interleaving are selected, so that any 11 consecutive RS symbols in the data stream after the convolution interleaving come from 11 different RS code words, which can be used for N = 126 and K = 110 FEC encoding mode, and can make the FEC cascading scheme including RS encoding and inner code encoding have optimal performance.

[0017] In some possible embodiments, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p = 4, r = 4, d = 40, Q ≥ 34, and to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 36 or 38 or 40. Alternatively, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p = 4, r = 4, d = 40, Q ≥ 35, and to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 36 or 38 or 40. Alternatively, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p = 8, r = 4, d = 40, Q ≥ 17, and to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 18 or 20 or 24. Alternatively, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p = 8, r = 4, d = 40, Q ≥ 18, and to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 18 or 20 or 24. Alternatively, the delay line with the largest serial number among the r delay lines includes 0 memory cells or the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p = 16, r = 4, d = 40, Q ≥ 9, and to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 10 or 12 or 16. By selecting appropriate r, d and Q parameters and implementation of the convolution interleaver, any 16 consecutive RS symbols in the data stream after convolution interleaving can come from 16 different RS code words, which can be used for FEC encoding with N = 176 and K = 160, and can make the FEC cascade scheme including RS encoding and inner code encoding have optimal performance.

[0018] In some possible embodiments, the number of information bits participating in FEC encoding is K, each code word after FEC encoding includes N bits, and N-K check bits in the code word are obtained by FEC encoding of K information bits. The first interleaving is used for cyclically shifting every K information bits in the first data stream.

[0019] In some possible embodiments, p = 4, and the first interleaving is used for cyclically shifting every K information bits in the first data stream i bits, 0 ≤ i < 4, and one of the following is satisfied:

[0020] Alternatively, p = 8, and the first interleaving is used for cyclically shifting every K information bits in the first data stream i bits, 0 ≤ i < 8, satisfies one of the following:

[0021] or, p = 16, the first interleaving is used to cyclically shift every K information bits in the first data stream i bits, 0≤i<16, satisfies one of the following:

[0022] In some possible implementation manners, the first data processing on the first data stream including FEC encoding and first interleaving includes one of the following manners. Manner 1: performing first interleaving on the first data stream, and performing FEC encoding on the first data stream after the first interleaving. Manner 2: performing FEC encoding on the first data stream, and performing first interleaving on the first data stream after the FEC encoding. Manner 3: performing FEC encoding on K information bits in the first data stream to obtain N-K check bits, and performing first interleaving on the K information bits to obtain N bits including the N-K check bits and the K information bits after the first interleaving, where K is a positive integer, and N>K. Here, various implementation manners of the first data processing are provided, which improves the expansibility of the scheme.

[0023] In some possible implementation manners, the second interleaving and the DP-16QAM symbol mapping on the m second data streams include: obtaining N bits in each second data stream to obtain m×N bits, the N bits including K information bits and N-K check bits in a codeword after FEC encoding; performing second interleaving on the m×N bits; and performing DP-16QAM symbol mapping on the m×N bits after the second interleaving to obtain N×m / 8 DP-16QAM symbols. That is, 1 codeword is obtained from each second data stream to obtain a total of m codewords, and the second interleaving is performed in combination with the m codewords to shuffle the bit order, thereby facilitating improvement of the overall burst performance of the concatenated code.

[0024] In some possible implementation manners, p = 8, m = 8, denotes the j0th bit in the N bits obtained from the i0th second data stream, 0≤i0≤7, 0≤j0≤N-1, and the 8 bits in the i th DP-16QAM symbol are denoted as 0≤i≤N-1, from It should be understood that, by using this mapping manner, the N bits in the second data stream are uniformly mapped to the 16QAM symbols in the X polarization direction and the Y polarization direction, which facilitates resistance to PDL damage.

[0025] In some possible implementation manners, the i-th bit of the N bits from the (i+7)th of the 8 second data streams;

[0026] the i-th bit of the N bits from the (i+7)th of the 8 second data streams;

[0027] the i-th bit of the N bits from the (i+7)th of the 8 second data streams;

[0028] the i-th bit of the N bits from the (i+7)th of the 8 second data streams;

[0029] the i-th bit of the N bits from the (i+7)th of the 8 second data streams;

[0030] the i-th bit of the N bits from the (i+7)th of the 8 second data streams;

[0031] the i-th bit of the N bits from the (i+7)th of the 8 second data streams;

[0032] the i-th bit of the N bits from the (i+7)th of the 8 second data streams.

[0033] It should be appreciated that by this mapping, the N bits in the second data stream are evenly mapped to 16QAM symbols in the X polarization direction and the Y polarization direction, which is beneficial to combat PDL impairment.

[0034] In some possible implementation manners, the second data processing on the m second data streams includes second interleaving, DP-16QAM symbol mapping and framing to obtain the one first dual-polarization symbol stream, which enriches the application scenarios of the scheme. Mode 1: the m second data streams are subjected to second interleaving and DP-16QAM symbol mapping to obtain second dual-polarization symbol streams, and the target symbol sequence is inserted into the second dual-polarization symbol streams respectively to obtain the first dual-polarization symbol stream. Mode 2: the m second data streams are subjected to second interleaving to obtain one third data stream, the target bit sequence is inserted into the third data stream to obtain a fourth data stream, and the fourth data stream is subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream, wherein the target bit sequence is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence. Mode 3: the m second data streams are subjected to second interleaving to obtain two third data streams, the target bit sequence is inserted into the two third data streams respectively to obtain two fourth bit streams, and the two fourth bit streams are subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream, wherein the target bit sequence is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence. Mode 4: the m second data streams are subjected to second interleaving to obtain four third data streams, the I component of the target bit sequence is inserted into two of the four third data streams respectively, and the Q component of the target bit sequence is inserted into the other two of the four third data streams respectively to obtain four fourth bit streams, and the four fourth bit streams are subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream, wherein the I component of the target bit sequence is subjected to DP-16QAM symbol mapping to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is subjected to DP-16QAM symbol mapping to obtain the Q component of the target symbol sequence.

[0035] In some possible implementation manners, the first dual-polarization symbol stream includes a plurality of dual-polarization symbol sequences, and a fixed position in each dual-polarization symbol sequence includes the target symbol sequence, and the target symbol sequence includes at least one of a frame synchronization symbol sequence, a training symbol sequence, a reserved symbol sequence and a pilot symbol sequence, so as to flexibly select the target symbol sequence to be inserted according to actual needs.

[0036] In some possible implementation manners, each code word subjected to FEC encoding includes K information bits and N-K check bits, and N=128, K=120, or N=126, K=110, or N=176, K=160, so as to flexibly select the FEC encoding mode according to actual needs.

[0037] In some possible implementation manners, m=4, 8, 16 or 32, so that a plurality of different scenarios can be compatible.

[0038] In some possible implementation manners, each 4 adjacent RS symbols in each first data stream are respectively from 4 RS code words, so that better anti-colored noise performance is achieved.

[0039] In some possible implementation manners, the p first data streams are obtained through 16: p PMA processing on 16 fifth data streams, and the 16 fifth data streams are obtained through physical coding sublayer (PCS) processing on the service data to be sent, and the PCS processing includes RS encoding. Here, a specific implementation manner of obtaining the p first data streams through data processing on the service data to be sent is provided, and the integrity of the scheme is improved.

[0040] In some possible implementation manners, the p first data streams are obtained through t: p PMA processing on t signals, and the t signals are obtained through 16: t PMA processing on 16 fifth data streams, and t is a positive integer multiple of 4. Here, a scheme of obtaining the p first data streams through two-step PMA processing on the data stream processed by the PCS is provided, and the scheme can better adapt to the application scenario shown in FIG. 2, wherein one step of the PMA processing is performed by the sending device, and the other step of the PMA processing is performed by the sending processing module.

[0041] In some possible implementation manners, the p first data streams are obtained through 16: p PMA processing on 16 fifth data streams. Here, a scheme of obtaining the p first data streams through one-step PMA processing on the data stream processed by the PCS is provided, and the scheme can better adapt to the application scenario shown in FIG. 3, and the PMA processing is performed by the sending device.

[0042] In some possible implementation manners, the p first data streams are obtained through t: p PMA processing on t signals based on symbol multiplexing. That is, for the application scenario shown in FIG. 2, the sending processing module performs t: p PMA processing on the t signals from the sending device based on symbol multiplexing to obtain the p first data streams, and the data processing procedure of the sending processing module is improved.

[0043] In some possible implementation manners, t = 8 and p = 8, or t = 16 and p = 8, or t = 4 and p = 8, or t = 8 and p = 16, or t = 16 and p = 16, or t = 4 and p = 16, or t = 4 and p = 4, or t = 8 and p = 4. Here, several possible implementation manners of the t: p PMA processing are provided, and the expansibility of the scheme is improved.

[0044] In some possible implementation manners, the p first data streams are obtained by processing service data to be transmitted through PCS processing including RS encoding. A manner of directly obtaining the p first data streams by performing PCS processing on the service data to be transmitted is provided, and PMA processing is not required, so that different implementation manners can be flexibly selected according to actual needs.

[0045] In some possible implementation manners, the data processing method provided by the embodiment of the present application is applied to scenarios including an Ethernet, an optical transport network, and space optical communication.

[0046] In a second aspect, the embodiment of the present application provides a data processing apparatus, including an acquisition unit and a processing unit. The acquisition unit is configured to acquire p first data streams processed through Reed-Solomon RS encoding, p is a positive integer multiple of 4, and p is an integer power of 2. Each a RS RS symbol in each first data stream is from a RS RS code word, a RS is greater than or equal to 4 and is an integer power of 2. The processing unit is configured to perform first data processing including forward error correction FEC encoding and first interleaving on the p first data streams to obtain m second data streams, m is an integer greater than or equal to p; and perform second data processing including second interleaving, DP-16QAM symbol mapping, and framing on the m second data streams to obtain 1 first dual-polarization symbol stream.

[0047] In some possible implementation manners, in a scenario where m > p, the processing unit is specifically configured to distribute each first data stream in the p first data streams to obtain m / p first sub-data streams, to obtain the m first sub-data streams, and perform FEC encoding and first interleaving on the m first sub-data streams to obtain the m second data streams.

[0048] In some possible implementation manners, each first sub-data stream obtained by distributing the 1 first data stream includes K consecutive bits in the 1 first data stream, K is a positive integer, and K is the number of information bits participating in FEC encoding. For example, an FEC encoding mode of N = 128 and K = 120 is adapted. For another example, an FEC encoding mode of N = 176 and K = 160 is adapted. Alternatively, each first sub-data stream obtained by distributing the 1 first data stream includes K0 consecutive bits in the 1 first data stream, K0 is an integer multiple of 40. For example, K is not an integer multiple of 40, wherein, represents rounding down. For example, K = 110, an FEC encoding mode of N = 126 and K = 110 can be adapted. A plurality of granularities of distributing the first data stream are provided, so that different FEC encoding modes can be adapted.

[0049] In some possible implementation, the processing unit is specifically configured to: perform convolution interleaving on the p first data streams respectively, perform FEC encoding and first interleaving on the p first data streams after convolution interleaving respectively to obtain m second data streams.

[0050] In some possible implementation, the processing unit is specifically configured to: perform convolution interleaving on the p first data streams respectively, perform FEC encoding and first interleaving on the p first data streams after convolution interleaving respectively to obtain m second data streams.

[0051] In some possible implementation, the processing unit is specifically configured to: delay bits from the first data streams according to r delay lines, r being an integer greater than 1, each delay line including a different number of storage units, the delay line including the least number of storage units including 0 storage unit, the difference of the number of storage units between each adjacent two delay lines being Q, each storage unit being configured to store d bits, the input bits being input to the r delay lines in sequence according to the serial number of the r delay lines, d bits being input to each delay line at a time and d bits being output from each delay line at a time, Q and d being integers greater than or equal to 1.

[0052] In some possible implementation, the delay line with the largest serial number in the r delay lines includes 0 storage unit, or the delay line with the smallest serial number in the r delay lines includes 0 storage unit. Here, multiple different implementations of convolution interleaving are provided to adapt to multiple different application scenarios.

[0053] In some possible implementation, d = a RS × 10.

[0054] In some possible implementation, a RS = 4 or 8.

[0055] In some possible implementation manners, the delay line with the largest serial number among the r delay lines includes 0 memory cells or the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p = 8, r = 3, d = 40, Q ≥ 23, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 24. Alternatively, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p = 16, r = 3, d = 40, Q ≥ 11, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 12 or 14 or 16. Alternatively, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p = 16, r = 3, d = 40, Q ≥ 12, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 12 or 14 or 16. Alternatively, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p = 4, r = 3, d = 40, Q ≥ 45, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 46 or 48. Alternatively, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p = 4, r = 3, d = 40, Q ≥ 46, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q = 46 or 48. For different values of p, appropriate r, d, and Q parameters and implementation manners of the convolution interleaving are selected, so that any 12 consecutive RS symbols in the data stream after convolution interleaving come from 12 different RS code words, which can be used for the FEC encoding mode of N = 128 and K = 120. Alternatively, appropriate r, d, and Q parameters and implementation manners of the convolution interleaving are selected, so that any 11 consecutive RS symbols in the data stream after convolution interleaving come from 11 different RS code words, which can be used for the FEC encoding mode of N = 126 and K = 110.

[0056] In some possible implementation, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p=4, r=4, d=40, Q≥34, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q=36 or 38 or 40. Alternatively, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p=4, r=4, d=40, Q≥35, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q=36 or 38 or 40. Alternatively, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p=8, r=4, d=40, Q≥17, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q=18 or 20 or 24. Alternatively, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p=8, r=4, d=40, Q≥18, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q=18 or 20 or 24. Alternatively, the delay line with the largest serial number among the r delay lines includes 0 memory cells or the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p=16, r=4, d=40, Q≥9, to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is considered to be a multiple of 2 or 4 or 8, for example, Q=10 or 12 or 16. By selecting appropriate r, d and Q parameters and implementation of the convolution interleaver, any 16 consecutive RS symbols in the data stream after convolution interleaving come from 16 different RS code words, which can be used for FEC encoding mode of N=176, K=160.

[0057] In some possible implementation, the number of information bits participating in FEC encoding is K, each code word after FEC encoding includes N bits, N-K check bits in the code word are obtained by FEC encoding of K information bits, and the first interleaving is used for cyclic shift of every K information bits in the first data stream.

[0058] In some possible implementation, p=4, and the first interleaving is used for cyclic shift of every K information bits in the first data stream i bits, 0≤i<4, satisfy one of the following:

[0059] Alternatively, p=8, and the first interleaving is used for cyclic shift of every K information bits in the first data stream i bits, 0≤i<8, satisfy one of the following:

[0060] Or, p = 16, the first interleaving is used to cyclically shift every K information bits in the first data stream i bits, 0≤i<16, satisfies one of the following:

[0061] In some possible implementation manners, the processing unit is specifically configured to perform one of the following manners. Manner 1: performing first interleaving on the first data stream, and performing FEC encoding on the first data stream after the first interleaving. Manner 2: performing FEC encoding on the first data stream, and performing first interleaving on the first data stream after the FEC encoding. Manner 3: performing FEC encoding on K information bits in the first data stream to obtain N-K check bits, and performing first interleaving on the K information bits to obtain N bits including the N-K check bits and the K information bits after the first interleaving, where K is a positive integer, and N>K.

[0062] In some possible implementation manners, the processing unit is specifically configured to: obtain N bits in each second data stream to obtain m×N bits, the N bits including K information bits and N-K check bits in a codeword after FEC encoding; perform second interleaving on the m×N bits; and perform DP-16QAM symbol mapping on the m×N bits after the second interleaving to obtain N×m / 8 DP-16QAM symbols.

[0063] In some possible implementation manners, p = 8, m = 8, denotes the j0th bit in the N bits obtained from the i0th second data stream, 0≤i0≤7, 0≤j0≤N-1, which is mapped to the 8 bits of the i th DP-16QAM symbol, denoted as 0≤i≤N-1, from the i th second data stream

[0064] In some possible implementation manners, from the i th bit in the N bits of the (i+4) %8 th second data stream;

[0065] from the i th bit in the N bits of the (i+5) %8 th second data stream;

[0066] from the i th bit in the N bits of the (i+6) %8 th second data stream;

[0067] from the i th bit in the N bits of the (i+7) %8 th second data stream;

[0068] the i-th bit of the N bits from the (i+2)th / 8 second data stream;

[0069] the i-th bit of the N bits from the (i+2)th / 8 second data stream;

[0070] the i-th bit of the N bits from the (i+2)th / 8 second data stream;

[0071] the i-th bit of the N bits from the (i+2)th / 8 second data stream.

[0072] In some possible implementation, the processing unit is specifically configured to perform one of the following ways. Way 1: performing second interleaving and DP-16QAM symbol mapping on the m second data streams to obtain a second dual-polarization symbol stream, and inserting the target symbol sequence into the second dual-polarization symbol stream respectively to obtain the first dual-polarization symbol stream. Way 2: performing second interleaving on the m second data streams to obtain 1 third data stream, inserting the target bit sequence into the third data stream to obtain a fourth data stream, and performing DP-16QAM symbol mapping on the fourth data stream to obtain the first dual-polarization symbol stream, wherein the target bit sequence is mapped to the target symbol sequence by DP-16QAM symbol mapping. Way 3: performing second interleaving on the m second data streams to obtain 2 third data streams, inserting the target bit sequence into the 2 third data streams respectively to obtain 2 fourth bit streams, and performing DP-16QAM symbol mapping on the 2 fourth bit streams to obtain the first dual-polarization symbol stream, wherein the target bit sequence is mapped to the target symbol sequence by DP-16QAM symbol mapping. Way 4: performing second interleaving on the m second data streams to obtain 4 third data streams, inserting the I component of the target bit sequence into 2 third data streams of the 4 third data streams respectively and inserting the Q component of the target bit sequence into the other 2 third data streams of the 4 third data streams respectively to obtain 4 fourth bit streams, and performing DP-16QAM symbol mapping on the 4 fourth bit streams to obtain the first dual-polarization symbol stream, wherein the I component of the target bit sequence is mapped to the I component of the target symbol sequence by DP-16QAM symbol mapping, and the Q component of the target bit sequence is mapped to the Q component of the target symbol sequence by DP-16QAM symbol mapping.

[0073] In some possible implementation, the first dual-polarization symbol stream comprises a plurality of dual-polarization symbol sequences, and a fixed position in each dual-polarization symbol sequence comprises the target symbol sequence, and the target symbol sequence comprises at least one of a frame synchronization symbol sequence, a training symbol sequence, a reserved symbol sequence and a pilot symbol sequence, so as to flexibly select the target symbol sequence to be inserted according to actual needs.

[0074] In some possible implementation manners, each code word after FEC encoding includes K information bits and N-K check bits, and N=128, K=120, or N=126, K=110, or N=176, K=160.

[0075] In some possible implementation manners, m=8, 16 or 32.

[0076] In some possible implementation manners, each 4 adjacent RS symbols in each first data stream are from 4 RS code words respectively.

[0077] In some possible implementation manners, the p first data streams are obtained by performing symbol multiplexing-based PMA processing on 16 fifth data streams, and the 16 fifth data streams are obtained by performing PCS processing including RS encoding on the service data to be sent.

[0078] In some possible implementation manners, the p first data streams are obtained by performing t:p PMA processing on t signals, and the t signals are obtained by performing 16:t PMA processing on 16 fifth data streams, and t is a positive integer multiple of 4.

[0079] In some possible implementation manners, the p first data streams are obtained by performing 16:p PMA processing on 16 fifth data streams.

[0080] In some possible implementation manners, the p first data streams are obtained by performing t:p PMA processing on t signals based on symbol multiplexing.

[0081] In some possible implementation manners, t=8, p=8; or t=16, p=8; or t=4, p=8; or t=8, p=16; or t=16, p=16; or t=4, p=16; or t=4, p=4; or t=8, p=4.

[0082] In some possible implementation manners, the p first data streams are obtained by performing PCS processing including RS encoding on the service data to be sent.

[0083] In some possible implementation manners, the data processing apparatus provided by the embodiments of the present application is applied to the scenarios including Ethernet, optical transport network and space optical communication.

[0084] In a third aspect, a chip is provided, which is configured to perform the method according to any of the embodiments of the first aspect.

[0085] Fourthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0086] Fifthly, embodiments of this application provide a transmitting device. The transmitting device includes a host-side device and an optical module as described in any embodiment of the fourth aspect. The optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

[0087] Sixthly, embodiments of this application provide an apparatus. The apparatus includes a processor and an interface. The processor is used to execute the method described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The apparatus may be a router, switch, server, or optical transport network equipment, etc.

[0088] In a seventh aspect, embodiments of this application provide a communication system, which includes the transmitting device and receiving device described in the fifth aspect, wherein the transmitting device is used to transmit optical signals to the receiving device.

[0089] Eighthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any embodiment of the first aspect to be implemented.

[0090] Ninthly, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first aspect. Attached Figure Description

[0091] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0092] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1;

[0093] Figure 3 is a schematic diagram of another communication system applied in the embodiments of this application;

[0094] Figure 4 is a flowchart illustrating a data processing method provided in an embodiment of this application.

[0095] Figure 5(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application;

[0096] Figure 5(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application;

[0097] Figure 6(a) is a schematic diagram of one embodiment of the present application for dual polarization symbol mapping and DSP framing;

[0098] Figure 6(b) is a schematic diagram of another embodiment of the present application for dual polarization symbol mapping and DSP framing;

[0099] Figure 6(c) is a schematic diagram of another embodiment of the present application for dual polarization symbol mapping and DSP framing;

[0100] Figure 6(d) is a schematic diagram of another embodiment of the present application for dual polarization symbol mapping and DSP framing;

[0101] Figure 7(a) is a data processing flow chart corresponding to the data processing method of the present application;

[0102] Figure 7(b) is another data processing flow chart corresponding to the data processing method of the present application;

[0103] Figure 7(c) is another data processing flow chart corresponding to the data processing method of the present application;

[0104] Figure 7(d) is another data processing flow chart corresponding to the data processing method of the present application;

[0105] Figure 7(e) is another data processing flow chart corresponding to the data processing method of the present application;

[0106] Figure 7(f) is another data processing flow chart corresponding to the data processing method of the present application;

[0107] Figure 8(a) is another data processing flow chart corresponding to the data processing method of the present application;

[0108] Figure 8(b) is another data processing flow chart corresponding to the data processing method of the present application;

[0109] Figure 8(c) is another data processing flow chart corresponding to the data processing method of the present application;

[0110] Figure 8(d) is another data processing flow chart corresponding to the data processing method of the present application;

[0111] Figure 8(e) is another data processing flow chart corresponding to the data processing method of the present application;

[0112] Figure 8(f) is another data processing flow chart corresponding to the data processing method of the present application;

[0113] Figure 8 (g) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application;

[0114] Figure 9 (a) is a schematic diagram of one embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0115] Figure 9 (b) is a schematic diagram of another embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0116] Figure 9 (c) is a schematic diagram of another embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0117] Figure 10 (a) is a schematic diagram of another embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0118] Figure 10 (b) is a schematic diagram of another embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0119] Figure 11 (a) is a schematic diagram of another embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0120] Figure 11 (b) is a schematic diagram of another embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0121] Figure 11 (c) is a schematic diagram of another embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0122] Figure 12 (a) is a schematic diagram of another embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0123] Figure 12 (b) is a schematic diagram of another embodiment of performing the first data processing and the second data processing in the embodiments of the present application;

[0124] Figure 13 is a schematic diagram of the format of a first data stream in the embodiments of the present application;

[0125] Figure 14 is a schematic diagram of one embodiment of convolution interleaving in the embodiments of the present application;

[0126] Figure 15 is a schematic diagram of another embodiment of convolution interleaving in the embodiments of the present application;

[0127] Figure 16 is a schematic diagram of one embodiment of inner code encoding in the embodiments of the present application;

[0128] Figure 17 is a schematic diagram of one embodiment of first interleaving in the embodiments of the present application;

[0129] FIG. 18 is a schematic diagram of a structure of a DSP frame according to an embodiment of the present application;

[0130] FIG. 19 is a schematic diagram of an embodiment of 1:4 distribution of data streams according to an embodiment of the present application;

[0131] FIG. 20 is a schematic diagram of an embodiment of 1:2 distribution of data streams according to an embodiment of the present application;

[0132] FIG. 21 is a schematic diagram of a structure of a data processing apparatus according to an embodiment of the present application;

[0133] FIG. 22 is a schematic diagram of a structure of an optical module according to an embodiment of the present application;

[0134] FIG. 23 is a schematic diagram of a structure of a transmitting device according to an embodiment of the present application. DETAILED DESCRIPTION

[0135] The embodiments of the present application provide a data processing method, apparatus and system. The cascaded FEC transmission scheme is simple to implement, low in power consumption, strong in burst resistance, and applicable to many transmission scenarios, especially applicable to actual coherent transmission scenarios in which there is colored noise.

[0136] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and are not intended to limit a specific order or sequence. It should be understood that the above-described terms can be interchanged as appropriate so that the embodiments described in the present application can be implemented in an order other than that described in the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to the process, method, product or device.

[0137] FIG. 1 is a schematic diagram of a communication system to which embodiments of the present application are applied. As shown in FIG. 1, the communication system includes a sending device 01, a sending processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network, the sending device 01 and the receiving device 05 can be a switch, a router, or a server, and the sending device 01 is also referred to as a client device at the sending end, and the receiving device 05 is also referred to as a client device at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client device is also referred to as a host device. The client device includes a client chip and an interface. The client chip is also referred to as a host chip. The connection interface between the sending device 01 and the sending processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The sending processing module 02 and the receiving processing module 04 can be an optical module, an electrical module, a connector, or other modules that process data during data transmission. For example, the processing module can be an LR optical module, such as a 1600LR module (a kind of coherent optical module). Moreover, the sending device 01, the sending processing module 02, the channel transmission medium 03, the receiving processing module 04, and the receiving device 05 in the communication system can support bidirectional transmission, or can support unidirectional transmission, which is not limited here.

[0138] FIG. 2 is a schematic diagram of a data transmission process in the communication system shown in FIG. 1. As shown in FIG. 2, in the process of transmitting data from the sending device 01 to the receiving device 05, the sending device 01 is configured to perform outer code encoding on the data, and then transmit the data encoded by the outer code to the sending processing module 02. The sending processing module 02 is configured to perform inner code encoding on the data encoded by the outer code, to obtain data encoded by the outer code and the inner code, and transmit the data encoded by the outer code and the inner code to the channel transmission medium 03. The channel transmission medium 03 is configured to transmit the data encoded by the outer code and the inner code to the receiving processing module 04. The receiving processing module 04 is configured to perform inner code decoding on the data encoded by the outer code and the inner code, and transmit the data decoded by the inner code to the receiving device 05. The receiving device 05 is configured to perform outer code decoding on the data decoded by the inner code.

[0139] It should be understood that the "inner" in the inner code and the "outer" in the outer code are only distinguished based on the distance of the execution subject operating on the data relative to the channel transmission medium 03. The execution subject operating on the inner code is closer to the channel transmission medium, and the execution subject operating on the outer code is farther away from the channel transmission medium. In the embodiments of the present application, since the data is transmitted from the sending end device 01 to the channel transmission medium 03 through the sending end processing module 02, and then transmitted from the channel transmission medium 03 to the receiving end device 05 through the receiving end processing module 04. The data encoded by the sending end device 01 is farther away from the channel transmission medium 03 than the data encoded by the sending end processing module 02, and the data decoded by the receiving end device 05 is farther away from the channel transmission medium 03 than the data decoded by the receiving end processing module 04. Therefore, the data encoded by the sending end device 01 is called data encoded by the outer code, the data encoded by the sending end processing module 02 is called data encoded by the inner code, the data decoded by the receiving end device 05 is called data decoded by the outer code, and the data decoded by the receiving end processing module 04 is called data decoded by the inner code. In a possible implementation, the inner code encoding and the outer code encoding described above are both in the form of FEC encoding, thereby forming a cascaded FEC transmission scheme. For example, the sending end device 01 can perform outer code encoding using RS code, and the sending end processing module 02 can perform inner code encoding using Hamming code. For another example, the sending end device 01 can perform outer code encoding using RS code, and the sending end processing module 02 can perform inner code encoding using Bose-Chaudhuri-Hocquenghem (BCH) code. The BCH code correcting a single error is equivalent to Hamming code. For another example, the sending end device 01 can perform outer code encoding using RS code, and the sending end processing module 02 can also perform inner code encoding using Polar code.

[0140] FIG. 3 is a schematic diagram of another communication system to which embodiments of the present application can be applied. As shown in FIG. 3, the communication system includes a sending device 01, a channel transmission medium 03, and a receiving device 05. The sending device 01 performs outer code encoding and inner code encoding on data, and the data after outer code encoding and inner code encoding is sent to the channel transmission medium 03. The receiving device 05 performs inner code decoding and outer code decoding on the data received from the channel transmission medium 03. Taking the communication system as an example of a data center network, the sending device 01 and the receiving device 05 can be switches, routers, servers, or other devices, and the sending device 01 is also referred to as a client-side device or a host device located at the sending end, and the receiving device 05 is also referred to as a client-side chip located at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side device includes a client-side chip and an interface. The client-side chip is also referred to as a host chip. The sending device 01, the channel transmission medium 03, and the receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not limited here. That is, the sending device 01 shown in FIG. 3 also integrates the functions of the sending processing module 02 shown in FIG. 2, and the receiving device 05 shown in FIG. 3 also integrates the functions of the receiving processing module 04 shown in FIG. 2. At this time, the sending device 01 can also use linear pluggable optics (LPO) technology, co-packaged optics (CPO) technology, or near packaged optics (NPO) technology.

[0141] It should be noted that, as shown in FIGS. 2 and 3, in some specific applications, the data after inner code encoding is further subjected to at least one of a DSP framing adding a sequence of frame alignment words (FAW Sequence), a sequence of training symbols, a sequence of reserved symbols, and a sequence of pilot symbols to obtain a DSP frame to be sent. Alternatively, the reserved symbols can also be referred to as fixed stuff (FS), and the frame alignment symbols can also be referred to as a multi-frame alignment signal (MFAS).

[0142] It should be noted that the above is an exemplary description of the application scenarios of the data processing method provided by the embodiments of the present application, and does not constitute a limitation on the application scenarios of the data processing method. Those skilled in the art can know that, as the business requirements change, the application scenarios can be adjusted according to the application requirements, and the embodiments of the present application do not enumerate them one by one.

[0143] FIG. 4 is a flow diagram of a data processing method provided by an embodiment of the present application. It should be understood that the data processing method is applied to a sending end, for example, it can be specifically implemented by the sender processing module 02 shown in FIG. 2, or it can be specifically implemented by the sender device 01 shown in FIG. 3.

[0144] 101. Obtain p first data streams that are RS encoded.

[0145] In the embodiments of the present application, the p first data streams are all data streams that are outer code encoded. For ease of introduction, the outer code encoding is taken as an example of RS encoding in the following description, and other encoding methods can also be used for outer code encoding in actual application. The data stream after RS encoding can include multiple RS code words, and the code length of the RS code is counted in units of symbols in the embodiments of the present application. The symbol in the RS code can be referred to as an RS symbol. For example, the RS code uses RS(544, 514) code, also known as KP4 code, and the code length of the RS code is 544 RS symbols, that is, the code word of the RS code includes 544 RS symbols, and one RS symbol contains 10 bits. Each a RS adjacent RS symbol in each of the first data streams comes from a RS RS code word, where a RS is greater than or equal to 4 and is an integer power of 2. In some specific scenarios, for example, in a 1.6T Ethernet transmission scenario, a RS = 4, that is, every 4 adjacent RS symbols in each of the first data streams come from 4 RS code words, p is an integer multiple of 4, and p is an integer power of 2.

[0146] 102. Perform first data processing including inner code encoding and first interleaving on the p first data streams respectively to obtain m second data streams.

[0147] Specifically, m is an integer greater than or equal to p, for example, p = 4 or 8 or 16, m = 4, 8, 16 or 32. If no distribution is performed on each first data stream, m = p; if distribution is performed on each first data stream, m > p. Taking p = 4 first data streams as an example, if no distribution is performed on each first data stream, first data processing is performed to obtain m = 4 second data streams. Taking p = 4 first data streams as an example, if 1:2 distribution is performed on each first data stream, first data processing is performed to obtain m = 8 second data streams. Taking p = 4 first data streams as an example, if 1:4 distribution is performed on each first data stream, first data processing is performed to obtain m = 16 second data streams. Taking p = 4 first data streams as an example, if 1:8 distribution is performed on each first data stream, first data processing is performed to obtain m = 32 second data streams. Taking p = 8 first data streams as an example, if no distribution is performed on each first data stream, first data processing is performed to obtain m = 8 second data streams. Taking p = 8 first data streams as an example, if 1:2 distribution is performed on each first data stream, first data processing is performed to obtain m = 16 second data streams. Taking p = 8 first data streams as an example, if 1:4 distribution is performed on each first data stream, first data processing is performed to obtain m = 32 second data streams.

[0148] The following describes the inner code encoding mode with 1 first data stream as an example. Specifically, inner code encoding is performed on each K information bits in the first data stream to generate N-K check bits, thereby obtaining an inner code codeword including N bits, where 1 < K < N. For example, the inner code encoding adopts a linear block code of N = 126 and K = 110, such as BCH(126, 110). For another example, the inner code encoding adopts a linear block code of N = 128 and K = 120, such as BCH(128, 120). For still another example, the inner code encoding adopts a linear block code of N = 176 and K = 160, such as BCH(176, 160).

[0149] In some scenarios, it is considered that K is a multiple of 10, and the K information bits in each inner code codeword correspond to K / 10 outer code RS symbols, and the corresponding K / 10 outer code RS symbols come from K / 10 different outer code RS codewords, so that the FEC cascade scheme including RS encoding and inner code encoding has optimal performance. For example, the inner code encoding adopts BCH (126, 110), K = 110 information bits in each inner code codeword correspond to K / 10 = 11 outer code symbols, and the corresponding K / 10 = 11 outer code symbols come from K / 10 = 11 different outer code RS codewords. For another example, the inner code encoding adopts a linear block code with N = 128 and K = 120, K = 120 information bits in each inner code codeword correspond to K / 10 = 12 outer code symbols, and the corresponding K / 10 = 12 outer code symbols come from K / 10 = 12 different outer code RS codewords. For another example, the inner code encoding adopts a linear block code with N = 176 and K = 160, K = 160 information bits in each inner code codeword correspond to K / 10 = 16 outer code symbols, and the corresponding K / 10 = 16 outer code symbols come from K / 10 = 16 different outer code RS codewords. In some possible scenarios, in order to make K information bits in each inner code codeword correspond to K / 10 different outer code RS codewords, the first data stream is further subjected to convolution interleaving processing before inner code encoding. The convolution interleaving processing will be described in detail below.

[0150] Specifically, the convolution interleaver performing the convolution interleaving processing includes r delay lines, each of which includes a different number of storage units, and the delay line with the smallest number of storage units includes 0 storage unit, and the difference between the number of storage units of each adjacent two delay lines is Q, where r is an integer greater than 1, and Q is an integer greater than or equal to 1. Each storage unit is used to store d bits, and d is an integer greater than or equal to 1. The bits in the input data stream of the convolution interleaver are sequentially input to the r delay lines according to the sequence number of the r delay lines, and d bits are input from each delay line at a time and d bits are output from each delay line at a time. In some specific applications, the convolution interleaver outputs d bits at a time. In other specific applications, the convolution interleaver outputs rxd bits at a time, the rxd bits come from the r delay lines, and include the d bits output from each delay line. The rxd bits in the data stream output by the convolution interleaver include the d bits output from each delay line.

[0151] It should be understood that the r delay lines respectively include 0 memory units, Q memory units, 2Q memory units, …, (r-1)Q memory units, each of which is used to store d bits. The r delay lines respectively correspond to r delay values, and the delay values include 0 bits, Qxd bits, 2Qxd bits, …, (r-1)Qxd bits. The more bits included in the delay value of the delay line, the longer the delay (also referred to as the time delay) of the data stream by the delay line. It should be understood that when the delay line does not contain memory units, the delay of the delay line is 0 bits, that is, no delay transmission. It should be understood that the memory unit is also referred to as a delay element.

[0152] FIG. 5(a) is a schematic diagram of a first structure of convolution interleaving processing in the embodiment of the application. As shown in FIG. 5(a), the number of memory units in the r delay lines decreases in turn according to the serial number of the r delay lines. That is, the delay line 0 has (r-1)Q memory units, each of the delay lines decreases by Q memory units in turn, and the delay line r-1 has 0 memory unit. FIG. 5(b) is a schematic diagram of a second structure of convolution interleaving processing in the embodiment of the application. As shown in FIG. 5(b), the number of memory units in the r delay lines increases in turn according to the serial number of the r delay lines. That is, the delay line 0 has 0 memory unit, each of the delay lines increases by Q memory units in turn, and the delay line r-1 has (r-1)Q memory units.

[0153] It should be noted that at the same time, the switch of the convolution interleaver input and output is located on the same delay line, and after the current delay line is single-inputted by d bits and outputted by d bits, the switch is switched to the next delay line, so as to ensure that the bits in the input data stream are inputted to the r delay lines in turn according to the serial number of the r delay lines, and the continuous rxd bits in the output data stream include the d bits outputted by each delay line. The specific data reading and writing operation is as follows: reading out d bits from the memory unit closest to the output port of the current delay line; transferring the d bits stored in each memory unit in the current delay line to the next memory unit. Then, write d bits into the memory unit closest to the input port of the current delay line. Then, switch to the next delay line and repeat the above operation.

[0154] It should be understood that when the same parameters r, Q and d are used, the convolution interleaving processing of FIG. 5(a) and the convolution interleaving processing of FIG. 5(b) are inverse operations of each other. That is, when the convolution interleaving structure shown in FIG. 5(a) is used in the sending processing module, the convolution deinterleaving corresponding to the receiving processing module uses the structure shown in FIG. 5(b). Similarly, when the convolution interleaving structure shown in FIG. 5(b) is used in the sending processing module, the convolution deinterleaving corresponding to the receiving processing module uses the structure shown in FIG. 5(a).

[0155] Typically, the number of bits stored in each memory cell is d = a. RS ×10. For example, in a 1.6T Ethernet transmission scenario, a RS =4, d=a RS ×10=40. It should be noted that each a in each of the first data streams... RS The adjacent RS symbols are respectively from a RS A different external code RS codeword, when a RS When the value is larger, in order to achieve K / 10 different external code RS codewords corresponding to K information bits in each internal codeword, the total number of bits in the storage unit (also called delay unit) of the convolutional interleaver is smaller, which means the latency and complexity of the convolutional interleaver are lower.

[0156] The first interleaving, included in the first data processing described above, is described in detail below. The first interleaving is used to interleave every K information bits in the first data stream to shuffle their order, thereby improving the overall burst resistance of the concatenated code. The first interleaving is also called bit shuffling or permutation. In some possible scenarios, the first interleaving is performed after internal code encoding; that is, the first data stream is first internally encoded, and then the internally encoded first data stream is subjected to the first interleaving. In other possible scenarios, the first interleaving is performed before internal code encoding; that is, the first data stream is first first interleaved, and then the first interleaved first data stream is subjected to internal code encoding. In still other possible scenarios, considering that the first interleaving is only used to interleave K information bits to shuffle their order, and the parity bits do not participate in the first interleaving, the first interleaving and internal code encoding can be processed in parallel. Specifically, the K information bits are represented by U, and internal code encoding is performed first to obtain the corresponding internal codeword (U, V), where the NK parity bits generated by the internal code encoding are represented by V. Then, the K information bits U in the codeword (U,V) are first interleaved to obtain N bits (W,V), where the K bits obtained from the first interleaving of the K information bits U are represented by W. This is equivalent to the internal code encoding and the first interleaving being processed in parallel; that is, the K information bits U are internally encoded to obtain NK parity bits V, and simultaneously, the K bits W obtained from the first interleaving of the K information bits U are combined to obtain the N bits (W,V) after internal code encoding and the first interleaving. For simplicity, the N bits (W,V) are also called the codeword interleaving sequence.

[0157] In some specific applications, the first interleaving is used to perform a right circular shift of K information bits. bits, where the integer In other specific applications, the first interleaving is used to cyclically shift K information bits to the left by δ bits. In this case, the first interleaving is also called a circular shift. It should be noted that a right circular shift of K information bits... Each bit is equivalent to a left circular shift of K information bits. The following description of the circular shift operation uses a right circular shift as an example. Typically, the number of bits used in a right circular shift for the first interleaving of m data streams is... Not exactly the same, among which, The number of bits to circularly shift to the right of the i-th data stream out of m data streams. For example, K is an integer multiple of 10. It is an integer multiple of 10. The first interleaving can further improve the overall scheme's resistance to colored noise.

[0158] It should be noted that for scenarios where m > p, the aforementioned first data processing also includes a distribution operation. Each of the p first data streams is distributed to obtain m / p first sub-data streams, resulting in a total of p × (m / p) = m first sub-data streams. These m first sub-data streams are then subjected to internal code encoding and first interleaving to obtain m second data streams. It should be understood that distribution and convolutional interleaving are decoupled; for example, only convolutional interleaving can be performed; or only distribution can be performed; or convolutional interleaving can be performed first, followed by distribution.

[0159] In some possible scenarios, distribution is performed at a granularity of K bits. For example, if a first data stream is distributed into four first sub-data streams, the 4 × K consecutive bits in the first data stream are distributed into the four corresponding sub-data streams. Each sub-data stream contains K consecutive bits from the 4 × K bits. In this case, the distribution is also called 1:(m / p)K-bit block distribution. The distribution operation can also be called de-muxing.

[0160] In other possible scenarios, distribution is performed in granularity of K0 bits. A consecutive (m / p) × K0 bits from one first data stream is distributed to its corresponding m / p first sub-data streams. Each first sub-data stream contains a consecutive K0 bits from the (m / p) × K0 bits, where K0 is an integer multiple of 40. As another example, K may not be an integer multiple of 40. in This indicates rounding down to the nearest integer. For example, K = 110.

[0161] 103. performing second data processing including second interleaving, dual-polarization symbol mapping and framing on the m second data streams to obtain one first dual-polarization symbol stream.

[0162] Specifically, one inner code word is obtained from each second data stream, and m inner code words are obtained from the m second data streams in total, with a bit number of m x N. The second interleaving is used to shuffle the order of the m x N bits of the m inner code words, so as to improve the burst resistance and the colored noise resistance of the concatenated FEC scheme. The second interleaving can also be referred to as code word interleaving. As an example, the second interleaving herein can be divided into two steps of multiplexing the m inner code words first, and then interleaving the m inner code words. As another example, the second interleaving herein can be implemented by one step, which has an effect equivalent to the above-mentioned implementation by two steps.

[0163] The data stream obtained after the second interleaving is subjected to dual-polarization symbol mapping and framing to obtain one first dual-polarization symbol stream to be transmitted. The framing herein can also be referred to as DSP framing. The following is described by taking DP-16QAM symbol mapping as an example of the dual-polarization symbol mapping. For example, the dual-polarization symbol mapping is used to map every 8 bits in the data stream obtained after the second interleaving into one dual-polarization 16QAM (DP-16QAM) symbol. Each DP-16QAM symbol includes a 16QAM symbol in an X polarization direction and a 16QAM symbol in a Y polarization direction, wherein the X polarization direction and the Y polarization direction are orthogonal to each other. Further, the 16QAM symbol in the X polarization direction includes an in-phase component and a quadrature-phase component in the X polarization direction, and the 16QAM symbol in the Y polarization direction includes an in-phase component and a quadrature-phase component in the Y polarization direction. It should be understood that the dual-polarization symbol mapping is also referred to as DP-16QAM symbol mapping, or 16QAM symbol mapping and polarization distribution. Specifically, the DP-16QAM symbol stream to be transmitted includes a plurality of DP-16QAM symbol sequences, and the DSP framing is used to insert a target symbol sequence at a fixed position of each DP-16QAM symbol sequence, and the DP-16QAM symbol sequence is also referred to as a DSP frame.

[0164] The following describes possible implementations of dual polarization symbol mapping and DSP framing in detail.

[0165] Figure 6(a) is a schematic diagram of one implementation of dual polarization symbol mapping and DSP framing in the embodiments of the present application. As shown in Figure 6(a), DSP framing is performed after DP-16QAM symbol mapping, and DSP framing is performed on a symbol basis. The m second data streams are first subjected to second interleaving and DP-16QAM symbol mapping to obtain a second dual polarization symbol stream, which can also be referred to as a pre-framing symbol stream. Then, the second dual polarization symbol stream is subjected to DSP framing, and specifically, a target symbol sequence is inserted into the symbol stream of the second dual polarization symbol stream in the X polarization direction and the Y polarization direction, respectively, to obtain a first dual polarization symbol stream to be transmitted. It should be understood that the value of the target symbol sequence inserted in the X polarization direction can not be exactly the same as the value of the target symbol sequence inserted in the Y polarization direction, and here they are collectively referred to as target symbol sequences without specific differentiation. For example, the target symbol sequence includes at least one of a frame alignment word sequence (FAW Sequence), a training symbol sequence, a reserved symbol sequence, and a pilot symbol sequence. Optionally, the reserved symbol can also be referred to as fixed stuff (FS), and the frame alignment symbol can also be referred to as a multi-frame alignment signal (MFAS).

[0166] In one possible scenario, the target symbol sequence is a pilot symbol sequence. In the X polarization direction or the Y polarization direction, one symbol at a fixed position in every N G symbols in a DSP frame is a pilot symbol. As an example, the first symbol in every N G symbols is a pilot symbol. Typically, N G = 32 or 64 or 96 or 128, etc. In the X polarization direction or the Y polarization direction, each pilot symbol is one of 3+3j, 3-3j, -3+3j, and -3-3j. Here j is the imaginary unit of a complex number. That is, each pilot symbol adopts one of the four outermost symbols in the 16QAM constellation diagram.

[0167] In some specific applications, the DSP framing operation adds one pilot symbol to every 63 DP-16QAM symbols in every 96x63=6048 pre-framed DP-16QAM symbols, resulting in 96x64=6144 DP-16QAM symbols to be transmitted. The 6144 DP-16QAM symbols to be transmitted are referred to as one DSP frame. It should be understood that the first symbol in every N G =64 symbols in the DSP frame is a pilot symbol. The 96x63=6048 pre-framed DP-16QAM symbols are obtained by performing DP-16QAM mapping on 6048x8=48384 bits in the data stream obtained by the second interleaving.

[0168] Fig. 6(b) is a schematic diagram of another embodiment of performing dual-polarization symbol mapping and DSP framing in the embodiments of the present application. As shown in Fig. 6(b), the DSP framing is performed before the DP-16QAM symbol mapping, and the DSP framing is performed on bits. Specifically, the m second data streams are second-interleaved to obtain one third data stream, the target bit sequence is inserted into the third data stream to obtain a fourth data stream, and the fourth data stream is subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream. The target bit sequence is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence.

[0169] Fig. 6(c) is a schematic diagram of another embodiment of performing dual-polarization symbol mapping and DSP framing in the embodiments of the present application. As shown in Fig. 6(c), the DSP framing is performed before the DP-16QAM symbol mapping, and the DSP framing is performed on bits. The data after the second interleaving is represented by two data streams. Specifically, the m second data streams are second-interleaved to obtain two third data streams, the target bit sequence X and the target bit sequence Y are inserted into the two third data streams respectively to obtain two fourth bit streams, and the two fourth bit streams are subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream. The target bit sequence X is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence in the X polarization direction, and the target bit sequence Y is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence in the Y polarization direction.

[0170] Fig. 6(d) is a schematic diagram of another embodiment of performing dual-polarization symbol mapping and DSP framing in the embodiments of the present application. As shown in Fig. 6(d), the DSP framing is performed before the DP-16QAM symbol mapping, and the DSP framing is performed on bits. The data after the second interleaving is represented by four data streams. Specifically, the m second data streams are second-interleaved to obtain four third data streams, the target bit sequence X and the target bit sequence Y are inserted into the four third data streams respectively to obtain four fourth bit streams, and the four fourth bit streams are subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream. The target bit sequence X is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence in the X polarization direction, and the target bit sequence Y is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence in the Y polarization direction. I, target bit sequence X Q , target bit sequence Y I , target bit sequence Y Q four fourth bit streams are obtained, and the four fourth bit streams are subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream. Wherein, target bit sequence X I is subjected to DP-16QAM symbol mapping to obtain the I component of the target symbol sequence in the X polarization direction, target bit sequence X Q is subjected to DP-16QAM symbol mapping to obtain the Q component of the target symbol sequence in the X polarization direction, target bit sequence Y I is subjected to DP-16QAM symbol mapping to obtain the I component of the target symbol sequence in the Y polarization direction, target bit sequence Y Q is subjected to DP-16QAM symbol mapping to obtain the Q component of the target symbol sequence in the Y polarization direction.

[0171] It should be noted that in some specific scenarios, the first dual-polarization symbol stream to be sent is described by using two symbol streams, one of which is the symbol stream of the first dual-polarization symbol stream in the X polarization direction, and the other is the symbol stream of the first dual-polarization symbol stream to be sent in the Y polarization direction. In another specific scenario, the first dual-polarization symbol stream is described by using four data streams, the first one is the data stream of the I component in the X polarization direction corresponding to the first dual-polarization symbol stream (referred to as X I data stream), the second one is the data stream of the Q component in the X polarization direction corresponding to the first dual-polarization symbol stream (referred to as X Q data stream), the third one is the data stream of the I component in the Y polarization direction corresponding to the first dual-polarization symbol stream (referred to as Y I data stream), and the fourth one is the data stream of the Q component in the Y polarization direction corresponding to the first dual-polarization symbol stream (referred to as Y Q data stream).

[0172] Considering the service transmission of 1.6T Ethernet (1.6 Terabit Ethernet, 1.6TE), the bit rate of p first data streams is 106.25*2*8=1700G bits per second in total. It should also be understood that the bit rate in the application materials is a nominal rate, and in actual applications, there is a certain offset range of the bit rate, for example, the bit rate has a ±V0 (ppm) error, where V0 can be 20, 25, 50 or 100, etc. Each of the first data streams is from four different RS code words for every four consecutive RS symbols, and each of the first data streams is also called a symbol-quartet stream. In some specific applications, the first data stream is also obtained through the physical media attachment (PMA) processing based on symbol multiplexing. More specifically, the first data stream is obtained through the PMA processing based on symbol-quartet multiplexing. It should be noted that in the embodiments of the present application, m0:m1 PMA means that m0 input data streams are symbol-multiplexed to obtain m1 output data streams. In some other specific applications, the first data stream also undergoes physical coding sublayer (PCS) processing.

[0173] Fig. 7(a) is a data processing flow diagram corresponding to the data processing method in the embodiment of the present application. As shown in Fig. 7(a), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also referred to as 16 PCS Lanes. Specifically, the 1.6T PCS processing includes four RS encoding processing units, i.e., RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after passing through the four RS encoding processing units is subjected to symbol distribution and interleave to obtain 16 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. Every four adjacent RS symbols in the 16 PCS Lanes come from four different RS codewords. The 16 PCS Lanes are subjected to 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. The bit rate of each signal in the 8 1.6T AUI-8 signals is 212.5G bits per second, which is subjected to PAM4 modulation, and the corresponding baud rate (also referred to as symbol rate) is 106.25GBaud, that is, the total bit rate of the 8 1.6T AUI-8 signals is 106.25x2x8=1700G bits per second. Considering 1.6T Ethernet service, the 1.6T PCS is also referred to as 1.6T BASE-R PCS, and the 1.6T 16:8PMA is also referred to as 1.6T BASE-R 16:8PMA. The 1.6T PCS processing and the 1.6T 16:8PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 8 1.6T AUI-8 signals, which are first subjected to 1.6T 8:8PMA to obtain p=8 first data streams, and then subjected to first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be sent.

[0174] Fig. 7(b) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in Fig. 7(b), 16 PCS Lanes pass through 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. The bit rate of each of the 16 1.6T AUI-16 signals is 106.25 Gbit / s, which is modulated by PAM4, and the corresponding baud rate (also referred to as symbol rate) is 53.125 Gbaud. That is, the total bit rate of the 16 1.6T AUI-16 signals is 106.25x16=1700 Gbit / s. The 1.6T PCS processing and the 1.6T 16:16PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 16 1.6T AUI-16 signals, first passes through the 1.6T 16:8PMA to obtain p=8 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0175] Fig. 7(c) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in Fig. 7(c), 16 PCS Lanes pass through 1.6T 16:8PMA based on 4-symbol multiplexing to obtain p=8 first data streams, and then perform first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted. The 1.6T PCS processing, the 1.6T 16:8PMA, the first data processing and the second data processing are implemented by operating in the transmitting device 01.

[0176] Fig. 8(a) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in Fig. 8(a), 16 PCS Lanes pass through 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. The bit rate of each of the 8 1.6T AUI-8 signals is 212.5 Gbit / s, which is modulated by PAM4, and the corresponding baud rate (also referred to as symbol rate) is 106.25 Gbaud. That is, the total bit rate of the 8 1.6T AUI-8 signals is 106.25x2x8=1700 Gbit / s. Considering 1.6T Ethernet service, the 1.6T PCS is also referred to as 1.6T BASE-R PCS, and the 1.6T 16:8PMA is also referred to as 1.6T BASE-R 16:8PMA. The 1.6T PCS processing and the 1.6T 16:8PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 8 1.6T AUI-8 signals, first passes through the 1.6T 8:16PMA to obtain p=16 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0177] Figure 8(b) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application. As shown in Figure 8(b), 16 PCS Lanes pass through 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. The bit rate of each of the 16 1.6T AUI-16 signals is 106.25G bits per second, which uses PAM4 modulation, and the corresponding baud rate (also referred to as symbol rate) is 53.125G Baud. The total bit rate of the 16 1.6T AUI-16 signals is 106.25x16=1700G bits per second. The 1.6T PCS processing and the 1.6T 16:16PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 16 1.6T AUI-16 signals, first passes through the 1.6T 16:16PMA to obtain p=16 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be sent.

[0178] Figure 8(c) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application. As shown in Figure 8(c), the total bit rate of the 16 PCS Lanes is 106.25x16=1700G bits per second. The 16 PCS Lanes are taken as p=16 first data streams, and first data processing and second data processing are performed to obtain 1 first dual-polarization symbol stream to be sent. The 1.6T PCS processing, the first data processing, and the second data processing are implemented by operating in the transmitting device 01.

[0179] Figure 8(d) is another data processing flow chart corresponding to the data processing method in the embodiments of the present application. As shown in Figure 8(d), 16 PCS Lanes pass through 1.6T 16:4PMA based on 4-symbol multiplexing to obtain 4 1.6T AUI-4 signals. The bit rate of each of the 4 1.6T AUI-4 signals is 425G bits per second, which uses PAM4 modulation, and the corresponding baud rate (also referred to as symbol rate) is 212.5G Baud. The 1.6T PCS processing and the 1.6T 16:4PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 4 1.6T AUI-4 signals, first passes through the 1.6T 4:16PMA to obtain p=16 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be sent.

[0180] It should be noted that in the scenarios facing 1.6T services in FIG. 7(a), FIG. 7(b) and FIG. 7(c), there are p = 8 first data streams participating in the first data processing and the second data processing. In the scenarios facing 1.6T services in FIG. 8(a), FIG. 8(b), FIG. 8(c) and FIG. 8(d), there are p = 16 first data streams participating in the first data processing and the second data processing. For p = 8 first data streams participating in the first data processing and the second data processing, in addition to being applicable to the above-mentioned scenarios of 1.6T services, it can also be applicable to other service scenarios containing 2 800G services, 4 400G services and the like, which are collectively 1.6T rate.

[0181] FIG. 7(d) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in FIG. 7(d), considering a 2 800G service scenario, wherein each 800G service data is processed by 800G PCS to obtain 32 PCS Lanes. Specifically, each 800G PCS processing contains 4 RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data stream obtained after the 4 RS encoding processing units is subjected to symbol distribution and interleaving to obtain 32 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. The 32 PCS Lanes are subjected to 800G 32:4PMA based on 4-symbol multiplexing to obtain 4 800G AUI-4 signals. The 2 800G service data is processed by the above-mentioned 800G PCS and 800G 32:4PMA to obtain a total of 2 groups of 800G AUI-4 signals, a total of 8 signal streams. The bit rate of each signal in the 2 groups of 800G AUI-4 signals is 212.5G bits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 106.25G Baud, that is, the total bit rate of the 2 groups of 800G AUI-4 signals is 106.25x2x4x2 = 1700G bits per second. The transmitting end processing module 02 receives the 2 groups of 800G AUI-4 signals, and each group of 800G AUI-4 signals is subjected to 800G 4:4PMA to obtain 4 first data streams, a total of p = 8 first data streams, and then the 8 first data streams are subjected to first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be sent.

[0182] Fig. 7(e) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in Fig. 7(e), four 400G service scenarios are considered, wherein each 400G service data is processed by 400G PCS to obtain 16 PCS Lanes. Specifically, each 400G PCS processing includes two RS encoding processing units, for example, the 400G PCS processing can include RS-A and RS-B, and the 400G PCS processing can also include RS-C and RS-D. The encoded data stream obtained by the two RS encoding processing units is then subjected to symbol distribution and interleaving to obtain 16 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. The 16 PCS Lanes are subjected to 400G 16:2PMA based on 4-symbol multiplexing to obtain 2 400G AUI-2 signals. Four 400G service data are processed by the above-mentioned 400G PCS and 400G 16:2PMA to obtain a total of four groups of 400G AUI-2 signals, a total of 8 signal streams. The bit rate of each signal in the four groups of 400G AUI-2 signals is 212.5G bits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 106.25G Baud. The total bit rate of the four groups of 400G AUI-2 signals is 106.25x2x4x2=1700G bits per second. The transmitting end processing module 02 receives the four groups of 400G AUI-2 signals, and each group of 400G AUI-2 signals is subjected to 400G 2:2PMA to obtain 2 first data streams, a total of p=8 first data streams, and then the first data processing and the second data processing are performed on the 8 first data streams to obtain 1 first dual-polarization symbol stream to be sent.

[0183] Fig. 7(f) is another data processing flow diagram corresponding to the data processing method in the embodiments of the present application. As shown in Fig. 7(f), 16 PCS Lanes are subjected to 1.6T 16:4PMA based on 4-symbol multiplexing to obtain 4 1.6T AUI-4 signals. The bit rate of each signal in the four 1.6T AUI-4 signals is 425G bits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 212.5G Baud. The 1.6T PCS processing and the 1.6T 16:4PMA are implemented by operating in the transmitting end device 01. The transmitting end processing module 02 receives the four 1.6T AUI-4 signals, first subjects them to 1.6T 4:8PMA to obtain p=8 first data streams, and then performs the first data processing and the second data processing to obtain 1 first dual-polarization symbol stream to be sent.

[0184] The data processing procedure for p = 4 is introduced below. FIG. 8(e) is another data processing procedure diagram corresponding to the data processing method in the embodiments of the present application. As shown in FIG. 8(e), 16 PCS Lanes are obtained through 1.6T 16:4 PMA based on 4-symbol multiplexing to obtain 4 1.6T AUI-4 signals. The bit rate of each of the 4 1.6T AUI-4 signals is 425 Gbit / s, which is modulated by PAM4, and the corresponding baud rate (also referred to as symbol rate) is 212.5 G Baud. The 1.6T PCS processing and the 1.6T 16:4 PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 4 1.6T AUI-4 signals, first obtains p = 4 first data streams through 1.6T 4:4 PMA, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0185] FIG. 8(f) is another data processing procedure diagram corresponding to the data processing method in the embodiments of the present application. As shown in FIG. 8(f), 16 PCS Lanes are obtained through 1.6T 16:8 PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. The 1.6T PCS processing and the 1.6T 16:8 PMA are implemented by operating in the transmitting device 01. The transmitting processing module 02 receives the 8 1.6T AUI-8 signals, first obtains p = 4 first data streams through 1.6T 8:4 PMA, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0186] FIG. 8(g) is another data processing procedure diagram corresponding to the data processing method in the embodiments of the present application. As shown in FIG. 8(g), 16 PCS Lanes are obtained through 1.6T 16:4 PMA based on 4-symbol multiplexing to obtain p = 4 first data streams, and first data processing and second data processing are performed to obtain 1 first dual-polarization symbol stream to be transmitted. The 1.6T PCS processing, the 1.6T 16:4 PMA, the first data processing and the second data processing are implemented by operating in the transmitting device 01.

[0187] The specific operations of the first data processing and the second data processing are further introduced below in combination with the values of p and m.

[0188] For the scenario of p=8, m=8. For example, as shown in FIG. 7(a), 8 first data streams are acquired from a 1.6T 8:8 PMA. For another example, as shown in FIG. 7(b) and FIG. 7(c), 8 first data streams are acquired from a 1.6T 16:8 PMA. For yet another example, as shown in FIG. 7(d), a total of 8 first data streams are acquired from 2 groups of 800G 32:4 PMAs. For still another example, as shown in FIG. 7(e), a total of 8 first data streams are acquired from 4 groups of 400G 16:2 PMAs. For yet another example, as shown in FIG. 7(f), 8 first data streams are acquired from a 1.6T 4:8 PMA.

[0189] FIG. 9(a) is a schematic diagram of one embodiment of performing first data processing and second data processing in the embodiments of the present application. As shown in FIG. 9(a), 8 first data streams (i.e., first data streams 0-7) are subjected to convolution interleaving, inner code encoding and first interleaving respectively to obtain 8 second data streams. Then, the 8 second data streams are subjected to second interleaving, and the data streams subjected to the second interleaving are subjected to DP-16QAM symbol mapping and DSP framing to obtain a first dual-polarization symbol stream to be transmitted. It can be seen that in the embodiment shown in FIG. 9(a), each first data stream subjected to convolution interleaving is subjected to inner code encoding and then first interleaving.

[0190] FIG. 9(b) is a schematic diagram of another embodiment of performing first data processing and second data processing in the embodiments of the present application. Different from the embodiment shown in FIG. 9(a), as shown in FIG. 9(b), each first data stream subjected to convolution interleaving is subjected to first interleaving and then inner code encoding.

[0191] FIG. 9(c) is a schematic diagram of another embodiment of performing first data processing and second data processing in the embodiments of the present application. Different from the embodiments shown in FIG. 9(a) and FIG. 9(b), as shown in FIG. 9(c), each first data stream subjected to convolution interleaving is subjected to inner code encoding and first interleaving in a parallel processing manner.

[0192] It should be noted that for the embodiments shown in FIG. 9(a), FIG. 9(b) and FIG. 9(c), in some scenarios requiring low latency, the convolution interleaving processing can be bypassed, which has the advantages of low latency and low power consumption. It should also be noted that the first data processing of p=8 described above can be applied to a scenario of a total of 1.6T rate including 1 1.6T service, 2 800G services, 4 400G services, etc., and can be applied to a wider scenario.

[0193] For the scenario of p=8, m=8, the possible embodiments of the second interleaving are introduced as follows.

[0194] One codeword interleaving sequence is obtained from each second data stream after the first data processing, resulting in a total of 8×N bits, called the first bit set, which can be represented as follows:

[0195] in This represents the j0th (0≤j0≤N-1) bit in the codeword interleaving sequence obtained from the second data stream i0 (0≤i0≤7). The first bit set, consisting of 8×N bits, undergoes a second interleaving to obtain a second bit set of 8×N bits. DP-16QAM symbol mapping is then performed on the second bit set, mapping every 8 bits to obtain one DP-16QAM symbol, resulting in a total of N DP-16QAM symbols, denoted as S0, S1, S2, ..., S... N-2 ,S N-1 Consider S i Let the 8 bits of the i-th (0≤i≤N-1)th DP-16QAM symbol in N DP-16QAM symbols be denoted as .

[0196] The first implementation of the second interleaving is described below. Consider that the number of bits N in the internal codeword is even. Taking 0≤i≤N / 2-1 as an example, it consists of 8 bits. From 8 bits Taking N / 2≤i≤N-1 as an example, 8 bits From 8 bits

[0197] The first specific embodiment of the second interleaving is given below, where 0≤i≤N-1.

[0198] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0199] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0200] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0201] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0202] the 2x(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream

[0203] the 2x(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream

[0204] the 2x(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream

[0205] the 2x(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream The second implementation of the second interleaving is described as follows. It is considered that the number of bits N included in the inner code code word does not need to be limited to even number, but can be odd number. Taking 0≤i≤N-1 as an example, 8 bits

[0206] the i-th bit in the code word interleaving sequence from the second data stream (i+4)%8

[0207] The second implementation of the second interleaving is described as follows. It is considered that the number of bits N included in the inner code code word does not need to be limited to even number, but can be odd number. Taking 0≤i≤N-1 as an example, 8 bits

[0208] the i-th bit in the code word interleaving sequence from the second data stream (i+4)%8

[0209] the i-th bit in the code word interleaving sequence from the second data stream (i+5)%8

[0210] the i-th bit in the code word interleaving sequence from the second data stream (i+6)%8

[0211] the i-th bit in the code word interleaving sequence from the second data stream (i+7)%8

[0212] the i-th bit in the code word interleaving sequence from the second data stream (i)%8

[0213] the i-th bit in the code word interleaving sequence from the second data stream (i+1)%8

[0214] ​​​​ the i-th bit in the code word interleaving sequence from the second data stream (i+2) % 8.

[0215] the i-th bit in the code word interleaving sequence from the second data stream (i+3) % 8.

[0216] For the scenario of p=8, m=32. For example, as shown in FIG. 7(a), 8 first data streams are acquired from a 1.6T 8:8 PMA. For another example, as shown in FIG. 7(b) and FIG. 7(c), 8 first data streams are acquired from a 1.6T 16:8 PMA. For yet another example, as shown in FIG. 7(d), a total of 8 first data streams are acquired from 2 groups of 800G 32:4 PMAs. For still another example, as shown in FIG. 7(e), a total of 8 first data streams are acquired from 4 groups of 400G 16:2 PMAs.

[0217] FIG. 10(a) is a schematic diagram of another implementation of performing first data processing and second data processing in embodiments of the present application. As shown in FIG. 10(a), 8 first data streams (i.e., first data streams 0-7) are subjected to convolution interleaving to obtain 8 convolution interleaved data streams. Each convolution interleaved data stream is subjected to 1:4 k-bit block distribution to obtain 4 first sub-data streams, and a total of 32 first sub-data streams are obtained. The 32 first sub-data streams are subjected to inner code encoding and first interleaving to obtain 32 second data streams. Considering that the number of bits included in an inner code code word N is even, 1 code word interleaving sequence is acquired from each second data stream, and a total of 32×N bits are obtained, referred to as a first bit set. The first bit set is subjected to second interleaving to obtain a second bit set including 32×N bits, and the second bit set is subjected to DP-16QAM symbol mapping to map each 8 bits to 1 DP-16QAM symbol, and a total of 4×N DP-16QAM symbols, i.e., S0, S1, S2, …, SN-1, SN, are obtained. N-2 4×N-1 . Considering that S i is the i-th (0≤i≤4×N-1) DP-16QAM symbol in the 4×N DP-16QAM symbols, 8 bits mapped to the i-th DP-16QAM symbol are denoted as It can be seen that in the implementation shown in FIG. 10(a), each first data stream subjected to convolution interleaving is subjected to inner code encoding and then first interleaving.

[0218] FIG. 10(b) is a schematic diagram of another implementation of performing first data processing and second data processing in embodiments of the present application. Different from the implementation shown in FIG. 10(a), as shown in FIG. 10(b), each first data stream subjected to convolution interleaving is subjected to first interleaving and then inner code encoding.​

[0219] It should be noted that for the embodiments shown in FIG. 10(a) and FIG. 10(b) above, in some scenarios requiring low latency, the convolution interleaving process can not be performed (bypassed), with the advantage of low latency and low power consumption.

[0220] For the scenario of p=8, m=32, a third specific embodiment of the second interleaving is given below, where 0≤i≤4×N-1.

[0221] the 2×(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream .

[0222] the 2×(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream .

[0223] the 2×(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream .

[0224] the 2×(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream .

[0225] the 2×(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream .

[0226] the 2×(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream .

[0227] the 2×(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream .

[0228] the 2×(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream .

[0229] For the scenario of p=16, m=16. For example, as shown in FIG. 8(a), 16 first data streams are acquired from a 1.6T 8:16PMA. For another example, as shown in FIG. 8(b), 16 first data streams are acquired from a 1.6T 16:16PMA. For yet another example, as shown in FIG. 8(c), 16 first data streams are acquired from a 1.6T PCS.

[0230] FIG. 11(a) is a schematic diagram of another embodiment of performing first data processing and second data processing in the embodiments of the present application. As shown in FIG. 11(a), 16 first data streams (i.e., first data streams 0-15) are subjected to convolution interleaving, inner code encoding and first interleaving respectively to obtain 16 second data streams. Considering that the number of bits included in an inner code codeword is even, 1 codeword interleaving sequence is acquired from each second data stream, and a total of 16×N bits are obtained, which are referred to as a first bit set. The first bit set is subjected to second interleaving to obtain a second bit set including 16×N bits, and the second bit set is subjected to DP-16QAM symbol mapping to map each 8 bits to 1 DP-16QAM symbol, and a total of 4×N DP-16QAM symbols, i.e., S0, S1, S2, …, S2×N-1, are obtained. N-2 4×N-1 . Considering that S i is the i-th (0≤i≤2×N-1) DP-16QAM symbol in the 2×N DP-16QAM symbols, 8 bits mapped to the i-th DP-16QAM symbol are referred to as It can be seen that in the embodiment shown in FIG. 10(a), each first data stream subjected to convolution interleaving is subjected to inner code encoding and then first interleaving.

[0231] FIG. 11(b) is a schematic diagram of another embodiment of performing first data processing and second data processing in the embodiments of the present application. Different from the embodiment shown in FIG. 11(a), as shown in FIG. 11(b), each first data stream subjected to convolution interleaving is subjected to first interleaving and then inner code encoding.

[0232] FIG. 11(c) is a schematic diagram of another embodiment of performing first data processing and second data processing in the embodiments of the present application. Different from the embodiments shown in FIG. 11(a) and FIG. 11(b), as shown in FIG. 11(c), each first data stream subjected to convolution interleaving is subjected to inner code encoding and first interleaving in a parallel processing manner.

[0233] It should be noted that for the embodiments shown in FIG. 11(a), FIG. 11(b) and FIG. 11(c), in some scenarios requiring low latency, the convolution interleaving processing can be bypassed, which has the advantages of low latency and low power consumption.

[0234] ​For the case of p = 16, m = 16, a fourth embodiment of the second interleaving is given below, where 0≤i≤2×N-1.

[0235] the 2×(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream .

[0236] the 2×(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream .

[0237] the 2×(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream .

[0238] the 2×(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream .

[0239] the 2×(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream .

[0240] the 2×(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream .

[0241] the 2×(i%(N / 2))+i%2-th bit in the code word interleaving sequence from the second data stream .

[0242] the 2×(i%(N / 2))+(i+1)%2-th bit in the code word interleaving sequence from the second data stream .

[0243] For the case of p = 16, m = 32. For example, as shown in FIG. 8(a), 16 first data streams are acquired from a 1.6T 8:16 PM A. For another example, as shown in FIG. 8(b), 16 first data streams are acquired from a 1.6T 16:16 PM A. For yet another example, as shown in FIG. 8(c), 16 first data streams are acquired from a 1.6T P C S.

[0244] Figure 12(a) is a schematic diagram of another embodiment of performing the first data processing and the second data processing according to the present application. As shown in Figure 12(a), 16 first data streams (i.e., first data streams 0-15) are subjected to convolution interleaving to obtain 16 convolution interleaved data streams. Each of the 16 convolution interleaved data streams is subjected to 1:2k-bit block distribution to obtain 2 first sub-data streams, and 32 first sub-data streams are obtained in total. The 32 first sub-data streams are subjected to inner code encoding and first interleaving to obtain 32 second data streams. It is assumed that the number of bits included in the inner code codeword is even. From each of the 32 second data streams, a codeword interleaving sequence of 1 codeword is obtained, and a total of 32xN bits are obtained, which is referred to as a first bit set. The first bit set is subjected to second interleaving to obtain a second bit set including 32xN bits, and the second bit set is subjected to DP-16QAM symbol mapping to map each 8 bits to 1 DP-16QAM symbol, and a total of 4xN DP-16QAM symbols, i.e., S0, S1, S2, …, S N-2 4×N-1 , are obtained. It is assumed that S i is the i-th (0≤i≤4xN-1) DP-16QAM symbol in the 4xN DP-16QAM symbols, and the 8 bits mapped to the i-th (0≤i≤4xN-1) DP-16QAM symbol are referred to as It can be seen that in the embodiment shown in Figure 12(a), each of the first data streams subjected to convolution interleaving is subjected to inner code encoding and then first interleaving.

[0245] Figure 12(b) is a schematic diagram of another embodiment of performing the first data processing and the second data processing according to the present application. Different from the embodiment shown in Figure 12(a), as shown in Figure 12(b), each of the first data streams subjected to convolution interleaving is subjected to first interleaving and then inner code encoding.

[0246] It should be noted that for the embodiments shown in Figures 12(a) and 12(b), in some scenarios requiring low latency, the convolution interleaving processing can be bypassed, which has the advantages of low latency and low power consumption.

[0247] For the scenario of p=16 and m=32, the third specific embodiment of the second interleaving described above can be used, which will not be described herein again.

[0248] In the following, several specific embodiments are given in combination with the above description of the first data processing and the second data processing.

[0249] ​Embodiment 1: This embodiment gives a specific implementation scheme of 8 first data streams when the transmitting device 01 transmits 1.6T service and the inner code encoding uses BCH (126, 110). Herein, p = 8, m = 8.

[0250] This embodiment acquires 8 first data streams from 1.6T 8:8 PMA as shown in Fig. 7(a), or 1.6T 16:8 PMA as shown in Fig. 7(b) and Fig. 7(c), or 1.6T 4:8 PMA as shown in Fig. 7(f). Fig. 13 is a format diagram of one first data stream in the embodiment of the present application. In combination with 1.6T PCS processing and 1.6T PMA processing, each first data stream satisfies the format as shown in Fig. 13, and each continuous 4 RS symbols are from 4 different RS codewords, i.e. from the above-mentioned RS-A, RS-B, RS-C, RS-D, totally 4 RS encoders. The adjacent 4 RS symbols are denoted as RS-FEC symbol-quartet.

[0251] Fig. 14 is a diagram of one implementation of convolution interleaving in the embodiment of the present application. As shown in Fig. 14, each convolution interleaver contains r = 3 delay lines, and each delay unit contains d = 40 bits, i.e. 4 RS symbols. Delay line 0 has 2Q delay units, delay line 1 has Q delay units, and delay line 2 has no delay unit. Fig. 15 is a diagram of another implementation of convolution interleaving in the embodiment of the present application. As shown in Fig. 15, each convolution interleaver contains r = 3 delay lines, and each delay unit stores d = 40 bits, i.e. 4 RS symbols. Delay line 0 has 0 delay unit, delay line 1 has Q delay units, and delay line 2 contains 2Q delay units.

[0252] For the convenience of description, A i (a) denotes the a-th RS-FEC symbol-quartet in the first data stream i, A' i (a) is the a-th RS-FEC symbol-quartet in the output data stream of the convolution interleaver i, which is output by 4 RS symbols from one delay line of the convolution interleaver, wherein a is an integer greater than or equal to 0, 0≤i<8. The specific implementation process of convolution interleaving is that A i (3t) is input to delay line 0, while delay line 0 outputs A' i (3t); then A i (3t+1) is input to delay line 1, while delay line 1 outputs A' i (3t+1); then A i (3t+2) is input to delay line 2, while delay line 2 outputs A' i (3t+2); and then A i(3t+3) is input to delay line 0, and delay line 0 outputs A′. i (3t+3); and so on. When Q≥23, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, let Q be a multiple of 2, 4, or 8, such as Q = 24, 26, 28, 32, etc. Where t is an integer greater than or equal to 0.

[0253] Then, the data stream output from each convolutional interleaver is encoded using internal code. The internal code employs extended BCH(126,110), which is obtained by shortening the T=2 BCH(127,113) constructed based on the GF(2^7) field by 3 bits to obtain BCH(124,110). Then, odd-bit parity and even-bit parity are added to BCH(124,110) to finally obtain BCH(126,110). Its corresponding generator polynomial is: g(x) = M1(x)·M3(x)·(x... 2 +1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x 2 +1)=x 16 +x 14 +x 11 + x 10 +x 9 +x 7 +x 5 +x 3 +x+1.

[0254] Figure 16 is a schematic diagram of one implementation of the internal code encoding in this application. As shown in Figure 16, the 3 delay lines of the convolutional interleaver are polled 11 times to output 33 consecutive RS-FEC symbol-quartets (i.e., 132 RS symbols), which is represented as {A′ i (3t),A′ i (3t+1),A′ i (3t+2),A′ i (3t+3),A′ i (3t+4),A′ i (3t+5),…,A′ i (3t+30),A′ i (3t+31),A′ i (3t+32)} is divided into 12 information bit sequences U.j Each information bit sequence contains 110 bits, represented by (u0, u1, ..., u...). 108 ,u 109 ) represents, and the information bit sequence U j This includes bits 110×j to 110×j+109 of the 33 RS-FEC symbol-quartets shown. For each information bit block U... j BCH(126,110) encoding with 16 parity bits results in a codeword C containing 126 internal code bits. j The 16 parity bits are represented as (v0, v1, ..., v 14 ,v 15 Then the internal codeword C j The 126 bits are represented as (u0, u1, ..., u 108 ,u 109 ,v0,v1,…,v 14 ,v 15 ), where 0≤j<12. Then the data stream i output by the internal code encoder i is processed by the first interleaver i to obtain the second data stream i, where 0≤i<8.

[0255] Figure 17 is a schematic diagram of one implementation of the first interleaving in this application. As shown in Figure 17, performing the first interleaving i on data stream i involves performing the first interleaving process on each BCH(126,110) codeword C in data stream i to obtain the codeword interleaving sequence C′. Specifically, this involves interleaving the 110 information bits (u0, u1, ..., u) of each BCH(126,110) codeword C. 108 ,u 109 Perform a left circular shift of (i*δ)%110 bits to obtain a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ), where w j = u(j+(i*δ)%110)%110, 0≤i<8, 0≤j<110, while the codeword C has 16 parity bits (v0,v1,…,v 14 ,v 15 The position of ) remains unchanged. Alternatively, the 110 information bits (u0, u1, ..., u) of each BCH(126, 110) codeword C in the data stream i are kept unchanged. 108 ,u 109 Perform a right circular shift. Each bit yields a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ),in, If 0 ≤ i < 8, 0 ≤ j < 110, then the 126 bits of the codeword interleaved sequence C′ are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v 15 ). Where δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the concatenated code after the first interleaving can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, and 80. The following example, using a rightward loop, shows the specific loop shifts corresponding to the first interlacing 0 to the first interlacing 7. The values ​​of are shown in Table 1.

[0256] Table 1

[0257] Then, a second interleaving is performed on the eight second data streams. Specifically, one codeword interleaving sequence C′ is obtained from each second data stream, totaling 8 × 126 bits. Let C' represent the j-th (0≤j<126) bit in the codeword interleaving sequence C′ obtained from the second data stream i (0≤i≤7). For ease of description, these 8 interleaving sequences C′ are called the first bit set. The first bit set is then subjected to a second interleaving to obtain 1004 consecutive bits in the data stream, which is represented as the second bit set. Let represent the (8i+j)th bit of the second bit set, where 0 ≤ i ≤ 125 and 0 ≤ j ≤ 7. Then, a specific embodiment of the second interleaving is:

[0258] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0259] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0260] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0261] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0262] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0263] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0264] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0265] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0266] Then, each second bit set is mapped using DP-16QAM symbols to obtain 126 DP-16QAM symbols, specifically by mapping 8 consecutive bits from the second bit set. Mapped to a DP-16QAM symbol S i Where 0≤i≤125, the specific mapping method is as follows: Mapped to DP-16QAM symbol S i The I-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The Q-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The I-path component in the Y-polarization direction; Mapped to DP-16QAM symbol S i The Q-path component in the Y-polarization direction.

[0267] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and DP-16QAM symbol mapping, each inner codeword is uniformly mapped to each constellation point of the DP-16QAM symbol. This ensures that errors in each DP-16QAM symbol at the receiver are uniformly mapped to each inner codeword, improving the performance of concatenated coding.

[0268] Figure 18 is a schematic diagram of a DSP frame structure in an embodiment of this application. As shown in Figure 18, the 6048 DP-16QAM symbols obtained after 48 consecutive second interleavings and DP-16QAM symbol mappings are finally encapsulated by inserting a pilot symbol every 63 DP-16QAM symbols, resulting in a DSP frame as shown in Figure 18. This frame contains 96 subframes, each containing 64 DP-16QAM symbols. The first symbol of each subframe is the inserted pilot symbol, and the remaining 63 symbols are the DP-16QAM symbols obtained from the second bit set mapping. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, and -3-3j, where j is the imaginary unit of a complex number.

[0269] Example 2: This Example 2 is a specific scheme based on Example 1, which first performs the first interleaving and then performs the corresponding internal code encoding.

[0270] In this embodiment 2, the eight first data streams are convolutionally interleaved according to the convolutional interleaving scheme given in embodiment 1. Then, each convolutionally interleaved data stream undergoes first interleaving and internal code encoding. Specifically, the 132 consecutive RS symbols, i.e., 33 RS-FEC-symbol-quartets, in each convolutionally interleaved data stream are represented as {A′ i (3t),A′ i (3t+1),A′ i (3t+2),A′ i (3t+3),A′ i (3t+4),A′ i (3t+5),…,A′ i (3t+30),A′ i (3t+31),A′ i (3t+32)} is divided into 12 information bit sequences U. j Each information bit sequence contains 110 bits, represented by (u0, u1, ..., u...). 108 ,u 109 ) represents, and the information bit sequence U j This includes bits 110×j to 110×j+109 of the 33 RS-FEC symbol-quartets shown. For each information bit sequence U... j The first interleaving is performed to obtain the information bit interleaving sequence W. j It contains 110 bits and is represented as (w0, w1, ..., w 108 ,w 109 Then, for each information bit, interleave the sequence W. jPerform BCH(126,110) encoding, and add 16 parity bits to obtain a 126-bit internal codeword C. j The 16 parity bits are represented as (v0, v1, ..., v 14 ,v 15 Then the internal codeword C j The 126 bits are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v 15 ), where 0≤j<12. The generator polynomial of BCH(126,110) is as described in Example 1.

[0271] One specific implementation of the first interleaving is as follows: A specific implementation of the first interleaving of the data stream i after convolutional interleaving is to perform the first interleaving on each information bit sequence U = (u0, u1, ..., u...) in the data stream i. 108 ,u 109 Perform a left circular shift (i*δ)% 110 bits to obtain an information bit interleaving sequence W = (w0, w1, ..., w...). 108 ,w 109 ), where w j = u(j+(i*δ)%110)%110. Or, for each information bit sequence U = (u0, u1, ..., u...) in data stream i... 108 ,u 109 Perform a right circular shift. This yields an information bit interleaving sequence W = (w0, w1, ..., w1) consisting of 110 information bits. 108 ,w 109 ),in Where 0≤i<8, 0≤j<110, δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the interleaved concatenated code can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, 80, and 90. Below, taking a rightward loop as an example, the specific loop shift values ​​corresponding to the first interlacing 0 to the first interlacing 31 are...

[0272] The eight second data streams, after the first interleaving and internal code encoding, undergo second interleaving, DP-16QAM mapping, and DSP framing processing according to the scheme given in Example 1 to obtain the first dual-polarization symbol stream to be sent, which will not be elaborated here.

[0273] Example 3: This example 3 provides a specific scheme for 16 first data streams when the transmitting device 01 transmits 1.6T service and the internal code encoding adopts BCH(126,110).

[0274] In this embodiment, 16 first data streams are obtained from the 1.6T 8:16PMA shown in Figure 8(a), or the 1.6T 16:16PMA shown in Figure 8(b), or the PCS module shown in Figure 8(c), or the 1.6T 4:16PMA shown in Figure 8(d). Then, a convolutional interleaver as shown in Figure 14 is used to convolve and interleave each first data stream. When Q≥11, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. Alternatively, a convolutional interleaver as shown in Figure 15 can be used to convolve and interleave each first data stream. When Q≥12, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords.

[0275] To reduce the difficulty of implementing high-speed convolutional interleavers, Q is set to a multiple of 2, 4, or 8, such as Q = 12 or 16.

[0276] Then, using the internal code encoding and first interleaving scheme in Example 1, each data stream that has undergone convolutional interleaving is first encoded with internal code and then interleaved with the first interleaving to obtain 16 second data streams. Alternatively, using the first interleaving and internal code encoding scheme in Example 2, each data stream that has undergone convolutional interleaving is first interleaved and then encoded with internal code to obtain 16 second data streams.

[0277] The first interleaving process for data stream i involves performing a first interleaving process on each BCH(126,110) codeword C in data stream i to obtain a codeword interleaving sequence C′. Specifically, this involves interleaving the 110 information bits (u0, u1, ..., u) of each BCH(126,110) codeword C in data stream i. 108 ,u 109 Perform a right circular shift. Each bit yields a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ),in, If 0 ≤ i < 16, 0 ≤ j < 110, then the 126 bits of the codeword interleaved sequence C′ are represented as (w0, w1, ..., w108 ,w 109 ,v0,v1,…,v 14 ,v 15 ). Where δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the concatenated code after the first interleaving can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, and 80. The following example, using a rightward loop, shows the specific loop shifts corresponding to the first interlacing 0 to the first interlacing 15. The values ​​of are shown in Table 2.

[0278] Table 2

[0279] Then, a second interleaving is performed on the 16 second data streams. Specifically, one codeword interleaving sequence C′ is obtained from each second data stream, totaling 16 × 126 bits. Let C' represent the j-th (0≤j≤126) bit in the codeword interleaving sequence C' obtained from the second data stream i (0≤i≤15). For convenience, this 16-bit interleaving sequence C' is called the first bit set. The first bit set is then subjected to a second interleaving to obtain 2016 consecutive bits in the second interleaved data stream, which is represented as the second bit set. This represents the (8i+j)th bit of the second bit set, where 0 ≤ i ≤ 251 and 0 ≤ j ≤ 7. A specific embodiment of the second interleaving is as follows:

[0280] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0281] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0282] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0283] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0284] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0285] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0286] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0287] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0288] Then, DP-16QAM symbol mapping is performed on each second bit set to obtain 252 DP-16QAM symbols. Specifically, 8 consecutive bits in the second bit set are mapped... Mapped to a DP-16QAM symbol S i Where 0≤i≤251, the specific mapping method is as follows: Mapped to DP-16QAM symbol S i The I-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The Q-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The I-path component in the Y-polarization direction; Mapped to DP-16QAM symbol S i The I-path component in the Y-polarization direction.

[0289] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and DP-16QAM symbol mapping, each inner codeword is uniformly mapped to each constellation point of the DP-16QAM symbol. This ensures that errors in each DP-16QAM symbol at the receiver are uniformly mapped to each inner codeword, improving the performance of concatenated coding.

[0290] Finally, 6048 DP-16QAM symbols obtained by mapping the second interleaving and DP-16QAM symbols for 24 times are inserted with a pilot symbol every 63 DP-16QAM symbols, and a DSP frame shown in Fig. 18 is encapsulated, which contains 96 sub-frames, each of which is 64 DP-16QAM symbols, wherein the first symbol of each sub-frame is the inserted pilot symbol, and the remaining 63 symbols are the DP-16QAM symbols obtained by mapping the second bit set. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, and -3-3j, where j is the imaginary unit.

[0291] Embodiment 4: This embodiment 4 gives a specific scheme for a 1:4 distribution scenario when the transmitting device 01 transmits 1.6T service and the inner code encoding uses BCH (126, 110).

[0292] In this embodiment, 8 first data streams are obtained from the 1.6T 8:8 PMA shown in Fig. 7(a) or the 1.6T 16:8 PMA shown in Figs. 7(b) and 7(c). Since the transmitting device 01 transmits 1.6T service, the first data stream output by the PMA in the transmitting processing module 02 after processing the data from the transmitting device 01 satisfies the format shown in Fig. 13, and each 4 consecutive RS symbols in the first data stream come from the above-mentioned RS-A, RS-B, RS-C, and RS-D, respectively. Each first data stream is sent to the convolution interleaver described in Embodiment 1 for convolution interleaving. Then, each convolution interleaved data stream is distributed by 1:4 to obtain 4 first sub-data streams.

[0293] Fig. 19 is a schematic diagram of an embodiment of the application for distributing the data stream by 1:4. As shown in Fig. 19, the B i (t) represents 12 consecutive RS symbols in the i-th convolution interleaved data stream, which contains A' i (3t), A' i (3t+1), A' i (3t+2) output by the three delay lines of the convolution interleaver i, respectively, i.e., B i (t) = (A' i (3t), A' i (3t+1), A' i (3t+2)). The convolution interleaved data stream i is distributed by 1:4 to obtain 4 first sub-data streams through distribution i, i.e., B i (4t), B i (4t+1), B i (4t+2), B i (4t+3) in the 48 consecutive RS symbols Bi Distribute (4t+j) to the first sub-data stream 4i+j, where 0≤i<8, 0≤j<4, and t is an integer. In this case, the granularity of distribution is 120 bits (i.e., 12 RS symbols). In other specific applications, the granularity of distribution can be 110 bits (i.e., 11 RS symbols), which means distributing 44 consecutive RS symbols B from the first data stream i. i (4t),B i (4t+1),B i (4t+2),B i B in (4t+3) i (4t+j) is distributed to the first sub-data stream 4i+j, where 0≤i<8, 0≤j<4, and t is an integer.

[0294] Another implementation of the 1:4 distribution of the data stream in this application embodiment is to divide every 33 consecutive RS-FEC-symbol-quartets in the convolutionally interleaved data stream into 12 information bit sequences U of length 110 bits, as shown in Figure 16. j Where 0 ≤ j < 12. Data distribution involves round-robin distribution of the information bit sequences to the four first sub-data streams. Specifically, for the i-th convolutionally interleaved data stream, information bit sequences U0, U4, and U8 are distributed to the first sub-data stream 4×i; information bit sequences U1, U5, and U9 are distributed to the first sub-data stream 4×i+1; and information bit sequences U2, U6, and U7 are distributed to the first sub-data stream 4×i+1. 10 Distribute to the first sub-data stream 4×i+2; information bit sequence U3, information bit sequence U7, information bit sequence U 11 Distribute it to the first sub-data stream 4×i+3.

[0295] Then, using the internal code encoding and first interleaving scheme in Example 1, each first sub-data stream is first internally encoded and then first interleaved to obtain 32 second data streams. Alternatively, using the first interleaving and internal code encoding scheme in Example 2, each first sub-data stream is first first interleaved and then internally encoded to obtain 32 second data streams.

[0296] Then, a second interleaving is performed on the 32 second data streams. Specifically, one codeword interleaving sequence C′ is obtained from each second data stream, totaling 32 × 126 bits. Let C' represent the j-th (0≤j≤126) bit in the codeword interleaving sequence C' obtained from the second data stream i (0≤i≤31). For convenience, this 32-bit interleaving sequence C' is called the first bit set. The first bit set is then subjected to a second interleaving to obtain 4032 consecutive bits in the data stream, which is represented as the second bit set. the 8thi+j bit of the second bit set, where 0≤i≤503, 0≤j≤7. One specific embodiment of the second interleaving is:

[0297] the 2×(i%63)+i%2 bit of the codeword interleaving sequence from the second data stream .

[0298] the 2×(i%63)+(i+1)%2 bit of the codeword interleaving sequence from the second data stream .

[0299] the 2×(i%63)+i%2 bit of the codeword interleaving sequence from the second data stream .

[0300] the 2×(i%63)+(i+1)%2 bit of the codeword interleaving sequence from the second data stream .

[0301] the 2×(i%63)+i%2 bit of the codeword interleaving sequence from the second data stream .

[0302] the 2×(i%63)+(i+1)%2 bit of the codeword interleaving sequence from the second data stream .

[0303] the 2×(i%63)+i%2 bit of the codeword interleaving sequence from the second data stream .

[0304] the 2×(i%63)+(i+1)%2 bit of the codeword interleaving sequence from the second data stream .

[0305] Each second bit set is then DP-16QAM symbol mapped to obtain 504 DP-16QAM symbols, specifically, the consecutive 8 bits in the second bit set are mapped to a DP-16QAM symbol S i , where 0≤i≤503, the corresponding specific mapping is: are mapped to the I component of the X polarization direction of the DP-16QAM symbol S i . mapped to the X polarization direction of the Q component of the DP-16QAM symbol S i mapped to the X polarization direction of the Q component of the DP-16QAM symbol S mapped to the Y polarization direction of the I component of the DP-16QAM symbol S i mapped to the Y polarization direction of the I component of the DP-16QAM symbol S mapped to the Y polarization direction of the Q component of the DP-16QAM symbol S i mapped to the Y polarization direction of the Q component of the DP-16QAM symbol S

[0306] For each component, the bit-to-symbol amplitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. The second interleaving and DP-16QAM symbol mapping can make each inner code uniformly mapped to each constellation point of the DP-16QAM symbol, so that the error of each DP-16QAM symbol at the receiving end is uniformly mapped to each inner code word, improving the performance of the concatenated code.

[0307] Finally, 6048 DP-16QAM symbols obtained by the above-mentioned second interleaving and DP-16QAM symbol mapping for 12 times are inserted with a pilot symbol every 63 DP-16QAM symbols, and a DSP frame shown in FIG. 18 is encapsulated, which contains 96 sub-frames, each of which is 64 DP-16QAM symbols, wherein the first symbol of each sub-frame is the inserted pilot symbol, and the remaining 63 symbols are the DP-16QAM symbols mapped by the second bit set. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, -3-3j, where j is the imaginary unit.

[0308] Embodiment 5: This embodiment 5 gives a specific scheme corresponding to 1:2 distribution when the transmitting device 01 transmits 1.6T service and the inner code coding uses BCH (126, 110).

[0309] In this embodiment, 16 first data streams are obtained from the 1.6T 8:16 PMA shown in FIG. 8(a), or the 1.6T 16:16 PMA shown in FIG. 8(b), or the PCS shown in FIG. 8(c), or the 1.6T 4:16 PMA shown in FIG. 8(d). Since the transmitting device 01 transmits 1.6T service, the first data stream output by the PMA in the transmitting processing module 02 after processing the data from the transmitting device 01 satisfies the format shown in FIG. 13, and each of the four consecutive RS symbols comes from the above-mentioned RS-A, RS-B, RS-C, RS-D, respectively. Each first data stream is sent to the convolution interleaver described in embodiment 1 for convolution interleaving. Then, each convolution interleaved data stream is distributed to obtain two first sub-data streams.

[0310] Figure 20 is a schematic diagram of one embodiment of the 1:2 distribution of the data stream in the present application. As shown in Figure 20, the B i (t) represents the consecutive 12 RS symbols in the i-th first data stream, which contains the A'(3t), A'(3t+1), A'(3t+2) consecutive 12 RS symbols output by the three delay lines of the convolutional interleaver i, i.e. B i (t) = (A'(3t), A'(3t+1), A'(3t+2)). i (t) = (A'(3t), A'(3t+1), A'(3t+2)). i (t) = (A'(3t), A'(3t+1), A'(3t+2)). i (t) = (A'(3t), A'(3t+1), A'(3t+2)). i (t) = (A'(3t), A'(3t+1), A'(3t+2)). i (t) = (A'(3t), A'(3t+1), A'(3t+2)). i (t) = (A'(3t), A'(3t+1), A'(3t+2)). i (t) = (A'(3t), A'(3t+1), A'(3t+2)). i (t) = (A'(3t), A'(3t+1), A'(3t+2)). i (t) = (A'(3t), A'(3t+1), A'(3t+2)).

[0311] One embodiment of the 1:2 distribution of the data stream in the present application is to divide each consecutive 33 RS-FEC-symbol-quartet in the convolutional interleaved data stream into 12 information bit sequences U j , where 0≤j<12, according to the manner shown in Figure 16. The data distribution is to poll distribute the information bit sequences to the two first sub data streams, i.e. for the i-th convolutional interleaved data stream, the information bit sequence U0, the information bit sequence U2, the information bit sequence U4, the information bit sequence U6, the information bit sequence U 8, , the information bit sequence U 10 are distributed to the first sub data stream 2×i; the information bit sequence U1, the information bit sequence U3, the information bit sequence U5, the information bit sequence U7, the information bit sequence U9, the information bit sequence U 11 are distributed to the first sub data stream 2×i+1.

[0312] Then, the 32 first sub data are encoded according to the inner code, first interleaving, second interleaving, DP-16QAM symbol mapping, and DSP framing scheme given in Embodiment 4 to obtain one to-be-transmitted first dual-polarization symbol stream.

[0313] Embodiment 6: This embodiment 6 is a specific scheme when considering the transmission of 2x800G service by the transmitting device 01 on the basis of Embodiment 1, Embodiment 2, or Embodiment 4.

[0314] In this embodiment, eight first data streams are obtained from two 800G 4:4PMA processors as shown in Figure 7(d). Combining 800G PCS processing and 800G 32:4PAM processing, each first data stream conforms to the format shown in Figure 13. Every four consecutive RS symbols come from four different RS codewords, namely, from the aforementioned four RS encoders: RS-A, RS-B, RS-C, and RS-D. These four consecutive RS symbols are represented as RS-FEC symbol-quartets. Then, a convolutional interleaver as shown in Figure 14 or Figure 15 is used to convolve and interleave each first data stream. Specifically, three consecutive RS-FEC symbol-quartets in the first data stream, i.e., every twelve consecutive RS symbols A... i (3t), A i (3t+1), A i A in (3t+2) i (3t+j) is fed into the j-th delay line of the convolutional interleaver, where 0≤j<2, and t is an integer. When the convolutional interleaver shown in Figure 14 is used, and Q≥45, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. When using the convolutional interleaver shown in Figure 15, when Q≥46, A′ in the data stream output by the convolutional interleaver i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q = 46, 48, or 52.

[0315] Then, the eight convolutionally interleaved data streams are subjected to internal code encoding, first interleaving, second interleaving, DP-16QAM symbol mapping, and DSP framing according to the scheme of Example 1 or Example 2 to obtain a first dual-polarization symbol stream to be transmitted. Alternatively, the eight convolutionally interleaved data streams are distributed, internally encoded, first interleaved, second interleaved, DP-16QAM symbol mapping, and DSP framing according to the scheme of Example 4 to obtain a first dual-polarization symbol stream to be transmitted.

[0316] Example 7: This Example 7 is a solution based on Example 1, Example 2 or Example 4, when considering the transmission of 4x400G services by the transmitting device 01.

[0317] In this embodiment, eight first data streams are obtained from the four 400G 2:2 PMAs shown in Figure 7(e). Combining 400G PCS processing and 400G 16:2 PAM processing, each first data stream conforms to the format shown in Figure 13. Every four consecutive RS symbols come from four different RS codewords, namely from the aforementioned RS-A, RS-B, RS-C, and RS-D encoders. These four consecutive RS symbols are represented as RS-FEC symbol-quartets. Then, a convolutional interleaver, as shown in Figure 14 or Figure 15, is used to convolve and interleave each first data stream. Specifically, every 12 consecutive RS symbols A in the first data stream are... i (3t), A i (3t+1), A i A in (3t+2) i (3t+j) is fed into the j-th delay line of the convolutional interleaver, where A i (3t+j) represents four consecutive RS symbols in the first data stream, where 0 ≤ j < 2, and t is an integer. When Q ≥ 91, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q = 92, 94, 96, or 100.

[0318] Then, the eight convolutionally interleaved data streams are subjected to internal code encoding, first interleaving, second interleaving, DP-16QAM symbol mapping, and DSP framing according to the scheme of Embodiment 1 or Embodiment 2 to obtain a first dual-polarization symbol stream to be transmitted. Alternatively, the eight convolutionally interleaved data streams are distributed, internally encoded, first interleaved, second interleaved, DP-16QAM symbol mapping, and DSP framing according to the scheme of Embodiment 4 to obtain a first dual-polarization symbol stream to be transmitted.

[0319] Example 8: This example 8 proposes a lower redundancy and lower power consumption internal code encoding scheme based on examples 1 to 7.

[0320] In this embodiment, the first data is convolutionally interleaved according to any of the convolutional interleaving schemes given in Embodiments 1 to 7. Then, each convolutionally interleaved data stream is encoded using internal code, which employs extended hamming (128, 120). Specifically, the encoding process involves encoding 12 consecutive RS symbols {A′} in the convolutionally interleaved data stream. i (3t),A′ i (3t+1),A′i (3t+2)} is taken as an information bit sequence U, and (u0,u1,…,u 118 ,u 119 The code is represented as follows: Each information bit sequence U is extended using Hamming (128, 120) encoding to add 8 check bits, resulting in a 128-bit codeword C. The 8 check bits are represented as (v0, v1, ..., v6, v7). Therefore, the 128 bits of the codeword C are represented as (u0, u1, ..., u...). 118 ,u 119 (v0,v1,…,v6,v7).

[0321] Then, the data stream i encoded with internal codes is interleaved first to obtain the second data stream i, where 0 ≤ i < 8 or 0 ≤ i < 16. The first interleaving of data stream i specifically involves interleaving each extended hamming (128, 120) codeword C in data stream i to obtain the codeword interleaving sequence C′. Specifically, each extended hamming (128, 120) codeword C has 120 information bits (u0, u1, ..., u...). 118 ,u 119 Perform a left circular shift of (i*δ) % 120 bits to obtain a sequence W = (w0, w1, ..., w...) bits. 118 ,w 119 ), where w j = u(j+(i*δ)%120)%120, 0≤j<120. The positions of the 8 parity bits (v0,v1,…,v6,v7) of codeword C remain unchanged. Alternatively, the 120 information bits (u0,u1,…,u) of each extended hamming(128,120) codeword C in data stream i are... 108 ,u 109 Perform a right circular shift. This yields a 120-bit sequence W = (w0, w1, ..., w...). 108 ,w 109 ),in If 0 ≤ j < 110, then the codeword interleaving sequence C′ represents (w0, w1, ..., w 118 ,w 119 (v0, v1, ..., v6, v7). Where δ and Both are integer multiples of 10, and δ and All are greater than 0 and less than 120.

[0322] Then, a second interleaving and DP-16QAM symbol mapping are performed on the m=8 or m=16 second data streams. Specifically, one codeword interleaving sequence C′ is obtained from each second data stream, totaling m×128 bits, and used... denotes the jth bit (0≤j≤127) in the interleaved sequence C' of the codeword obtained in the second data stream i (0≤i≤m-1). For convenience of description, the m interleaved sequences C' are referred to as a first bit set, and the second interleaving of the first bit set results in m x 128 consecutive bits in the data stream, which is referred to as a second bit set. The second bit set is denoted by denotes the 8i+jth bit in the second bit set, where 0≤j≤7. A specific embodiment of the second interleaving is:

[0323] the 2x(i%64)+i%2th bit in the interleaved sequence C' of the codeword from the second data stream .

[0324] the 2x(i%64)+(i+1)%2th bit in the interleaved sequence C' of the codeword from the second data stream .

[0325] the 2x(i%64)+i%2th bit in the interleaved sequence C' of the codeword from the second data stream .

[0326] the 2x(i%64)+(i+1)%2th bit in the interleaved sequence C' of the codeword from the second data stream .

[0327] the 2x(i%64)+i%2th bit in the interleaved sequence C' of the codeword from the second data stream .

[0328] the 2x(i%64)+(i+1)%2th bit in the interleaved sequence C' of the codeword from the second data stream .

[0329] the 2x(i%64)+i%2th bit in the interleaved sequence C' of the codeword from the second data stream .

[0330] the 2x(i%64)+(i+1)%2th bit in the interleaved sequence C' of the codeword from the second data stream .

[0331] 8 bits are mapped to a DP-16QAM symbol S i in the following manner: map the I component of the X polarization direction to s i map the Q component of the X polarization direction to s i map the I component of the Y polarization direction to s i map the Q component of the Y polarization direction to s i

[0332] For each component, the bit-to-symbol amplitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. The second interleaving and symbol mapping can make each inner code word uniformly map to each constellation point of the DP-16QAM symbol, and make each DP-16QAM symbol uniformly map to each inner code word, thus improving the performance of the concatenated coding.

[0333] Finally, 6144 DP-16QAM symbols obtained by the above second interleaving and mapping are inserted with a pilot symbol every 65 DP-16QAM symbols, and a DSP frame as shown in Fig. 18 is obtained, which contains 96 sub-frames, each of which is 65 DP-16QAM symbols, wherein the first symbol of each sub-frame is the inserted pilot symbol, and the remaining 64 symbols are DP-16QAM symbols mapped from the second bit set. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, -3-3j, where j is the imaginary unit.

[0334] Embodiment 9: This embodiment 9 gives a specific scheme for the case that the transmitting device 01 transmits 1.6T service and the inner code coding uses BCH (126, 110) when there are four first data streams.

[0335] In this embodiment, the four first data streams are obtained from the 1.6T 4:4 PMA as shown in Fig. 8(e), or the 1.6T 8:4 PMA as shown in Fig. 8(f), or the 1.6T 16:4 PMA as shown in Fig. 8(g). Then, convolution interleaving is performed on each first data stream, and when Q≥46, the 12 consecutive RS symbols A'(3t), A'(3t+1), A'(3t+2) in the data stream output by the convolution interleaver come from 12 different RS code words. i i i To reduce the difficulty of high-speed implementation of the convolution interleaver, let Q be a multiple of 2 or 4 or 8, such as Q=46 or 48, etc.

[0336] ​​​​​​Then, each convolutionally interleaved data stream is first encoded using internal codes and then subjected to a first interleaving to obtain four second data streams. Alternatively, each convolutionally interleaved data stream is first interleaved and then encoded using internal codes to obtain four second data streams.

[0337] The first interleaving process for data stream i involves performing a first interleaving process on each BCH(126,110) codeword C in data stream i to obtain a codeword interleaving sequence C′. Specifically, this involves interleaving the 110 information bits (u0, u1, ..., u) of each BCH(126,110) codeword C in data stream i. 108 ,u 109 Perform a right circular shift. Each bit yields a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ),in, If 0 ≤ i < 4, 0 ≤ j < 110, then the 126 bits of the codeword interleaved sequence C′ are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v 15 ). Where δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the concatenated code after the first interleaving can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, and 80. The following example, using a rightward loop, shows the specific cyclic shifts corresponding to the first interleaving 0 to the first interleaving 3. The values ​​of are shown in Table 3.

[0338] Table 3

[0339] Example 10: Based on Example 9, consider a specific scheme where the internal code encoding uses BCH(176,160) encoding and corresponds to 4 first data streams. In this example, the convolutional interleaver uses r=4 and d=40. When Q≥35, the 16 consecutive RS symbols in the data stream output by the convolutional interleaver come from 16 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q=36 or 40. Then, each convolutionally interleaved data stream is first encoded using internal code and then first interleaved to obtain 4 second data streams. Alternatively, each convolutionally interleaved data stream is first interleaved and then encoded using internal code to obtain 4 second data streams.

[0340] Embodiment 11: Based on Embodiment 10, considering that the inner code encoding adopts BCH (176, 160) encoding, and a specific scheme corresponding to 8 first data streams. In this embodiment, the convolution interleaver adopts r=4 and d=40, and when Q≥18, 16 consecutive RS symbols in the data stream output by the convolution interleaver come from 16 different RS codewords. In order to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is a multiple of 2 or 4 or 8, such as Q=18 or 20 or 24, etc. Then, each convolution interleaved data stream is first inner code encoded and then first interleaved to obtain 8 second data streams. Or, each convolution interleaved data stream is first interleaved and then inner code encoded to obtain 8 second data streams.

[0341] Embodiment 12: Based on Embodiment 10, considering that the inner code encoding adopts BCH (176, 160) encoding, and a specific scheme corresponding to 16 first data streams. In this embodiment, the convolution interleaver adopts r=4 and d=40, and when Q≥9, 16 consecutive RS symbols in the data stream output by the convolution interleaver come from 16 different RS codewords. In order to reduce the difficulty of high-speed implementation of the convolution interleaver, Q is a multiple of 2 or 4 or 8, such as Q=10 or 12 or 16, etc. Then, each convolution interleaved data stream is first inner code encoded and then first interleaved to obtain 16 second data streams. Or, each convolution interleaved data stream is first interleaved and then inner code encoded to obtain 16 second data streams.

[0342] FIG. 21 is a structural schematic diagram of a data processing apparatus in an embodiment of the present application. As shown in FIG. 21, the data processing apparatus includes an acquisition unit 201 and a processing unit 202. The acquisition unit 201 is configured to perform the operation in step 101 in the above embodiments, and the processing unit 202 is configured to perform the operations in steps 102 and 103 in the above embodiments. It should be understood that the data processing apparatus provided in the present application can also be implemented in other manners. For example, the division of the units in the above apparatus is merely a logical function division, and other division manners can be adopted in actual implementation, for example, a plurality of units or components can be combined or integrated into another system. In addition, each functional unit in each embodiment of the present application can be integrated in a processing unit, or each functional unit can be a separate physical unit, or two or more functional units can be integrated in a processing unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0343] Figure 22 is a schematic diagram of a structure of an optical module according to an embodiment of the present application. As shown in Figure 22, the optical module includes a processor 301 and an interface 302. The processor 301 is configured to perform the operations of step 102 and step 103 in the above-described embodiments. In one possible implementation, the processor 301 includes the processing unit 202 shown in Figure 21. The interface 302 can be a transceiver or an input / output interface. The interface 302 is configured to receive a signal from another device and transmit the signal to the processor 301 or transmit a signal from the processor 301 to the other device. As an example, the processor 301 performs the first data processing and the second data processing to obtain the first dual-polarization symbol stream, and transmits the first dual-polarization symbol stream through the interface 302. In this example, the interface 302 can specifically refer to an electrical interface. As another example, the processor 301 performs the first data processing and the second data processing to obtain the first dual-polarization symbol stream, and a modulator in the optical module performs signal processing such as electro-optical conversion on the first dual-polarization symbol stream to obtain an optical signal, and transmits the optical signal through the interface 302. In this example, the interface 302 can specifically refer to an optical interface. Optionally, the optical module can further include a memory 303. The memory 303 is configured to store program instructions and data.

[0344] Generally, an optical module includes optoelectronic devices, a processor, and an interface. The optoelectronic devices include a transmitter device and a receiver device. The transmitting end of the optical module converts an electrical signal into an optical signal and transmits the optical signal through an optical fiber. The receiving end of the optical module receives an optical signal and converts the optical signal into an electrical signal.

[0345] It should be noted that the types of optical modules in the embodiments of the present application include, but are not limited to, normal optical modules, near package optics (NPO) modules, co-packaged optics (CPO) modules, and the like. The functions that can be implemented by the normal optical modules include, but are not limited to, digital signal processing (DSP) and clock data recovery (CDR), and the like. For example, the normal optical module converts an analog signal into a digital signal, performs DSP on the digital signal, and then converts the digital signal into an analog signal to be sent to a host-side device. Since the DSP needs to be retimed, the normal optical module can also be referred to as a retimed module. The normal optical module is connected to the host-side device through an attachment unit interface (AUI). The NPO module and the CPO module do not have a pluggable optical module physical package form, and are closer to the host-side device. The NPO module and the CPO module can also be referred to as optical engines. The NPO technology or the CPO technology is a technology of "packaging" the host-side device (or the host-side chip) and the optical engine. When the host-side device and the optical engine are packaged by using the NPO technology, the optical engine can be referred to as an NPO module. When the host-side device and the optical engine are packaged by using the CPO technology, the optical engine can be referred to as a CPO module.

[0346] FIG. 23 is a schematic structural diagram of a sending device in an embodiment of the present application. As shown in FIG. 23, the sending device includes a host-side device 401 and an optical module 402. The host-side device 401 is configured to send data to the optical module 402. The optical module 402 generates an optical signal according to the data sent by the host-side device 401, and sends the optical signal through a channel. For example, the host-side device can be a switch, a router, a server, or the like. The sending device can be a communication device including the host-side device 401 and the optical module 402. It should also be understood that the sending device in the embodiments of the present application is named based on the direction of data flow, and does not limit the functions of the device. For example, the sending device can also have a receiving function.

[0347] The embodiments of the present application also provide an optical transport network (OTN) device, which comprises a line side device and a client side device. The client side device can also be referred to as a tributary side device in some scenarios. The line side device comprises a processor and an interface. The processor is configured to execute the data processing method described in the above embodiments. The interface can be a transceiver or an input / output interface. The interface is configured to receive a signal from another device outside the line side device and transmit the signal to the processor, or transmit a signal from the processor to another device outside the line side device.

[0348] The embodiments of the present application also provide a chip. The chip integrates a circuit for implementing the functions of the processor described above and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, the chip can be connected to an external memory through the interface. The chip can complete the method steps of any one or more of the above embodiments. Alternatively, the chip implements the actions performed by the data processing device in the above embodiments according to program codes stored in the memory.

[0349] As an example, the chip in the embodiments of the present application can be a central processing unit (CPU), and can also be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, a transistor logic device, a hardware component or any combination thereof. The general-purpose processor can be a microprocessor, or can be any conventional processor, and can also be a processing circuit implementing specific functions.

[0350] The embodiments of the present application also provide a computer readable storage medium, which comprises a program or instructions. When the program or instructions are executed on a computer, the program or instructions cause the computer to implement the method performed by the above method embodiments.

[0351] It should be understood that the processor mentioned in the embodiments of the present application can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit or the like. When implemented by software, the processor can be a general-purpose processor, which implements by reading software codes stored in a memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0352] As an example, the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor, and can also be a processing circuit that implements specific functions.

[0353] The memory in the embodiments of the present application can be a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a network device or a terminal device. Of course, the processor and the storage medium can also exist as discrete components in the network device or the terminal device.

[0354] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof.

[0355] When implemented by using hardware, the data processing method provided by the embodiments of the present application can be implemented without reading software codes or instructions, for example, by using a CPU, a DSP, an ASIC, an FPGA, other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0356] When implemented using software, the functions can be implemented using one or more computer programs or instructions stored or executed in at least one computer-readable medium. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a computer-readable signal. The computer-readable medium can include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, DVDs, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or any other suitable type of machine-readable medium. Suitable machine-readable media for storing or transmitting software include hardware- or software-readable media that store data which can be accessed by one or more computer systems. A computer-readable medium stores computer-executable instructions or data that, in combination with the computer system, cause the computer system to operate. For example, a non-transitory computer-readable medium comprising a computer-readable medium that does not undergo a transformation during transmission is any medium that stores data that is not transmitted but is accessed by the computer system. Examples of non-transitory computer-readable media include random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc. The term "computer-readable medium" includes, but is not limited to, portable or fixed computer-readable media that store data for use by or in connection with the computer system. The computer-readable medium can be a computer- readable storage medium or a computer-readable signal medium.

[0357] Finally, it should be noted that the above merely illustrates the embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

A data processing method, characterized by, Comprise: Obtaining p first data streams which are Reed-Solomon (RS) encoded, p is a positive integer multiple of 4 and is an integer power of 2, each of the first data streams has a RS number of adjacent RS symbols which are from a RS number of RS codewords, wherein the number a RS is greater than or equal to 4 and is an integer power of 2; performing first data processing including forward error correction (FEC) encoding and first interleaving on the p first data streams respectively to obtain m second data streams, m being an integer greater than or equal to p; performing second data processing including second interleaving, dual polarization 16 quadrature amplitude modulation (DP-16QAM) symbol mapping and framing on the m second data streams to obtain 1 first dual polarization symbol stream. The method of claim 1, wherein m > p, performing first data processing including FEC encoding and first interleaving on the p first data streams respectively to obtain m second data streams comprises: performing distribution on each of the p first data streams to obtain m / p first sub-data streams, performing FEC encoding and first interleaving on the m first sub-data streams respectively to obtain the m second data streams. The method according to claim 2, characterized in that each of the first sub-data streams obtained by distribution of 1 first data stream comprises K consecutive bits in the 1 first data stream, K being a positive integer, wherein K is the number of information bits participating in the FEC encoding. or each of the first sub-data streams obtained by distribution of 1 first data stream comprises K0 consecutive bits in the 1 first data stream, K0 being an integer multiple of 40. The method according to claim 2 or 3, characterized in that The number of information bits participating in the FEC encoding is K, and each of the first sub-data streams obtained by distribution of 1 first data stream comprises K0 consecutive bits in the 1 first data stream, K = 110 and K0 = 120. The method according to any one of claims 2 to 4, characterized in that performing first data processing including FEC encoding and first interleaving on the p first data streams respectively to obtain m second data streams comprises: performing convolution interleaving on the p first data streams respectively, performing distribution on each of the p first data streams subjected to the convolution interleaving to obtain m / p first sub-data streams, performing FEC encoding and first interleaving on the m first sub-data streams to obtain the m second data streams. The method of claim 1, wherein performing first data processing including FEC encoding and first interleaving on the p first data streams respectively to obtain m second data streams comprises: performing convolution interleaving on the p first data streams respectively, performing FEC encoding and first interleaving on the p first data streams subjected to the convolution interleaving to obtain the m second data streams. The method according to claim 5 or 6, characterized in that performing convolution interleaving on 1 first data stream comprises: delaying bits from the first data stream according to r delay lines, r being an integer greater than 1, each delay line comprising a different number of storage units, the delay line comprising the smallest number of storage units comprising 0 storage units, the difference in the number of storage units between each adjacent two delay lines being Q, each storage unit being used to store d bits, the input bits being input into the r delay lines in sequence according to the serial numbers of the r delay lines, d bits being input into each delay line at a time and d bits being output from each delay line at a time, Q and d both being integers greater than or equal to 1. The method of claim 7, wherein the delay line with the largest serial number in the r delay lines comprises 0 storage units, or the delay line with the smallest serial number in the r delay lines comprises 0 storage units. The method according to claim 7 or 8, characterized in that p=8, r=3, d=40, Q³23; or, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p=16, r=3, d=40, Q³11; or, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p=16, r=3, d=40, Q³12; or, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p=4, r=3, d=40, Q³45; or, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p=4, r=3, d=40, Q³46; or, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p=4, r=4, d=40, Q³34; or, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p=4, r=4, d=40, Q³35; or, the delay line with the largest serial number among the r delay lines includes 0 memory cells, p=8, r=4, d=40, Q³17; or, the delay line with the smallest serial number among the r delay lines includes 0 memory cells, p=8, r=4, d=40, Q³18; or, p=16, r=4, d=40, Q³9. The method according to any one of claims 1 to 9, characterized in that The number of information bits participating in the FEC encoding is K, each code word after the FEC encoding includes N bits, and N-K check bits in the code word are obtained by the K information bits after the FEC encoding. The first interleaving is used for cyclically shifting every K information bits in the first data stream. The method of claim 10, wherein p = 4, the first interleaving is used to cyclically shift every K information bits in the first data stream i one bit, 0 < i < 4, satisfies one of the following: Alternatively, p = 8, and the first interleaving is used to cyclically shift every K information bits in the first data stream i one bit, 0 < i < 8, satisfies one of the following: Alternatively, p = 16, and the first interleaving is used to cyclically shift every K information bits in the first data stream i bits, 0 < i < 16, satisfies one of the following: The method according to any one of claims 1 to 11, characterized in that The first data processing including FEC encoding and first interleaving on the first data stream includes: FEC encoding on the first data stream, and first interleaving on the first data stream after the FEC encoding; or, FEC encoding on the first data stream, and first interleaving on the first data stream after the FEC encoding; or, FEC encoding on K information bits in the first data stream to obtain N-K check bits, and first interleaving on the K information bits to obtain N bits including the N-K check bits and the K information bits after the first interleaving, wherein the K is a positive integer, and N>K. The method according to any one of claims 1 to 12, characterized in that The second interleaving and DP-16QAM symbol mapping on the m second data streams include: obtaining N bits in each of the second data streams to obtain m×N bits, wherein the N bits include K information bits and N-K check bits in a code word after the FEC encoding; second interleaving on the m×N bits; DP-16QAM symbol mapping on the m×N bits after the second interleaving to obtain N×m / 8 DP-16QAM symbols. The method of claim 13, wherein p = 8, m = 8, represents the j0th bit in N bits obtained from the i0th second data stream, 0≤i0≤7, 0≤j0≤N-1, mapped to the 8-bit representation of the i-th DP-16QAM symbol as from The method of claim 14, wherein the i-th bit in N bits from the (i+4) %8 second data stream; the i-th bit in N bits from the (i+5) %8 second data stream; the i-th bit in N bits from the (i+6) %8 second data stream; the i th bit in the N bits from the (i+7) th 8-bit second data stream; the i th bit in the N bits from the (i) th 8-bit second data stream; the i th bit in the N bits from the (i+1) th 8-bit second data stream; the i th bit in the N bits from the (i+2) th 8-bit second data stream; the i th bit in the N bits from the (i+3) th 8-bit second data stream. The method according to any one of claims 1 to 15, characterized in that the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: or, the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: or, the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: or, the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: The method of claim 16, wherein the first dual-polarization symbol stream comprises a plurality of dual-polarization symbol sequences, and a fixed position in each of the dual-polarization symbol sequences comprises the target symbol sequence, and the target symbol sequence comprises at least one of a frame synchronization symbol sequence, a training symbol sequence, a reserved symbol sequence and a pilot symbol sequence. The method according to any one of claims 1 to 17, characterized in that each code word after the FEC encoding comprises K information bits and N-K check bits, and N=128, K=120, or N=126, K=110, or N=176, K=160. The method according to any one of claims 1 to 18, characterized in that m=4, 8, 16 or 32. The method according to any one of claims 1 to 19, characterized in that each of the first data streams comprises 4 RS symbols, and each of the 4 RS symbols is from a 4 RS code word. the i th bit in the N bits from the (i+7) th 8-bit second data stream; the i th bit in the N bits from the (i) th 8-bit second data stream; the i th bit in the N bits from the (i+1) th 8-bit second data stream; the i th bit in the N bits from the (i+2) th 8-bit second data stream; the i th bit in the N bits from the (i+3) th 8-bit second data stream. the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: or, the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: or, the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: or, the second data processing on the m second data streams comprises second interleaving, DP-16QAM symbol mapping and framing to obtain 1 first dual-polarization symbol stream, which comprises one of the following: the first dual-polarization symbol stream comprises a plurality of dual-polarization symbol sequences, and a fixed position in each of the dual-polarization symbol sequences comprises the target symbol sequence, and the target symbol sequence comprises at least one of a frame synchronization symbol sequence, a training symbol sequence, a reserved symbol sequence and a pilot symbol sequence. each code word after the FEC encoding comprises K information bits and N-K check bits, and N=128, K=120, or N=126, K=110, or N=176, K=160. m=4, 8, 16 or 32. each of the first data streams comprises 4 RS symbols, and each of the 4 RS symbols is from a 4 RS code word. The method according to any one of claims 1 to 20, characterized in that The p first data streams are obtained by 16 fifth data streams through physical media attachment (PMA) processing based on symbol multiplexing, and the 16 fifth data streams are obtained by service data to be sent through physical coding sublayer (PCS) processing including RS encoding. The method of claim 21, wherein The p first data streams are obtained by t signals through t:p PMA processing, and the t signals are obtained by the 16 fifth data streams through 16:t PMA processing, t being a positive integer multiple of 4. The method of claim 21, wherein The p first data streams are obtained by the 16 fifth data streams through 16:p PMA processing. The method according to any one of claims 1 to 20, characterized in that The p first data streams are obtained by t signals through t:p PMA processing based on symbol multiplexing. The method according to claim 22 or 24, characterized in that t=8, p=8; or, t=16, p=8; or, t=4, p=8; Or, t=8, p=16; Or, t=16, p=16; Or, t=4, p=16; Or, t=4, p=4; Or, t=8, p=4. The method according to any one of claims 1 to 20, characterized in that The p first data streams are obtained by service data to be sent through PCS processing including RS encoding. The method according to any one of claims 1 to 26, characterized in that The data processing method is applied to scenarios including Ethernet, optical transport network, and space optical communication. A data processing device, characterized by The data processing apparatus includes an acquisition unit and a processing unit. The acquisition unit is configured to acquire p first data streams subjected to Reed-Solomon (RS) encoding, p is a positive integer multiple of 4, and p is an integer power of 2; each a RS adjacent RS symbol in each of the first data streams is from an RS codeword, where a RS > 4 and is an integer power of 2. RS ​ The processing unit is configured to perform first data processing including forward error correction (FEC) encoding and first interleaving on the p first data streams respectively to obtain m second data streams, m being an integer greater than or equal to p. The m second data streams are subjected to second data processing including second interleaving, dual-polarization 16-quadrature amplitude modulation (DP-16QAM) symbol mapping, and framing to obtain one first dual-polarization symbol stream. A chip characterized by The chip is configured to perform the method in any of claims 1 to 27. An optical module characterized by comprising: The optical module includes a processor and an interface, the processor is configured to perform the method in any of claims 1 to 27, and the interface is configured to transmit and receive signals. A transmitting device characterized by comprising: The sending device includes a host-side device and the optical module in claim 30, the optical module is configured to generate an optical signal according to data from the host-side device, and send the optical signal. A communication system characterized by Comprising: The sending device in claim 31 and the receiving device, the sending device is configured to send signals to the receiving device.

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