Backplane cascade system, address allocation method and computer device

Abstract

Provided in the present application are a backplane cascade system, an address allocation method and a computer device. The backplane cascade system comprises a mainboard and N backplanes; the mainboard comprises a connector and a complex programmable logic device; each backplane comprises an uplink connector, a downlink connector and a shift register, N>1, and N being a positive integer; the mainboard is connected to the first backplane via the connector and is used for transmitting an address signal to the first backplane by means of the connector; the uplink connector of the i-th backplane is connected to the downlink connector of the i-th backplane; the uplink connector of the i-th backplane is connected to the shift register of the i-th backplane which is used for shifting bits of the address signal; the downlink connector of the i-th backplane is connected to the uplink connector of the (i+1)-th backplane and is used for transmitting the bit-shifted address signal to the (i+1)-th backplane. Only one CPLD is required to be provided on the mainboard, and the mainboard can automatically allocate addresses to external devices on each of the backplanes, thus aiding in maintenance and reducing cost.

Description

Backplane cascading systems, address allocation methods, and computer equipment

[0001] This application claims priority to Chinese Patent Application No. 202410564115.7, filed on May 8, 2024, entitled “Backplane Cascading System, Address Allocation Method and Computer Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and more specifically, to a backplane cascading system, an address allocation method, and a computer device. Background Technology

[0003] Backplane design generally needs to meet the following basic functions: support temperature / power consumption monitoring, support hard disk information / real-time status reading, and support hard disk status LEDs. These functions are all implemented by the BMC (Baseboard Management Controller) through I2C (Inter-Integrated Circuit) / I3C (Improved Inter-Integrated Circuit) bus to transmit data.

[0004] In some solutions, assembling and managing multiple backplanes mainly involves three forms: 1) Setting multiple connectors on the motherboard, each connector corresponding to a node. The server motherboard's Baseboard Management Controller (BMC) can distinguish the location of each node in the system based on the connector, thus accessing the corresponding node. However, setting up multiple connectors occupies a lot of physical space, and multiple cables leading from the motherboard can cause assembly difficulties and affect heat dissipation, while also increasing costs. 2) Cascading multiple nodes, using configurable address bus devices on the nodes. Different peripheral circuits configure the bus devices to different addresses. The server motherboard's Baseboard Management Controller (BMC) can access the corresponding node based on the address. However, using different peripheral lines for differentiation requires a separate bill of materials (BOM) for each node. Material (BOM) has high subsequent management and maintenance costs, especially when there are many cascaded nodes, which can easily cause confusion. When setting up a logic programming device at each node and cascading multiple nodes, the motherboard first transmits a signal of a certain frequency to the logic programming device of the first node, and then transmits it to the next node after frequency division, and so on. The logic programming device of each node assigns different addresses to the devices on the node according to the different frequencies it identifies. However, each node requires a logic programming device, which increases material costs and maintenance costs.

[0005] The preceding description is intended to provide general background information and does not necessarily constitute prior art.

[0006] Summary of the Invention

[0007] The purpose of this application is to provide a backplane cascading system, an address allocation method, and a computer device to solve the problems of difficult assembly, high maintenance costs, and high labor costs in the prior art.

[0008] In a first aspect, embodiments of this application provide a backplane cascading system, including: a motherboard and N backplanes, the motherboard including a connector and a complex programmable logic device, and the backplane including an uplink connector, a downlink connector and a shift register; wherein, N>1, and N is a positive integer;

[0009] The motherboard connects to the first backplane via a connector, which is used to transmit address signals to the first backplane.

[0010] The uplink connector of the i-th backplane is connected to the downlink connector of the i-th backplane, and the uplink connector of the i-th backplane is connected to the shift register of the i-th backplane for shifting the address signal; 1≤i≤N;

[0011] The downlink connector of the i-th backplane is connected to the uplink connector of the (i+1)-th backplane to transmit the shifted address signal to the (i+1)-th backplane.

[0012] In one embodiment, the shift register of the i-th backplane includes a data pin, a clock signal pin, and the data input pin and clock signal pin are connected to the uplink connector of the i-th backplane.

[0013] The data pins receive address signals transmitted by complex programmable logic devices via an uplink connector;

[0014] The clock signal pin is connected to the downlink connector of the i-th backplane.

[0015] In one embodiment, the motherboard and N backplanes are connected via a daisy-chain topology.

[0016] In one embodiment, the backplane further includes at least one external device, which is connected to the shift register.

[0017] Shift registers assign address information to external devices.

[0018] In one embodiment, the external device includes a first device, a second device, and a third device;

[0019] The first device, the second device, and the third device are each connected to the shift register;

[0020] The shift register assigns address information to the first, second, and third devices.

[0021] In one embodiment, the data pins of the first device, the second device, and the third device are connected together via an I2C bus and connected to a downlink connector, and the clock signal pins of the first device, the second device, and the third device are connected together via an I2C bus and connected to a downlink connector.

[0022] In one embodiment, the motherboard includes a baseboard management controller, which is connected to external devices in each backplane in a daisy-chain topology.

[0023] The baseboard management controller accesses the external device based on the address assigned to it.

[0024] In one embodiment, the system includes a set of I2C buses, which are connected to the uplink connector of the i-th backplane via the downlink connector of the (i-1)th backplane. Within the i-th backplane, the I2C buses are connected to the downlink connector via the uplink connector.

[0025] In one embodiment, a set of I2C buses includes data transmission lines and clock transmission lines, through which the baseboard management controller transmits signals to each backplane.

[0026] Secondly, embodiments of this application also provide an address allocation method based on the aforementioned backplane cascading system, the method comprising:

[0027] The motherboard transmits address signals to the first backplane connected to the connector via a connector;

[0028] The i-th backplane receives the address signal transmitted by the (i-1)-th backplane through the uplink connector, and shifts and transmits the address signal to the downlink connector of the i-th backplane through the shift register.

[0029] The downlink connector of the i-th backplane transmits the shifted address signal to the (i+1)-th backplane.

[0030] Thirdly, embodiments of this application provide a computer device including any of the aforementioned backplane cascade systems.

[0031] Fourthly, embodiments of this application provide a computer device, including: a memory and a processor;

[0032] The memory stores instructions that the computer executes;

[0033] The processor executes computer execution instructions stored in memory, causing the processor to perform the various possible implementations of the second aspect above.

[0034] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement various possible implementations of the second aspect above.

[0035] Sixthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements various possible implementations of the second aspect above.

[0036] The backplane cascading system provided in this application includes: a motherboard and N backplanes. The motherboard includes a connector and a complex programmable logic device (CPL). The backplanes include an uplink connector, a downlink connector, and a shift register; where N>1, and N is a positive integer. The motherboard is connected to the first backplane via the connector to transmit address signals to the first backplane. The uplink connector of the i-th backplane is connected to the downlink connector of the i-th backplane, and the uplink connector of the i-th backplane is connected to the shift register of the i-th backplane to shift the address signals; 1≤i≤N. The downlink connector of the i-th backplane is connected to the uplink connector of the (i+1)-th backplane to transmit the shifted address signals to the (i+1)-th backplane. The address signals are transmitted to the backplanes via the CPL on the motherboard, and the shift registers in the backplanes shift the address signals. The motherboard can automatically and intelligently assign different addresses to each backplane. Furthermore, the connection between the backplanes is simple, assembly is easy, maintenance is convenient, and it saves manpower and resources, reducing costs. Attached Figure Description

[0037] Figure 1 is a schematic diagram of the backplane cascade system provided in an embodiment of this application;

[0038] Figure 2 is a schematic diagram of the backplane cascade system provided in an embodiment of this application;

[0039] Figure 3 is a schematic diagram of a shift register provided in an embodiment of this application;

[0040] Figure 4 is a flowchart of an address allocation method provided in an embodiment of this application;

[0041] Figure 5 is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0042] First, let me explain the terms used in this application:

[0043] Complex Programmable Logic Device (CPLD): CPLD refers to an integrated circuit device with programmable logic functions. It typically consists of programmable logic units (PLUs) and programmable interconnect resources, and can be programmed according to user needs to implement specific logic functions.

[0044] Board Management Controller (BMC): A BMC is an integrated circuit device typically used to manage and monitor the board (motherboard) functions of servers or other computing devices. A BMC typically includes components such as a processor, memory, network interface, and sensors. It can operate independently of the main processor and provides remote management, monitoring, diagnostics, and control functions.

[0045] Daisy-chain topology: This is a network topology where each device is connected to its immediate neighbors via a separate connection, forming a ring link. In a daisy-chain topology, data is transmitted along the link; each device receives data and passes it on to the next device until the data reaches its destination. This topology is typically used to connect multiple devices in series, such as external storage devices, sensors, and controllers.

[0046] In existing solutions, core devices such as servers and switches need to be equipped with multiple nodes simultaneously. To manage and assemble multiple nodes while considering requirements such as motherboard resource allocation, overall cable management, heat dissipation, and cost, there are generally three approaches. The first approach uses multiple connectors on the motherboard, with each connector corresponding to a node. Nodes are distinguished and accessed / controlled based on the connector. This results in numerous cables, making assembly difficult and affecting heat dissipation. The second approach uses configurable address bus devices on each node, cascading multiple nodes. This requires different peripheral circuits to distinguish different devices, leading to higher maintenance costs and potential confusion when there are many nodes. The third approach uses a programmable logic device (PLD) on each node, allocating addresses through the PLD, which increases material and maintenance costs.

[0047] Based on the above scenarios, it is clear that existing technologies face challenges in managing and assembling multiple nodes, including assembly difficulties, high material costs, and high maintenance costs.

[0048] The backplane cascading system provided in this application transmits address signals to each backplane through complex programmable logic devices on the motherboard. The shift registers in the backplanes shift the address signals, and the motherboard can automatically and intelligently assign different addresses to each backplane. Secondly, the connection between each backplane is simple, the assembly is simple, the maintenance is convenient, and it saves manpower and material resources and reduces costs.

[0049] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0050] As shown in Figure 1, Figure 1 is a structural schematic diagram of a backplane cascading system provided in an embodiment of this application. This embodiment of the application provides a backplane cascading system, including: a motherboard and N backplanes. The motherboard includes a connector and a complex programmable logic device. The backplanes include an uplink connector, a downlink connector and a shift register; wherein, N>1, and N is a positive integer.

[0051] The motherboard is connected to the first backplane via a connector to transmit address signals to the first backplane. The uplink connector of the i-th backplane is connected to the downlink connector of the i-th backplane, and the uplink connector of the i-th backplane is connected to the shift register of the i-th backplane to shift the address signals. 1≤i≤N.

[0052] The downlink connector of the i-th backplane is connected to the uplink connector of the (i+1)-th backplane to transmit the shifted address signal to the (i+1)-th backplane.

[0053] In this application, only one complex programmable logic device (CPL) is set on the motherboard. The CPL transmits address signals to each backplane through the CPL, shifts the address signals through a shift register, and transmits the shifted address signals to the next backplane through a connector. This enables the management of each backplane, reduces costs, and the backplane cascade system of this solution is simple to assemble and maintain.

[0054] In one embodiment, the address signal sent by the complex programmable logic device is 8N bits of data. Here, N corresponds to the number of backplanes.

[0055] In one embodiment, the shift register of the i-th backplane includes a data pin, a clock signal pin, and the data input pin and clock signal pin are connected to the uplink connector of the i-th backplane.

[0056] The data pins receive address signals transmitted by complex programmable logic devices via an uplink connector;

[0057] The clock signal pin is connected to the downlink connector of the i-th backplane.

[0058] As shown in Figure 1, taking the first backplane as an example, the data pin D_IN and clock signal pin CLK of the shift register are connected to the data pin D_IN and clock signal pin CLK of the shift register through the connector and the uplink connector of the first backplane. The complex programmable logic device sends an address signal to the first backplane. According to the principle of the shift register, the clock signal CLK is triggered by the rising edge. With each rising edge, the shift register starts to shift. The shift register transmits the shifted address signal to the next backplane through the downlink connector.

[0059] In one embodiment, the motherboard connector, uplink connector, and downlink connector each include at least four pins: PIN1, PIN2, PIN3, and PIN4. The number of pins on the motherboard connector, uplink connector, and downlink connector are identical. The clock and address signals of the Complex Programmable Logic Device (CPLD) enter the first backplane through the motherboard connector and connect to PIN1 and PIN2 of the uplink connector on the first backplane. The uplink connector connects to a shift register, with PIN1 of the uplink connector connected to the CLK pin of the shift register, and PIN2 of the uplink connector connected to the D_IN pin of the shift register. A connecting line is led out from the connection line between the uplink connector pins and the CLK pin of the shift register and connects to PIN1 of the downlink connector. Thus, the clock signal can be transmitted to the next backplane via the downlink connector after being triggered on the rising edge.

[0060] In one embodiment, the shift register includes an 8-bit output interface: D0, D1, D2, D3, D4, D5, D6, and D7, wherein D7 is connected to the PIN2 pin of the downlink connector on the first backplane for transmitting the shifted address signal.

[0061] Figure 3 shows the schematic diagram of the shift register provided in this embodiment. The shift register consists of eight flip-flops. A simple 8-flip-flop parallel input parallel output shift register is shown in Figure 3. The output data at the parallel output terminal appears simultaneously with the input data. Table 1 is a function table diagram of the shift register. Table 1 shows the function table of the shift register. When the clock signal changes, the input data will be shifted sequentially.

[0062] Table 1 Function table of shift registers

[0063] In one embodiment, the motherboard and N backplanes are connected via a daisy-chain topology.

[0064] Specifically, as shown in Figure 1, the clock signal connection between the motherboard and each backplane of a complex programmable logic device (CPL) is a daisy-chain topology. This can be simply understood as the motherboard's clock signal lines branching off into different branches, which connect to different backplanes. The backplane cascading system provided in this application can intelligently assign backplane numbers, fulfilling the daisy-chain topology routing requirements for I2C signals and effectively solving backplane identification and I2C link signal integrity issues. It employs a cascaded address shifting design, achieving pure hardware shifting on the board, resulting in strong system reliability and stability. Automatic encoding is achieved through master-slave node interconnection, intelligently assigning backplane numbers and device addresses, effectively avoiding errors from manual assembly. Signal transmission via cascading and driver units realizes a daisy-chain topology, improving bus signal integrity.

[0065] In one embodiment, the backplane also includes at least one external device, which is connected to a shift register; the shift register assigns address information to the external device.

[0066] In one embodiment, as shown in FIG1, the backplane includes three external devices, namely a first device, a second device, and a third device; the first device, the second device, and the third device are respectively connected to a shift register; the shift register allocates address information for the first device, the second device, and the third device.

[0067] Specifically, A1, A2, and A3 in the first, second, and third devices are used to receive the address allocated by the shift register. The A3 ports in the first, second, and third devices are interconnected, meaning that the high-order bits (A3) of the addresses of the first, second, and third devices are the same, while the low-order bits (A2 and A1) are different.

[0068] In one embodiment, the motherboard includes a baseboard management controller, which is connected to external devices in each backplane in a daisy-chain topology.

[0069] The baseboard management controller accesses the external device based on the address assigned to it.

[0070] In one embodiment, the system includes a set of I2C buses, which are connected to the uplink connector of the i-th backplane via the downlink connector of the (i-1)th backplane. Within the i-th backplane, the I2C buses are connected to the downlink connector via the uplink connector.

[0071] In one embodiment, a set of I2C buses includes data transmission lines and clock transmission lines, through which the baseboard management controller transmits signals to each backplane.

[0072] Optionally, the baseboard management controller's data signal (SDA) is connected to each backplane via a data transmission line, and the baseboard management controller's clock signal (SCL) is connected to each backplane via a clock transmission line. The server motherboard, as the master node, is the signal source for all uplinks. The BMC chip on the motherboard is used for server platform management. As an I2C master device, the BMC provides a set of I2C bus interfaces, consisting of two signal lines: I2C_SDA (Serial Data) and I2C_SCL (Serial Clock), providing I2C data and clock signals. This supports functions such as temperature / power consumption monitoring, hard drive information / real-time status reading, and hard drive status LED display on the backplane. Each backplane connects to the I2C bus via uplink and downlink connectors; that is, the I2C bus is connected to the backplane via its uplink connector, and each backplane has at least one external device connected to the I2C bus.

[0073] Specifically, the data signal (SDA) of the baseboard management controller is connected to the uplink connector of the first backplane via PIN3 of the first connector on the motherboard, and then to PIN3 of the downlink connector on the first backplane. The clock signal (SCL) of the baseboard management controller is connected to the uplink connector of the first backplane via PIN4 of the first connector on the motherboard, and then to PIN4 of the downlink connector on the first backplane. The clock and data signals of the baseboard management controller are also connected to external devices on each backplane for accessing and transmitting data to these devices. The connection method with the second backplane follows the same pattern and will not be described further here.

[0074] In one embodiment, the data pins of the first device, the second device, and the third device are connected together via an I2C bus and connected to a downlink connector, and the clock signal pins of the first device, the second device, and the third device are connected together via an I2C bus and connected to a downlink connector.

[0075] In one embodiment, as shown in FIG2, FIG2 is a schematic diagram of a backplane cascade system provided in an embodiment of the present application. The backplane cascade system includes a motherboard 110 and three backplanes 121, 122 and 123. The complex programmable logic device in the motherboard needs to send 24-bit address signals, namely 00000000, 00101010 and 01010100.

[0076] On the backplane, the clock signal of the complex programmable logic device (CPL) is connected to the CLK pin of the shift register, and the address signal of the CPL is connected to the D_IN pin of the shift register. According to the principle of the shift register, the shift register is triggered on the rising edge of the CLK signal. On each rising edge of CLK, the shift register shifts the data one position to the left, i.e., Dn = Dn-1. Thus, the GPIO data corresponding to the shift register on the first backplane is D0~D7 = 00000000; the GPIO data corresponding to the shift register on the second backplane is D0~D7 = 00101010; and the GPIO data corresponding to the shift register on the third backplane is D0~D7 = 01010100. Ports A1, A2, and A3 in the first, second, and third devices are used to receive the address signals output by the shift register.

[0077] For example, the first device in the backplane is an FRU (Field Replacement Unit), such as the GT24C128D, with an I2C address of 1010A3A2A1X; the second device is a temperature sensor, such as the TMP175, with an I2C address of 1001A3A2A1X; and the third device is an I / O expander (IO). For example, the PCA9555 has an I2C address of 0100A3A2A1X. The address signal transmitted by the complex programmable logic device is shifted by a shift register, resulting in different addresses output on each backplane. 0X represents hexadecimal. Here, the binary is converted to hexadecimal, and the addresses of different devices on each backplane are as follows: First backplane: I2C address of the first device is 0XA0, the second device is 0X90, and the third device is 0X40; Second backplane: I2C address of the first device is 0XA1, the second device is 0X91, and the third device is 0X41; Third backplane: I2C address of the first device is 0XA2, the second device is 0X92, and the third device is 0X42. Each device in the backplane has a different address. This shows that the address signal sent by the complex programmable logic device can intelligently assign addresses to different devices through the backplane cascading system. The circuit is simple, easy to assemble and maintain. Secondly, the solution is simple to implement, has a wide range of applications, and is not limited.

[0078] The motherboard's baseboard management controller (BMC) connects to each backplane via a daisy-chain topology. Addresses assigned by complex programmable logic devices (CPLs) allow access to the corresponding devices, completing the backplane cascading scheme. In this example, the server motherboard can automatically assign address information to external devices on each backplane using a preset address mapping table (the specific process is described in the preceding embodiments and will not be repeated here). The BMC in the server motherboard obtains information from the CPLD registers on the motherboard, including the address information of all external devices on each backplane. The BMC writes the obtained address information of the external devices into the addressing array, and then addresses the external devices on the backplane step by step according to the addressing array to obtain backplane information and monitor the backplane status.

[0079] As shown in Figure 4, Figure 4 illustrates an address allocation method provided in one embodiment of this application. This application also provides an address allocation method based on the aforementioned backplane cascading system, which includes the following steps:

[0080] Step S502: The motherboard transmits the address signal to the first backplane connected to the connector via the connector;

[0081] Step S504: The i-th backplane receives the address signal transmitted by the (i-1)-th backplane through the uplink connector, and shifts and transmits the address signal to the downlink connector of the i-th backplane through the shift register.

[0082] Step S506: The downlink connector of the i-th backplane transmits the shifted address signal to the (i+1)-th backplane.

[0083] In this embodiment, the structure of the backplane cascade system can refer to any of the foregoing embodiments. The address allocation and other processes for external devices on the backplane can be referred to the relevant descriptions in the foregoing embodiments, and will not be repeated here. To enable those skilled in the art to better understand the embodiments of this application, the following specific examples illustrate the embodiments of this application.

[0084] This application provides a computer device including any of the aforementioned backplane cascade systems.

[0085] As shown in Figure 5, an embodiment of this application provides a computer device 50 including at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus 504.

[0086] The memory stores instructions that the computer executes;

[0087] The processor executes computer execution instructions stored in memory, causing the processor to perform various possible implementations of the address allocation method described above.

[0088] This application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement various possible implementations of the address allocation method described above.

[0089] This application provides a computer program product, including a computer program that, when executed by a processor, implements various possible implementations of the address allocation method described above.

[0090] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0091] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0092] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0093] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0094] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0095] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0096] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0097] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0098] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0099] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0100] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0101] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0102] Finally, it should be noted that other embodiments of this application will readily conceive of by those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and alterations may be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A backplane cascade system, characterized in that, include: A motherboard and N backplanes, wherein the motherboard includes a connector and a complex programmable logic device, and the backplanes include an uplink connector, a downlink connector, and a shift register; wherein N>1, and N is a positive integer; The motherboard is connected to the first backplane via the connector, and is used to transmit address signals to the first backplane via the connector; The uplink connector of the i-th backplane is connected to the downlink connector of the i-th backplane, and the uplink connector of the i-th backplane is connected to the shift register of the i-th backplane for shifting the address signal; 1≤i≤N; The downlink connector of the i-th backplane is connected to the uplink connector of the (i+1)-th backplane to transmit the shifted address signal to the (i+1)-th backplane.

2. The backplane cascade system according to claim 1, characterized in that, The shift register of the i-th backplane includes a data pin and a clock signal pin, and the data input pin and the clock signal pin are connected to the uplink connector of the i-th backplane. The data pin receives the address signal transmitted by the complex programmable logic device through the uplink connector; The clock signal pin is connected to the downlink connector of the i-th backplane.

3. The backplane cascade system according to claim 1, characterized in that, The motherboard and the N backplanes are connected via a daisy-chain topology.

4. The backplane cascade system according to claim 2, characterized in that, The backplane also includes at least one external device, which is connected to the shift register. The shift register assigns address information to the external device.

5. The backplane cascade system according to claim 4, characterized in that, The external devices include a first device, a second device, and a third device; The first device, the second device, and the third device are respectively connected to the shift register; The shift register assigns address information to the first device, the second device, and the third device.

6. The backplane cascade system according to claim 5, characterized in that, The data pins of the first device, the second device, and the third device are connected together via an I2C bus and connected to the downlink connector. The clock signal pins of the first device, the second device, and the third device are connected together via an I2C bus and connected to the downlink connector.

7. The backplane cascade system according to claim 4, characterized in that, The motherboard includes a baseboard management controller, which is connected to external devices in each of the backplanes in a daisy-chain topology. The baseboard management controller accesses the external device based on the address assigned to it.

8. The backplane cascade system according to claim 7, characterized in that, The system includes a set of I2C buses. The I2C buses are connected to the uplink connector of the i-th backplane via the downlink connector of the (i-1)-th backplane. Within the i-th backplane, the I2C buses are connected to the downlink connector via the uplink connector.

9. The backplane cascade system according to claim 8, characterized in that, The set of I2C buses includes data transmission lines and clock transmission lines, and the baseboard management controller transmits signals to each backplane through the data transmission lines and the clock transmission lines.

10. An address allocation method, characterized in that, Based on the backplane cascade system according to any one of claims 1-9, the method comprises: The motherboard transmits address signals to the first backplane connected to the connector via the connector. The i-th backplane receives the address signal transmitted by the (i-1)-th backplane through the uplink connector, and shifts and transmits the address signal to the downlink connector of the i-th backplane through the shift register. The downlink connector of the i-th backplane transmits the shifted address signal to the (i+1)-th backplane.

11. A computer device, characterized in that, The backplane cascade system includes any one of claims 1-9.

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