Arithmetic control device and method

The arithmetic control device and method dynamically adjust decimal point and bit division positions to maintain CNN inference accuracy by tracking saturation counts, addressing issues in existing CNN hardware performance due to inappropriate step sizes and bit division, thus improving convolution operations with more bits than input data bits.

WO2026013818A1PCT designated stage Publication Date: 2026-01-15NT T INC
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Patent Information

Application Number
PCT/JP2024/025017
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-07-10
Publication Date
2026-01-15

AI Technical Summary

Technical Problem

Existing convolutional neural network (CNN) hardware faces challenges in maintaining inference accuracy due to inappropriate step sizes and bit division positions during convolution operations, leading to clipping and reduced performance when performing calculations with more bits than the input data bits, especially in fixed-point int-type multiply-and-accumulate circuits.

Method used

An arithmetic control device and method that dynamically adjusts decimal point positions and bit division positions by using counters to track saturation occurrences, allowing for precise convolution operations even when exceeding input data bits, by dividing data into upper and lower parts and adjusting positions based on saturation counts and data distributions.

Benefits of technology

This approach prevents a decrease in inference accuracy by optimizing decimal point and bit division positions, ensuring accurate convolution operations even when using more bits than input data bits, thereby enhancing CNN performance and reducing clipping during accumulation.

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Abstract

When an arithmetic control unit according to the present invention is to extract high-bit data larger than a bit width for output based on a decimal point position, from a cumulative memory of a fixed bit width in which a decimal point position and a division position are set, the cumulative memory storing a cumulative addition result of a multiply-accumulate operation result between input data and a kernel, in an arithmetic circuit that divides data into higher-order data and lower-order data on the basis of the division position and extracts and outputs the higher-order data and the lower-order data, the number of times that each of the higher-order data and the lower-order data exceed an upper limit and fall below a lower limit of a given numerical range is acquired from a counter, and on the basis of the acquired lower limit count for the lower-order side, and the upper limit count for the lower-order side or the upper limit count for the upper-order side, a decimal point position for calculating the next input data is determined and set in the arithmetic circuit, and on the basis of the lower limit count for the higher-order side, a data distribution of the higher-order data and the lower-order data, and a data distribution of the kernel, the division position for calculating the next input data is determined and set in the arithmetic circuit.
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Citation Information

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