Method, communication device, and processing device for transmitting transport block, storage medium, method, communication device, and processing device for receiving transport block, and storage medium

Abstract

This communication device may: determine Co OCBs on the basis of Cd DCBs related to a transport block; determine Cp PCBs on the basis of channel coding for each of the Co OCBs; and perform transmission on the basis of the Cd DCBs and the Cp PCBs. Each of the Co OCBs may include Lo non-consecutive outer code symbol groups (OCSGs) from each of the Cd DCBs, where Lo is an integer greater than 1.

Description

Method for transmitting a transport block, communication device, processing device, and storage medium, and method for receiving a transport block, communication device, processing device, and storage medium

[0001] This specification relates to wireless communication systems.

[0002] Various devices and technologies, such as machine-to-machine (M2M) communication, machine-type communication (MTC), and smartphones and tablet PCs (personal computers) that require high data transmission rates, are emerging and becoming widespread. Consequently, the amount of data required to be processed on cellular networks is rapidly increasing. To meet this rapidly increasing data processing demand, technologies such as carrier aggregation and cognitive radio, which enable more efficient use of frequency bands, are being developed, as well as multi-antenna and multi-BS cooperation technologies to increase the data capacity transmitted within a limited frequency range.

[0003] As more and more communication devices demand greater capacity, the need for enhanced mobile broadband (eMBB) communications is emerging, surpassing legacy radio access technology (RAT). Furthermore, massive machine type communication (mMTC), which connects multiple devices and objects to provide diverse services anytime, anywhere, is a key issue to be considered in next-generation communications.

[0004] Additionally, discussions are underway on communication systems designed to accommodate reliability- and latency-sensitive services and user equipment (UE). The introduction of next-generation wireless access technologies is being discussed, including enhanced mobile broadband (eMBB), mMTC, and ultra-reliable and low latency communication (URLLC).

[0005] Advances in communication technology are driving the need for increasingly larger transport blocks to be transmitted simultaneously. When errors occur during the transmission of large transport blocks, efficient methods and devices for recovering from transmission errors are required.

[0006] The technical tasks to be achieved by this specification are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art related to this specification from the detailed description below.

[0007] In one aspect of the present specification, a method is provided for a communication device to transmit a transport block in a wireless communication system. The method comprises: C based on the transport block d Obtaining data code blocks (DCBs); the C d C from the dog DCBs o Determine the outer code blocks (OCBs) of the C o Determine the outer parity bits by applying channel coding to each of the dog OCBs; C based on the outer parity bits p Determine the parity code blocks (PCBs); the C d Dog DCBs and the above C p Add internal parity bits to each of the dog PCBs (C d +Cp ) determines the parity additional CBs; and the (C d +C p ) comprises performing a first transmission based on the parity additional CBs, wherein the C o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0008] In another aspect of the present disclosure, a communication device for transmitting a transport block in a wireless communication system is provided. The communication device comprises: at least one transceiver; at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations, the operations comprising: C based on the transport block d Obtaining data code blocks (DCBs); the C d C from the dog DCBs o Determine the outer code blocks (OCBs) of the C o Determine the outer parity bits by applying channel coding to each of the dog OCBs; C based on the outer parity bits p Determine the parity code blocks (PCBs); the C d Dog DCBs and the above C p Add internal parity bits to each of the dog PCBs (C d +C p ) determines the parity additional CBs; and the (C d +C p) comprises performing a first transmission based on the parity additional CBs, wherein the C o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0009] In another aspect of the present disclosure, a processing device is provided. The processing device comprises: at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations, the operations comprising: C based on the transport block d Obtaining data code blocks (DCBs); the C d C from the dog DCBs o Determine the outer code blocks (OCBs) of the C o Determine the outer parity bits by applying channel coding to each of the dog OCBs; C based on the outer parity bits p Determine the parity code blocks (PCBs); the C d Dog DCBs and the above C p Add internal parity bits to each of the dog PCBs (C d +C p ) determines the parity additional CBs; and the (C d +C p ) comprises performing a first transmission based on the parity additional CBs, wherein the C o Each of the dog OCBs is the above C d L from each of the DCBso It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0010] In another aspect of the present specification, a computer-readable storage medium is provided. The storage medium stores at least one program code comprising instructions that, when executed, cause at least one processor to perform operations, the operations comprising: C based on the transport block d Obtaining data code blocks (DCBs); the C d C from the dog DCBs o Determine the outer code blocks (OCBs) of the C o Determine the outer parity bits by applying channel coding to each of the dog OCBs; C based on the outer parity bits p Determine the parity code blocks (PCBs); the C d Dog DCBs and the above C p Add internal parity bits to each of the dog PCBs (C d +C p ) determines the parity additional CBs; and the (C d +C p ) comprises performing a first transmission based on the parity additional CBs, wherein the C o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0011] In another aspect of the present specification, a method is provided for a communication device to receive a transport block in a wireless communication system, the communication device comprising: (C d +C p ) receiving a first transmission associated with parity supplementary code blocks (CB); and said (C d +C p ) determines the transport block based on decoding of the parity additional CBs, and (C d +C p ) Parity appended CBs are Cs to which each internal parity bit is appended. d Dog data code blocks (DCBs) and C p Corresponds to the parity code blocks (PCBs), and the C d The dog DCBs contain bits of the above transport blocks, and the C p The dog PCBs contain external parity bits, and the external parity bits are C o It is obtained through channel coding for outer code blocks (OCBs) of the dogs, and the C o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0012] In another aspect of the present disclosure, a communication device for receiving a transport block in a wireless communication system is provided. The communication device comprises: at least one transceiver; at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations, the operations comprising: (C d +C p ) receiving a first transmission associated with parity supplementary code blocks (CB); and said (C d +C p ) determines the transport block based on decoding of the parity additional CBs, and (C d +C p ) Parity appended CBs are Cs to which each internal parity bit is appended. d Dog data code blocks (DCBs) and C p Corresponds to the parity code blocks (PCBs), and the C d The dog DCBs contain bits of the above transport blocks, and the C p The dog PCBs contain external parity bits, and the external parity bits are C o It is obtained through channel coding for outer code blocks (OCBs) of the dogs, and the C o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0013] In another aspect of the present disclosure, a processing device is provided. The processing device comprises: at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations, the operations comprising: (C d +C p ) receiving a first transmission associated with parity supplementary code blocks (CB); and said (C d +C p ) determines the transport block based on decoding of the parity additional CBs, and (C d +C p ) Parity appended CBs are Cs to which each internal parity bit is appended. d Dog data code blocks (DCBs) and C p Corresponds to the parity code blocks (PCBs), and the C d The dog DCBs contain bits of the above transport blocks, and the C p The dog PCBs contain external parity bits, and the external parity bits are C o It is obtained through channel coding for outer code blocks (OCBs) of the dogs, and the C o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0014] In another aspect of the present disclosure, a computer-readable storage medium is provided. The storage medium stores at least one program code comprising instructions that, when executed, cause at least one processor to perform operations, the operations comprising: (C d +C p ) receiving a first transmission associated with parity supplementary code blocks (CB); and said (C d +C p ) determines the transport block based on decoding of the parity additional CBs, and (C d +C p ) Parity appended CBs are Cs to which each internal parity bit is appended. d Dog data code blocks (DCBs) and C p Corresponds to the parity code blocks (PCBs), and the C d The dog DCBs contain bits of the above transport blocks, and the C p The dog PCBs contain external parity bits, and the external parity bits are C o It is obtained through channel coding for outer code blocks (OCBs) of the dogs, and the C o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0015] In each aspect of this specification, each DCB has K g L containing dog bits g The dog OCSGs can be determined, where K g = K s *L sis. The above L g The last of the dog OCSGs is K f It may contain filler bits, where K f = K g *L g - K d And, K d is the size of the corresponding DCB, and K f is a non-negative integer.

[0016] In each aspect of this specification, the OCSGs of each DCB are of size C o *L o,max It is written in column-first order in the block interleaver, where L o,max = Ceil(L g / C o ), L g is the number of OCSGs in each DCB; and DCBs 0 to C d Each C for -1 d The OCSGs recorded in row o of the dog block interleavers can be extracted to determine OCB o, where 0<=o<=C o It's -1.

[0017] For each aspect of this specification, the OCSG x of OCB o can be determined based on: OCSG [o, x] = OCSG<i, a> = OCSG <FLOOR(x / L o ), o + (x mod L o )C o >, where 0≤o <C o and 0≤x <L o C d , o and x are integers, and OCSG<i, a> is the OCSG a of DCB i, where 0≤i <C d and 0≤a <L g , i and a are integers, and L g is the number of OCSGs in each DCB.

[0018] For each aspect of this specification, each PCB is associated with each OCB.g *C p Among the outer parity symbol groups (OPSG), L o It may contain discontinuous OPSGs, where L g is the number of OPSGs in each PCB.

[0019] In each aspect of this specification, L obtained based on OCB o o *C p Dog OPSGs are size C o *L o,max In C p The dog block interleavers are recorded in row o, where L o,max = Ceil(L g / C o ), L g is the number of OPSGs in each PCB; and the C p Among the block interleavers, OPSGs are extracted in the column-wise priority from the block interleaver for PCB j, and PCB j can be determined, where 0<=j<=C. p It's -1.

[0020] For each aspect of this specification, the OPSG b of PCB j can be determined based on: OPSG<j, b> = OPSG [o, y] = OPSG [b mod C o , jL o + FLOOR(b / C o )], where 0≤j <C p and 0≤b <L g , j and b are integers, OPSG [o, y] is OPSG y generated from OCB o, where 0≤o <C o and 0≤y <L o C p , o and y are integers, and L g is the number of OPSGs in each PCB.

[0021] In each aspect of this specification, each OPSG is K gmay include dog parity bits. The above C o Determining the outer parity bits by applying channel coding to each of the OCBs: K from each OCB g *L o *C p This may include determining the dog parity bits.

[0022] In each aspect of this specification, L o can be determined by: 0≤o <M이면 L o = CEIL{L g / C o} and M≤o <C o This side L o = FLOOR{L g / C o}, where M is L g mod C o and L g is the number of OCSGs in each DCB or the number of OPSGs in each PCB.

[0023] In each aspect of this specification, C o can be determined by: C o = CEIL{K d C d / K o,max} and here here K d is the size of DCB, and K o,max is the maximum size of OCB.

[0024] In each aspect of this specification, K g can be a positive integer multiple of 8.

[0025] The above problem solving methods are only some of the examples of this specification, and various examples reflecting the technical features of this specification can be derived and understood by a person having ordinary knowledge in the relevant technical field based on the detailed description below.

[0026] According to some implementations of this specification, wireless communication signals can be transmitted and received efficiently. Consequently, the overall throughput of a wireless communication system can be increased.

[0027] According to some implementations of this specification, if an error occurs during the transmission of a transport block, it may be possible for the transmitter to retransmit only a small amount of outer code parity so that the receiver can recover only the code blocks that experienced the transmission error.

[0028] Some implementations of this specification allow a receiver to reduce processing time and power consumption by using external code parity to recover only code blocks that have transmission errors.

[0029] The effects according to this specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art related to this specification from the detailed description below.

[0030] To aid in understanding implementations of this specification, the accompanying drawings, which are included as part of the detailed description, provide examples of implementations of this specification and, together with the detailed description, illustrate implementations of this specification:

[0031] Figure 1 illustrates an example of a communication system 1 to which implementations of the present specification are applied;

[0032] FIG. 2 is a block diagram illustrating examples of communication devices capable of performing a method according to the present specification.

[0033] FIG. 3 illustrates another example of a wireless device capable of performing implementation(s) of this specification;

[0034] Figure 4 is the 3rd generation partnership project (3 rd It illustrates an example of a frame structure available in a wireless communication system based on the 3rd Generation Partnership Project (3GPP);

[0035] Figure 5 illustrates a processing process on the transmission side for a transport block (TB);

[0036] Figures 6 and 7 are drawings illustrating a parity check matrix H of a low density parity check (LDPC) code using a bipartite graph;

[0037] Figure 8 is an example of a block diagram for a polar encoder;

[0038] Figures 9 and 10 illustrate transmissions of parity for forward error correction (FEC);

[0039] FIG. 11 illustrates outer code block (OCB)(s) ​​and outer code parity generated according to some implementations of this specification;

[0040] FIG. 12 illustrates some implementations of the present specification that reduce the probability of occurrence of burst errors for code blocks;

[0041] Figures 13 and 14 illustrate implementation examples of an OCB configuration and PCB generation method;

[0042] Figure 15 is an example of an external decoding procedure of a receiver;

[0043] Figure 16 is an example of representing LDPC belief propagation (BP) decoding as a bipartite graph;

[0044] FIG. 17 illustrates a channel encoding process according to some implementations of the present specification;

[0045] Figure 18 illustrates a channel decoding process according to some implementations of the present specification.

[0046] Hereinafter, implementations according to this specification will be described in detail with reference to the attached drawings. The detailed description provided below, together with the attached drawings, is intended to describe exemplary implementations of this specification and is not intended to represent the only possible implementations of this specification. The detailed description below includes specific details to provide a thorough understanding of this specification. However, one of ordinary skill in the art will appreciate that this specification may be practiced without these specific details.

[0047] In some cases, to avoid ambiguity in the concepts of this specification, known structures and devices may be omitted or illustrated in block diagram form focusing on the core functions of each structure and device. Furthermore, identical components are described using the same drawing reference numerals throughout this specification.

[0048] The techniques, devices, and systems described below can be applied to various wireless multiple access systems. Examples of multiple access systems include code division multiple access (CDMA) systems, frequency division multiple access (FDMA) systems, time division multiple access (TDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single carrier frequency division multiple access (SC-FDMA) systems, and multi-carrier frequency division multiple access (MC-FDMA) systems. CDMA can be implemented in wireless technologies such as Universal Terrestrial Radio Access (UTRA) or CDMA2000. TDMA can be implemented in wireless technologies such as Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), and Enhanced Data Rates for GSM Evolution (EDGE) (i.e., GERAN). OFDMA can be implemented in wireless technologies such as IEEE (Institute of Electrical and Electronics Engineers) 802.11 (WiFi), IEEE 802.16 (WiMAX), IEEE 802-20, and E-UTRA (evolved-UTRA). UTRA is part of UMTS (Universal Mobile Telecommunication System), and 3GPP (3rd Generation Partnership Project) LTE (Long Term Evolution) is a part of E-UMTS that uses E-UTRA.3GPP LTE adopts OFDMA for the downlink (DL) and SC-FDMA for the uplink (UL). LTE-A (LTE-advanced) is an evolved form of 3GPP LTE.

[0049] For convenience of explanation, the following description assumes that this specification applies to 3GPP-based communication systems, such as LTE and NR. However, the technical features of this specification are not limited to this. For example, although the detailed description below is based on a mobile communication system corresponding to a 3GPP LTE / NR system, it can also be applied to any other mobile communication system, except for features specific to 3GPP LTE / NR.

[0050] For terms and technologies used in this specification that are not specifically explained, reference may be made to 3GPP-based standard documents, such as 3GPP TS 36.211, 3GPP TS 36.212, 3GPP TS 36.213, 3GPP TS 36.321, 3GPP TS 36.300 and 3GPP TS 36.331, 3GPP TS 37.213, 3GPP TS 38.211, 3GPP TS 38.212, 3GPP TS 38.213, 3GPP TS 38.214, 3GPP TS 38.300, 3GPP TS 38.331, etc.

[0051] In the examples of this specification described below, the expression "assumes" that a device "assumes" that the entity transmitting the channel transmits the channel in a manner consistent with the "assume." The entity receiving the channel may mean that, under the assumption that the channel was transmitted in a manner consistent with the "assume," the entity receiving the channel receives or decodes the channel in a manner consistent with the "assume."

[0052] In this specification, UE may be fixed or mobile, and includes various devices that communicate with a BS (base station) to transmit and / or receive user data and / or various control information. UE may be called (Terminal Equipment), MS (Mobile Station), MT (Mobile Terminal), UT (User Terminal), SS (Subscribe Station), wireless device, PDA (Personal Digital Assistant), wireless modem, handheld device, etc. In addition, in this specification, BS generally refers to a fixed station that communicates with UE and / or other BS, and exchanges various data and control information with UE and other BS. BS may be called by other terms such as ABS (Advanced Base Station), NB (Node-B), eNB (evolved-NodeB), BTS (Base Transceiver System), Access Point, PS (Processing Server), etc. In particular, the BS in UTRAN is called a Node-B, the BS in E-UTRAN is called an eNB, and the BS in a new radio access technology network is called a gNB. For convenience of explanation, BSs are collectively referred to as BSs below, regardless of the type or version of communication technology.

[0053] In this specification, a node refers to a fixed point that can transmit / receive radio signals by communicating with a UE. Various types of BSs can be used as nodes regardless of their names. For example, BSs, NBs, eNBs, pico-cell eNBs (PeNBs), home eNBs (HeNBs), relays, and repeaters can be nodes. Furthermore, a node may not be a BS. For example, it can be a radio remote head (RRH) or a radio remote unit (RRU). RRHs, RRUs, etc. generally have a lower power level than the BS. Since an RRH or RRU (hereinafter referred to as RRH / RRU) is generally connected to a BS via a dedicated line such as an optical cable, cooperative communication between an RRH / RRU and a BS can be performed more smoothly than cooperative communication between BSs that are generally connected via a wireless line. Each node is equipped with at least one antenna. The antenna may be a physical antenna, an antenna port, a virtual antenna, or an antenna group. A node is also called a point.

[0054] In this specification, a cell refers to a certain geographical area where one or more nodes provide communication services. Therefore, in this specification, communicating with a specific cell may mean communicating with a BS or node that provides communication services to the specific cell. In addition, the downlink / uplink signal of a specific cell refers to a downlink / uplink signal from / to a BS or node that provides communication services to the specific cell. A cell that provides uplink / downlink communication services to a UE is specifically referred to as a serving cell. In addition, the channel state / quality of a specific cell refers to the channel state / quality of a channel or communication link formed between a BS or node that provides communication services to the specific cell and the UE. In a 3GPP-based communication system, a UE can measure a downlink channel state from a specific node using CRS (Cell-specific Reference Signal) resources transmitted by antenna port(s) of the specific node on CRS resources allocated to the specific node and / or CSI-RS (Channel State Information Reference Signal) resources transmitted.

[0055] Meanwhile, 3GPP-based communication systems use the concept of cells to manage radio resources, and cells associated with radio resources are distinguished from cells in geographical areas.

[0056] A "cell" in a geographical area can be understood as the coverage over which a node can provide a service using a carrier, and a "cell" in a radio resource is associated with a bandwidth (BW), which is a frequency range configured by the carrier. Since downlink coverage, which is the range over which a node can transmit a valid signal, and uplink coverage, which is the range over which a node can receive a valid signal from a UE, depend on the carrier carrying the signal, the coverage of a node is also associated with the coverage of the "cell" of the radio resource used by the node. Therefore, the term "cell" can sometimes be used to mean the coverage of a service provided by a node, sometimes a radio resource, and sometimes the range over which a signal using the radio resource can reach with a valid intensity.

[0057] Meanwhile, the 3GPP communication standard uses the concept of a cell to manage radio resources. A "cell" associated with radio resources is defined as a combination of downlink resources (DL resources) and uplink resources (UL resources), i.e., a combination of a DL component carrier (CC) and an UL CC. A cell can be configured with DL resources alone or a combination of DL resources and UL resources. If carrier aggregation is supported, the linkage between the carrier frequency of the DL resources (or DL ​​CC) and the carrier frequency of the UL resources (or UL CC) can be indicated by system information. For example, the combination of DL resources and UL resources can be indicated by a System Information Block Type 2 (SIB2) linkage. Here, the carrier frequency can be the same as or different from the center frequency of each cell or CC. When carrier aggregation (CA) is established, the UE has only one radio resource control (RRC) connection with the network. One serving cell provides non-access stratum (NAS) mobility information during RRC connection establishment / re-establishment / handover, and one serving cell provides security input during RRC connection re-establishment / handover. Such a cell is called a primary cell (Pcell). A Pcell is a cell operating on the primary frequency where the UE performs initial connection establishment procedures or initiates connection re-establishment procedures.Depending on the UE capability, secondary cells (Scells) can be configured to form a set of serving cells together with Pcells. An Scell ​​can be configured after RRC (Radio Resource Control) connection establishment, and is a cell that provides additional radio resources in addition to the resources of a special cell (SpCell). The carrier corresponding to a Pcell in downlink is called a downlink primary CC (DL PCC), and the carrier corresponding to a Pcell in uplink is called an UL primary CC (DL PCC). The carrier corresponding to an Scell ​​in downlink is called a DL secondary CC (DL SCC), and the carrier corresponding to the Scell ​​in uplink is called an UL secondary CC (UL SCC).

[0058] For dual connectivity (DC) operation, the term SpCell refers to a Pcell of a master cell group (MCG) or a Pcell of a secondary cell group (SCG). A SpCell supports PUCCH transmission and contention-based random access and is always activated. An MCG is a group of serving cells associated with a master node (e.g., BS) and consists of a SpCell (Pcell) and optionally one or more Scells. For a UE configured for DC, an SCG is a subset of serving cells associated with a secondary node and consists of a PSCell and zero or more Scells. A PSCell is the primary Scell ​​of an SCG. For a UE in RRC_CONNECTED state that is not configured for CA or DC, there is only one serving cell consisting solely of Pcells. For a UE in RRC_CONNECTED state configured as CA or DC, the term serving cells refers to the set of cells consisting of SpCell(s) and all Scell(s). In DC, two medium access control (MAC) entities are configured in the UE: one for the MCG and one for the SCG.

[0059] For a UE where CA is set and DC is not set, a Pcell PUCCH group consisting of a Pcell and zero or more Scells and a Scell ​​PUCCH group consisting of only Scell(s) may be set. In the case of an Scell, an Scell ​​(hereinafter referred to as a PUCCH cell) on which a PUCCH associated with the cell is transmitted may be set. An Scell ​​indicated as a PUCCH Scell ​​belongs to an Scell ​​PUCCH group, and PUCCH transmission of the relevant UCI is performed on the PUCCH Scell, and an Scell ​​where a PUCCH Scell ​​is not indicated or is a Pcell indicated as a cell for PUCCH transmission, belongs to a Pcell PUCCH group, and PUCCH transmission of the relevant UCI is performed on the Pcell.

[0060] In a wireless communication system, a UE receives information from a base station (BS) via the downlink (DL), and the UE transmits information to the base station via the uplink (UL). The information transmitted and / or received by the BS and UE includes data and various control information, and various physical channels exist depending on the type and purpose of the information they transmit and / or receive.

[0061] 3GPP-based communication standards define downlink physical channels corresponding to resource elements that carry information originating from higher layers, and downlink physical signals corresponding to resource elements that are used by the physical layer but do not carry information originating from higher layers. For example, the physical downlink shared channel (PDSCH), physical broadcast channel (PBCH), and physical downlink control channel (PDCCH) are defined as downlink physical channels, and reference signals and synchronization signals are defined as downlink physical signals. A reference signal (RS), also referred to as a pilot, refers to a signal with a predefined special waveform that is known to the BS and UE. For example, the demodulation reference signal (DMRS) and the channel state information RS (CSI-RS) are defined as downlink reference signals. 3GPP-based communication standards define uplink physical channels corresponding to resource elements that carry information originating from higher layers, and uplink physical signals corresponding to resource elements that are used by the physical layer but do not carry information originating from higher layers.For example, a physical uplink shared channel (PUSCH), a physical uplink control channel (PUCCH), and a physical random access channel (PRACH) are defined as uplink physical channels, and a demodulation reference signal (DMRS) for uplink control / data signals and a sounding reference signal (SRS) used for uplink channel measurement are defined.

[0062] In this specification, the Physical Downlink Control CHannel (PDCCH) refers to a set of time-frequency resources (e.g., resource elements (REs)) that carry Downlink Control Information (DCI), and the Physical Downlink Shared CHannel (PDSCH) refers to a set of time-frequency resources that carry downlink data. In addition, the Physical Uplink Control CHannel (PUCCH), Physical Uplink Shared CHannel (PUSCH), and Physical Random Access CHannel (PRACH) refer to sets of time-frequency resources that carry Uplink Control Information (UCI), uplink data, and random access signals, respectively. Hereinafter, the expression that a user equipment transmits / receives a PUCCH / PUSCH / PRACH is used with the same meaning as transmitting / receiving uplink control information / uplink data / random access signal on or through the PUCCH / PUSCH / PUCCH / PRACH, respectively. In addition, the expression that a BS transmits / receives a PBCH / PDCCH / PDSCH is used with the same meaning as transmitting broadcast information / downlink control information / downlink data on or through the PBCH / PDCCH / PDSCH, respectively.

[0063] In this specification, radio resources (e.g., time-frequency resources) scheduled or configured by the BS to the UE for transmission or reception of PUCCH / PUSCH / PDSCH are also referred to as PUCCH / PUSCH / PDSCH resources.

[0064] Since the communication device receives SSB, DMRS, CSI-RS, PBCH, PDCCH, PDSCH, PUSCH, and / or PUCCH in the form of radio signals on a cell, it cannot selectively receive through an RF receiver only radio signals including only a specific physical channel or only a specific physical signal, or selectively receive through an RF receiver only radio signals excluding only a specific physical channel or only a physical signal. In actual operation, the communication device first receives radio signals on a cell through an RF receiver, converts the radio signals, which are RF band signals, into baseband signals, and decodes physical signals and / or physical channels within the baseband signals using one or more processors. Thus, in some implementations of the present specification, not receiving a physical signal and / or a physical channel may not actually mean that the communication device does not receive wireless signals containing the physical signal and / or physical channel at all, but rather that it does not attempt to recover the physical signal and / or physical channel from the wireless signals, e.g., does not attempt to decode the physical signal and / or the physical channel.

[0065] As more and more communication devices demand greater communication capacity, the need for improved mobile broadband communication over existing radio access technology (RAT) is emerging. Furthermore, massive MTC, which connects numerous devices and objects to provide diverse services anytime, anywhere, is also a key issue to be considered in next-generation communications. Furthermore, communication system design that considers reliability and latency-sensitive services / UEs is being discussed. The introduction of next-generation RATs that take advanced mobile broadband communication, massive MTC, and URLLC (Ultra-Reliable and Low Latency Communication) into account is currently under discussion. 3GPP is currently conducting studies on next-generation mobile communication systems beyond EPC. For convenience, this technology is referred to as new RAT (NR) or 5G RAT, and a system that uses or supports NR is referred to as an NR system.

[0066] FIG. 1 illustrates an example of a communication system 1 to which implementations of the present specification are applied. Referring to FIG. 1, the communication system (1) applied to the present specification includes a wireless device, a BS, and a network. Here, the wireless device refers to a device that performs communication using a wireless access technology (e.g., 5G NR (New RAT), LTE (e.g., E-UTRA)) and may be referred to as a communication / wireless / 5G device. Although not limited thereto, the wireless device may include a robot (100a), a vehicle (100b-1, 100b-2), an XR (eXtended Reality) device (100c), a hand-held device (100d), a home appliance (100e), an IoT (Internet of Things) device (100f), and an AI device / server (400). For example, the vehicle may include a vehicle equipped with a wireless communication function, an autonomous vehicle, a vehicle capable of performing vehicle-to-vehicle communication, etc. Here, the vehicle may include an Unmanned Aerial Vehicle (UAV) (e.g., a drone). XR devices include AR (Augmented Reality) / VR (Virtual Reality) / MR (Mixed Reality) devices, and may be implemented in the form of a Head-Mounted Device (HMD), a Head-Up Display (HUD) installed in a vehicle, a television, a smartphone, a computer, a wearable device, a home appliance, digital signage, a vehicle, a robot, etc. Mobile devices may include a smartphone, a smart pad, a wearable device (e.g., a smart watch, smart glasses), a computer (e.g., a laptop, etc.), etc. Home appliances may include a TV, a refrigerator, a washing machine, etc. IoT devices may include sensors, smart meters, etc. For example, a BS or network may also be implemented as a wireless device, and a specific wireless device may act as a BS / network node to other wireless devices.

[0067] Wireless devices (100a to 100f) can be connected to a network (300) via a BS (200). Artificial Intelligence (AI) technology can be applied to the wireless devices (100a to 100f), and the wireless devices (100a to 100f) can be connected to an AI server (400) via a network (300). The network (300) can be configured using a 3G network, a 4G (e.g., LTE) network, a 5G (e.g., NR) network, etc. The wireless devices (100a to 100f) can communicate with each other via the BS (200) / network (300), but can also communicate directly (e.g., sidelink communication) without going through the BS / network. For example, vehicles (100b-1, 100b-2) can communicate directly (e.g., V2V (Vehicle to Vehicle) / V2X (Vehicle to Everything) communication). In addition, IoT devices (e.g., sensors) can communicate directly with other IoT devices (e.g., sensors) or other wireless devices (100a to 100f).

[0068] Wireless communication / connection (150a, 150b) can be performed between wireless devices (100a~100f) / BS (200) - BS (200) / wireless devices (100a~100f). Here, the wireless communication / connection can be performed through various wireless access technologies (e.g., 5G NR) for uplink / downlink communication (150a) and sidelink communication (150b) (or D2D communication). Through the wireless communication / connection (150a, 150b), the wireless device and the BS / wireless device can transmit / receive wireless signals to / from each other. To this end, at least some of various configuration information setting processes for transmitting / receiving wireless signals, various signal processing processes (e.g., channel encoding / decoding, modulation / demodulation, resource mapping / demapping, etc.), and resource allocation processes can be performed based on various proposals of this specification.

[0069] FIG. 2 is a block diagram illustrating examples of communication devices capable of performing a method according to the present specification. Referring to FIG. 2, a first wireless device (100) and a second wireless device (200) can transmit and / or receive wireless signals via various wireless access technologies (e.g., LTE, NR). Here, {the first wireless device (100), the second wireless device (200)} can correspond to {the wireless device (100x), the BS (200)} and / or {the wireless device (100x), the wireless device (100x)} of FIG. 1.

[0070] A first wireless device (100) includes one or more processors (102) and one or more memories (104), and may further include one or more transceivers (106) and / or one or more antennas (108). The processor (102) controls the memories (104) and / or the transceivers (106), and may be configured to implement functions, procedures, and / or methods described / suggested below. For example, the processor (102) may process information in the memory (104) to generate first information / signals, and then transmit a wireless signal including the first information / signals via the transceivers (106). In addition, the processor (102) may receive a wireless signal including second information / signals via the transceivers (106), and then store information obtained from signal processing of the second information / signals in the memory (104). The memory (104) may be connected to the processor (102) and may store various information related to the operation of the processor (102). For example, the memory (104) may perform some or all of the processes controlled by the processor (102), or may store software code including commands for performing the procedures and / or methods described / proposed below. Here, the processor (102) and the memory (104) may be part of a communication modem / circuit / chip designed to implement wireless communication technology (e.g., LTE, NR). The transceiver (106) may be connected to the processor (102) and may transmit and / or receive wireless signals via one or more antennas (108). The transceiver (106) may include a transmitter and / or a receiver. The transceiver (106) may be used interchangeably with an RF (Radio Frequency) unit. In this specification, a wireless device may also mean a communication modem / circuit / chip.

[0071] The second wireless device (200) includes one or more processors (202), one or more memories (204), and may further include one or more transceivers (206) and / or one or more antennas (208). The processor (202) controls the memories (204) and / or the transceivers (206), and may be configured to implement the functions, procedures, and / or methods described / suggested below. For example, the processor (202) may process information in the memory (204) to generate third information / signals, and then transmit a wireless signal including the third information / signals via the transceivers (206). In addition, the processor (202) may receive a wireless signal including fourth information / signals via the transceivers (206), and then store information obtained from signal processing of the fourth information / signals in the memory (204). The memory (204) may be connected to the processor (202) and may store various information related to the operation of the processor (202). For example, the memory (204) may perform some or all of the processes controlled by the processor (202), or may store software code including commands for performing the procedures and / or methods described / proposed below. Here, the processor (202) and the memory (204) may be part of a communication modem / circuit / chip designed to implement wireless communication technology (e.g., LTE, NR). The transceiver (206) may be connected to the processor (202) and may transmit and / or receive wireless signals via one or more antennas (208). The transceiver (206) may include a transmitter and / or a receiver. The transceiver (206) may be used interchangeably with an RF unit. In this specification, a wireless device may also mean a communication modem / circuit / chip.

[0072] The wireless communication technology implemented in the wireless device (100, 200) of the present specification may include not only LTE, NR, and 6G, but also Narrowband Internet of Things for low-power communication. At this time, for example, NB-IoT technology may be an example of LPWAN (Low Power Wide Area Network) technology, and may be implemented with standards such as LTE Cat NB1 and / or LTE Cat NB2, and is not limited to the above-described names. Additionally or alternatively, the wireless communication technology implemented in the wireless device (XXX, YYY) of the present specification may perform communication based on LTE-M technology. At this time, for example, LTE-M technology may be an example of LPWAN technology, and may be called by various names such as eMTC (enhanced Machine Type Communication). For example, LTE-M technology can be implemented by at least one of various standards such as 1) LTE CAT 0, 2) LTE Cat M1, 3) LTE Cat M2, 4) LTE non-BL (non-Bandwidth Limited), 5) LTE-MTC, 6) LTE Machine Type Communication, and / or 7) LTE M, and is not limited to the above-described names. Additionally or alternatively, the wireless communication technology implemented in the wireless device (XXX, YYY) of the present specification can include at least one of ZigBee, Bluetooth, and Low Power Wide Area Network (LPWAN) considering low-power communication, and is not limited to the above-described names. For example, ZigBee technology can create personal area networks (PAN) related to small / low-power digital communication based on various standards such as IEEE 802.15.4, and can be called by various names.

[0073] Hereinafter, hardware elements of the wireless device (100, 200) will be described in more detail. Although not limited thereto, one or more protocol layers may be implemented by one or more processors (102, 202). For example, one or more processors (102, 202) may implement one or more layers (e.g., functional layers such as a physical (PHY) layer, a medium access control (MAC) layer, a radio link control (RLC) layer, a packet data convergence protocol (PDCP) layer, a radio resource control (RRC) layer, and a service data adaptation protocol (SDAP) layer). One or more processors (102, 202) may generate one or more protocol data units (PDUs) and / or one or more service data units (SDUs) according to the functions, procedures, proposals, and / or methods disclosed in this document. One or more processors (102, 202) may generate messages, control information, data or information according to the functions, procedures, proposals and / or methods disclosed herein. One or more processors (102, 202) may generate signals (e.g., baseband signals) including PDUs, SDUs, messages, control information, data or information according to the functions, procedures, proposals and / or methods disclosed herein and provide the signals to one or more transceivers (106, 206). One or more processors (102, 202) may receive signals (e.g., baseband signals) from one or more transceivers (106, 206) and obtain PDUs, SDUs, messages, control information, data or information according to the functions, procedures, proposals and / or methods disclosed herein.

[0074] One or more processors (102, 202) may be referred to as a controller, a microcontroller, a microprocessor, or a microcomputer. One or more processors (102, 202) may be implemented by hardware, firmware, software, or a combination thereof. For example, one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), one or more Digital Signal Processing Devices (DSPDs), one or more Programmable Logic Devices (PLDs), or one or more Field Programmable Gate Arrays (FPGAs) may be included in one or more processors (102, 202). The functions, procedures, proposals, and / or methods disclosed in this document may be implemented using firmware or software, and the firmware or software may be implemented to include modules, procedures, functions, etc. Firmware or software configured to perform the functions, procedures, suggestions and / or methods disclosed in this document may be included in one or more processors (102, 202) or stored in one or more memories (104, 204) and executed by one or more processors (102, 202). The functions, procedures, suggestions and / or methods disclosed in this document may be implemented using firmware or software in the form of codes, instructions and / or sets of instructions.

[0075] One or more memories (104, 204) may be coupled to one or more processors (102, 202) and may store various forms of data, signals, messages, information, programs, codes, instructions, and / or commands. The one or more memories (104, 204) may be configured as ROM, RAM, EPROM, flash memory, hard drives, registers, cache memory, computer-readable storage media, and / or combinations thereof. The one or more memories (104, 204) may be located internally and / or externally to the one or more processors (102, 202). Additionally, the one or more memories (104, 204) may be coupled to the one or more processors (102, 202) via various technologies, such as wired or wireless connections.

[0076] One or more transceivers (106, 206) can transmit user data, control information, wireless signals / channels, etc., as mentioned in the methods and / or flowcharts of this document, to one or more other devices. One or more transceivers (106, 206) can receive user data, control information, wireless signals / channels, etc., as mentioned in the functions, procedures, proposals, methods and / or flowcharts of this document, from one or more other devices. For example, one or more transceivers (106, 206) can be coupled to one or more processors (102, 202) and can transmit and / or receive wireless signals. For example, one or more processors (102, 202) can control one or more transceivers (106, 206) to transmit user data, control information, or wireless signals to one or more other devices. Additionally, one or more processors (102, 202) may control one or more transceivers (106, 206) to receive user data, control information, or wireless signals from one or more other devices. Additionally, one or more transceivers (106, 206) may be coupled to one or more antennas (108, 208), and one or more transceivers (106, 206) may be configured to transmit and / or receive user data, control information, wireless signals / channels, or the like, as referred to in the functions, procedures, proposals, methods, and / or operational flowcharts disclosed in this document, via one or more antennas (108, 208). In this document, one or more antennas may be multiple physical antennas or multiple logical antennas (e.g., antenna ports). One or more transceivers (106, 206) may convert received user data, control information, wireless signals / channels, etc. from RF band signals to baseband signals for processing using one or more processors (102, 202).One or more transceivers (106, 206) may convert user data, control information, wireless signals / channels, etc. processed by one or more processors (102, 202) from baseband signals to RF band signals. For this purpose, one or more transceivers (106, 206) may include an (analog) oscillator and / or filter.

[0077] FIG. 3 illustrates another example of a wireless device capable of performing implementation(s) of the present specification. Referring to FIG. 3, the wireless device (100, 200) corresponds to the wireless device (100, 200) of FIG. 2 and may be composed of various elements, components, units, and / or modules. For example, the wireless device (100, 200) may include a communication unit (110), a control unit (120), a memory unit (130), and an additional component (140). The communication unit may include a communication circuit (112) and a transceiver(s) (114). For example, the communication circuit (112) may include one or more processors (102, 202) and / or one or more memories (104, 204) of FIG. 2. For example, the transceiver(s) (114) may include one or more transceivers (106, 206) and / or one or more antennas (108, 208) of FIG. 2. The control unit (120) is electrically connected to the communication unit (110), the memory unit (130), and the additional components (140) and controls the overall operation of the wireless device. For example, the control unit (120) may control the electrical / mechanical operation of the wireless device based on the program / code / command / information stored in the memory unit (130). In addition, the control unit (120) may transmit information stored in the memory unit (130) to an external device (e.g., another communication device) via a wireless / wired interface through the communication unit (110), or store information received from an external device (e.g., another communication device) via a wireless / wired interface in the memory unit (130).

[0078] The additional configuration (140) may be configured in various ways depending on the type of the wireless device. For example, the additional configuration (140) may include at least one of a power unit / battery, an input / output (I / O) unit, a driving unit, and a computing unit. Although not limited thereto, the wireless device may be implemented in the form of a robot (Fig. 1, 100a), a vehicle (Fig. 1, 100b-1, 100b-2), an XR device (Fig. 1, 100c), a portable device (Fig. 1, 100d), a home appliance (Fig. 1, 100e), an IoT device (Fig. 1, 100f), a UE for digital broadcasting, a hologram device, a public safety device, an MTC device, a medical device, a fintech device (or a financial device), a security device, a climate / environmental device, an AI server / device (Fig. 1, 400), a BS (Fig. 1, 200), a network node, etc. Wireless devices may be mobile or stationary depending on the use / service.

[0079] In FIG. 3, various elements, components, units / parts, and / or modules within the wireless device (100, 200) may be interconnected entirely via a wired interface, or at least some may be wirelessly connected via a communication unit (110). For example, within the wireless device (100, 200), the control unit (120) and the communication unit (110) may be wired, and the control unit (120) and a first unit (e.g., 130, 140) may be wirelessly connected via the communication unit (110). In addition, each element, component, unit / part, and / or module within the wireless device (100, 200) may further include one or more elements. For example, the control unit (120) may be configured with one or more processor sets. For example, the control unit (120) may be configured as a set of a communication control processor, an application processor, an electronic control unit (ECU), a graphics processing processor, a memory control processor, etc. As another example, the memory unit (130) may be configured as a random access memory (RAM), a dynamic RAM (DRAM), a read only memory (ROM), a flash memory, a volatile memory, a non-volatile memory, and / or a combination thereof.

[0080] In this specification, at least one memory (e.g., 104 or 204) can store instructions or programs that, when executed, cause at least one processor operably connected to the at least one memory to perform operations according to some embodiments or implementations of the present specification.

[0081] In this specification, a computer-readable (non-volatile) storage medium can store at least one instruction or computer program, which when executed by at least one processor causes the at least one processor to perform operations according to some embodiments or implementations of this specification.

[0082] In this specification, a processing device or apparatus may include at least one processor and at least one computer memory operatively connected to the at least one processor. The at least one computer memory may store instructions or programs, which, when executed, cause at least one processor operatively connected to the at least one memory to perform operations according to some embodiments or implementations of the present specification.

[0083] In this specification, a computer program may be stored in at least one computer-readable (non-volatile) storage medium and may include program code that, when executed, performs operations according to some implementations of the present specification or causes at least one processor to perform operations according to some implementations of the present specification. The computer program may be provided in the form of a computer program product. The computer program product may include at least one computer-readable (non-volatile) storage medium.

[0084] A communications device of the present specification comprises at least one processor; and at least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations according to the example(s) of the present specification described below.

[0085] Figure 4 illustrates an example of a frame structure available in a 3GPP-based wireless communication system.

[0086] The structure of the frame in Fig. 4 is merely an example, and the number of subframes, the number of slots, and the number of symbols in the frame can be varied. In an NR system, OFDM numerology (e.g., subcarrier spacing (SCS)) may be set differently between multiple cells aggregated to a single UE. Accordingly, the (absolute time) duration of a time resource (e.g., a subframe, a slot, or a transmission time interval (TTI)) consisting of the same number of symbols may be set differently between the aggregated cells. Here, the symbol may include an OFDM symbol (or a cyclic prefix - orthogonal frequency division multiplexing (CP-OFDM) symbol), an SC-FDMA symbol (or a discrete Fourier transform-spread-OFDM (DFT-s-OFDM) symbol). In this specification, the terms symbol, OFDM-based symbol, OFDM symbol, CP-OFDM symbol, and DFT-s-OFDM symbols are interchangeable.

[0087] Referring to Figure 4, in the NR system, uplink and downlink transmissions are organized into frames. Each frame is T f = (△f max *N f / 100)*T c = 10 ms duration, divided into two half-frames of 5 ms each. Here, T is the basic time unit for NR. c = 1 / (△fmax *N f ) and △f max = 480*10 3 Hz, and N f =4096. For reference, T is the basic time unit for LTE. s = 1 / (△f ref *N f,ref ) and △f ref = 15*10 3 Hz, and N f,ref =2048. T c Wow T s is a constant κ = T s / T c = 64 relationship. Each half-frame consists of 5 subframes, and the duration of a single subframe (SF) is T sf is 1ms. Subframes are further divided into slots, and the number of slots in a subframe depends on the subcarrier spacing. Each slot consists of 14 or 12 OFDM symbols based on the cyclic prefix. For a normal cyclic prefix (CP), each slot consists of 14 OFDM symbols, and for an extended CP, each slot consists of 12 OFDM symbols. The numerology is exponentially scalable with a subcarrier spacing △f = 2. u *Depends on 15 kHz. The following table shows the subcarrier spacing for regular CP △f = 2. u *Number of OFDM symbols per slot at 15 kHz (N) slot symb ), number of slots per frame (N frame,u slot ) and the number of slots per subframe (N subframe,u slot ) is shown.

[0088]

[0089] The following table shows the subcarrier spacing for extended CP △f = 2.u *Indicates the number of OFDM symbols per slot, the number of slots per frame, and the number of slots per subframe at 15 kHz.

[0090]

[0091] For a subcarrier spacing setting u, slots are n in increasing order within a subframe. u s ∈ {0, ..., nsubframe,u slot - 1} and n in increasing order within the frame u s,f ∈ {0, ..., n frame,u slot - Numbered as 1}.

[0092] A slot contains multiple symbols (e.g., 14 or 12) in the time domain. For each numeral (e.g., subcarrier spacing) and carrier, a common resource block (CRB) N is indicated by higher-layer signaling (e.g., radio resource control (RRC) signaling). start,u grid Starting from,N size,u grid,x *N RB sc Dog subcarriers and N subframe,u symb A resource grid of OFDM symbols is defined, where N size,u grid,x is the number of resource blocks (RBs) in the resource grid, and the subscript x is DL for downlink and UL for uplink. N RB sc is the number of subcarriers per RB, and in 3GPP-based wireless communication systems, N RB scis typically 12. For a given antenna port p, subcarrier spacing configuration u, and transmission direction (DL or UL), there is one resource grid. The carrier bandwidth N for subcarrier spacing configuration u size,u grid is given to the UE by higher layer parameters (e.g., RRC parameters) from the network. Each element in the resource grid for antenna port p and subcarrier spacing configuration u is called a resource element (RE), and one complex symbol can be mapped to each RE. Each RE in the resource grid is uniquely identified by an index k in the frequency domain and an index l indicating the symbol position relative to a reference point in the time domain. In an NR system, an RB is defined by 12 consecutive subcarriers in the frequency domain. In an NR system, RBs can be classified into common resource blocks (CRBs) and physical resource blocks (PRBs). CRBs are numbered upwards from 0 in the frequency domain for the subcarrier spacing configuration u. The center of subcarrier 0 of CRB 0 for the subcarrier spacing configuration u coincides with 'Point A', which is a common reference point for the resource block grids. PRBs for subcarrier spacing u are defined within the bandwidth part (BWP) and range from 0 to N. size,u BWP,i -1, where i is the number of the bandwidth part. Common resource block n u CRB and bandwidth part i within physical resource block n PRB The relationship between the two is as follows: n u PRB = n u CRB +N start,u BWP,i , here N start,u BWP,iis a common resource block (BRB) whose bandwidth part starts relative to CRB 0. A BWP comprises multiple consecutive RBs in the frequency domain. For example, a BWP may be a given numeral u within a BWP i on a given carrier. i A subset of contiguous CRBs defined for a carrier. A carrier may include up to N (e.g., 5) BWPs. A UE may be configured to have one or more BWPs on a given component carrier. Data communication is performed through the activated BWPs, and only a predetermined number (e.g., 1) of BWPs configured for the UE may be activated on the carrier.

[0093] A UE configured with carrier aggregation may be configured to use one or more cells. If the UE is configured to have multiple serving cells, the UE may be configured to have one or more cell groups. The UE may be configured to have multiple cell groups associated with different BSs. Alternatively, the UE may be configured to have multiple cell groups associated with a single BS. Each cell group of the UE consists of one or more serving cells, and each cell group includes a single PUCCH cell configured with PUCCH resources. The PUCCH cell may be a Pcell or an Scell ​​configured as a PUCCH cell among the Scells of the corresponding cell group. Each serving cell of the UE belongs to one of the cell groups of the UE and does not belong to multiple cell groups.

[0094] Figure 5 illustrates a processing process on the transmission side for a transport block (TB).

[0095] To enable the receiver to correct errors encountered in wireless signals over the wireless channel, the transmitter encodes the information it sends using a forward error correction code before transmitting it. The receiver demodulates the received signal and then decodes the error correction code to restore the transmitted information. This decoding process corrects errors in the received signal caused by the wireless channel.

[0096] Data arrives at the coding block in the form of up to two transport blocks per TTI per DL / UL cell. The following coding steps can be applied to each transport block in a DL / UL cell:

[0097] - Add a cyclic redundancy check (CRC) to the transport block;

[0098] - Code block segmentation and code block CRC attachment;

[0099] - Channel coding;

[0100] - Rate matching;

[0101] - Code block concatenation.

[0102] In actual communication systems, for ease of implementation, transport blocks larger than a certain size are divided into several smaller data blocks for encoding. These smaller data blocks are called code blocks. While code blocks typically have the same size, due to the size limitations of the channel encoder's internal interleaver, one code block among multiple code blocks may have a different size. After error-correcting encoding is performed on code blocks of a given interleaver size, interleaving is performed to reduce the impact of burst errors that occur during transmission over a wireless channel. These blocks are then mapped to actual radio resources and transmitted. Since the amount of radio resources used in actual transmission is constant, rate matching must be performed on the encoded code blocks to accommodate this. Typically, rate matching is achieved through puncturing or repetition. For example, if the amount of wireless resources, i.e., the number of transmission bits that can be transmitted by the wireless resources, is M, and the coded bit sequence, i.e., the number of output bits of the encoder, is N, then if M and N are different, rate matching is performed to adjust the length of the coded bit sequence to match M. If M>N, all or part of the bits of the coded bit sequence are repeated so that the length of the rate-matched sequence becomes equal to M. M <N이면, 레이트 매칭된 시퀀스의 길이가 M과 같아지도록, 코딩된 비트 시퀀스의 비트들 중 일부가 펑처링되며, 펑처링된 비트는 전송에서 제외된다.

[0103] That is, in a wireless communication system, the transmitting end encodes data to be transmitted using channel coding having a specific code rate, and then adjusts the code rate of the data to be transmitted through a rate matching process consisting of puncturing and repetition.

[0104] The output bit sequence after rate matching and code block concatenation is modulated into modulation symbols through a modulator according to a modulation scheme. The modulation symbols are mapped to radio resources allocated by the base station and transmitted to the receiver through the radio resources. The decoding process of the channel code is the reverse process of the encoding process, and a decoder corresponding to each encoder of the transmitter is used in the decoding process performed at the receiver. The receiver performs decoding for each code block (CB), then constructs a TB, and finally checks whether the TB CRC passes or fails. In the current LTE / LTE-A system, the CB CRC is used for fast decoding termination. For example, if the CB CRC fails, the receiver can generate a NACK without decoding other CBs.

[0105] There are various types of error-correcting codes. For example, turbo codes consist of a recursive systematic convolution encoder and an interleaver. In practical implementations of turbo codes, an interleaver facilitates parallel decoding, and one such interleaver is the quadratic polynomial permutation (QPP). This QPP interleaver is known to maintain good performance only for a certain data block size. Turbo code performance is known to improve as the data block size increases. However, in actual communication systems, for ease of implementation, data blocks larger than a certain size are divided into several smaller data blocks for encoding. These smaller data blocks are called code blocks. While code blocks typically have the same size, due to the size limitations of the QPP interleaver, one code block among multiple code blocks may have a different size.

[0106] Among error-correcting codes, the low-density parity check (LDPC) code is a linear block code with low density because most of the elements of the parity check matrix H are 0. It was proposed by Gallager in 1962. The LDPC code was so complex that it was impossible to implement with the technology available at the time of its proposal, so it was forgotten until it was rediscovered in 1995 and its excellent performance was proven, and since then, active research on it has been conducted (References: [1] Robert G. Gallager, "Low-Density Parity-Check Codes", The MIT Press, September 15, 1963. [2] D. J. C. McCay, Good error-correcting codes based on very sparse matrices, IEEE Trans. Inform. Theory, IT-45, pp.399-431(1999)). Currently, LDPC codes are mainly used in 802.11n (see 'IEEE P802.11n=D10: 'Draft IEEE Standard for Local Metropolitan networks-Specific requirements. Part 11: Wireless LAN Medium Access Control (MAC), and Physical Layer (PHY) specifications: Enhancements for Higher Throughput', March 2006.'), 802.11ac, and digital video broadcasting (DVB). Typically, in standards that apply LDPC (e.g., the DVB standard), encoding is performed using a parity-check matrix instead of a generator matrix.Since the parity check matrix of the LDPC code has a very small number of 1s, it can be decoded through iterative decoding even in a very large block size. As the block size becomes very large, it shows performance approaching Shannon's channel capacity limit like a turbo code. In the above parity check matrix, the number of 1s included in a row or column is called a weight. The LDPC code can be described by an (nk)*n parity check matrix H. The generator matrix G corresponding to the parity check matrix H can be obtained by the following mathematical equation.

[0107]

[0108]

[0109] Here, c is a codeword, and x is an information bit. The decoder of the receiving device must obtain the information bit (x) from the codeword (c), which is the encoding result by the transmitting device, and finds x by using the property that Hc = 0. That is, when the received codeword is c', the value of Hc' is calculated, and if the result is 0, the k bits in front of c' are determined to be decoded information bits. If the value of Hc' is not 0, a sum-product algorithm through a graph, a belief propagation algorithm, etc. are used to find c' that satisfies the value of Hc' as 0, and x is restored. The check expression Hc' = 0 is c'H according to the relationship between the corresponding information bit and the corresponding generator matrix G. T =0, and thus the check formula can change depending on the relationship between the information bits and the generator matrix G.

[0110] Figures 6 and 7 illustrate the parity check matrix H of an LDPC code using a bipartite graph.

[0111] In the parity check matrix illustrated in Fig. 6(a), a '1' in a row represents an edge connected to a check node in the bipartite graph, and a '1' in a column represents an edge connected to a variable node. Fig. 6(b) illustrates a portion of a bipartite graph corresponding to the parity check matrix illustrated in Fig. 6(a). Referring to Fig. 6(b), the nodes on the left side of the reciprocal graph represent variable nodes, and the nodes on the right side represent check nodes.

[0112] Figure 7 illustrates another parity check matrix and the entire bipartite lines.

[0113] Referring to Fig. 7, since the product of the parity check matrix H and the codeword c' must be '0', the sum of the hard decision values ​​of the variable nodes connected to any check node must be '0'. Mathematical formulas for the hard decision for each check node are exemplified in Fig. 7(b). Checking at a check node whether the sum of the variable node(s) connected to the check node is '0' in this way is called a syndrome check.

[0114] Among error-correcting codes, polar codes are codes that provide a new framework to solve the problems of existing channel codes. They were invented by Arikan of Bikent University (Reference: E. Arikan, "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," in IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, July 2009). Polar codes are the first mathematically proven capacity-achieving codes with low encoding and decoding complexity. Polar codes outperform turbo codes at large information block lengths without any error flow. Hereinafter, channel coding using polar codes is called polar coding. Polar codes are known as codes that can achieve channel capacity in a given binary discrete memoryless channel. This can only be achieved when the information block size is sufficiently large. In other words, polar codes are codes that can achieve channel capacity by increasing the code size N infinitely. Polar codes have low encoding and decoding complexity and can be successfully decoded. Polar codes are a type of linear block error correction code, and recursive multiple concatenation is the basic building block for polar codes and the basis for code construction. The physical transformation of a channel, which converts physical channels into virtual channels, occurs based on recursive multiple concatenation. When multiple channels are multiplied and accumulated, most of the channels either improve or worsen, and the idea behind polar codes is to utilize good channels.For example, data is sent at rate 1 through good channels and at rate 0 through bad channels. In other words, channel polarization causes the channels to go from a normal state to a polarized state.

[0115] Figure 8 is an example of a block diagram for a polar encoder.

[0116] Figure 8(a) illustrates the base module of a polar code, and in particular, it is a diagram illustrating the first-level channel combining for polar coding. In Figure 8(a), W2 represents the entire equivalent channel obtained by combining two binary discrete memoryless channels (B-DMC), W, . Here, u1 and u2 represent binary input source bits, and y1 and y2 represent output coded bits. Channel combining is the process of concatenating B-DMC channels in parallel.

[0117] Figure 8(b) shows the basic matrix F for the basic module, and the binary input source bits u1, u2 to the basic matrix F and the corresponding output x1, x2 have the following relationship.

[0118]

[0119] Channel W2 can achieve a symmetric capacity I(W), which is the highest rate. In B-DMC W, the symmetric capacity is an important parameter, which is used to measure the rate, and is the highest rate at which reliable communication can occur over the channel W. B-DMC can be defined as follows.

[0120]

[0121] It is possible to synthesize or create a second set of N binary input channels from N independent copies of a given B-DMCW, said channels having properties {W N (i) : 1 <= i <= N}. As N increases, some of the channels tend to have capacities close to 1, while the rest tend to have capacities close to 0. This is called channel polarization. In other words, channel polarization uses N independent copies of a given B-DMCW to create a second set of N channels {W N (i) : is a process that generates {1 <= i <= N}, and the channel polarization effect increases as N increases, all symmetric capacity terms {I(W N (i) )} tends to be either 0 or 1 except for the vanishing fraction of these indices i. In other words, the idea behind channel polarization in polar codes is to transform N copies (i.e., N transmissions) of a channel with symmetric capacity I(W) (e.g., an additive white Gaussian noise channel) into extreme channels with capacities close to 1 or 0. Among the N channels, the I(W) fraction will be perfect channels and the 1-I(W) fraction will be completely noise channels. Then, information bits are sent only through good channels, and inputs to other channels are frozen as 1 or 0. The amount of channel polarization increases with the block length.

[0122] There are predetermined information block sizes that provide optimal performance depending on the error correction code. While many coding schemes are available that offer high capacity information performance at large information block lengths, most of them do not consistently perform well across a wide range of information block lengths and code rates. However, turbo codes, low-density parity check (LDPC) codes, and polar codes have shown promising BLER performance over a wide range of coding rates and code lengths. With the increasing demands for various use cases such as enhanced mobile broadband (eMBB), massive IoT, and URLLC, there is a need for coding schemes that provide stronger channel coding efficiency. Furthermore, there is a growing need for increased capacity, i.e., an increase in the maximum number of subscribers that a channel can currently accommodate.

[0123] Below, implementations of this specification relating to encoding and decoding devices, methods, and procedures for error correction codes for recovering transmission errors occurring in communication systems are described. The following symbols, abbreviations, or terms are used in connection with the implementations of this specification described.

[0124] - ACK: Acknowledgement

[0125] - ARQ: Automatic Repeat request

[0126] - AWGN: Additive White Gaussian Noise

[0127] - BLER: Block Error Rate

[0128] - BP: Belief Propagation

[0129] - CB: Code Block

[0130] - CBS: Code Block Size

[0131] - CRC: Cyclic Redundancy Check

[0132] - DCB: Data Code Block

[0133] - DCI: Downlink Control Information

[0134] - FEC: Forward Error Correction

[0135] - GF: Galois Field

[0136] - HARQ: Hybrid Automatic Repeat request

[0137] - HARQ-ACK: Hybrid Automatic Repeat request Acknowledgement

[0138] - LDPC: Low Density Parity Check

[0139] - LLR: Log-Likelihood Ratio

[0140] - NACK: Negative Acknowledgement

[0141] - OCB: Outer Code Block

[0142] - OCS: Outer Code Symbol

[0143] - OCSG: Outer Code Symbol Group

[0144] - OCW: Outer CodeWord

[0145] - OPS: Outer Parity Symbol

[0146] - OPSG: Outer Parity Symbol Group

[0147] - PCB: Parity Code Block

[0148] - TB: Transport Block

[0149] - TBS: Transport Block Size

[0150] As previously explained, in communication systems such as LTE and NR, a single large transport block (TB) can be divided into multiple smaller code blocks (CBs) for transmission. As transmission rates increase and new service demands evolve, the size of the transport block can increase. As the transport block size increases, the number of code blocks increases, even if the maximum code block size is limited.

[0151] The number of code blocks is C, and the error probability of a code block is BLER. CB If so, the error probability BLER of the transport block TB can be expressed as follows.

[0152]

[0153] Referring to the above equation, it can be seen that as the number of code blocks increases, the error probability of the code blocks must decrease to maintain the target error probability of the transport blocks. In communication systems, it can be difficult to reduce the error probability of the code blocks below a certain level due to various factors such as white noise (AWGN), wireless channel fading, and interference signals. Consequently, achieving the target error probability of the transport blocks can be difficult.

[0154] If a transmission error occurs for a transport block, the error can be recovered by retransmitting the transport block. For example, hybrid automatic request (HARQ) is a technology that combines forward error correction (FEC) and automatic repeat request (ARQ). The transmitter transmits all or part of the encoded coded bits using FEC, and the receiver detects whether there is an error in the received data and transmits a HARQ-ACK signal indicating an acknowledgment (ARQ) or negative ARQ (NACK) of the received data to the transmitter. If the receiver determines that the received data does not have an error or is below a certain threshold, the transmitter transmits new data, whereas if the received data contains an error, the transmitter retransmits the corresponding data block. The receiver combines the retransmitted data block with the previously transmitted data block and decodes it again to detect whether there is an error. That is, the receiver notifies the transmitter of any errors in the transport block, and the transmitter, upon detecting a transmission error, can retransmit the entire transport block to recover from the transmission error. As the number of code blocks increases, the transmitter must retransmit all code blocks in the transport block if an error occurs in any of them, which can increase the retransmission overhead.

[0155] Below, several implementations of this specification are described, which relate to devices, methods, and procedures that can reduce the error probability of a transport block when a transmitter divides a transport block into multiple code blocks for transmission, and reduce retransmission overhead when a transmission error occurs.

[0156] As previously explained, in wireless communication systems such as LTE and NR, the transmitter divides a transport block (TB) into multiple data code blocks (DCBs) (code block segmentation), and performs encoding on each DCB, such as an LDPC code, turbo code, or polar code, and transmits them along with parity bits. The receiver decodes each DCB, and if all DCBs are decoded without error, the receiver can assemble the DCBs (code block assembly) to restore the transmitted TB.

[0157] DCBs may fail to be decoded at the receiver due to factors such as white noise, fading, or interference. In these cases, the receiver cannot recover the complete TB, and recovery processes such as HARQ-ACK feedback and HARQ retransmission may be required. These retransmission procedures can increase transmission delay and incur overhead in the feedback signaling and retransmission processes. In cases where decoding fails due to deep fading or strong interference, even HARQ retransmission and soft combining may not be able to efficiently recover the TB.

[0158] Encoding in the transmitter

[0159] Figures 9 and 10 illustrate transmissions of parity for forward error correction (FEC).

[0160] As mentioned earlier, as the TBS increases, the number of CBs may increase, and as the number of CBs increases, the error requirements for each CB also become more stringent to satisfy the BLER. Since an error in a specific CB requires retransmission of the entire TB, HARQ transmission efficiency also decreases. One approach to addressing this issue is to improve CB BLER during inter-CB decoding through inter-CB encoding. For this purpose, applying channel coding in addition to conventional channel coding can be considered.

[0161] Referring to Fig. 9(a), the transmitter can generate parity by applying an FEC code between multiple DCBs and transmit this parity along with the DCBs in the initial transmission. Alternatively, referring to Fig. 9(b), if an error occurs in the initial transmission, the transmitter can transmit parity when performing a retransmission, thereby improving the aforementioned problems.

[0162] Parity generated from multiple DCBs ("Inter-DCB parity" in FIG. 9) can be generated and transmitted as one or more parity code blocks (PCBs), as illustrated in FIG. 10. As illustrated in FIG. 10, the transmitter can generate and transmit parity for each DCB and each PCB by applying forward error correction codes to each DCB and each PCB. The transmitter can add a CRC before applying forward error correction codes to each DCB and each PCB.

[0163] Hereinafter, the forward error correction code applied between multiple DCBs is called an outer code, and the parity generated by the outer code ("Inter-DCB parity" in FIG. 9 and parity included in the PCB in FIG. 10) is called outer code parity or outer parity. The encoding of the outer code is called outer code encoding or outer encoding, and the decoding is called outer code decoding or outer decoding. In contrast, the forward error correction code applied to each DCB and each PCB is called an inner code, and the parity generated from the inner code ("Parity" in FIG. 10) is called inner code parity or inner parity. Encoding of the inner code is called inner code encoding or inner encoding, and decoding is called inner code decoding or inner decoding.

[0164] External codes can improve system performance by enabling the receiver to recover from DCBs with errors due to deep fading in a fading channel using DCB(s) without errors and PCB(s). Furthermore, the transmitter can retransmit only a number of PCB(s) equal to the number of DCBs with errors, rather than retransmitting all DCBs, thereby allowing the receiver to recover from errors. Therefore, applying external codes can reduce retransmission overhead.

[0165] The problem is how to determine the outer code block (OCB) from the CBs for inter-CB encoding, and how to generate PCB(s) from the outer code parity obtained from the OCBs.

[0166] Below, several implementations of this specification are described for generating external code parity (i.e., "Inter-DCB parity"). Also described below are implementations of this specification for generating PCB(s) from external code parity.

[0167] Figure 11 illustrates outer code block (OCB)(s) ​​and outer code parity generated according to some implementations of this specification. In some implementations of this specification, an OCB is configured to include a portion of each of the DCBs, but not include bits of DCBs included in other OCBs. For example, OCB 0 includes DCB 0 through DCB C. d -1 Each part is included, and OCB 1 contains DCB 0 to DCB C that are not included in OCB 0. d -1 Some of the bits of each are included, and OCB o includes DCB 0 to DCB C that are not included in OCB 0 to OCB o-1. d -1 Some of the bits in each DCB are included, and the bits in one OCB are not included in another OCB. According to some implementations of this specification, the transmitter can generate one or more OCBs from multiple DCBs, generate an outer code parity from each OCB, and then generate one or more PCBs from the outer code parity generated from the one or more OCBs.

[0168] In Fig. 11, d is a data bit, and p is an outer code parity bit. In channel coding, a code symbol is a unit to which channel coding is applied. One outer code symbol (OCS) may be composed of one or more data bits (d), and one outer code symbol group (OCSG) may be composed of one or more OCSs. One outer parity symbol (OPS) may be composed of one or more parity bits (p), and one outer parity symbol group (OPSG) may be composed of one or more OPSs. The number of OCSs or OPSs that make up an OCSG or OPSG may vary depending on the system design. The number of bits that make up an OCS or OPS may be determined depending on the type of channel coding. For example, GF(2 n) based Reed-Solomon code, n bits form one OCS. If the outer code is a GF(256) based Reed-Solomon code, one OCS may be composed of 8 bits of data, one OCSG may be composed of 1 OCS, one OPS may be composed of 8 bits of parity, and one OPSG may be composed of 1 OPS. As another example, if the outer code is a binary LDPC code, one OCS may be composed of 1 bit of data, one OPS may be composed of 1 bit of parity, and one OCSG and one OPSG may be composed of 1 OCS and 1 OPS, respectively. As another example, if the outer code is a binary LDPC code, one OCS may be composed of 1 bit of data, one OPS may be composed of 1 bit of parity, and one OCSG and one OPSG may be composed of 8 OCSs and 8 OPSs, respectively. As another example, when the outer code is a polar code, one OCS may be composed of one bit of data, one OPS may be composed of one bit of parity, and one OCSG and one OPSG may be composed of one OCS and one OPS, respectively. In some implementations of this specification, the number of OCSs or OPSs included in each OCSG and OPSG may be 1, or may be defined or set to be a positive integer multiple of a byte (i.e., 8 bits), considering that data is generally stored and processed in units of bytes in digital systems with memory, such as computer systems and communication systems.

[0169] An OCB may be formed from one OCS from each of the DCBs, but in some implementations of the present specification, as illustrated in FIG. 11, an OCB may be formed from multiple OCSs from each of the DCBs. An OCB may also be formed from one OCSG from each of the DCBs, but in some implementations of the present specification, as illustrated in FIG. 11, an OCB may be formed from multiple OCSGs from each of the DCBs.

[0170] In some implementations of this specification, the size of the DCB, including filler bit(s), and the size of the PCB may be defined as being the same. This is because if the sizes of the DCB and the PCB are different, the base station or, in the case of direct UE-to-UE communication, the scheduling UE must signal the sizes of the DCB and the PCB differently.

[0171] Referring to FIG. 11, one or more OCBs can be generated from multiple DCBs. Each OCB can extract one or more OCSGs from each DCB and be configured by collecting multiple OCSGs extracted from multiple DCBs.

[0172] The size of DCB (number of data bits) is K d , the number of DCBs is C d , the maximum size of OCB (maximum number of data bits) is K o,max Then, the transmitter has the number of OCBs C as follows: o can be obtained.

[0173]

[0174] The number of bits for each OCS is K s , the number of OCS for each OCSG is L s If so, the number of OCSGs in each DCB is L g can be obtained as follows.

[0175]

[0176] Size K of DCB d Go K s Wow L s Wow L g The product of (i.e., K s L s L g ) is less than the maximum number of DCBs, the transmitter may add filler bit(s) to each DCB. The size of the filler to be added is K. f can be obtained as in mathematical formula 8.

[0177]

[0178] OCB o(0≤o <C o , o is an integer) is the number of OCSGs to be extracted from each DCB. o When we say, L o can be determined by mathematical expressions 9 and 10.

[0179]

[0180]

[0181] Size K of OCB o o can be obtained as follows.

[0182]

[0183] As defined in Equation 10, L o Since there are two types, the sizes of OCBs obtained from DCBs may be different. L o >1 may mean that OCSs (or OCSGs) that form the OCB are extracted from multiple locations within each DCB.

[0184] The transmitter can generate external parity by performing external code encoding on each OCB. The transmitter generates external parity as shown in Fig. 11. p It can be transmitted in the form of PCBs. The size of the PCB (i.e., the number of parity bits) is K p If you say K pis the size of DCB K d can be as follows. One OPS on each PCB is K s It consists of parity bits and one OPSG is L s If it consists of OPS, the size P of the external parity to be generated from OCB o o can be obtained as follows.

[0185]

[0186] The size N of each outer codeword (OCW) composed of each OCB and its parity o can be expressed as follows.

[0187]

[0188] Each OCW o(0≤o <C o , o is an integer) outer code rate R o can be expressed as follows.

[0189]

[0190] The transmitter is L from each OCW o o We can extract the OPSGs of a single PCB. The size of the PCB is K. p can be expressed as follows: L o >1 may mean that OPSs (or OPSGs) that will form the PCB are extracted from multiple locations within each OCW.

[0191]

[0192] For example, the size K of DCB d 64, number of DCBs C d is 10 and the maximum size of OCB is K o,max If the number of OCBs is 144, then the number of OCBs is C o is 5 by mathematical expression 6. The maximum size of OCB K o,maxis a system parameter and may be equal to or different from the maximum size of the DCB. K o,max is predefined or can be set by the base station. The number of bits for each OCS is K. s is 1 and the number of OCSs for each OCSG is L s If is 8, the number of OCSGs of each DCB is L g becomes 8 by mathematical formula 7. In this case, the size of the filler K f Since it becomes 0 by Equation 8, there is no need to add a filler. Since M becomes 3 in Equation 9, the number of OCSGs to be extracted from each DCB to construct OCB o (0≤o<5, o is an integer) L o is 2(0≤o<3) or 1(3≤o<5) by mathematical expression 10. Therefore, the size K of OCB o o becomes 160 (0≤o<3) or 80 (3≤o<5) by mathematical expression 11. When the transmitter wants to transmit the external parity generated by performing external code encoding on each OCB to two PCBs, where one OPS consists of one parity bit and one OPSG consists of eight OPSs, the size P of the external parity to be generated from OCB o o is 32 (0≤o<3) or 16 (3≤o<5) by mathematical expression 12. The size N of each OCW o o By mathematical expression 13, it becomes 192 (0≤o<3) or 96 (3≤o<5). External code rate R o can be calculated by mathematical formula 14 and is equal to '5 / 6' for all OCWs. The size K of the PCB p is calculated as 64 by mathematical expression 15, and the size K of DCB d and the size of the filler K f It becomes equal to the added value.

[0193] In the example of Fig. 11, the OCW may be composed of adjacent OCSGs within the DCB and adjacent OPSGs within the PCB. In this case, if a burst error occurs in the DCB or PCB, a burst error may also occur in the OCW, making recovery difficult at the receiver.

[0194] Figure 12 illustrates some implementations of the present specification that reduce the probability of burst errors for a code block. In particular, Figure 12 is an example of a method for reducing the probability of burst errors by spacing out OCSGs and OPSGs belonging to the same OCW within a DCB and a PCB. For example, the transmitter may extract OCSGs belonging to the same OCB within a DCB so that they are spaced apart by the number of OCBs within the DCB. The transmitter may also generate PCBs so that OPSGs belonging to the same OCW are transmitted within a PCB so that they are spaced apart by the number of OCBs within the DCB. In some implementations of the present specification, the total number of OCBs, the number of OCBs within a DCB, and the number of OCWs within a PCB may be the same.

[0195] There are various ways to ensure that OCSGs and OPSGs belonging to the same OCW are separated from each other within the DCB and PCB. That is, the OCB configuration and PCB generation method of FIG. 12 can be implemented in various ways. FIG. 13 and FIG. 14 illustrate implementation examples of the OCB configuration and PCB generation method.

[0196] The OCB configuration and PCB generation method of FIG. 12 can be implemented using block interleavers for each DCB and each PCB, for example, as illustrated in FIG. 13. In some implementations of this specification, the size of the block interleaver for the PCB and the size of the block interleaver for the DCB may be the same. Referring to FIG. 13, the transmitter may have C rows for each DCB and each PCB. o and the number of columns is L o,max Using OCSG and OPSG block interleavers, the OCB can be configured and the PCB generated by following the procedure: where L o,max is L o It is the largest value among the values. Referring to mathematical expression 10, for example, L o,max = CEIL(L g / C o ) may be.

[0197] > S1. The transmitter sequentially stores (writes) the OCSGs of each DCB in the column direction to each DCB block interleaver. When one column is full, it moves to the next column and stores.

[0198] > S2. Read the OCSGs of the DCB block interleavers row-wise to create an OCB. Each row becomes one OCB.

[0199] > S3. Perform outer code encoding on each OCB to generate parity and OPSG. The generated OPSGs are stored in the row direction of the PCB block interleavers.

[0200] > S4. Each PCB block interleaver's OPSGs are read in the column direction to generate each PCB. After reading one column, the next column is read.

[0201] Another implementation example of the OCB configuration and PCB generation method is DCB i(0≤i <C d, i is an integer) are OCSGs belonging to OCSG<i, a> (0≤a <L g , a is an integer), and OCB o(0≤o <C o , o is an integer) are OCSGs that constitute OCSG [o, x] (0≤x <L o C d , x is an integer), then OCSG [o, x] can be expressed as follows.

[0202]

[0203] Here, OCSG [o, x] means OCSG x of OCB o, and OCSG<i, a> means OCSG a of DCB i.

[0204] PCB j(0≤j <C p , j is an integer) of OPSGs<j, b> (0≤b <L g , b is an integer), OCB o(0≤o <C o , o is an integer) are generated from OPSGs OPSG [o, y] (0≤y <L o C p , y is an integer), then OPSG<j, b> can be expressed as follows.

[0205]

[0206] Here, OPSG [o, y] means OPSG y generated from OCB o, and OPSG<j, b> means OPSG b of PCB j.

[0207] Fig. 14 is another implementation example of an OCB configuration and PCB generation method. The example of Fig. 14 is an example of generating two PCBs, each consisting of 13 OPSGs, from three DCBs, each consisting of 13 OCSGs. Referring to Fig. 14, OCBs can be configured and PCB(s) can be generated using each DCB and PCB block interleaver. In the example of Fig. 14, the number of OCBs (or the number of OCWs) C o is 5, L ois 3(0≤o<3) or 2(3≤o<5), L o,max The block interleaver size of DCB and PCB is 5 rows and 3 columns. The indices of OCSGs and the indices of OPSGs can be calculated by Equations 16 and 17, as indicated in each OCSG and each OPSG in Fig. 14.

[0208] In some implementations of this specification, the transmitter may construct one or more OCBs from a plurality of DCBs as described above, generate an outer code parity from the OCBs, and generate one or more PCBs from the generated outer code parity. The transmitter may add a CRC to each DCB and PCB. The transmitter may perform internal encoding on each DCB and PCB (with or without a CRC) to generate an inner code parity and transmit it along with each DCB and PCB.

[0209] Decoding at the receiver

[0210] The receiver can perform internal decoding of each DCB using the internal code parity transmitted together. If the transmitter transmits each DCB with a CRC, the receiver can determine whether decoding was successful by checking the CRC of each DCB that has completed internal decoding. If the transmitter does not transmit a CRC for each DCB, the receiver can determine whether decoding was successful by checking the syndrome of the internal code. If the internal decoding of all DCBs is successful, the receiver can reconstruct the TB by assembling the DCBs (code block assembly). The receiver can determine whether there is a transmission error by checking the CRC of the TB. In some implementations, if all DCBs are decoded without error or successfully, decoding of the PCB may be omitted. In some implementations, internal decoding of the DCB and internal decoding of the PCB may be performed together to reduce decoding delay.

[0211] If a transmission error is identified after internal decoding of the DCBs, the receiver can perform external decoding using external code parity.

[0212] If the transmitter performs internal encoding, such as DCB, by converting the external code parity into one or more PCBs and transmitting them, the receiver can perform internal decoding of the PCBs before performing external decoding. If the transmitter transmits each PCB with a CRC added, the receiver can determine whether decoding is successful by checking the CRC of each PCB that has completed internal decoding. If the transmitter does not transmit a CRC for each PCB, the receiver can determine whether decoding is successful by checking the syndrome of the internal code.

[0213] When performing soft decision decoding with an external decoding method, the receiver can saturate the soft decision value (e.g., log-likelihood ratio (LLR)) of DCB and PCB for which no transmission error has been confirmed through CRC or syndrome in internal decoding to a minimum or maximum value depending on the decoded bit or symbol.

[0214] When distortion information due to puncturing or burst interference for URLLC traffic transmission is given among DCB and PCB that are confirmed to have transmission errors, the receiver can set the bits or symbols affected by the puncturing and interference to a soft decision cancellation value (e.g., a value midway between the maximum and minimum values ​​of the soft decision value). For example, if the soft decision value is LLR and the maximum value of the LLR is +7 and the minimum value is -7, the soft decision value of the bits or symbols affected by the puncturing and interference can be set to 0.

[0215] When erasure decoding is performed using an external decoding method, the receiver can set bits or symbols of DCB and PCB that are confirmed to have transmission errors through CRC or syndrome in internal decoding to erasure values.

[0216] When decoding multiple OCWs, the receiver can calculate the reliability of each OCW and then decode them in order from lowest to highest reliability. After each OCW decoding is completed, the CRCs of the DCBs that encountered errors are rechecked. Once all DCB errors have been corrected, decoding of the remaining OCWs is stopped, thereby reducing external decoding complexity.

[0217] The reliability of each OCW can be calculated based on the soft decision values ​​of the bits or symbols belonging to the OCW. If the soft decision values ​​of DCBs and PCBs that are confirmed to have no transmission errors are set to the minimum or maximum values, the reliability of each OCW can be calculated based only on the soft decision values ​​associated with DCBs or PCBs that have transmission errors. For example, if the outer code is a binary LDPC code and the soft decision values ​​are LLRs, the reliability of each OCW can be calculated by adding up the absolute values ​​of all LLRs belonging to the OCW. If the LLRs of DCBs and PCBs that are confirmed to have no transmission errors are set to the minimum or maximum values, the reliability of each OCW can be calculated by adding up only the absolute values ​​of the LLRs associated with DCBs or PCBs that have transmission errors.

[0218] For example, consider a case where a transmitter constructs five OCBs from three DCBs using a binary LDPC code as an outer code, as shown in Fig. 14, and transmits two PCBs generated from the outer code parity of each OCB. If DCBs 0 and 1, and PCB 0 have successfully internally decoded and thus no transmission errors, and DCB 2 and PCB 1 have failed internally decoding and thus transmission errors remain, the receiver can set all LLRs of DCBs 0 and 1, and PCB 0 to their minimum or maximum values. The receiver can calculate the reliability by adding the absolute values ​​of the LLRs of the bits belonging to the OCSG and OPSG of DCB 2 and PCB 1 for each OCW. For example, the receiver can calculate the reliability of OCW 1 by adding the absolute values ​​of the LLRs of the bits belonging to OCSG [1,6], [1,7], [1,8] and OPSG [1,3], [1,4], [1,5].

[0219] Figure 15 illustrates an example of an external decoding procedure of a receiver. The receiver can set the soft decision values ​​of DCBs and PCBs based on the internal decoding results (S1501). For example, the receiver can set the soft decision values ​​of DCBs and PCBs that have successfully undergone internal decoding, i.e., have no errors, to a minimum or maximum value. The receiver can set the soft decision values ​​of DCBs and PCBs that have failed internal decoding, i.e., have errors, among the soft decision values, which are affected by puncture and interference, to an erased value. The receiver can calculate the reliability of all OCWs that have not undergone external decoding and sort the OCWs in ascending order of reliability. The receiver can perform external decoding of the OCW with the lowest reliability among the OCWs that have not undergone external decoding (S1502). After the external decoding of the OCW with the lowest reliability is completed, the receiver can re-check whether there are errors in the DCB and PCB that had errors using CRC or syndrome (S1503). The receiver can check whether there are any DCBs with errors remaining (S1504). If there are no DCBs with errors (S1504, No), i.e., if all DCBs have been repaired from errors, the receiver can terminate the external decoding procedure. If there are DCBs with errors (S1504, Yes), the receiver can check whether there are any OCWs that have not yet been externally decoded (S1505). If all OCWs have been externally decoded (S1505, No), the receiver can terminate the external decoding procedure. If there are any OCWs that have not yet been externally decoded (S1505, Yes), the receiver can check whether there are any DCBs or PCBs whose errors have been repaired from external decoding (S1506). If there is no DCB or PCB that has recovered errors by external decoding (S1506, No), the receiver can perform external decoding starting with the next less reliable OCW (S1502).If there is a DCB or PCB whose error has been corrected by external decoding (S1506, Yes), the receiver updates the soft decision values ​​of the DCB or PCB to the minimum or maximum value (S1507), recalculates the reliability of all OCWs that have not been externally decoded, and then performs external decoding starting with the OCW with the lowest reliability (S1502). In some implementations, the receiver may also recheck whether the PCB is erroneous for steps S1506 and S1507.

[0220] When the receiver uses the Belief Propagation (BP) algorithm for external decoding, the computational complexity can be reduced by updating only the nodes associated with the DCBs and PCBs with errors at each iteration of the belief propagation. Fig. 16 is an example of representing LDPC BP decoding as a bipartite graph. In particular, Fig. 16 is an example of representing LDPC BP decoding as a bipartite graph when a binary LDPC code is used as the external code, each DCB and PCB contains 2 bits of data or parity, and one OCW consists of 3 DCBs and 2 PCBs. The circular nodes on the top are variable nodes, and the rectangular nodes on the bottom are check nodes. Consider the case where DCBs 0 and 1, and PCB 0 succeed in internal decoding (i.e., no errors), and DCB 2 and PCB 1 fail in internal decoding (i.e., have errors). In this case, the receiver can reduce the decoding computational complexity by updating only variable nodes 4 and 5 belonging to DCB 2, variable nodes 8 and 9 belonging to PCB 1, and check nodes 1, 3, 5, 6, and 7 connected to these variable nodes, and not updating the remaining variable nodes and check nodes.

[0221] According to some implementations of this specification, the probability of transmission errors, transmission delay, and retransmission overhead can be reduced in communication systems that divide a single transport block into multiple code blocks and transmit them. Consequently, the QoS of services requiring low-latency, ultra-high-speed transmission, such as XR, can be improved. Furthermore, transmission delays due to HARQ feedback and retransmissions can be reduced in systems with long round trip times (RTTs), such as non-terrestrial networks (NTNs).

[0222] According to some implementations of this specification, OCSs forming an OCB can be extracted from multiple locations within each DCB or PCB, thereby preventing burst errors from occurring within the DCB or PCB. Consequently, the probability of successful decoding of the DCB or PCB at the receiver can be increased.

[0223] Figure 17 illustrates a channel encoding process according to some implementations of the present specification.

[0224] A communications device or encoder may perform operations according to some implementations of the present disclosure in connection with channel encoding. The communications device or encoder may include at least one transceiver; at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure. A processing device for the communications device or encoder may include at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure. A computer-readable (non-volatile) storage medium may store at least one computer program comprising instructions that, when executed by at least one processor, cause the at least one processor to perform operations according to some implementations of the present disclosure. A computer program or computer program product may be recorded on at least one computer-readable (non-volatile) storage medium and may contain instructions that, when executed, cause (at least one processor) to perform operations according to some implementations of the present specification.

[0225] Referring to FIG. 17, a method performed by the communication device, or in the communication device, the encoder, the processing device, the computer-readable (non-volatile) storage medium, and / or the computer program product, the operations: C based on the transport block d Obtaining data code blocks (DCBs) (S1701); the above C d C from the dog DCBs oDetermine the outer code blocks (OCBs) of the dog (S1703); the C o For each of the dog OCBs, the outer parity bits are determined by applying channel coding, and C is determined based on the outer parity bits. p Generate parity code blocks (PCBs) (S1705); the above C d Dog DCBs and the above C p Add internal parity bits to each of the dog PCBs (C d +C p ) determines the parity additional CBs; and the (C d +C p ) may include performing a first transmission based on the parity additional CBs. The C o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0226] Figure 18 illustrates a channel decoding process according to some implementations of the present specification.

[0227] A communications device or decoder may perform operations according to some implementations of the present disclosure in connection with channel decoding. The communications device may include at least one transceiver; at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure. A processing device for the communications device or decoder may include at least one processor; and at least one computer memory operably connected to the at least one processor and storing instructions that, when executed, cause the at least one processor to perform operations according to some implementations of the present disclosure. A computer-readable (non-volatile) storage medium may store at least one computer program comprising instructions that, when executed by at least one processor, cause the at least one processor to perform operations according to some implementations of the present disclosure. A computer program or computer program product may be recorded on at least one computer-readable (non-volatile) storage medium and may contain instructions that, when executed, cause (at least one processor) to perform operations according to some implementations of the present specification.

[0228] Referring to FIG. 18, in a method performed by the communication device, or in the communication device, the decoder, the processing device, the computer-readable (non-volatile) storage medium, and / or the computer program product, the operations are: (C d +C p ) receiving a first transmission related to parity additional code blocks (code blocks, CB) (S1801); and the (C d +C p) may include determining the transport block (S1803) based on decoding of the parity additional CBs. (C d +C p ) Parity appended CBs are Cs to which each internal parity bit is appended. d Dog data code blocks (DCBs) and C p Corresponds to the parity code blocks (PCBs), and the C d The dog DCBs contain bits of the above transport blocks, and the C p The dog PCBs contain external parity bits, and the external parity bits are C o It is obtained through channel coding for outer code blocks (OCBs) of the dogs, and the C o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1.

[0229] In some implementations related to FIG. 17 or FIG. 18, each of K from each DCB g L containing dog bits g The dog OCSGs can be determined, where K g = K s *L s is. The above L g The last of the dog OCSGs is K f It may contain filler bits, where K f = K g *L g - K d And, K d is the size of the corresponding DCB, and K f is a non-negative integer.

[0230] In some implementations related to FIG. 17 or FIG. 18, the OCSGs of each DCB are of size C o *L o,max It is written in column-first order in the block interleaver, where L o,max = Ceil(L g / C o ), L g is the number of OCSGs in each DCB; and DCBs 0 to C d Each C for -1 d The OCSGs recorded in row o of the dog block interleavers can be extracted to determine OCB o, where 0<=o<=C o It's -1.

[0231] In some implementations related to FIG. 17 or FIG. 18, the OCSG x of OCB o may be determined based on: OCSG [o, x] = OCSG<i, a> = OCSG <FLOOR(x / L o ), o + (x mod L o )C o >, where 0≤o <C o and 0≤x <L o C d , o and x are integers, and OCSG<i, a> is the OCSG a of DCB i, where 0≤i <C d and 0≤a <L g , i and a are integers, and L g is the number of OCSGs in each DCB.

[0232] In some implementations related to FIG. 17 or FIG. 18, each PCB has an L associated with each OCB. g *C p Among the outer parity symbol groups (OPSG), L o It may contain discontinuous OPSGs, where L g is the number of OPSGs in each PCB.

[0233] In some implementations related to Fig. 17 or Fig. 18, L obtained based on OCB o o *C p Dog OPSGs are size C o *L o,max In C p The dog block interleavers are recorded in row o, where L o,max = Ceil(L g / C o ), L g is the number of OPSGs in each PCB; and the C p Among the block interleavers, OPSGs are extracted in the column-wise priority from the block interleaver for PCB j, and PCB j can be determined, where 0<=j<=C. p It's -1.

[0234] In some implementations related to FIG. 17 or FIG. 18, the OPSG b of PCB j may be determined based on: OPSG<j, b> = OPSG [o, y] = OPSG [b mod C o , jL o + FLOOR(b / C o )], where 0≤j <C p and 0≤b <L g , j and b are integers, OPSG [o, y] is OPSG y generated from OCB o, where 0≤o <C o and 0≤y <L o C p , o and y are integers, and L g is the number of OPSGs in each PCB.

[0235] In some implementations related to FIG. 17 or FIG. 18, each OPSG has K g may include dog parity bits. The above C o Determining the outer parity bits by applying channel coding to each of the OCBs: K from each OCB g *L o *C p This may include determining the dog parity bits.

[0236] In some implementations related to FIG. 17 or FIG. 18, L o can be determined by: L for 0≤o< M o = CEIL{L g / C o} and M≤o< C o About L o = FLOOR{L g / C o}, where M is L g mod C o and L g is the number of OCSGs in each DCB or the number of OPSGs in each PCB.

[0237] In some implementations related to FIG. 17 or FIG. 18, C o can be determined by mathematical formula 6.

[0238] In some implementations of this specification, the number of OCSGs in each DCB and the number of OPSGs in each PCB may be the same.

[0239] In some implementations of this specification, K g can be a positive integer multiple of 8.

[0240] As described above, the examples disclosed herein are provided to enable those skilled in the art to implement and practice the present disclosure. While the examples have been described above with reference to the examples of the present disclosure, those skilled in the art will appreciate that various modifications and variations may be made to the examples of the present disclosure. Accordingly, the present disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0241] Implementations of this specification may be used in wireless communication systems, base stations, user equipment, or other equipment.

Claims

1. When a communication device transmits a transport block in a wireless communication system, C based on the above transport block d Obtain dog data code blocks (DCBs); C above d C from the dog DCBs o Determine the outer code blocks (OCBs); C above o Determine the outer parity bits by applying channel coding to each of the dog OCBs; C based on the above external parity bits p Determine the parity code blocks (PCBs); C above d Dog DCBs and the above C p Add internal parity bits to each of the dog PCBs (C d +C p ) determines the additional CBs with parity; and Above (C d +C p ) includes performing a first transmission based on the parity additional CBs, C above o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1, Method of transmitting transport blocks.

2. In paragraph 1, From each DCB, each K g L containing dog bits g Including determining the dog OCSGs, Above L g The last of the dog OCSGs is K f Includes dog filler bits, K f = K g *L g - K d And, K d is the size of the corresponding DCB, and K f is a non-negative integer, Method of transmitting transport blocks.

3. In paragraph 2, K g is a positive integer multiple of 8, Method of transmitting transport blocks.

4. In paragraph 2, OCSGs of each DCB are of size C o *L o,max The block interleaver records in column-first order, where L o,max = Ceil(L g / C o ), L g is the number of OCSGs in each DCB; and DCBs 0 ~ C d Each C for -1 d It involves extracting OCSGs recorded in row o of the dog block interleavers to determine OCB o, where 0<=o<=C. o -1, Method of transmitting transport blocks.

5. In paragraph 1, OCSG x of OCB o is determined based on: OCSG [o, x] = OCSG<i, a> = OCSG <FLOOR(x / L o ), o + (x mod L o )C o >, where 0≤o <C o and 0≤x <L o C d , o and x are integers, and OCSG<i, a> is the OCSG a of DCB i, where 0≤i <C d and 0≤a <L g , i and a are integers, and L g is the number of OCSGs in each DCB, Method of transmitting transport blocks.

6. In paragraph 1, Each PCB has an L associated with each OCB. g *C p Among the outer parity symbol groups (OPSG), L o Includes discontinuous OPSGs, where L g is the number of OPSGs in each PCB, Method of transmitting transport blocks.

7. In paragraph 6, L obtained based on OCB o o *C p Dog OPSGs size C o *L o,max In C p Record in row o of the dog block interleavers, where L o,max = Ceil(L g / C o ), L g is the number of OPSGs in each PCB; and C above p It includes determining PCB j by extracting OPSGs from the block interleaver for PCB j among the block interleavers in the column direction first, where 0<=j<=C. p -1, Method of transmitting transport blocks.

8. In paragraph 6, The OPSG b of PCB j is determined based on: OPSG<j, b> = OPSG [o, y] = OPSG [b mod C o , jL o + FLOOR(b / C o )], where 0≤j <C p and 0≤b <L g , j and b are integers, OPSG [o, y] is OPSG y generated from OCB o, where 0≤o <C o and 0≤y <L o C p , o and y are integers, and L g is the number of OPSGs in each PCB, Method of transmitting transport blocks.

9. In paragraph 6, Each OPSG is K g Contains dog parity bits, C above o Applying channel coding to each of the dog OCBs to determine the outer parity bits: K from each OCB g *L o *C p Including determining the dog parity bits, Method of transmitting transport blocks.

10. In paragraph 1, L o is determined by: 0≤o <M에 대해 L o = CEIL{L g / C o } and M≤o <C o About L o = FLOOR{L g / C o }, where M is L g mod C o and L g is the number of OCSGs in each DCB, Method of transmitting transport blocks.

11. In paragraph 1, C o = CEIL{K d C d / K o,max }, where K d is the size of DCB, and K o,max is the maximum size of OCB, Method of transmitting transport blocks.

12. When a communication device transmits a transport block in a wireless communication system, At least one transmitter / receiver; at least one processor; and At least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations, said operations comprising: C based on the above transport block d Obtain dog data code blocks (DCBs); C above d C from the dog DCBs o Determine the outer code blocks (OCBs); C above o Determine the outer parity bits by applying channel coding to each of the dog OCBs; C based on the above external parity bits p Determine the parity code blocks (PCBs); C above d Dog DCBs and the above C p Add internal parity bits to each of the dog PCBs (C d +C p ) determines the additional CBs with parity; and Above (C d +C p ) includes performing a first transmission based on the parity additional CBs, C above o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1, Communication device.

13. In a processing device in a wireless communication system, at least one processor; and At least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations, said operations comprising: C based on transport blocks d Obtain dog data code blocks (DCBs); C above d C from the dog DCBs o Determine the outer code blocks (OCBs); C above o Determine the outer parity bits by applying channel coding to each of the dog OCBs; C based on the above external parity bits p Determine the parity code blocks (PCBs); C above d Dog DCBs and the above C p Add internal parity bits to each of the dog PCBs (C d +C p ) determines the additional CBs with parity; and Above (C d +C p ) includes performing a first transmission based on the parity additional CBs, C above o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1, Processing unit.

14. In a computer-readable storage medium, The storage medium stores at least one program code comprising instructions that, when executed, cause at least one processor to perform operations, the operations comprising: C based on transport blocks d Obtain dog data code blocks (DCBs); C above d C from the dog DCBs o Determine the outer code blocks (OCBs); C above o Determine the outer parity bits by applying channel coding to each of the dog OCBs; C based on the above external parity bits p Determine the parity code blocks (PCBs); C above d Dog DCBs and the above C p Add internal parity bits to each of the dog PCBs (C d +C p ) determines the additional CBs with parity; and Above (C d +C p ) includes performing a first transmission based on the parity additional CBs, C above o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1, Storage media.

15. When a communication device receives a transport block in a wireless communication system, (C d +C p ) receiving a first transmission associated with parity supplementary code blocks (CB); and Above (C d +C p ) based on decoding of the additional CBs with a parity of 1, including determining the transport block, Above (C d +C p ) Parity appended CBs are Cs to which each internal parity bit is appended. d Dog data code blocks (DCBs) and C p Corresponds to the parity code blocks (PCBs), C above d The dog DCBs contain the bits of the above transport blocks, C above p The dog PCBs contain external parity bits, The above external parity bits are C o It is obtained through channel coding for outer code blocks (OCBs). C above o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1, How to receive transport blocks.

16. When a communication device receives a transport block in a wireless communication system, At least one transmitter / receiver; at least one processor; and At least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations, said operations comprising: (C d +C p ) receiving a first transmission associated with parity supplementary code blocks (CB); and Above (C d +C p ) based on decoding of the additional CBs with a parity of 1, including determining the transport block, Above (C d +C p ) Parity appended CBs are Cs to which each internal parity bit is appended. d Dog data code blocks (DCBs) and C p Corresponds to the parity code blocks (PCBs), C above d The dog DCBs contain the bits of the above transport blocks, C above p The dog PCBs contain external parity bits, The above external parity bits are C o It is obtained through channel coding for outer code blocks (OCBs). C above o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1, Communication device.

17. In a processing device in a wireless communication system, at least one processor; and At least one computer memory operably connected to said at least one processor and storing instructions that, when executed, cause said at least one processor to perform operations, said operations comprising: (C d +C p ) receiving a first transmission associated with parity supplementary code blocks (CB); and Above (C d +C p ) includes determining a transport block based on decoding of the additional CBs with a parity of 1, Above (C d +C p ) Parity appended CBs are Cs to which each internal parity bit is appended. d Dog data code blocks (DCBs) and C p Corresponds to the parity code blocks (PCBs), C above d The dog DCBs contain the bits of the above transport blocks, C above p The dog PCBs contain external parity bits, The above external parity bits are C o It is obtained through channel coding for outer code blocks (OCBs). C above o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1, Processing unit.

18. In a computer-readable storage medium, The storage medium stores at least one program code comprising instructions that, when executed, cause at least one processor to perform operations, the operations comprising: (C d +C p ) receiving a first transmission associated with parity supplementary code blocks (CB); and Above (C d +C p ) includes determining a transport block based on decoding of the additional CBs with a parity of 1, Above (C d +C p ) Parity appended CBs are Cs to which each internal parity bit is appended. d Dog data code blocks (DCBs) and C p Corresponds to the parity code blocks (PCBs), C above d The dog DCBs contain the bits of the above transport blocks, C above p The dog PCBs contain external parity bits, The above external parity bits are C o It is obtained through channel coding for outer code blocks (OCBs). C above o Each of the dog OCBs is the above C d L from each of the DCBs o It contains non-consecutive outer code symbol groups (OCSG), where L o is an integer greater than 1, Storage media.

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