Computing-in-memory unit and control method therefor, and electronic device

Abstract

A computing-in-memory unit and a control method therefor, and an electronic device. The computing-in-memory unit comprises: at least one column of memory cells, each memory cell comprising a read transistor (T1) and a write transistor (T2), wherein a first electrode (E1) of the read transistor (T1) is connected to a summing line (SL), a second electrode (E2) thereof is connected to a reference voltage terminal (Vrefn), and a first gate electrode (G1) thereof is connected to an action line (act); and a third electrode (G3) of the write transistor (T2) is connected to a second gate electrode (G2) of the read transistor, a fourth electrode (E4) thereof is connected to a write bit line (WBL), and a third gate electrode (G3) thereof is connected to a write word line (WWL). First electrodes (E1) of memory cells in the same column are connected to the same summing line (SL); the action line is connected to a data input circuit; and the data input circuit is configured to determine the level of a voltage signal that corresponds to data to be operated, and input the voltage signal of the corresponding level to the action line (act), wherein voltage values of the voltage signal of different levels are different.

Description

An in-memory computing unit, a control method thereof and an electronic device

[0001] The present application claims priority to the Chinese patent application No. 2024111408592, filed on August 19, 2024, and entitled "An in-memory computing unit, a control method thereof and an electronic device", the content of which should be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design in the field of semiconductor technology, in particular to an in-memory computing unit, a control method thereof and an electronic device. BACKGROUND

[0003] The application of big data is developing rapidly, and the amount of data is increasing exponentially. The energy consumption of data transmission between memory and processor has become the main part of computing energy consumption, and has become the bottleneck of big data computing energy efficiency. Therefore, giving memory computing ability, reducing data movement and reducing running energy consumption, that is, developing in-memory computing, has become an effective means to improve the energy efficiency of big data computing.

[0004] SUMMARY

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The embodiments of the present disclosure provide an in-memory computing unit, comprising: at least one column of storage units, the storage unit comprising a read transistor and a write transistor, the read transistor comprising a first electrode, a second electrode, a first gate electrode, and a second gate electrode, the first electrode being connected to a sum line, the second electrode being connected to a reference voltage terminal, the first gate electrode being connected to an operation line, the write transistor comprising a third gate electrode, a third electrode, and a fourth electrode, the third electrode being connected to the second gate electrode, the fourth electrode being connected to a write bit line, and the third gate electrode being connected to a write word line, the first electrodes of the read transistors of the storage units in the same column being connected to the same sum line; the operation line being connected to a data input circuit, and different storage units in the same column being connected to different operation lines.

[0007] The data input circuit is configured to determine the level of the voltage signal corresponding to the data to be operated, and input the voltage signal of the corresponding level to the operation line, wherein the voltage values of the voltage signals of different levels are different.

[0008] In some embodiments, the sum line and the write bit line connected to the same storage unit are the same signal line.

[0009] In some embodiments, the voltage value of the voltage signal corresponding to the data to be operated is positively correlated with the size of the data to be operated.

[0010] In some embodiments, the read transistor has a turn-on current corresponding to different levels of voltage signals arranged in equal difference.

[0011] In some embodiments, the in-memory computing unit includes a plurality of columns of memory cells, in which the first gate electrodes of memory cells in a same row are connected to a same operation line, and the third gate electrodes of memory cells in the same row are connected to a same write word line.

[0012] In some embodiments, the memory cells store weight values, and the in-memory computing unit further includes a data output circuit connected to the sum line, configured to detect a current of the sum line, and determine a dot product value of input data to be operated and the weight values stored in a column of the memory cells connected to the sum line according to the current of the sum line.

[0013] In some embodiments, the memory cells store weight values, the in-memory computing unit includes at least two columns of memory cells, and each two memory cells in a same row are taken as a group, referred to as a composite memory cell, and two sum lines connected to a column of composite memory cells are referred to as a group of sum lines.

[0014] The in-memory computing unit further includes a data output circuit connected to a group of the sum lines, configured to detect a difference between currents of two sum lines in the same group, and determine a dot product value of input data to be operated and the weight values stored in a column of the composite memory cells connected to the two sum lines according to the difference between the currents of the two sum lines.

[0015] Embodiments of the present disclosure provide a control method of an in-memory computing unit, including: determining a level of a voltage signal corresponding to data to be operated, and inputting the voltage signal of the corresponding level to an operation line, wherein voltage values of the voltage signals of different levels are different.

[0016] In some embodiments, the method further includes: determining a dot product value of input data to be operated and weight values stored in a column of the memory cells connected to the sum line according to the current of the sum line.

[0017] In some embodiments, the method further includes: detecting a difference between currents of two sum lines in the same group, and determining a dot product value of input data to be operated and the weight values stored in a column of the composite memory cells connected to the two sum lines according to the difference between the currents of the two sum lines.

[0018] Embodiments of the present disclosure provide an electronic device, including the in-memory computing unit described above.

[0019] Other features and advantages of the present application will be set forth in the following specification, and in part will become apparent to those persons skilled in the art upon reference thereto, or can be learned by practice of the application. Other advantages of the application can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the specification.

[0020] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the detailed description and the accompanying drawings.

[0021] SUMMARY

[0022] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. The drawings are provided for merely the purposes of illustration and description and can not be used to impose a limitation of the scope of this application.

[0023] FIG. 1 is a schematic diagram of a memory unit according to an example embodiment;

[0024] FIG. 2 is a schematic diagram of a memory unit according to another example embodiment;

[0025] FIG. 3 is a graph of voltage and current according to an example embodiment;

[0026] FIG. 4 is a schematic diagram of an in-memory computing unit according to an example embodiment;

[0027] FIG. 5 is a schematic diagram of an in-memory computing unit according to another example embodiment.

[0028] DETAILED DESCRIPTION

[0029] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0030] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms used by a person skilled in the art to which the present disclosure pertains.

[0031] The embodiments of the present disclosure are not necessarily limited to the sizes of the components shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect true proportions. In addition, the drawings schematically show limited embodiments, and the embodiments of the present disclosure are not limited to the embodiments shown in the drawings.

[0032] The ordinal numbers "first", "second", "third", etc. in the present disclosure are set to avoid confusion of the components, and do not represent any order, number, or importance.

[0033] In the present disclosure, unless clearly specified and limited otherwise, the terms "mounting", "connection", and "linking" should be interpreted broadly. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or a connection within two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0034] In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0035] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity, or in the case of changing the direction of current in circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0036] In the present disclosure, "connection" includes the case where the constituent elements are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0037] A typical in-memory computing unit is a Dot-Product Engine (DPE). The DPE is a key circuit to implement a neural network. A typical unit of a neural network is that a plurality of inputs are outputted after weighted summation. This operation can be implemented by a DPE circuit. In one technical solution, the DPE can be implemented by using a single-gate 2T0C memory cell. In this solution, the DPE can include a plurality of single-gate 2T0C memory cells distributed in an array, the memory cells in the same row are connected to the same operation line, the memory cells in the same column are connected to the same summation line, the data to be operated is converted into a pulse signal and loaded to the operation line, different data correspond to pulse signals of different widths, and the dot product value of the data to be operated and the weight value stored in the memory cell connected to the summation line can be obtained by detecting the voltage accumulated on the summation line. Since the data to be operated is implemented by using pulse signals of different widths, the dot product value cannot be obtained by detecting the current. That is, only the dot product value can be obtained by detecting the voltage. Since the charging and discharging of the electric charge need a certain time, the detection speed of this solution is slow.

[0038] In the embodiments of the present disclosure, the in-memory computing unit is implemented by using a double-gate 2T0C memory cell, and the data to be operated is converted into a voltage signal of different voltage values and input to the operation line. Compared with the implementation solution in which the data to be operated is converted into a pulse signal of different widths, the voltage and current detection modes can be supported in this embodiment, and when the detection is performed by the current detection mode, the detection speed can be improved.

[0039] FIG. 1 is an equivalent circuit diagram of one memory cell in an in-memory computing unit provided by an embodiment of the present disclosure. As shown in FIG. 1, the memory cell provided by the embodiment of the present disclosure can include a read transistor T1 and a write transistor T2. The read transistor T1 can include a first electrode E1, a second electrode E2, a first gate electrode G1 and a second gate electrode G2. The first electrode E1 is connected to a summation line (Sum Line, SL), the second electrode E2 is connected to a reference voltage end Vrefn, and the first gate electrode G1 is connected to an operation line act. The write transistor T2 includes a third gate electrode G3, a third electrode E3 and a fourth electrode E4. The third electrode E3 is connected to the second gate electrode G2, the fourth electrode E4 is connected to a write bit line (WBL), and the third gate electrode G3 is connected to a write word line (WWL). The storage node SN includes the second gate electrode G2. The operation line act is equivalent to the read word line (RWL) connected to the conventional memory cell. The summation line SL is equivalent to the read bit line (RBL) connected to the conventional memory cell.

[0040] In some embodiments, as shown in FIG. 2, the fourth electrode E4 and the first electrode E1 of the storage unit can be connected together. That is, the write bit line (WBL) and the sum line SL of the storage unit connection can be the same signal line.

[0041] The operation line act is loaded with data to be operated, and the level of the corresponding voltage signal can be determined according to the data to be operated, and the voltage signal of the corresponding level is input to the operation line act, wherein the voltage values of the voltage signals of different levels are different. After the voltage is loaded on the operation line act, the corresponding conduction current is generated to the sum line SL according to the data stored in the storage node SN. When the sum line SL is connected to a plurality of storage units, the conduction currents of the plurality of storage units are input to the sum line SL. In some embodiments, except for the voltage signal corresponding to the voltage value of 0, the voltage values of the voltage signals of other levels are greater than the turn-on threshold voltage of the read transistor T1 when the data stored in the storage node is "1".

[0042] In some embodiments, the voltage value of the voltage signal corresponding to the data to be operated is positively correlated with the size of the data to be operated. That is, the data to be operated corresponding to the voltage signal with a high voltage value is greater than or equal to the data to be operated corresponding to the voltage signal with a low voltage value.

[0043] FIG. 3 is a schematic diagram of the voltage-current relationship provided by an exemplary embodiment. In FIG. 3, the horizontal axis V RWL is the voltage loaded on the operation line act, and the vertical axis I cell is the current output to the sum line SL (which is the logarithmic value of the actual current), and W is the weight value stored in the storage node SN, which can be logical data "0" or logical data "1". As shown in FIG. 3, in this embodiment, the voltage signal can be divided into four levels, 00, 01, 10, and 11, each level corresponding to a different voltage value. When the value stored in the storage node SN is "0" (i.e., the voltage stored in the storage node SN is the voltage corresponding to the logical data "0"), I cell is close to 0, that is, the read transistor T1 is off at this time; when the value stored in the storage node SN is "1" (i.e., the voltage stored in the storage node SN is the voltage corresponding to the logical data "1"), the output I cell is different, so that the dot product value can be determined by detecting the current. The number of levels shown in FIG. 3 is only an example, and the embodiments of the present disclosure are not limited thereto, and other number of levels can be used.

[0044] In some embodiments, the difference between the current output by adjacent levels can be the same except for level "00". For example, when the value stored in the storage node SN is "1", the difference between the current corresponding to level "10" and the current corresponding to level "01" (here, the actual current, not the logarithmic value) is the same as the difference between the current corresponding to level "11" and the current corresponding to level "10". That is, the on currents corresponding to different levels of voltage signals in the read transistor T1 are in an arithmetic progression or an approximate arithmetic progression. Here, the on current does not include the current when the level is "00", and the read transistor T1 is considered to be turned off when the level is "00". This approach facilitates subsequent conversion of the detected current into a summation value.

[0045] FIG. 4 is a schematic diagram of an in-memory computing unit according to an embodiment of the present disclosure. As shown in FIG. 4, the in-memory computing unit according to an embodiment of the present disclosure can include a plurality of rows and a plurality of columns of storage units, which are shown in FIG. 1 or FIG. 2, and the storage units shown in FIG. 2 are taken as an example in FIG. 4. The first electrodes E1 of the read transistors T1 of the storage units in the same column are connected to the same summation line SL, and the first electrodes E1 of the read transistors T1 of the storage units in different columns are connected to different summation lines SL (e.g., the first summation line SL0 and the second summation line SL1 shown in FIG. 4); each row of storage units is connected to the same operation line act (e.g., the first operation line act0 and the second operation line act1 shown in FIG. 4), and different storage units in the same column are connected to different operation lines act. The third gate electrodes G3 of each row of storage units can be connected to the same write word line (e.g., the first write word line WWL0 and the second write word line WWL1 shown in FIG. 4), and the operation lines act are connected to data input circuits, each operation line act can be connected to one data input circuit, and different operation lines act can be connected to different data input circuits. Each summation line SL can be connected to one data output circuit, and different summation lines SL can be connected to different data output circuits. Only two rows and two columns of storage units are shown in FIG. 4, which is only an example and can include more rows and more columns of storage units.

[0046] The data input circuit is configured to determine the level of the voltage signal corresponding to the data to be operated, and input the voltage signal of the corresponding level to the operation line act, wherein the voltage values of the voltage signals of different levels are different.

[0047] The data output circuit is configured to detect the current of the sum line SL, and determine the dot product value of the input data to be operated in the column of the storage unit connected with the sum line SL and the weight value stored in the storage unit according to the current of the sum line SL. However, the embodiments of the present disclosure are not limited thereto. The data output circuit can detect the voltage of the sum line SL, and determine the dot product value of the input data to be operated in the column of the storage unit connected with the sum line SL and the weight value stored in the storage unit according to the voltage of the sum line SL. The current detection scheme has a faster detection speed and is more resistant to interference than the voltage detection scheme. That is, the embodiments of the present disclosure can support voltage and current mode detection of the signal on the sum line SL. In addition, compared with the single-gate 2T0C, the operation line (equivalent to the read word line) of the double-gate 2T0C can be free from the IR drop problem, and the double-gate 2T0C has the advantage of low leakage compared with the single-gate 2T0C.

[0048] When the data stored in the storage unit is "1", different currents are generated to the sum line SL according to different voltages input to the operation line act; the currents generated by different storage units on the same sum line SL are all loaded on the sum line SL, and the dot product value of the input data to be operated in the column of the storage unit and the weight value stored in the column of the storage unit can be obtained according to the current on the sum line SL. For example, the dot product value output by the sum line SL connected with the jth column of storage units is ∑wj i,j ·act i , wherein act i is the input data to be operated in the storage unit of the i+1th row, w i,j is the weight value stored in the storage unit of the i+1th row and the j+1th column, i is 0 to m-1, m is the number of rows of the storage unit, j is 0 to n-1, and n is the number of columns of the storage unit.

[0049] In some embodiments, the data input circuit can include a digital-to-analog conversion circuit.

[0050] In some embodiments, the data output circuit can include an analog-to-digital conversion circuit.

[0051] Figure 5 is an equivalent circuit diagram of an in-memory computing unit according to another example embodiment. In this embodiment, the in-memory computing unit can include a plurality of rows and a plurality of columns of memory cells, the first electrodes E1 of the read transistors T1 of the memory cells in the same column are connected to the same sum line SL, and the first electrodes E1 of the read transistors T1 of the memory cells in different columns are connected to different sum lines SL (e.g., the first sum line SL0, the second sum line SL1, the third sum line SL2, and the fourth sum line SL3 as shown in Figure 5); each row of memory cells is connected to the same operation line act (e.g., the first operation line act0 and the second operation line act1 as shown in Figure 5), and different memory cells in the same column are connected to different operation lines act. The third gate electrodes G3 of each row of memory cells can be connected to the same write word line (e.g., the first write word line WWL0 and the second write word line WWL1 as shown in Figure 5). In this embodiment, two memory cells are taken as a group, referred to as a composite memory cell 10, for example, every two adjacent memory cells in the same row are taken as a group, referred to as a composite memory cell 10, and the two sum lines SL connected to a column of composite memory cells 10 are referred to as a group of sum lines. For example, the first sum line SL0 and the second sum line SL1 are a group of sum lines, and the third sum line SL2 and the fourth sum line SL3 are a group of sum lines.

[0052] The operation line act is connected to a data input circuit, and each operation line act can be connected to one data input circuit, and different operation lines act can be connected to different data input circuits. The data input circuit is configured to determine the level of the voltage signal corresponding to the data to be operated, and input the voltage signal of the corresponding level to the operation line act, wherein the voltage values of the voltage signals of different levels are different.

[0053] The in-memory computing unit can further include a data output circuit connected to a group of sum lines SL, and the data output circuit is configured to detect the difference between the currents of two sum lines SL in the same group, and determine the dot product value of the input data to be operated and the weight value stored in the composite memory cell 10 in a column of composite memory cells 10 connected to the two sum lines SL according to the difference between the currents of the two sum lines SL; or, detect the difference between the voltages of two sum lines SL in the same group, and determine the dot product value of the input data to be operated and the weight value stored in the composite memory cell 10 in a column of composite memory cells 10 connected to the two sum lines SL according to the difference between the voltages of the two sum lines SL.

[0054] The scheme provided in this embodiment uses differential signals to calculate the dot product value, and when there is interference in the circuit, the interference can be removed by differential method, so the anti-interference performance is better.

[0055] The weight values of the composite storage unit 10 are shown in Table 1. Taking the composite storage unit 10 shown in FIG. 5 as an example, the left storage unit and the right storage unit are the left storage unit and the right storage unit in the composite storage unit 10 shown in FIG. 5, respectively.

[0056] Table 1: Weight values of composite storage unit

[0057] That is, when the weight values stored in the two storage units in the composite storage unit 10 are both "0", the weight value of the composite storage unit 10 is "0"; when the weight value stored in one of the two storage units is "0" and the weight value stored in the other is "1", the weight value of the composite storage unit 10 is "1" or "-1". In some embodiments, when the electrical parameter of the sum line SL to which the left storage unit is connected is subtracted from the electrical parameter of the sum line SL to which the right storage unit is connected in the data output circuit, the weight value of the composite storage unit 10 is "1" when the weight value stored in the left storage unit is "1" and the weight value stored in the right storage unit is "0"; the weight value of the composite storage unit 10 is "-1" when the weight value stored in the left storage unit is "0" and the weight value stored in the right storage unit is "1", as shown in Table 1. In other embodiments, when the electrical parameter of the sum line SL to which the right storage unit is connected is subtracted from the electrical parameter of the sum line SL to which the left storage unit is connected in the data output circuit, the weight value of the composite storage unit 10 is "1" when the weight value stored in the right storage unit is "1" and the weight value stored in the left storage unit is "0"; the weight value of the composite storage unit 10 is "-1" when the weight value stored in the right storage unit is "0" and the weight value stored in the left storage unit is "1". The electrical parameter is a voltage value or a current value.

[0058] The embodiments of the present disclosure also provide an electronic device comprising the in-memory computing unit described in the foregoing embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0059] Although the embodiments of the present disclosure are as described above, the content described above is only an embodiment adopted for the purpose of facilitating understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. An in-memory computing unit, comprising: At least one column of memory cells, the memory cells comprising a read transistor and a write transistor, the read transistor comprising a first electrode, a second electrode, a first gate electrode, a second gate electrode, the first electrode connected to a sum line, the second electrode connected to a reference voltage terminal, the first gate electrode connected to an operation line, the write transistor comprising a third gate electrode, a third electrode, a fourth electrode, the third electrode connected to the second gate electrode, the fourth electrode connected to a write bit line, the third gate electrode connected to a write word line, the first electrodes of the read transistors of the memory cells in the same column connected to the same sum line; the operation lines connected to a data input circuit, different memory cells in the same column connected to different operation lines; the data input circuit configured to determine a level of a voltage signal corresponding to the data to be operated, and input the voltage signal of the corresponding level to the operation line, wherein the voltage values of the voltage signals of different levels are different.

2. The in-memory computing cell of claim 1, wherein, The sum line and the write bit line connected to the same memory cell are the same signal line.

3. The in-memory computing cell of claim 1, wherein, The voltage value of the voltage signal corresponding to the data to be operated is positively correlated with the size of the data to be operated.

4. The in-memory computing cell of claim 1, wherein, The in-memory computing unit comprises a plurality of columns of memory cells, in the plurality of columns of memory cells, the first gate electrodes of the memory cells in the same row are connected to the same operation line, and the third gate electrodes of the memory cells in the same row are connected to the same write word line.

5. The in-memory computing cell of claim 1, wherein, The on currents of the read transistors corresponding to voltage signals of different levels are arranged in equal difference.

6. The in-memory computing cell of any one of claims 1 to 5, wherein, The memory cells store weight values, and the in-memory computing unit further comprises a data output circuit connected to the sum line, the data output circuit configured to detect the current of the sum line, and determine the dot product value of the data to be operated input in the column of memory cells connected to the sum line and the weight values stored in the memory cells according to the current of the sum line.

7. The in-memory computing cell of any one of claims 1 to 5, wherein, The memory cells store weight values, the in-memory computing unit comprises at least two columns of memory cells, and every two memory cells in the same row are taken as a group, referred to as a composite memory cell, and two sum lines connected to a column of composite memory cells are referred to as a group of sum lines; The in-memory computing unit further comprises a data output circuit connected to a group of sum lines, the data output circuit configured to detect the difference between the currents of the two sum lines in the same group, and determine the dot product value of the data to be operated input in the column of composite memory cells connected to the two sum lines and the weight values stored in the composite memory cells according to the difference between the currents of the two sum lines.

8. A control method of an in-memory computing unit as claimed in any one of claims 1 to 7, comprising: Determine a level of a voltage signal corresponding to the data to be operated, and input the voltage signal of the corresponding level to the operation line, wherein the voltage values of the voltage signals of different levels are different.

9. The control method of the in-memory computing unit according to claim 8, wherein, The in-memory computing unit is any one of the in-memory computing units in claims 1 to 6, and the method further comprises detecting the current of the sum line, and determining the dot product value of the data to be operated input in the column of memory cells connected to the sum line and the weight values stored in the memory cells according to the current of the sum line.

10. The control method of the in-memory computing unit according to claim 8, wherein, The in-memory computing unit is the in-memory computing unit of claim 7, and the method further comprises detecting a difference between currents of two of the sum lines of the same group, and determining a dot product value of input data to be operated on and weight values stored in the composite memory cells connected to the two sum lines according to the difference between the currents of the two sum lines.

11. An electronic device comprising the in-memory computing unit of any one of claims 1 to 7.

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