Optoelectronic device with improved current injection and manufacture thereof

Abstract

The invention concerns an optoelectronic device configured to achieve uniform charge carrier injection into the active region through a plurality of cavities with controllable position, dimensions, and distribution density. The plurality of cavities is formed through partial coalescence of lateral growth fronts in a facet controlled epitaxial lateral overgrowth (FACELO) process prior to device heterostructure deposition.

Description

[0001] 2024PF00419

[0002] OPTOELECTRONIC DEVICE WITH IMPROVED CURRENT INJECTION AND MANUFACTURE THEREOF

[0003] The current application claims priority of the German patent application DE 10 2024 123 926 . 3 dated August 21 , 2024 , the disclosure of which is incorporated herein in its entirety by reference . The present invention concerns an optoelectronic device with improved charge carrier inj ection into the active region .

[0004] BACKGROUND

[0005] The use of semiconductor-based optoelectronic devices such as LEDs , lasers , solar cells , etc . in a variety of applications is accompanied by increasing demand for improved performance , in particular, increased quantum efficiency . In this regard, lateral inj ection of carriers into the active region through v-pits has been presented as promising approach to improvement of device performance .

[0006] V-pits can intentionally be opened during epitaxial growth of semiconductor layers , from threading dislocations propagating from underlying semiconductor material . The location, and density of the threading dislocations follows a random distribution .

[0007] Configuration of growth conditions may allow control of the density of threading dislocations , but the location cannot be controlled by conventional approaches . Furthermore , while the range of dimensions of resultant v-pits may be controllable , uniformity and reproducibility remain a challenge .

[0008] It is an obj ect of the present application to address the abovementioned challenges relating to achievement of uniform and reproducible improvement in performance of semiconductor-based optoelectronic devices .

[0009] SUMMARY OF THE INVENTION

[0010] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims . 2024PF00419

[0011] Optoelectronic semiconductor devices generate light through radiative recombination of charge carriers from doped semiconductor layers , i . e . holes and electrons , said recombination taking part within an active region . The active region is commonly configured as a multi-quantum well structure , comprising quantum well layers arranged between quantum barrier layers , wherein the barrier layers comprise a material characterized by a larger bandgap than the quantum well layers . Diffusion of electrons throughout the multi-quantum well structure is facilitated by the relatively high mobility of electrons . However , the lower mobility of holes results in lower diffusion of holes from quantum wells adj acent to p-doped semiconductor layers across quantum barrier layers . In optoelectronic devices with multiple quantum well layers , radiative recombination is thereby limited to active region layers adj acent to p-doped layers , reducing the internal quantum efficiency and thereby the performance of the optoelectronic device .

[0012] Use of intentionally opened v-pits as sites for charge carrier inj ection into the active region of LEDs has been proposed as a means of mitigating the limited mobility of holes across quantum barriers in the active region . V-pits characteristically form in the shape of inverted hexagonal pyramids . During epitaxial growth, semiconductor material deposited along the inclined sidewalls characterizing the v- pits forms thinner layers in comparison to material growing on substantially horizontal planes . A multi-quantum well structure arranged along inclined v-pit sidewalls will thus be characterized by thinner barrier layers , which leads to a decrease in the obstructive effect of the barrier layers to hole mobility . Diffusion of holes from quantum wells arranged directly adj acent to p-doped semiconductor material into quantum wells arranged further away is facilitated by the thinner barrier layers , thus holes can be more efficiently inj ected laterally into the quantum well structure through the inclined sidewalls of the v-pits .

[0013] The achievable improvement in quantum efficiency through lateral inj ection via intentionally opened v-pits is however limited by the random location and density of randomly occurring v-pits . Additionally, the threading dislocations required for formation of v-pits in 2024PF00419 semiconductor material are crystal defects associated with detrimental effects on optical and electrical properties of the resultant optoelectronic devices . Approaches targeted at reducing the density of threading dislocations in epitaxially grown semiconductor material to achieve improved material quality and associated improvements in optical and electrical properties of optoelectronic devices are counteractive to implementation of lateral carrier inj ection via intentionally opened v-pits .

[0014] The inventors propose implementation of an approach that simultaneously allows reduction of threading dislocation density in epitaxially grown semiconductor material while allowing lateral inj ection of charge carriers into the active region of an optoelectronic device through inclined sidewalls of artificially formed v-shaped cavities . The proposed approach uses facet controlled epitaxial layer overgrowth ( FACELO ) to achieve substantially defect free epitaxial layers with controlled partial coalescence of lateral growth facets to produce cavities whose location, density and dimensions are controllable through adj ustment of growth parameters and design of hard mask . Optoelectronic devices with uniform and controllable current inj ection efficiency can thereby be produced .

[0015] In the FACELO approach, a mask with defined openings is deposited on a semiconductor layer , and semiconductor material is overgrown above the mask until coalescence . Threading dislocations originating in the semiconductor material below the mask cannot penetrate the mas k and are terminated . Additionally, through suitable selection of growth parameters , threading dislocations propagating through openings in the mask are configured to bend during lateral overgrowth and annihilate , resulting in an upper surface with reduced threading dislocation density .

[0016] The proposed invention utilizes the lateral overgrowth approach of FACELO , but the process is terminated before full coalescence , resulting in an upper surface comprising a plurality of cavities with inclined sidewalls . The position and density of the plurality of cavities is controlled by the patterning of the mask, whereas the 2024PF00419 dimensions of the cavities are controlled by the overgrowth layer thickness , which is a function of growth parameters such as chamber temperature , pressure , and growth time . The cavities thus formed differ from intentionally opened v-pits through conventional means , in that the underlying material beneath the cavities is not associated with corresponding threading dislocations originating from the substrate . However, a limited number of threading dislocations may arise along planes of coalescence of overgrown semiconductor layers , forming above the mask .

[0017] Uniform distribution of the cavities in the proposed optoelectronic device results in uniform inj ection and carrier density, thereby improving brightness and voltage by tuning the artificial V-pit density and size . The density and dimensions of the cavities are controllable , allowing production of devices with predetermined current inj ection characteristics . Furthermore , the absence of a reliance on threading dislocations for the formation of the cavities allows configuration of performance characteristics of the optoelectronic device independent of the defect density of underlying buffer layers . The proposed approach is applicable to a wide variety of material systems , in particular , materials where formation of intentionally opened v-pits for current inj ection is difficult to achieve due to non-conducive growth conditions with regard to v-pit formation .

[0018] A method of manufacturing an optoelectronic device according to some aspects of the proposed principle involves an initial step of providing a buffer layer . In some aspects , the buffer layer comprises GaN . In some aspects , the step of providing a buffer layer involves providing a bulk GaN substrate . The bulk substrate is in some aspects subj ected to surface treatment in preparation for epitaxial growth, wherein such surface treatment may include polishing , annealing , and / or structuring . In other aspects of the proposed principle , the step of providing a buffer layer comprises a step of depositing a layer of semiconductor material , particularly GaN, on the surface of a growth substrate . The growth substrate comprises a suitable material for epitaxial growth of semiconductor material , including but not limited to sapphire and silicon . In some aspects the buffer layer is undoped . In other aspects , 2024PF00419 the buffer layer comprises n-doped material . The buffer layer may comprise a plurality of sublayers , each comprising different dopant concentration or material composition .

[0019] In a subsequent step , a patterned mask is deposited on a surface of the buffer layer . In some aspects , the patterning comprises a plurality of regularly arranged, regularly shaped mas k elements , in particular , mask elements of substantially identical size and shape , wherein the density and location of the mas k elements corresponds to a desired resultant density and location of cavities for lateral inj ection of charge carriers . In other aspects , the patterning comprises a plurality of regularly arranged openings of substantially identical size and shape within the mas k . In some aspects , each of the plurality of mas k openings or elements is circular in shape . In other aspects , the mas k openings or elements are hexagonal , rectangular, triangular or any other polygonal shape . The plurality of mask openings or elements is arranged in a regular matrix corresponding to a desired arrangement of cavities in the epitaxially grown layers . In some aspects , the mas k openings or elements are arranged in a grid-like pattern with fixed lateral spacing along at least one lateral axis . In some aspects , regions of mask material designated to correspond to separation planes to be used in singulation of optoelectronic devices from the semiconductor stack are characterized by a different lateral spacing between mask openings or elements , such that the separation planes are pre-formed during the epitaxial growth process .

[0020] Thereafter , a first semiconductor layer , in particular , a first n- doped layer is deposited above the patterned mask . Deposition may be performed using processes including but not limited to Metalorganic Vapor Phase Epitaxy (MOVPE ) , Molecular Beam Epitaxy (MBE ) , Hydride Vapor Phase Epitaxy ( HVPE ) and / or sputtering . The deposition of semiconductor material results in initial vertical growth originating from the openings in the mas k material , with the deposited material growing from surfaces of the buffer layer exposed through the openings in the mask . Further deposition results in further vertical growth in addition to lateral growth of semiconductor material , with the epitaxial layer spreading laterally from openings in the mask material 2024PF00419 to cover the underlying mask . The mask material obstructs propagation of threading dislocations from the underlying buffer layer , such that the propagation of threading dislocations into semiconductor material above the mas k is restricted to material corresponding to openings in the mask .

[0021] In some aspects , the deposition of material to achieve lateral overgrowth is achieved in a plurality of overgrowth processes , optionally involving variation of process parameters such as chamber flow rate , temperature and pressure . In some aspects , a first lateral overgrowth step is performed to form isolated islands located at the mask openings , followed by at least one subsequent regrowth wherein further lateral overgrowth is performed to achieve partial coalescence of lateral growth facets and formation of a plurality of hexagonally- shaped cavities with inclined sidewalls . In multi-step deposition processes , threading dislocations propagating through the openings in the mas k may bend such that they propagate laterally and terminate at the inclined facets of the inclined facets of the overgrowth material , such that during subsequent regrowth, significantly defect-reduced material is deposited . Following the formation of the plurality of cavities , additional doped or undoped layers of semiconductor material may be deposited, wherein the composition, sequence , number and thickness of such layers is dependent on desired functionality . In some aspects , in particular, wherein the first semiconductor layer is undoped, such additional layers include a first doped layer , in particular , a first n-doped layer .

[0022] In a subsequent step , an active region is deposited on the surface of the first doped layer . The active region comprises a multi-quantum well structure with quantum well layers arranged between quantum barrier layers characterized by a larger bandgap than the quantum well layers . In some aspects the active region comprises alternating layers of a ternary nitride , in particular, InGaN or AlGaN, or quaternary nitride , in particular, AlInGaN and a binary nitride , in particular , GaN . In other aspects , the active region comprises alternating layers of a ternary nitride such as InGaN with the barrier layers and well layers comprising different compositions of In . In other aspects , the active 2024PF00419 region comprises a superlattice adj acent to the n-doped layer . In some aspects , the superlattice comprises InGaN, which may be undoped or n- doped . In other aspects , the active region comprises a superlattice on a surface facing away from the first doped layer . In such aspects , the superlattice may serve as an electron blocking layer . In other aspects , the active region is arranged between two cladding layers .

[0023] During deposition of the active region and optional superlattice and / or cladding layers , the deposited semiconductor material follows a template provided by the underlying first doped layer , such that the active region comprises the first plurality of cavities originating in the first doped layer . In aspects wherein the active region further comprises an Indium-containing underlayer, remaining threading dislocations may open up and form a second plurality of unintentional cavities . The dimensions of the second plurality of cavities are substantially smaller than the dimensions of the first plurality of cavities . Additionally, the location and density of the second plurality of cavities are characterized by a random distribution . The unintentionally produced second plurality of cavities does not , however, limit the effect of the homogeneously distributed first plurality of cavities as inj ection of charge carriers into the active region is mainly dominated by the first plurality of cavities .

[0024] In a subsequent processing step , a second doped layer, in particular , a p-doped layer is deposited on the surface of the active region . In some aspects , the depositing of the second doped layer is configured such that the first and potentially second plurality of cavities are filled in, resulting in a smooth upper surface facing away from the active region . In some aspects a smooth upper surface is produced by planarizing the upper surface of the second doped layer . In other aspects , a substantially uniform second doped layer is deposited on the active region such that the upper surface of the second doped layer comprises the first plurality of cavities , and potentially the second plurality of cavities .

[0025] Further aspects of the proposed invention address the dimensions of the first plurality of cavities . In some aspects of the proposed 2024PF00419 principle , a substantially constant lateral distance between adj acent openings in the patterned mas k results in substantially identical dimensions in each of the first plurality of cavities . In some aspects , a maximum depth of the first plurality of cavities is achieved by controlling the FACELO process such that lateral overgrowth of the first doped layer is terminated substantially immediately upon contact of laterally expanding facets . In these aspects , material of the first doped layer covering the mask surface at a vertex of at least some of the first plurality of cavities is minimized . In other aspects , a longer growth time and a corresponding thicker first doped layer is achieved by allowing lateral overgrowth to continue after initial coalescence of the laterally expanding facets such that a depth of the first plurality of cavities becomes smaller . Dependent on the process conditions during the lateral overgrowth of the mas k, the ideal size of the first plurality of cavities can be achieved for any desired overgrowth thickness . In some aspects , one or more set of growth parameters and conditions are used to grow the first plurality of cavities . Furthermore , the growth can continue to partially fill the first plurality of cavities .

[0026] In some aspects , the dimensions of the first plurality of cavities are additionally or alternatively controlled by adj ustment of the dimensions and / or spacing of the openings in the patterned mask . Smaller mask elements spaced more closely together allow the desired cavity depth to be achieved in a shorter amount of time and corresponds to a smaller cavity depth in comparison to larger mask elements and / or mask elements spaced farther apart . The reduction in growth time achievable by decreasing the size of mas k elements however needs to be balanced against a higher probability of propagation of threading dislocations from the underlying buffer layer , in particular , a greater probability of unintentionally opened secondary plurality of v-pits . Growth parameters in such aspects need to be configured to increase the probability of bending and lateral propagation of threading dislocations originating from the buffer layer so that a high-quality epitaxial layer is achieved . 2024PF00419

[0027] Further aspects of the proposed principle concern an optoelectronic device configured to achieve improved current inj ection . The optoelectronic device comprises a first doped layer, an active region and a second doped layer . The active region is arranged between the first doped layer and the second doped layer . The first doped layer and the active region comprise a first plurality of cavities comprising inclined sidewalls . The active region is configured as a multi-quantum well structure , with quantum well layers arranged between quantum barrier layers . The quantum barrier layers are characterized by a larger bandgap than the quantum well layers . Quantum well and quantum barrier layers comprise a smaller thickness along the inclined sidewalls of the first plurality of cavities in comparison to substantially horizontal regions of the quantum well and quantum barrier layers . In some aspects , each of the first plurality of cavities is characterized by a hexagonal inverted pyramid .

[0028] In some aspects , the first doped layer, the second doped layer and the active region comprise nitride-based semiconductor material , in particular GaN . In other aspects , the semiconductor layers additionally or alternatively comprise other binary, ternary or quaternary nitrides The active region may comprise binary, ternary or quaternary nitride materials , in particular , GaN, InGaN, AlGaN and / or InAlGaN . In some aspects , the active region comprises a ternary nitride such as InGaN with the quantum barriers and quantum wells comprising different indium composition .

[0029] Some aspects of the optoelectronic device comprise cavities with lateral dimensions between 0 . 05 pm and 5 pm, in particular, between 0 . 1 pm and 0 . 5 pm. A lateral distance between each of the first plurality of cavities and an adj acent one of the first plurality of cavities is in some aspects between 0 . 5 pm and 20 pm, and in particular , between 1 pm and 5 pm.

[0030] The proposed optoelectronic device comprises in some aspect ' s lateral dimensions betweenl pm and 5 mm . 2024PF00419

[0031] While the exemplary aspects described herein focus on nitride-based semiconductor materials , the proposed invention is not limited thereto .

[0032] SHORT DESCRIPTION OF THE DRAWINGS

[0033] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0034] Figure 1 shows a partial top view of an optoelectronic device during an intermediate processing stage in accordance with some aspects of the proposed principle ;

[0035] Figures 2A to 2E illustrate steps in a method of manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;

[0036] Figure 3 shows an exemplary aspect of an optoelectronic device in accordance with some aspects of the proposed principle ;

[0037] Figures 4A to 4C illustrate some exemplary aspects of an optoelectronic device in accordance with some aspects of the proposed principle .

[0038] DETAILED DESCRIPTION

[0039] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea . 2024PF00419

[0040] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0041] Figure 1 shows a partial top view of an optoelectronic device during an intermediate processing stage ( 1 ) according to the proposed principle . The optoelectronic device , in particular, an LED device , comprises a first plurality of cavities ( 12 ) in the shape of inverted pyramids , particularly, hexagonal pyramids . A lateral dimension x of each of the first plurality of cavities ( 12 ) , in particular, measured across the broadest part of the cavity opening, is substantially equal . The first plurality of cavities is arranged in a regular lattice or matrix , such that a first lateral distance Px between proj ections of the centers of adj acent cavities along a first lateral axis is substantially constant for each of the first plurality of cavities , and a second lateral distance Py between proj ections of the centers of adj acent cavities along a second lateral axis is substantially constant for each of the first plurality of cavities . In some aspects , the first and second lateral distances Px and Py are equal . A density of the first plurality of cavities is configured to achieve a determined rate of carrier inj ection into the active region of the optoelectronic device , additionally taking into consideration the dimensions of each cavity for maximizing the device optoelectronic performance , in particular , the available surface area on the inclined sidewalls of the cavity as well as the area in between the cavities .

[0042] Some aspects of the proposed optoelectronic device further comprise a second plurality of cavities ( 14 ) , wherein the density, location and dimensions of the second plurality of cavities ( 14 ) is characterized by a random distribution . Each one of the second plurality of cavities is associated with a threading dislocation originating within the 2024PF00419 underlying semiconductor material and propagating along a direction of epitaxial growth and connected to a vertex of the cavity.

[0043] Some steps in the manufacture of an optoelectronic device in accordance with the proposed principle are illustrated in Figures 2A to 2E. In an initial step, shown in Figure 2A, a buffer layer (20) is provided. In some aspects, the buffer layer comprises a bulk GaN template. In other aspects, not illustrated herein, the buffer layer comprises a GaN sublayer deposited on a growth substrate, wherein the growth substrate comprises sapphire, silicon or any suitable material for epitaxial growth of semiconductor layers. Subsequently, a patterned mask (22) is deposited on a surface of the buffer layer (20) . In some aspects, the patterned mask comprises a plurality of regularly shaped, regularly distributed elements (22) of mask material, in particular, hexagonal or circular mask elements, arranged such that each mask element is laterally distanced from adjacent mask elements and preferably isolated from each other. In other aspects, the patterned mask comprises a plurality of regularly shaped, regularly distributed openings (21) surrounded by mask material (22) through which an upper surface of the buffer layer (20) is exposed. The openings may comprise any shape, in particular hexagonal or circular.

[0044] Thereafter, as illustrated in Figure 2B, a first semiconductor layer, in particular, a first doped layer (24) is deposited on the exposed upper surface of the buffer layer, above the patterned mask (22) . Initial epitaxial growth occurs vertically from the openings within the patterned mask (22) . As further deposition occurs, lateral growth of the first doped layer above adjacent material of the patterned mask (22) takes place, as shown in Figure 2C. The ratio of lateral to vertical expansion is such that inclined sidewalls (23) are formed, with the deposited semiconductor material initially forming elevated truncated pyramids in aspects comprising a plurality of mask openings surrounded by mask material, or any particular shape with inclined side walls in aspects comprising a plurality of isolated mask elements surrounded . 2024PF00419

[0045] Thereafter , further deposition of semiconductor material results in increased lateral growth, shown by arrows originating from the mas k opening ( 21 ) in Figure 2C , such that the semiconductor material grown from the non-mas ked areas partially coalesce , with a first plurality of cavities ( 12 ) in the form of inverted hexagonal pyramids forming along the plane of coalescence . Each of the first plurality of cavities is located above material of the patterned mas k . The location and distribution density of the first plurality of cavities is precisely controlled by suitably designing the patterned mas k . In some aspects , a lateral distance p between adj acent cavities ( 12 ) is constant . The dimensions of the cavities are controlled by suitable sizing of the openings in the patterned mask or the area of the mas k itself and / or adj ustment of process parameters , in particular, parameters determining the thickness h of the deposited material .

[0046] In some aspects , the initial deposition and cavity formation steps illustrated in Figures 2B and 2C involve depositing an undoped layer of semiconductor material , subsequently followed by deposition of a first doped layer on a surface of the laterally overgrown semiconductor layer . In other aspects , lateral overgrowth is performed using an undoped material , subsequently followed by introduction of a dopant , in particular, an n-dopant .

[0047] Additional sublayers of doped or undoped semiconductor material , in particular , comprising binary, ternary or quaternary nitrides , may be deposited thereafter . Additionally functional layers such as binary, ternary and quarternary super lattices are deposited such as but not limited to InxAlyGazN / InxAlyGazN .

[0048] In a subsequent step, an active region ( 25 ) is deposited on the surface of the first doped layer ( 24 ) . The active region comprises a multiquantum well structure , characterized by quantum well layers arranged between quantum barrier layers . During depositing of the active region, material deposited along inclined sidewalls of the first plurality of cavities ( 12 ) forms thinner layers in comparison to material deposited on substantially horizontally aligned planes . In some aspects , an electron blocking layer comprising p-doped semiconductor material is 2024PF00419 subsequently deposited on a surface of the active region facing away from the first doped layer . The electron blocking layer confines charge carriers originating from the first doped layer, improving the lifetime of the optoelectronic device . Such an electron blocking layer is in some aspects configured as a superlattice . Other configurations of the electron blocking layer, including but not limited to a simple AlGaN layer, or a graded layer may be implemented . In other aspects , a superlattice is deposited between the first doped layer and the active region, wherein the superlattice may comprise n-doped semiconductor material .

[0049] A second doped layer ( 26 ) is thereafter deposited on a surface of the active region ( 25 ) , filling in the first plurality of cavities ( 12 ) . In some aspects , the material of the second doped layer is deposited such that a substantially planar upper surface is formed facing away from the active region . In other aspects , for example , as illustrated in Figure 3 , the second doped layer is deposited such that the second doped layer comprises the first plurality of cavities .

[0050] Figures 4A to 4C illustrate variations in the manufacturing process of an optoelectronic device according to the proposed principle . In some aspects , a maximum thickness hmaxof the first doped or undoped layer is achieved during the lateral overgrowth process by terminating epitaxial growth as soon as or shortly after laterally expanding facets make contact above the patterned mas k, such that a minimal thickness of first doped or undoped layer material forms the bottoms of the first plurality of cavities . The first plurality of cavities formed in this manner are characterized by a maximum achievable cavity depth dmaxusing the proposed process , with the depth of the first plurality of cavities within the first doped layer substantially equal to the thickness hoptof the first doped or undoped layer above the patterned mask .

[0051] In other aspects , illustrated in Figure 4B , by continuation of overgrowth using growth conditions suitable for coalescence a desired cavity depth d2smaller than the maximum achievable depth dmaxis achieved . The dimensions of the first plurality of cavities are in other aspects configured through suitable dimensioning of the lateral 2024PF00419 15 dimensions Lopening and the lateral dimensions Lmaskof the mask openings or deposited mas k area . Larger openings combined with smaller areas of mask material between adj acent openings , as illustrated in Figure 4C , result in cavities with smaller dimensions , and / or allows more rapid 5 processing of the optoelectronic devices , as a smaller thickness of the first doped layer is required to achieve the desired cavity dimensions . Conversely, smaller mask openings combined with larger areas of mas k material results in deeper cavities , allowing a larger thickness of the first doped layer to be grown before lateral overgrowth0 leads to coalescence of expanding growth facets .

[0052] 2024PF00419 16

[0053] LIST OF REFERENCES

[0054] 1 optoelectronic device

[0055] 12 cavity

[0056] 5 14 unintentionally opened v-pit

[0057] 20 buffer layer

[0058] 21 mask opening

[0059] 22 patterned mask

[0060] 23 inclined sidewalls of first doped layer0 24 first doped layer

[0061] 25 active region

[0062] 26 second doped layer cavity depth h, h2, hmaxthickness of first doped layer lateral dimension of mas k opening lateral dimension of mas k material

[0063] P, Px, Py lateral distance between adj acent cavities

Claims

2024PF00419CLAIMS1 . Optoelectronic device comprising :A first doped or undoped layer ( 24 ) ; an active region ( 25 ) arranged on a surface of the first doped or undoped layer ; a second doped layer ( 26 ) arranged on a surface of the active region facing away from the first doped or undoped layer ; wherein at least the first doped or undoped layer and the active region comprise a first plurality of cavities comprising inclined sidewalls , and wherein a vertex of each of the first plurality of cavities facing away from the second doped layer is laterally and optionally vertically distanced from threading dislocations in the first doped layer and / or the active region .2 . Device according to claim 1 , wherein a surface of the second doped layer facing away from the active region is substantially planar .3 . Device according to claim 1 , wherein a surface of the second doped layer facing away from the active region comprises the first plurality of cavities .4 . Device according to any of the preceding claims , wherein the first doped layer comprises at least some threading dislocations , wherein at least some of the threading dislocations are characterized by a change in the direction of propagation, and / or wherein at least some of the threading dislocations terminate below an upper surface of the first doped layer adj acent to the active region .5 . Device according to any of the preceding claims , further comprising at least one superlattice arranged at least at one of :Between the first doped layer and the active region;Between the active region and the second doped layer .6 . Device according to any of the previous claims , further comprising a second plurality of cavities , wherein a vertex of each of the second plurality of cavities is located above a threading2024PF00419 dislocation, particularly originating from the substrate , and / or wherein at least one of the location, density of the second plurality of cavities is characterized by a random distribution .7 . Device according to any of the preceding claims , wherein the first plurality of cavities is arranged to form a regular matrix .8 . Device according to any of the preceding claims , wherein a lateral dimension of each of the first plurality of cavities measured along an arbitrary axis perpendicular to the direction of epitaxial growth is between 0 . 05 pm and 5 pm, in particular , between 0 . 1pm and 0 . 5 pm.9 . Device according to any of the preceding claims comprising lateral dimensions between 1 pm and 5 mm.10 . Device according to any of the preceding claims , wherein a lateral distance between each one of the plurality of cavities and an adj acent one of the plurality of cavities along a first axis perpendicular to the direction of epitaxial growth is substantially constant .11 . Device according to any of the preceding claims , wherein the lateral distance between adj acent cavities along at least one axis is between 0 . 5 pm and 20 pm, in particular , between 1 pm and 5 pm .12 . Device according to any of the preceding claims , wherein a density of cavities in the first doped layer is configured to correspond to a determined rate of carrier inj ection into the active region .13 . Device according to any of the preceding claims , further comprising a patterned structure located beneath the first doped layer and the plurality of cavities , wherein optionally the patterned structure is SiO2 and / or SiN .14 . Method of processing an optoelectronic device , comprising the steps : Providing a buffer layer on a growth substrate ;Arranging a patterned mas k on a surface of the buffer layer, said patterned mas k comprising a plurality of isolated openings arranged in a regular pattern or comprising a plurality of2024PF00419 isolated mas k elements surrounded by openings devoid of mas k material and arranged in a regular pattern;Depositing a first doped layer on an upper surface of the buffer layer through the plurality of openings in the patterned mask, such that a first plurality of cavities are formed above material of the patterned mask, said cavities comprising inclined sidewalls ;Depositing an active region on a surface of the first doped layer facing away from the buffer layer, such that an upper surface of the active region comprises the first plurality of cavities with inclined sidewalls ;Depositing a second doped layer on a surface of the active region facing away from the first doped layer .15 . Method according to claim 14 , wherein the step of depositing a first doped layer on an upper surface of the buffer layer comprises the steps :-Depositing an initial undoped layer on the upper surface of the buffer layer, such that a first plurality of cavities is formed above material of the patterned mask, said cavities comprising inclined sidewalls ;-Depositing at least one subsequent doped layer on the surface of the initial undoped layer , such that an upper surface of the at least one subsequent doped layer comprises the first plurality of cavities .16 . Method according to claim 14 , wherein the step of depositing a first doped layer on an upper surface of the buffer layer comprises the steps :Depositing an initial undoped layer on the upper surface of the buffer layer, such that a first plurality of cavities i formed above material of the patterned mask, said cavities comprising inclined sidewalls ;Introducing a dopant into the initial undoped layer such that at least part of the initial undoped layer comprises doped semiconductor material .2024PF00419 2017 . Method according to any of the preceding claims , wherein the plurality of openings in the patterned mask or the plurality of isolated mask elements comprise one of the following :Circular;Hexagonal ;Triangle ; andRectangular .18 . Method according to any of the preceding claims 14 to 17 , wherein the step of depositing a second doped layer comprises depositing a substantially uniform thickness of semiconductor material such that the second doped layer comprises the first plurality of cavities .19 . Method according to any of the preceding claims 14 to 17 , wherein the step of depositing a second doped layer further comprises planarizing a surface of the second doped layer facing away from the active region .20 . Method according to any of claims 14 to 19 , wherein the step of depositing a first doped or undoped layer comprises a first deposition step with a first set of process parameters , and at least one second deposition step with a second set of different process parameters .21 . Method according to claim 20 , wherein the first deposition step comprises vertically and laterally growing the first doped or undoped layer to form a plurality of pyramid-shaped protrusions around the mask openings or any particular shape with inclined side walls above the non-mas ked areas , and wherein the at least one second deposition step comprises laterally expanding the first doped layer with minimal vertical growth to achieve partial coalescence of laterally expanding growth facets .22 . Method according to any of claims 14 to 21 , further comprising a step of depositing a superlattice at least at one of the following : Between the first doped layer and the active region; Between the active region and the second doped layer .2024PF00419 - 21 -23 . Method according to any of claims 14 to 22 , wherein the growth substrate comprises one of sapphire , GaN or silicon and / or wherein the buffer layer comprises GaN or InGaN or AlGaN .

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