Electronic apparatus, solid-state imaging device, and control method

Abstract

[Problem] To determine a weak sunspot. [Solution] An electronic apparatus comprises a first capacitor, a second capacitor, a comparator, a first switch, and a second switch. The first capacitor includes a first end connected to a reference signal output circuit that outputs a reference signal. The second capacitor includes a first end connected to a pixel that outputs an electric signal and includes a light-receiving element. The comparator includes a first input end connected to a second end of the first capacitor, and a second input end connected to a second end of the second capacitor, and compares the reference signal with the electric signal. The first switch is connected to the first end of the first capacitor and the second end of the first capacitor. The second switch is connected to the first end of the second capacitor and the second end of the second capacitor.

Description

Electronic device, solid-state imaging device, and control method

[0001] The present disclosure relates to an electronic device, a solid-state imaging device, and a control method.

[0002] This solid-state imaging device often uses, for example, a complementary metal oxide semiconductor (CMOS) sensor. CMOS sensors have an analog-to-digital converter (ADC) that converts the analog signal output from pixels with light-receiving elements into a digital signal. To obtain this digital signal, correlated double sampling (CDS) is used to suppress reset noise from the amplifier transistors that output the pixel. This readout is performed twice, during the reset period and the data period, and compared with a ramp signal to obtain the difference between them.

[0003] To prevent the occurrence of sunspots, a phenomenon in which the output from a pixel that receives light from a high-brightness object in a captured image turns black, one method is to clamp the output value from the pixel when the reset signal in the CDS is read out, thereby preventing the output from the pixel from crossing the ramp signal during the reset period and preventing the occurrence of sunspots.

[0004] However, if the signal leaks to the extent that it crosses the reset level due to carriers leaking into the floating diffusion region after a reset known as a weak sunspot, the ramp signal and the analog signal from the pixel may cross during the reset period, making it impossible to obtain a brightness value as an appropriate digital signal.

[0005] In addition, pixel source followers are generally composed of n-type transistors such as n-type Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), which can only clamp the signal in the direction that decreases its DC level, making them difficult to use with Hall sensors such as short-wave infrared (SWIR) sensors.

[0006] Japanese Patent Publication No. 2020-28117

[0007] Therefore, one non-limiting problem that the embodiments of the present disclosure aim to solve is to reduce false detection of weak sunspots. The problem that the embodiments of the present disclosure aim to solve can also be, as some further non-limiting examples, a problem corresponding to the effects described in the embodiments. In other words, a problem that corresponds to at least one of the effects described in the description of the embodiments of the present disclosure can be considered to be a problem that the present disclosure aims to solve.

[0008] According to one embodiment, an electronic device includes a first capacitor, a second capacitor, a comparator, a first switch, and a second switch. The first capacitor has a first terminal connected to a reference signal output circuit that outputs a reference signal. The second capacitor has a first terminal connected to a pixel that outputs an electrical signal and has a light receiving element. The comparator has a first input terminal connected to the second terminal of the first capacitor and a second input terminal connected to the second terminal of the second capacitor, and compares the reference signal with the electrical signal. The first switch is connected to the first terminal of the first capacitor and the second terminal of the first capacitor. The second switch is connected to the first terminal of the second capacitor and the second terminal of the second capacitor.

[0009] The reference signal output circuit includes a digital-to-analog converter (DAC) and can output a ramp signal that is an analog signal.

[0010] The device may further include a counter connected to the output terminal of the comparator and counting the time required for the reference signal to change until the electrical signal matches the reference signal based on a comparison result between the reference signal and the electrical signal.

[0011] The counter may count the electrical signal when the floating diffusion region of the pixel is reset, and may count the electrical signal when carriers acquired by the light receiving element through light reception are accumulated in the floating diffusion region.

[0012] The first switch and the second switch may be turned on at a timing before the floating diffusion region of the pixel is reset, and may be turned off at a timing before the floating diffusion region is reset.

[0013] The first switch and the second switch may be turned on at a timing before the first input terminal and the second input terminal of the comparator are reset, and may be turned off at a timing before the first input terminal and the second input terminal are reset.

[0014] At the input or output terminal of the counter, if the electrical signal is at a first level when the first switch and the second switch are turned on, it may be determined that the electrical signal does not indicate a saturated brightness value, and if the electrical signal is at a second level when the first switch and the second switch are turned on, it may be determined that the electrical signal indicates a saturated brightness value.

[0015] The first level may be a voltage level when the floating diffusion region is in a reset state, and the second level may be a voltage level when the floating diffusion region is in a saturated state.

[0016] According to one embodiment, a solid-state imaging device uses any of the electronic devices described above to obtain the luminance values ​​of the pixels as digital signals, thereby obtaining image information.

[0017] According to one embodiment, a control method is provided for an electronic device comprising: a first capacitor having a first terminal connected to a reference signal output circuit that outputs a reference signal; a second capacitor having a first terminal connected to a pixel that outputs an electrical signal and has a light receiving element; a comparator having a first input terminal connected to a second terminal of the first capacitor and a second input terminal connected to the second terminal of the second capacitor, and comparing the reference signal with the electrical signal; a first switch connected to the first terminal of the first capacitor and the second terminal of the first capacitor; and a second switch connected to the first terminal of the second capacitor and the second terminal of the second capacitor;

[0018] It may be determined whether or not the acquired electrical signal indicates a saturated brightness value based on the value of the electrical signal acquired between when the first switch and the second switch are turned on and when they are turned off.

[0019] FIG. 1 is a block diagram schematically showing an example of a solid-state imaging device according to an embodiment. FIG. 2 is a diagram schematically showing a semiconductor substrate on which a solid-state imaging device according to an embodiment is mounted. FIG. 3 is a diagram schematically showing a semiconductor substrate on which a solid-state imaging device according to an embodiment is mounted. FIG. 4 is a circuit diagram showing an outline of a partial configuration of an ADC according to an embodiment. FIG. 5 is a circuit diagram showing an outline of a non-limiting example of a pixel according to an embodiment. FIG. 6 is a diagram showing an example of a timing chart of a solid-state imaging device according to an embodiment. FIG. 7 is a diagram showing an example of timing in the case of a shortest shutter according to an embodiment. FIG. 8 is a diagram showing an example of timing in the case of a shortest shutter according to an embodiment.

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0021] 1 is a diagram showing a portion of a solid-state imaging device (image sensor) according to an embodiment. The solid-state imaging device 1 includes at least a first driving circuit 10, a second driving circuit 12, a pixel array 14, an analog-to-digital conversion circuit (hereinafter referred to as ADC 16), and a logic circuit 18.

[0022] The solid-state imaging device 1 may have a configuration in which some of these components are omitted, or may optionally include other necessary components. For example, the solid-state imaging device 1 may include elements such as a control circuit that controls each component, a power supply circuit that supplies power to each component, an input / output interface that inputs and outputs signals, and a memory circuit that temporarily or non-temporarily stores data.

[0023] The first drive circuit 10 is a circuit that selects which line of the pixel array 14 the pixels 140 in the pixel array 14 belong to and are to be put into a drivable state. The first drive circuit 10 applies signals that put the pixels 140 in a drivable state to the pixels 140 in the respective lines via signal lines 100 arranged along the line direction.

[0024] The second drive circuit 12 is a circuit that controls which column of pixels 140 should be output from among the pixels 140 that belong to a line selected by the first drive circuit 10 provided in the pixel array 14. The solid-state imaging device 1 outputs from the pixels 140 that belong to a column specified by the second drive circuit 12 in a line that has been selected and is in a drivable state by the first drive circuit 10. The second drive circuit 12 applies signals that drive the pixels 140 that belong to each column to output pixel signals via signal lines 120 arranged along the column direction.

[0025] The pixel array 14 is an area in which pixels 140 are arranged. The pixels 140 are arranged in a two-dimensional array along the line direction and column direction within the pixel array 14. Each pixel 140 has a light receiving element, performs photoelectric conversion on light incident on the pixel 140, and outputs an analog signal based on the intensity of the incident light. Each pixel 140 has a pixel circuit that outputs a signal photoelectrically converted by the light receiving element.

[0026] The signal output from each pixel 140 is output to the ADC 16 via a signal line 160 arranged for each column or for each pixel, for example. That is, the ADC 16 may be a conversion circuit provided for each column or for each pixel. As another example, the ADC 16 may be a conversion circuit provided for each region other than a column in the pixel array 14.

[0027] The ADC 16 is a circuit that converts the analog signal output from the pixel 140 into a digital signal and outputs the digital signal. The ADC 16 converts the analog signal into a digital signal by, for example, comparing the analog signal output from the pixel 140 with a ramp signal that is a reference signal, and counting the time from when the ramp signal starts to be output to when the signal resulting from the comparison is inverted.

[0028] The digital signal generated by the ADC 16 is output to the logic circuit 18. The logic circuit 18 performs various processes on the digital signal and then outputs image data. The logic circuit 18 can also perform, for example, color adjustment, signal processing, image processing, and optionally machine learning processing to generate image data or perform recognition processing.

[0029] FIG. 2 is a diagram showing an example of the arrangement of a pixel array 14 and an ADC 16 according to an embodiment. The solid-state imaging device 1 may be formed as a semiconductor substrate 2 having a portion stacked thereon. As an example, the solid-state imaging device 1 is mounted on a semiconductor substrate 2 having a first substrate 20 and a second substrate 22 stacked thereon. Note that a stacked structure of three or more layers is not excluded. For example, other layers including a memory circuit or a logic circuit 18 may be stacked thereon. The logic circuit 18 may be arranged on the same layer as the ADC 16.

[0030] These substrates may be stacked by any method, such as chip-on-chip (CoC), chip-on-wafer (CoW), or wafer-on-wafer (WoW). Connection between layers may be made by any method, such as via holes or micro-dumps. The signal lines 160 connecting between layers may be made of, for example and without limitation, metals such as Cu, Ag, Au, and Al, or alloys or compounds of these or other materials.

[0031] The first substrate 20 includes at least a pixel array 14. The pixel array 14 outputs a signal based on the intensity of incident light output from each pixel circuit to a signal line 160 provided for each column, and the analog signal is propagated to the second substrate 22 via the signal line provided for each column.

[0032] The second substrate 22 includes at least the ADC 16. The ADC 16 can include a column ADC 162 for each signal line 160 for each column in the pixel array 14. Note that a configuration in which one column ADC 162 is provided for multiple columns, or a configuration in which multiple column ADCs 162 are provided for one column, may also be used.

[0033] The column ADC 162 converts analog signals output from the pixels 140 belonging to the column into digital signals and outputs them, and image data is formed in the subsequent logic circuit.

[0034] 3 is a diagram showing another example of the arrangement of a pixel array 14 and an ADC 16 according to an embodiment. The solid-state imaging device 1 is formed as a semiconductor substrate 2 in which a first substrate 20 and a second substrate 22 are stacked, as in FIG.

[0035] 3, the ADC 16 is configured to include a pixel ADC 164 provided for each pixel 140. The pixel ADC 164 converts the analog signal output via the signal line 160 for each corresponding pixel 140 into a digital signal and outputs the digital signal.

[0036] Although the above example shows a case where a column ADC and a pixel ADC are provided, the configuration of the solid-state imaging device 1 in the present disclosure is not limited to this. For example, the solid-state imaging device 1 may be configured such that the pixel array 14 is divided into multiple areas and an area ADC is provided for each area, or may be configured such that an ADC processes outputs from any number of pixels 140.

[0037] Furthermore, without being limited to the above, the solid-state imaging device 1 may be formed of one semiconductor layer, or may be formed by laminating three or more semiconductor layers.

[0038] Next, the configuration of an ADC that appropriately detects weak sunspots in this disclosure will be described.

[0039] FIG. 4 is a circuit diagram illustrating a portion of the ADC 16 according to an embodiment, particularly a comparator included in the ADC 16. The comparator 170 is included in the ADC 16 (e.g., the column ADC 162 or the pixel ADC 164) and compares a reference signal with an electrical signal output from a pixel and outputs a comparison result. The comparator 170 includes, for example, transistors M1, M2, M3, M4, M5, M6, and a current source I1. The comparator 170 compares signals input via capacitors C1 and C2. The discharge of capacitors C1 and C2 is controlled by switches SW1 and SW2, respectively.

[0040] In this disclosure, for convenience, the capacitor C1, the capacitor C2, the switch SW1, and the switch SW2 are configured to be provided outside the comparator 170, but this is not limited to this. For example, in a broad sense, the comparator 170 may be configured to include the capacitor C1, the capacitor C2, the switch SW1, and the switch SW2. These are issues of delimiting names and are not related to the essential configuration of the present disclosure.

[0041] The reference signal line REF is a signal line connected to a reference signal output circuit that outputs a reference signal. The reference signal output circuit (not shown) is a circuit that outputs a reference signal for converting an analog signal into a digital signal, and is configured, for example, with a digital-to-analog conversion circuit (DAC) for generating the reference signal Vref. The reference signal output circuit can generate a ramp signal, which is an analog signal, as a reference signal to be used in CDS.

[0042] The input signal line VSL is a signal line that connects to an analog electrical signal output from the pixel 140. The pixel 140 has a light receiving element, and outputs an analog signal Vsl having an intensity corresponding to the received light to the comparator 170 via the input signal line VSL. As described above, an electrical signal is output from each pixel 140 in the pixel array 14 to the comparator 170 corresponding to that pixel 140 at a timing based on the control of the first drive circuit 10 and the second drive circuit 12.

[0043] The capacitor C1 is connected to the input terminal of the reference signal, and has a first terminal connected to the reference signal line REF and a second terminal connected to the driving terminal (gate) of the transistor M1. The capacitor C1 forms, for example, a sampling capacitance for the reference signal.

[0044] The capacitor C2 is a capacitor connected to the input terminal of the electrical signal, with a first terminal connected to the input signal line VSL and a second terminal connected to the driving terminal (gate) of the transistor M2. The capacitor C2 forms, for example, a sampling capacitance for the input signal.

[0045] The comparator 170 has a first input terminal formed by a gate of a transistor M1, to which a reference signal is input via a capacitor C1, and a second input terminal formed by a gate of a transistor M2, to which an electrical signal is input via a capacitor C2.

[0046] The transistor M1 is, for example, an n-type MOSFET, and has a gate connected to the second terminal of the capacitor C1, a first terminal (drain) connected to the second terminal of the transistor M3, and a second terminal (source) connected to the current source I1. The transistor M1 operates as a first input terminal of the comparator 170. The transistor M1 generates a drain current based on a reference signal Vref applied to its gate.

[0047] The transistor M2 is, for example, an n-type MOSFET, and has a gate connected to the second terminal of the capacitor C2, a first terminal (drain) connected to the second terminal of the transistor M4, and a second terminal (source) connected to the current source I1. The transistor M2 operates as the second input terminal of the comparator 170. The transistor M2 generates a drain current based on the electrical signal Vsl applied to its gate.

[0048] The sources of the transistors M1 and M2 are connected to the negative power supply voltage line VSS (which may be a power supply voltage line for applying a ground voltage) via a current source I1, and the drain currents of the transistors M1 and M2 may be controlled by this current source I1.

[0049] The transistor M3 is, for example, a p-type MOSFET, and has a gate connected to the gate of the transistor M4, a first terminal (source) connected to the positive power supply voltage line VDD, and a second terminal (drain) connected to the drain of the transistor M1. The gate of the transistor M3 is also connected to the drain.

[0050] The transistor M4 is, for example, a p-type MOSFET, and has a gate connected to the gate of the transistor M3, a first terminal (source) connected to the positive power supply voltage line VDD, and a second terminal (drain) connected to the drain of the transistor M2.

[0051] The transistors M1 to M4 constitute a commonly known comparator circuit with the above configuration. The drains of the transistors M2 and M4 are connected to the output signal line OUT, and the comparison result between the reference signal Vref and the electrical signal Vsl is output from this connection node.

[0052] The transistor M5 is, for example, a p-type MOSFET, and has a first terminal (source) connected to the drain of the transistor M1 and a second terminal (drain) connected to the gate of the transistor M1. That is, when the transistor M5 is turned on, it sets the drain and gate potentials of the transistor M1 to the same potential.

[0053] The transistor M6 is, for example, a p-type MOSFET, and has a first terminal (source) connected to the drain of the transistor M2 and a second terminal (drain) connected to the gate of the transistor M2. That is, when the transistor M6 is turned on, it sets the drain and gate potentials of the transistor M2 to the same potential.

[0054] The same signal Vaz is applied to the gates of the transistors M5 and M6, and the transistors M5 and M6 operate as transistors that initialize the potentials of the gates of the transistors M1 and M2 at appropriate timings under the control of the signal Vaz.

[0055] The switch SW1 is connected between the first and second terminals of the capacitor C1. When the switch SW1 is turned on, it shorts both ends of the capacitor C1, making the potentials at both ends of the capacitor C1 the same. In other words, while the switch SW1 is on, it applies the absolute value of the reference signal Vref input from the reference signal line REF to the gate of the transistor M1.

[0056] The switch SW2 is connected between the first and second terminals of the capacitor C2. When the switch SW2 is turned on, it shorts both ends of the capacitor C2, making the potentials at both ends of the capacitor C2 the same. In other words, while the switch SW2 is on, it applies the absolute value of the electrical signal Vsl input from the input signal line VSL to the gate of the transistor M2.

[0057] Switches SW1 and SW2 turn on and off in sync. With these connections, while switches SW1 and SW2 are on, the difference in absolute value between reference signal Vref and electrical signal Vsl can be output from output signal line OUT.

[0058] The output signal line OUT is connected to, for example, a logic circuit (including a counter) not shown, and this logic circuit generates a digital signal corresponding to the intensity of light received by the pixel 140 based on the comparison result between the reference signal Vref, which is the output from the comparator 170, and the electrical signal Vsl. The counter counts, for example, the time required for the reference signal to change until the reference signal Vref and the electrical signal Vsl match, and generates a digital signal corresponding to the electrical signal Vsl, which is an analog signal, using the CDS technique.

[0059] The configuration of the comparator 170 is shown as a non-limiting example and is not limited to the circuit diagram of Fig. 4. For example, a comparator in which the transistors M1 and M2 are p-type MOSFETs connected to the power supply voltage line VDD via a current source, and the transistors M3 and M4 are n-type MOSFETs connected to the power supply voltage line VSS can also be configured to include a switch SW1 for the capacitor C1 and a switch SW2 for the capacitor C2, thereby achieving the same effect.

[0060] More specifically, the counter counts the electrical signal Vsl when the floating diffusion region of the pixel 140 is reset and when the carriers acquired by the light receiving element through light reception are accumulated in the floating diffusion region, and generates a digital signal corresponding to the intensity of the received light using the CDS method.

[0061] 5 is a diagram showing an example of a pixel 140 according to one embodiment. This diagram is a circuit diagram shown as a simple example to explain the operation of the comparator 170 described above, but the configuration of the pixel 140 is not limited to this example, and the processing in this disclosure can be applied to various forms of pixel circuits that are widely and commonly used.

[0062] The pixel 140 includes a light-receiving element P, a transfer gate TRG, a floating diffusion region FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

[0063] The light receiving element P is, for example, a light receiving element including a photoelectric conversion element, and outputs an analog signal based on the intensity of the received light.

[0064] The transfer gate TRG is a transistor that turns on / off based on a signal from the second drive circuit 12 applied to its gate via a signal line 120, and transfers the signal output from the light receiving element P to the floating diffusion region FD at the appropriate timing.

[0065] The floating diffusion region FD is a region that applies a voltage based on the carriers output from the light-receiving element P and transferred by the transfer gate TRG to the gate of the amplifier transistor AMP.

[0066] The reset transistor RST is a transistor that resets the voltage stored in the floating diffusion region FD at the appropriate time by applying a reset voltage Vrst to its gate. When the reset transistor RST turns on, the potential of the floating diffusion region FD is reset.

[0067] The amplifier transistor AMP is a transistor in which a voltage due to the accumulated carriers in the floating diffusion region FD is applied to the gate, and a drain current corresponding to the voltage applied to the gate, i.e., the strength of the signal transferred to the floating diffusion region FD, flows.

[0068] The selection transistor SEL is a transistor that turns on / off based on a signal from the first drive circuit 10 applied to its gate via a signal line 100, and selects the drive state for each line to output the drain current of the amplification transistor AMP to the signal line 160 (input signal line VSL).

[0069] At the appropriate timing when the select transistor SEL is off, the floating diffusion region FD is reset by the reset transistor RST and transitions to the initial state, at which point the ADC 16 (counter) acquires a count value corresponding to the reset phase signal.

[0070] For example, in a pixel 140 selected by the first drive circuit 10 via the signal line 100, an analog signal based on the intensity of light received by the light receiving element P is output from the amplifying transistor AMP to the ADC 16 via the input signal line VSL at the timing when the second drive circuit 12 transfers the signal via the signal line 120. At this timing, the ADC 16 and the counter acquire a count value corresponding to the data read phase.

[0071] From the count value in the reset phase and the count value in the data readout phase, the logic circuit (including a counter) can obtain the intensity value of light received by each pixel by the CDS as digital data.

[0072] As described above, the configuration of the pixel 140 is not limited to this. As another non-limiting example, the pixel 140 may have a configuration that can realize global shutter processing. In this case, the leakage of carriers from the light-receiving element P to the floating diffusion region FD via the transfer gate TRG in the following description can be interpreted as the leakage of carriers from the memory region to the floating diffusion region FD via the transfer gate TRG.

[0073] 6 is a timing diagram for the pixel 140 and the comparator 170. As an example, processing for adjacent lines belonging to the same column using the column ADC 162 is shown.

[0074] AVS is a signal for switching switches SW1 and SW2. Vrst and Vaz are signals for switching the reset transistor RST in FIG. 5 and transistors M5 and M6 in FIG. 4, respectively. Vref (dotted line) indicates the voltage applied to the gate of transistor M1, and Vsl (solid line) indicates the voltage applied to the gate of transistor M2. Vout indicates the potential output from the output signal line OUT.

[0075] First, in processing the n-th line, AVS is turned on, and the switches SW1 and SW2 are turned on, so that both ends of the capacitors C1 and C2 have the same potential.

[0076] At this timing, light of an intensity other than sunlight is incident on the photosensitive element P of the pixel 140 on the nth line, so no signal leaks from the photosensitive element P to the floating diffusion region FD via the transfer gate TRG. As a result, the voltage Vsl applied to the gate of transistor M2 becomes the reset phase level. The voltage Vref applied to the gate of transistor M1 becomes the potential of the reference voltage Vref output by the reference signal output circuit.

[0077] The output voltage Vout outputs a value indicating Vsl > Vref (a value corresponding to the first level) while the switches SW1 and SW2 are on. In this case, by referring to this signal, the counter and logic circuit can detect that the pixel 140 on the nth line is not receiving a signal that results in a sunspot.

[0078] The first level indicates the voltage level of the electrical signal Vsl when the floating diffusion region FD is in a reset state.

[0079] The subsequent processing involves turning off switches SW1 and SW2, and then turning on reset transistor RST, transistor M5, and transistor M6, as in the normal CDS method, to reset floating diffusion region FD and capacitors C1 and C2, and then performing counting processing using the counter.

[0080] At this time, the switches SW1 and SW2, the reset transistor RST, the transistor M5, and the transistor M6 are controlled so as not to be turned on at the same time, i.e., AVS is controlled so as not to be turned on at the same time as at least one of Vrst and Vaz.

[0081] The pixel 140 on the next (n+1)th line receives a signal that may indicate a sunspot (including a weak sunspot). In this case, carriers are flowing into the floating diffusion region FD from the light-receiving element P via the transfer gate TRG. Therefore, when AVS is turned on, that is, when switches SW1 and SW2 are turned on, the value of the electrical signal Vsl reaches a level at which the floating diffusion region FD is saturated.

[0082] The output voltage Vout outputs a value indicating Vsl < Vref (a value corresponding to the second level) while the switches SW1 and SW2 are on. By referring to this result, the counter and logic circuit can detect that the pixel 140 on the (n+1)th line is receiving light of such a high intensity that the floating diffusion region FD is saturated.

[0083] The second level indicates the voltage level of the electrical signal Vsl when the floating diffusion region FD is saturated.

[0084] The subsequent processing may or may not involve counting using a counter, as in the case of a normal CDS method. When the logic circuit obtains the result of this comparison, it determines that the pixel 140 is a (weak) sunspot, and therefore it can set the intensity of the light received by this pixel 140 to the maximum value.

[0085] That is, the solid-state imaging device 1 turns on the switches SW1 and SW2 to acquire the value of the electrical signal Vsl before reading the electrical signal Vsl for each pixel 140, and then turns off the switches SW1 and SW2 to perform CDS processing. By performing this control, the solid-state imaging device 1 can acquire the output signal Vout as shown in FIG.

[0086] As described above, according to this embodiment, by providing a switch that connects both ends of the sampling capacitor at the input terminal of the comparator 170, it is possible to determine whether carriers, which indicate that the light receiving element P has received high-intensity light that could cause sunspots, are leaking into the floating diffusion region FD by appropriately controlling this switch. Using this result, it is possible to appropriately detect sunspots, including weak sunspots.

[0087] Furthermore, although the above describes the case where the carriers are electrons, the method disclosed herein also makes it possible to appropriately detect sunlight, including weak sunlight, by using a similar configuration when the carriers are holes.

[0088] The comparator 170 including the capacitor C1, the capacitor C2, the switch SW1, and the switch SW2 can be implemented as an electronic device as a comparator. By including the electronic device, the solid-state imaging device 1 can acquire the luminance value of an appropriate pixel as a digital signal and acquire image information.

[0089] For the above process to be performed properly, the reference voltage Vref must be properly defined. This reference voltage Vref will be explained below.

[0090] Figure 7 shows an example of the shortest shutter speed in one embodiment, where the period from shutter release to data readout corresponds to one CDS period. The dynamic range of the floating diffusion region FD can be set to 1.6 V, as a non-limiting example. In the case of weak sunlight, the electrical signal Vsl resulting from the potential of the floating diffusion region FD gradually changes due to leakage from the transfer gate TRG on the light-receiving element P side.

[0091] Assume that Qs is 800 mV at the readout timing. The time from the shutter timing to the auto-zero timing can be approximately 10 μsec, and the time from the auto-zero timing to the data readout phase can be approximately 5 μsec.

[0092] The voltage Vb, which is the minimum potential difference during the readout phase, should be around 800 mV. In this case, during the reset and data readout period, the sun will be detected if the voltage Va of the reference signal Vref and electrical signal Vsl at the auto-zero timing is (1.6 V - 0.8 V) ÷ 15 μsec × 10 μsec = 533 mV or greater.

[0093] By setting the determination below this threshold, it is possible to prevent false detections when the sun is weak.

[0094] FIG. 8 is a timing diagram for considering variations in the threshold voltage of the amplifier transistor AMP in the pixel 140. In the case of FIG. 7, we consider whether Va can be determined by subtracting 533 mV = ΔVsl. The comparison voltage to be considered depends on the output from each pixel 140, and variations in this output are largely dependent on variations in the electrical signal Vsl. This variation is caused by variations in the threshold voltage AVT of the amplifier transistor AMP in the pixel 140.

[0095] If the AVT variation is 1σ = 50 mVrms, when the reference signal Vref is lowered by AVT 3σ = ΔVref = 150 mV on one side of the normal reset phase of the electrical signal Vsl (for example, 2.7 V), it is possible to properly determine the sun even for pixels where the electrical signal Vsl is originally 3σ higher.

[0096] As described above, by setting an appropriate determination level, it is possible to appropriately detect sunspots including weak sunspots.

[0097] The above-described embodiment may be modified as follows.

[0098] (1) An electronic device comprising: a first capacitor having a first end connected to a reference signal output circuit that outputs a reference signal; a second capacitor having a first end connected to a pixel that outputs an electrical signal and has a light receiving element; a comparator having a first input end connected to a second end of the first capacitor and a second input end connected to a second end of the second capacitor, and comparing the reference signal with the electrical signal; a first switch connected to the first end of the first capacitor and the second end of the first capacitor; and a second switch connected to the first end of the second capacitor and the second end of the second capacitor.

[0099] (2) The electronic device according to (1), wherein the reference signal output circuit includes a digital-to-analog converter (DAC) and outputs the ramp signal, which is an analog signal.

[0100] (3) The electronic device according to (2), further comprising: a counter connected to the output terminal of the comparator, which counts the time required for the reference signal to change until the electrical signal matches the reference signal based on a comparison result between the reference signal and the electrical signal.

[0101] (4) The electronic device described in (3), wherein the counter counts the electrical signal at the timing when the floating diffusion region of the pixel is reset, and counts the electrical signal at the timing when carriers acquired by the light receiving element through light reception are accumulated in the floating diffusion region.

[0102] (5) The electronic device according to (4), wherein the first switch and the second switch are turned on and off at a timing before the floating diffusion region of the pixel is reset.

[0103] (6) The electronic device according to (4) or (5), wherein the first switch and the second switch are turned on at a timing before the first input terminal and the second input terminal of the comparator are reset, and are turned off at a timing before the first input terminal and the second input terminal are reset.

[0104] (7) An electronic device according to (5) or (6), wherein, at the input or output terminal of the counter, if the electrical signal is at a first level when the first switch and the second switch are turned on, it is determined that the electrical signal does not indicate a saturated brightness value, and if the electrical signal is at a second level when the first switch and the second switch are turned on, it is determined that the electrical signal indicates a saturated brightness value.

[0105] (8) The electronic device according to (7), wherein the first level is a voltage level when the floating diffusion region is in a reset state, and the second level is a voltage level when the floating diffusion region is in a saturated state.

[0106] (9) A solid-state imaging device, using the electronic device according to any one of (1) to (8), to obtain the luminance value of the pixel as a digital signal and acquire image information.

[0107] (10) In an electronic device comprising: a first capacitor having a first end connected to a reference signal output circuit that outputs a reference signal; a second capacitor having a first end connected to a pixel having a light receiving element and outputting an electrical signal; a comparator having a first input end connected to a second end of the first capacitor and a second input end connected to the second end of the second capacitor, and comparing the reference signal with the electrical signal; a first switch connected to the first end of the first capacitor and the second end of the first capacitor; and a second switch connected to the first end of the second capacitor and the second end of the second capacitor, the electronic device comprising: a control method for turning on the first switch and the second switch at a timing before reading the electrical signal for each pixel, acquiring a value of the electrical signal, turning off the first switch and the second switch, and acquiring a luminance value for each pixel by correlated double sampling.

[0108] (11) The control method described in (10), wherein the value of the electrical signal acquired between the time when the first switch and the second switch are turned on and the time when they are turned off is used to determine whether the acquired electrical signal indicates a saturated brightness value.

[0109] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents.

[0110] 1: solid-state imaging device, 10: first drive circuit, 100: signal line, 12: second drive circuit, 120: signal line, 14: pixel array, 140: pixel, P: light receiving element, TRG: transfer gate, FD: floating diffusion region, RST: reset transistor, AMP: amplifying transistor, SEL: selection transistor, 16: ADC, 160: signal line, 162: column ADC, 164: pixel ADC, 170: comparator, M1, M2, M3, M4, M5, M6: transistor, I1: current source, C1, C2: capacitor, SW1, SW2: switch, REF: reference signal line, VSL: input signal line, OUT: output signal line, 2: semiconductor substrate, 20: first substrate, 22: second substrate

Claims

1. An electronic device comprising: a first capacitor having a first end connected to a reference signal output circuit that outputs a reference signal; a second capacitor having a first end connected to a pixel that outputs an electrical signal and has a light receiving element; a comparator having a first input end connected to a second end of the first capacitor and a second input end connected to a second end of the second capacitor, and comparing the reference signal with the electrical signal; a first switch connected to the first end of the first capacitor and the second end of the first capacitor; and a second switch connected to the first end of the second capacitor and the second end of the second capacitor.

2. The electronic device according to claim 1, wherein the reference signal output circuit includes a digital-to-analog converter (DAC) and outputs the ramp signal, which is an analog signal.

3. The electronic device of claim 2, further comprising: a counter connected to the output terminal of the comparator, which counts the time required for the reference signal to change until the electrical signal matches the reference signal based on the comparison result between the reference signal and the electrical signal.

4. The electronic device according to claim 3, wherein the counter counts the electrical signal when the floating diffusion region of the pixel is reset, and counts the electrical signal when carriers acquired by the light receiving element through light reception are accumulated in the floating diffusion region.

5. The electronic device according to claim 4, wherein the first switch and the second switch are turned on and off at a timing before the floating diffusion region of the pixel is reset.

6. The electronic device according to claim 5, wherein the first switch and the second switch are turned on at a timing before the first input terminal and the second input terminal of the comparator are reset, and are turned off at a timing before the first input terminal and the second input terminal are reset.

7. The electronic device according to claim 6, wherein, at the input terminal or output terminal of the counter, if the electrical signal is at a first level when the first switch and the second switch are turned on, it is determined that the electrical signal does not indicate a saturated brightness value, and if the electrical signal is at a second level when the first switch and the second switch are turned on, it is determined that the electrical signal indicates a saturated brightness value.

8. The electronic device according to claim 7, wherein the first level is a voltage level when the floating diffusion region is in a reset state, and the second level is a voltage level when the floating diffusion region is in a saturated state.

9. A solid-state imaging device using the electronic device according to claim 1 to obtain the brightness values ​​of the pixels as digital signals and acquire image information.

10. In an electronic device comprising: a first capacitor having a first end connected to a reference signal output circuit that outputs a reference signal; a second capacitor having a first end connected to a pixel having a light receiving element, the pixel outputting an electrical signal; a comparator having a first input end connected to a second end of the first capacitor and a second input end connected to the second end of the second capacitor, the comparator comparing the reference signal with the electrical signal; a first switch connected to the first end of the first capacitor and the second end of the first capacitor; and a second switch connected to the first end of the second capacitor and the second end of the second capacitor, the electronic device comprising: a control method for turning on the first switch and the second switch at a timing before reading the electrical signal for each pixel, acquiring the value of the electrical signal, turning off the first switch and the second switch, and acquiring a luminance value for each pixel by correlated double sampling.

11. The control method according to claim 10, further comprising determining whether or not the acquired electrical signal indicates a saturated brightness value based on the value of the electrical signal acquired between the time the first switch and the second switch are turned on and the time they are turned off.

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