Method for manufacturing semiconductor device

Abstract

The present disclosure relates, for example, to a hybrid bonding method in which an organic insulating film is used as an insulating film. In hybrid bonding methods in which an organic insulating film is used, heating at the time of bonding sometimes results in a thermal expansion difference between the organic insulating film and a terminal electrode that is formed of a metal or the like, and it is necessary to provide, in advance, a specific level difference D between the tip surface of the terminal electrode and the surface of the organic insulating film. In the present disclosure, in order to provide such a level difference D, the surface of a semiconductor substrate 100 is irradiated with nitrogen plasma. With this nitrogen plasma irradiation, an organic insulating film 102 of the semiconductor substrate 100 is etched by the nitrogen plasma so that a surface 102a of the organic insulating film 102 is positioned further back than a tip surface 103a of an electrode 103.

Description

Manufacturing method for semiconductor devices

[0001] This disclosure relates to a method for manufacturing a semiconductor device.

[0002] In recent years, with the rapid increase in functionality of electronic devices, exemplified by AI / HPC, semiconductor packages have been rapidly becoming larger and denser. This trend extends beyond high-density surface mounting to include inorganic (silicon) or organic interposer (Bridge die / RDL) technologies, 2.xD mounting using these technologies, and 3D mounting (HBM / Chiplet) utilizing TSVs, resulting in increasing complexity and diversification of both package structures and mounting processes. For example, Resonaq Corporation, with its "Packaging Solution Center" as its main base, is developing next-generation semiconductor packaging process technologies from the customer's (semiconductor manufacturer's) perspective, combining mounting processes and materials.

[0003] As such technologies in the field of semiconductor packaging, Patent Documents 1 to 3 disclose examples of hybrid bonding technologies used in wafer-to-wafer (W2W) bonding processes or chip-on-wafer (CoW) bonding processes in three-dimensional packaging of semiconductor devices.

[0004] Japanese Patent Publication No. 2021-197430, Japanese Patent Publication No. 2021-197431, Japanese Patent Publication No. 2018-528622

[0005] In hybrid bonding technologies described in Patent Document 1, etc., organic materials (resins) are sometimes used in the insulating portion. In this case, the difference in thermal expansion coefficients (linear thermal expansion coefficient CTE) between the metal material constituting the terminal electrode and the organic material constituting the insulating portion can cause a displacement of the surface, potentially resulting in bonding defects in the insulating portion or terminal electrode. For this reason, there is a need for a method that can easily create a desired step difference between the surface of the organic insulating film of the semiconductor substrate used in hybrid bonding and the tip surface of the electrode.

[0006] The present disclosure aims to provide a method for manufacturing a semiconductor device that allows for the easy creation of a desired step difference between the surface of the organic insulating film on the semiconductor substrate and the leading edge of the electrode in a hybrid bonding method using an organic insulating film.

[0007] [1] A method for manufacturing a semiconductor device according to one aspect of the present disclosure comprises the steps of: preparing a first semiconductor substrate having a first substrate body, a first organic insulating film and a first electrode provided on one surface of the first substrate body; and irradiating the surface of the first semiconductor substrate with nitrogen plasma. In the nitrogen plasma irradiation step, at least the first organic insulating film is etched with nitrogen plasma such that the surface of the first organic insulating film is closer to the first substrate body than the tip surface of the first electrode.

[0008] In this semiconductor device manufacturing method, at least the first organic insulating film is etched by nitrogen plasma such that the surface of the first organic insulating film is closer to the main body of the first substrate than the tip surface of the first electrode. In this case, although nitrogen plasma is irradiated toward both the first organic insulating film and the first electrode, the amount etched by the nitrogen plasma will differ due to differences in the elastic moduli of the two materials. Therefore, with this manufacturing method, by changing the nitrogen plasma conditions according to the materials of the organic insulating film and the electrode, or the difference in their elastic moduli, it becomes possible to easily create a desired step difference between the surface of the organic insulating film on the semiconductor substrate and the tip surface of the electrode in a hybrid bonding method using an organic insulating film.

[0009] [2] In the semiconductor device manufacturing method described in [1] above, in the step of irradiating with nitrogen plasma, the flow rate of the plasma gas is 3.38 × 10 －２ Pa・m ３ / sec (20 sccm) to 1.69 Pa·m ３ The flow rate of the plasma gas may be 3.38 × 10⁻¹⁰. －２ Pa・m ３ By having a flow rate of 20 sccm or more, etching by nitrogen plasma is promoted, allowing the step difference between the surface of the organic insulating film on the semiconductor substrate and the tip surface of the electrode to be brought to the desired value at an early stage. On the other hand, the flow rate of the plasma gas is 1.69 Pa·m ３ By keeping the pressure below / sec (1000 sccm), surface roughening of the organic insulating film and electrodes due to nitrogen plasma can be suppressed.

[0010] [3] In the semiconductor device manufacturing method described in [1] or [2] above, the plasma output may be 10W to 1000W in the step of irradiating with nitrogen plasma. By setting the plasma output to 10W or more, etching by nitrogen plasma can be promoted, and the step difference between the surface of the organic insulating film on the semiconductor substrate and the tip surface of the electrode can be brought to a desired value at an early stage. On the other hand, by setting the plasma output to 1000W or less, surface roughening of the organic insulating film and the electrode by nitrogen plasma can be suppressed.

[0011] [4] In the semiconductor device manufacturing method of any of [1] to [3] above, the plasma treatment time in the step of irradiating with nitrogen plasma may be 180 seconds or less. By limiting the plasma treatment time to 180 seconds or less, it is possible to suppress surface roughening of the organic insulating film and electrodes by nitrogen plasma while creating a desired step between the surface of the organic insulating film on the semiconductor substrate and the tip surface of the electrode.

[0012] [5] In any of the semiconductor device manufacturing methods described in [1] to [4] above, the elastic modulus of the first organic insulating film may be 7.5 GPa or less. In this case, it becomes possible to easily create a desired step between the surface of the organic insulating film on the semiconductor substrate and the tip surface of the electrode.

[0013] [6] In the semiconductor device manufacturing method of any of [1] to [5] above, in the step of irradiating with nitrogen plasma, nitrogen plasma may be irradiated onto the surface of the first semiconductor substrate such that the step distance between the surface of the first organic insulating film and the tip surface of the first electrode is 15 nm or more and 100 nm or less. In this case, when the first semiconductor substrate is joined to another substrate by hybrid bonding, the amount of displacement between the surface of the first organic insulating film and the tip surface of the first electrode is reduced due to thermal expansion, making it possible to more reliably join the first semiconductor substrate to the other substrate.

[0014] [7] The method for manufacturing a semiconductor device according to any of [1] to [6] above further comprises a step of polishing a first organic insulating film and a first electrode provided on one surface of a first semiconductor substrate, wherein the step of polishing the first semiconductor substrate may be performed before the step of irradiating with nitrogen plasma. In the polishing step, the surface roughness of the surface of the first organic insulating film of the first semiconductor substrate and the tip surface of the first electrode can be reduced, and the step can be set to a desired value, but it is difficult to adjust the step to a fine level. Therefore, if the desired step is not obtained in the polishing step, the step can be further adjusted by performing a plasma irradiation step after the polishing step. Thus, this manufacturing method makes it possible to reduce bonding defects in hybrid bonding.

[0015] [8] In the semiconductor device manufacturing method described in [7] above, the polishing step of the first semiconductor substrate may be performed so that the surface roughness Ra of each surface of the first organic insulating film and the first electrode becomes 2.0 nm or less. In this case, it is possible to more reliably reduce bonding defects in hybrid bonding.

[0016] [9] A method for manufacturing a semiconductor device according to any of [1] to [8] above may further include the steps of: preparing a second semiconductor substrate having a second substrate body, a second organic insulating film and a second electrode provided on one surface of the second substrate body; aligning the second electrode of the second semiconductor substrate with respect to the first electrode of the first semiconductor substrate; and heating and pressurizing the first semiconductor substrate and the second semiconductor substrate to bond the first organic insulating film and the second organic insulating film to each other, and to bond the first electrode and the second electrode to each other. In this case, the first semiconductor substrate and the second semiconductor substrate can be bonded by hybrid bonding. The hybrid bonding referred to herein may be hybrid bonding used in either a Wafer-to-Wafer (W2W) bonding process or a Chip-on-Wafer (CoW) bonding process.

[0017]

[10] The method for manufacturing a semiconductor device described in [9] above further comprises a step of irradiating the surface of a second semiconductor substrate with nitrogen plasma, wherein in the step of irradiating the second semiconductor substrate with nitrogen plasma, at least the second organic insulating film may be etched with nitrogen plasma such that the surface of the second organic insulating film is closer to the main body of the second substrate than the tip surface of the second electrode. In this case, by changing the conditions of the nitrogen plasma according to the materials of the organic insulating film and the electrode, or the difference in elastic modulus between them, it is possible to easily create a desired step difference between the surface of the organic insulating film on the semiconductor substrate and the tip surface of the electrode, even in the second semiconductor substrate.

[0018] According to this disclosure, in a hybrid bonding method using an organic insulating film, a desired step difference can be easily created between the surface of the organic insulating film on the semiconductor substrate and the leading edge of the electrode.

[0019] Figure 1 is a schematic cross-sectional view showing an example of a semiconductor device (CoW) manufactured by a semiconductor device manufacturing method according to one embodiment of the present disclosure. Figure 2 is a diagram showing the manufacturing method of the semiconductor device shown in Figure 1 in sequence. Figure 3 is a schematic diagram showing the plasma process in the manufacturing method of the semiconductor device shown in Figure 2. Figure 4 is a diagram showing the bonding method in the manufacturing method of the semiconductor device shown in Figure 2.

[0020] Hereinafter, several embodiments of this disclosure will be described in detail, with reference to the drawings as necessary. In the following description, the same or corresponding parts will be denoted by the same reference numerals, and redundant descriptions will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. When terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "downward" are used in this specification, they are for illustrative purposes only and do not necessarily mean that the relative positions are permanent. Moreover, the dimensional ratios in the drawings are not limited to those shown.

[0021] In this specification, the term "layer" includes not only structures that are formed across the entire surface when observed in a plan view, but also structures that are formed in only a part of the surface. Furthermore, in this specification, the term "process" includes not only independent processes, but also processes that are not clearly distinguishable from other processes, as long as their intended function is achieved. In addition, numerical ranges indicated using "~" indicate a range that includes the numbers written before and after "~" as the minimum and maximum values, respectively.

[0022] (Configuration of Semiconductor Device) Figure 1 is a schematic cross-sectional view showing an example of a semiconductor device manufactured by the manufacturing method according to this embodiment. As shown in Figure 1, the semiconductor device 1 is, for example, an example of a semiconductor package, and comprises a plurality of semiconductor chips 10 and a semiconductor substrate 20, and has a chip-on-wafer (CoW) structure. The plurality of semiconductor chips 10 are manufactured by dicing a semiconductor substrate 100, which will be described later. The plurality of semiconductor chips 10 are mounted on the semiconductor substrate 20 to form a three-dimensional mounting structure. The semiconductor substrate 20 may be, for example, a substrate on which a plurality of semiconductor chips, such as an LSI (Large scale Integrated Circuit) chip or a CMOS (Complementary Metal Oxide Semiconductor) sensor, are formed at locations corresponding to each semiconductor chip 10. Each semiconductor chip 10 may be, for example, an LSI or a memory chip. The plurality of semiconductor chips 10 and the semiconductor substrate 20 are finely bonded together by hybrid bonding, which will be described later, so that their respective terminal electrodes and the insulating films around them are firmly and precisely bonded to each other without misalignment. The semiconductor device 1 may be further fragmented into individual semiconductor devices, comprising at least one semiconductor chip 10 further fragmented from the configuration shown in Figure 1, and a substrate portion which is a part of a semiconductor substrate 20 corresponding to the fragmented semiconductor chip 10. Furthermore, the manufacturing method according to this embodiment may be applied to a W2W bonding process, in which case semiconductor substrates are bonded together.

[0023] (Method for Manufacturing a Semiconductor Device) Next, the method for manufacturing the semiconductor device 1 will be explained with reference to Figures 2 to 4. Figure 2 is a diagram showing, in order, the method for manufacturing the semiconductor device shown in Figure 1. Figure 3 is a diagram schematically showing the plasma process in the method for manufacturing the semiconductor device shown in Figure 2. Figure 4 is a diagram showing the bonding method in the method for manufacturing the semiconductor device shown in Figure 2.

[0024] The semiconductor device 1 can be manufactured, for example, through the following steps (a) to (j): (a) A step of preparing a semiconductor substrate 100 corresponding to a plurality of semiconductor chips 10, having a substrate body 101, an insulating film 102, and a plurality of electrodes 103. (b) A step of preparing a semiconductor substrate 200 having a substrate body 201, an insulating film 202, and a plurality of electrodes 203. (c) A step of polishing the insulating film 102 of the semiconductor substrate 100 together with the electrodes 103. (d) A step of polishing the insulating film 202 of the semiconductor substrate 200 together with the electrodes 203. (e) A step of irradiating the insulating film 102 and electrodes 103 of the semiconductor substrate 100 with nitrogen plasma. (f) A step of irradiating the insulating film 202 and electrodes 203 of the semiconductor substrate 200 with nitrogen plasma. (g) A step of separating the semiconductor substrate 100 into individual pieces and obtaining a plurality of semiconductor chips 10, each having an insulating film portion 102b corresponding to the insulating film 102 and an electrode 103. (h) A step of aligning the electrodes 103 of each of the multiple semiconductor chips 10 with respect to the electrodes 203 of the semiconductor substrate 200. (i) A step of joining the insulating film portions 102b of each of the multiple semiconductor chips 10 with the insulating film 202 of the semiconductor substrate 200. (j) A step of joining the electrodes 103 of each of the multiple semiconductor chips 10 with the electrodes 203 of the semiconductor substrate 200.

[0025] [Steps (a) and (b)] Step (a) is a step of preparing a semiconductor substrate 100 (second semiconductor substrate), which is a silicon substrate on which integrated circuits consisting of semiconductor elements and wiring connecting them are formed, corresponding to a plurality of semiconductor chips 10. In step (a), as shown in Figure 2(a), a plurality of electrodes 103 (second electrodes) made of copper or aluminum are provided at predetermined intervals on one surface 101a of a substrate body 101 (second substrate body) made of silicon or the like, and an insulating film 102 (second organic insulating film) made of an inorganic or organic material is provided. The electrodes 103 are terminal electrodes for exposing integrated circuits formed on the semiconductor substrate 100 to the outside by penetrating the insulating film 102. The insulating film 102 may be provided on one surface 101a of the substrate body 101 and then the plurality of electrodes 103 may be provided, or the plurality of electrodes 103 may be provided on one surface 101a of the substrate body 101 and then the insulating film 102 may be provided.

[0026] Step (b) is a step of preparing a semiconductor substrate 200 (first semiconductor substrate), which is a silicon substrate on which an integrated circuit consisting of semiconductor elements and wiring connecting them is formed. In step (b), as shown in Figure 2(a), a plurality of electrodes 203 (first electrodes) made of copper or aluminum are provided at predetermined intervals on one surface 201a of a substrate body 201 (first substrate body) made of silicon or the like, and an insulating film 202 (first organic insulating film) made of an inorganic or organic material is provided. The electrodes 203 are terminal electrodes for exposing the integrated circuit etc. formed on the semiconductor substrate 200 to the outside by penetrating the insulating film 202. The insulating film 202 may be provided on one surface 201a of the substrate body 201 and then the plurality of electrodes 203 may be provided, or the plurality of electrodes 203 may be provided on one surface 201a of the substrate body 201 and then the insulating film 202 may be provided.

[0027] The insulating film 102 and insulating film 202 used in steps (a) and (b) are composed of an organic material. The organic material used in the insulating film may be, for example, polyimide, polyimide precursor (e.g., polyimiamic ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or PBO precursor. These organic materials may be, for example, silicon oxide (SiO₂ ２Compared to inorganic materials such as ), it has a lower modulus of elasticity and is a soft material. By using such an organic material, when bonding the insulating films together in step (i) described later, even if there are fine foreign matter (debris) on the insulating film, it is absorbed into the insulating film, preventing bonding defects due to foreign matter and ensuring reliable bonding of the insulating films together. The modulus of elasticity of the organic material constituting insulating film 102 and insulating film 202 may be, for example, 7.0 GPa or less, 5.0 GPa or less, 3.5 GPa or less, 3.0 GPa or less, or 2.5 GPa or less. The modulus of elasticity here refers to Young's modulus. Because the insulating film is composed of an organic material having such a modulus of elasticity, in steps (e) and (f) described later, it is possible to easily reduce the thickness of the insulating film by nitrogen plasma irradiation. Furthermore, the organic material constituting insulating film 102 and insulating film 202 preferably has a coefficient of thermal expansion of 70 ppm / K or less, and more preferably 50 ppm / K or less.

[0028] Furthermore, since the organic material used in the insulating film is liquid or soluble in a solvent, each insulating film can be easily formed as a thin film by spin coating or the like. Moreover, since these organic materials have heat resistance, they can withstand the temperature (for example, high temperatures of 300°C or higher) when joining electrodes 103 and 203 in step (j) described later, and the bonding between the insulating films does not deteriorate due to high temperatures. As the organic material constituting insulating film 102 and insulating film 202, a photosensitive resin, a thermosetting non-conductive film (NCF), or a thermosetting resin may be used. This organic material may also be an underfill material. In addition, insulating films 102 and insulating films 202 may be insulating films containing both inorganic and organic materials, or one insulating film may be formed from an inorganic material and the other insulating film may be formed from an organic material. The inorganic material used in the insulating film may be, for example, silicon oxide (SiO2). ２ ) etc.

[0029] The thickness of the insulating film 102 may be 20 μm or less. By making the thickness of the insulating film 102 sufficiently thin, the wiring and other components formed from the electrodes 103 can be made finer. For example, the minimum size (electrode width) of the electrode 103 formed within the insulating film 102 is determined by the thickness of the insulating film 102 and the aspect ratio of the photosensitive material used. If the aspect ratio of the photosensitive material is, for example, 1:1 (aperture width:depth), the electrode width of the electrode 103 can be 20 μm or less by making the thickness of the insulating film 102 20 μm or less. However, the thickness of the insulating film 102 may be thicker than 20 μm. In this case, when bonding the insulating films together in step (i) described later, more foreign matter can be embedded in the resin insulating film 102, and the insulating films can be joined together more reliably. It is also possible to improve the adhesion between the insulating films by relieving the stress when joining the insulating films together with one of the resin insulating films.

[0030] Furthermore, the thickness of the insulating film 102 may be 1 μm or more. In this case, by embedding minute foreign matter within the resin insulating film, it is possible to ensure good connection between the insulating film 102 and the insulating film 202 even if minute foreign matter remains. For example, the size of foreign matter that can be embedded in the insulating film 102 is determined by the thickness of the resin insulating film 102. If the thickness of the insulating film 102 is, for example, 1 μm, foreign matter with a diameter or width of 1 μm can be embedded within the insulating film 102. That is, according to this manufacturing method, even if debris smaller than the thickness of the insulating film 102 exists, it is possible to ensure good connection between the insulating film 102 and the insulating film 202 by embedding the debris in the resin insulating film. Note that the thickness of the insulating film 202 may be 20 μm or less, thicker than 20 μm, or 1 μm or more, similar to the insulating film 102. The insulating film 202 may also have debris embedded in it as described above.

[0031] [Steps (c) and (d)] Step (c) is a step of polishing the semiconductor substrate 100. In step (c), the surface of the insulating film 102 on which the electrode 103 is provided is polished using the CMP (Chemical Mechanical Polishing) method. This polishing is preferably performed before step (e), which involves irradiating with plasma. This is because the plasma irradiation in step (e) may cause the surface of the insulating film 102 to become rough, and the average roughness of the surface of the insulating film 102 is reduced in advance before bonding by hybrid bonding. Through such polishing, the average roughness of the surface of the insulating film 102 is set to 2.0 nm or less, preferably 1.2 nm or less, and more preferably 1.0 nm or less, enabling the hybrid bonding described later. Debris on the surface of the semiconductor substrate 100 may be removed by this polishing. In addition, in this polishing step, a part of the step between the surface 102a of the insulating film 102 and the tip surface 103a of the electrode 103 may be formed.

[0032] Step (d) is a step of polishing the semiconductor substrate 200. In step (d), the surface of the insulating film 202 on which the electrode 203 is provided is polished using the CMP method. This polishing is preferably performed before step (f). This is because, similar to step (c), the plasma irradiation in step (f) may cause the surface of the insulating film 202 to become rough, and the average roughness of the surface of the insulating film 202 is reduced before bonding by hybrid bonding. By such polishing, the average roughness of the surface of the insulating film 202 is set to 2.0 nm or less, preferably 1.2 nm or less, and more preferably 1.0 nm or less, enabling the hybrid bonding described later. Debris on the surface of the semiconductor substrate 200 may be removed by this polishing. In addition, in this polishing step, a part of the step between the surface 202a of the insulating film 202 and the tip surface 203a of the electrode 203 may be formed.

[0033] In step (c) and step (d), the polishing may be performed so that the thickness of the insulating film 102 is the same as the thickness of the insulating film 202. For example, the polishing may be performed so that the thickness of the insulating film 102 is greater than the thickness of the insulating film 202. On the other hand, the polishing may be performed so that the thickness of the insulating film 102 is less than the thickness of the insulating film 202. When the thickness of the insulating film 102 is greater than the thickness of the insulating film 202 and the insulating film 102 is formed of an organic material, most of the debris adhering to the bonding interface during dicing the semiconductor chip 10 or during chip mounting can be included by the insulating film 102, and the bonding failure can be reduced. On the other hand, when the thickness of the insulating film 102 is less than the thickness of the insulating film 202, the height of the mounted semiconductor chip 10, that is, the semiconductor device 1 can be reduced.

[0034] [Steps (e) and (f)] Step (e) is a step of irradiating the insulating film 102 and the electrode 103 of the semiconductor substrate 100 with nitrogen plasma. In step (e), as shown in FIGS. 3(a) and 3(b), the insulating film 102 is etched by nitrogen plasma so that the surface 102a of the insulating film 102 is closer to the substrate body 101 (inner side) than the tip surface 103a of the electrode 103. In step (e), for example, the semiconductor substrate 100 is placed in a decompression chamber, and nitrogen plasma is irradiated onto the surface of the semiconductor substrate 100 for etching. As the conditions of the nitrogen plasma, the flow rate of the plasma gas (nitrogen gas) is 3.38×10 －２ Pa·m ３ / sec (20 sccm) to 1.69 Pa·m ３The flow rate may be / sec (1000 sccm) (both meaning the flow rate at 1 atmosphere and 0°C), the plasma output may be 10W to 1000W, and the plasma processing time may be 180 seconds or less. The plasma processing time may be 140 seconds or less, or 100 seconds or less. The plasma processing time may also be 30 seconds or more. By irradiating with such plasma, as shown in Figure 3(b), the step D between the surface 102a of the insulating film 102 and the tip surface 103a of the electrode 103 becomes 15 nm to 100 nm. This step D is due to the difference in elastic modulus between the insulating film 102 and the electrode 103. Nitrogen plasma may be irradiated so that the step D between the surface 102a of the insulating film 102 and the tip surface 103a of the electrode 103 becomes 35 nm to 75 nm.

[0035] In step (e), the insulating film 102 may be etched with nitrogen plasma and argon plasma. That is, in step (e), etching may be performed by irradiating the surface of the semiconductor substrate 100 with nitrogen plasma and argon plasma. The conditions for the argon plasma may be the same as or different from those for the nitrogen plasma.

[0036] At the end of step (e), the surface roughness Ra of the insulating film 102 may be 2.0 nn or less, preferably 1.2 nm or less, and more preferably 1.0 nm or less. At the end of step (e), the surface roughness Ra of the electrode 103 may be 2.0 nn or less, preferably 1.2 nm or less, and more preferably 1.0 nm or less. At the end of step (e), the surface roughness Rz of the electrode 103 may be 12.0 nn or less, preferably 10.0 nm or less, and more preferably 8.0 nm or less. At the end of step (e), the surface roughness Rq of the electrode 103 may be 2.0 nn or less, preferably 1.5 nm or less, and more preferably 1.0 nm or less.

[0037] Note that the surface roughness Ra here is the arithmetic mean roughness (Ra) defined by the JIS standard (JIS B 0601-2001). The surface roughness Rz is the ten-point mean roughness (Rz) defined by the JIS standard (JIS B 0601-2001). The surface roughness Rq is the root mean square height of the second power (Rq) defined by the JIS standard (JIS B 0601-2001).

[0038] Step (f) is a step of irradiating the insulating film 202 and the electrode 203 of the semiconductor substrate 200 with nitrogen plasma. In step (f), as in step (e), the insulating film 202 is etched with nitrogen plasma so that the surface 202a of the insulating film 202 is closer to the substrate body 201 (the back side) than the tip surface 203a of the electrode 203. In step (f), for example, the semiconductor substrate 200 is placed in a vacuum chamber, and nitrogen plasma is irradiated onto the surface of the semiconductor substrate 200 for etching. As the conditions of the nitrogen plasma, the flow rate of the plasma gas (nitrogen gas) may be 3.38×10 －２ Pa·m ３ / sec (20 sccm) to 1.69 Pa·m ３ / sec (1000 sccm) (both mean the flow rate at 1 atm and 0°C), the plasma output may be 10 W to 1000 W, and the plasma treatment time may be 180 seconds or less. Note that the plasma treatment time may be 140 seconds or less, or 100 seconds or less. Also, the plasma treatment time may be 30 seconds or more. By such irradiation of the plasma, as shown in (b) of FIG. 3, the step D between the surface 202b of the insulating film 202 and the tip surface 203a of the electrode 203 becomes 15 nm or more and 100 nm or less. Such a step D is formed due to the difference in the elastic modulus between the insulating film 202 and the electrode 203. The plasma may be irradiated so that the step D between the surface 202b of the insulating film 202 and the tip surface 203a of the electrode 203 becomes 35 nm or more and 75 nm or less.

[0039] In step (f), the insulating film 202 may be etched with nitrogen plasma and argon plasma. That is, in step (f), etching may be performed by irradiating the surface of the semiconductor substrate 200 with nitrogen plasma and argon plasma. The conditions for the argon plasma may be the same as or different from those for the nitrogen plasma.

[0040] At the end of step (f), the surface roughness Ra of the insulating film 202 may be 2.0 nn or less, preferably 1.2 nm or less, and more preferably 1.0 nm or less. At the end of step (e), the surface roughness Ra of the electrode 203 may be 2.0 nn or less, preferably 1.2 nm or less, and more preferably 1.0 nm or less. At the end of step (f), the surface roughness Rz of the electrode 203 may be 12.0 nn or less, preferably 10.0 nm or less, and more preferably 8.0 nm or less. At the end of step (f), the surface roughness Rq of the electrode 203 may be 2.0 nn or less, preferably 1.5 nm or less, and more preferably 1.0 nm or less.

[0041] [Step (g)] Step (g) is a step of separating the semiconductor substrate 100 into individual pieces and obtaining a plurality of semiconductor chips 10. After polishing the semiconductor substrate 200 is completed, in step (g), the polished semiconductor substrate 100 is separated into individual pieces and a plurality of semiconductor chips 10 (semiconductor substrates) are obtained, each having an insulating film portion 102b corresponding to the insulating film 102 and at least one electrode 103. In step (g), the semiconductor substrate 100 is placed on a dicing tape and separated into a plurality of semiconductor chips 10 by cutting means such as dicing from the insulating film 102 toward the substrate body 101. When dicing the semiconductor substrate 100, the insulating film 102 may be covered with a protective material or the like before being separated into individual pieces. In step (g), the insulating film 102 of the semiconductor substrate 100 is divided into insulating film portions 102b corresponding to each semiconductor chip 10, as shown in Figure 2(b). Similarly, the substrate body 101 is divided into corresponding substrate portions 101b. As a dicing method for separating the semiconductor substrate 100 into individual pieces, for example, plasma dicing, stealth dicing, or laser dicing can be used. In step (g), after the separation by dicing is completed, the separated semiconductor chips 10 may be cleaned.

[0042] [Step (h)] Step (h) is a step in which the electrodes 103 of each of the multiple semiconductor chips 10 are aligned with respect to the electrodes 203 of the semiconductor substrate 200, as shown in Figure 2(c) (left side) and Figure 4(a). In step (h), each semiconductor chip 10 is aligned so that each electrode 103 of each semiconductor chip 10 faces the corresponding electrode 203 of the semiconductor substrate 200. Figure 4(a) is a schematic diagram that is an enlarged part of Figure 2(c). As shown in Figure 4(a), in the stage before heating for bonding, steps remain formed between the insulating film portion 102b and the electrode 103, and between the insulating film 202 and the electrode 203. That is, the electrodes 103 and 203 protrude from the surfaces of the insulating film portion 102b and the insulating film 202.

[0043] [Step (i)] Step (i) is a step of bonding each insulating film portion 102b of the plurality of semiconductor chips 10 to the insulating film 202 of the semiconductor substrate 200. In step (i), after removing organic matter or metal oxides attached to the surface of each semiconductor chip 10 and the semiconductor substrate 200, the semiconductor chips 10 are aligned with the semiconductor substrate 200. Once this is completed, as shown in Figure 2(c) (right side) and Figure 4(b), the insulating film portions 102b of each of the plurality of semiconductor chips 10 are bonded to the insulating film 202 of the semiconductor substrate 200 as a hybrid bond. At this time, the insulating film portions 102b of the plurality of semiconductor chips 10 and the insulating film 202 of the semiconductor substrate 200 may be uniformly heated before bonding. Heating for bonding causes the insulating film, which is made of organic material, to expand more than the electrode, eliminating the step between the insulating film portion 102b and the electrode 103, and the step between the insulating film 202 and the electrode 203. This step may be completely eliminated, so that the surfaces of the insulating film portion 102b and the electrode 103 are flush, and the surfaces of the insulating film 202 and the electrode 203 are flush, or a slight step may remain. The temperature difference between the semiconductor chip 10 and the semiconductor substrate 200 during bonding is preferably 10°C or less. By heating and bonding at such a uniform temperature, the insulating film portion 102b and the insulating film 202 are bonded to form an insulating bond, and multiple semiconductor chips 10 are mechanically firmly attached to the semiconductor substrate 200. Furthermore, because the heating and bonding is performed at a uniform temperature, misalignment at the bonding site is less likely to occur, and high-precision bonding can be achieved. At this attachment stage, the electrode 103 of the semiconductor chip 10 and the electrode 203 of the semiconductor substrate 200 are spaced apart from each other and not connected (however, alignment is performed). The bonding of the semiconductor chip 10 to the semiconductor substrate 200 may be performed by other bonding methods, such as room temperature bonding.

[0044] [Step (j)] Step (j) is a step in which the electrodes 103 of each of the multiple semiconductor chips 10 are joined to the electrodes 203 of the semiconductor substrate 200. In step (j), as shown in Figure 2(d), once the bonding in step (i) is completed, a predetermined heat H or pressure or both is applied to join the electrodes 103 of the multiple semiconductor chips 10 to the electrodes 203 of the semiconductor substrate 200 as a hybrid bond. When the electrodes 103 and 203 are made of copper, the annealing temperature in step (j) is preferably 150°C to 400°C, and more preferably 200°C to 300°C. Through this joining process, the electrodes 103 and their corresponding electrodes 203 are joined to form an electrode joint, and the electrodes 103 and 203 are firmly joined mechanically and electrically. Note that the electrode joining in step (j) is performed after the bonding in step (i), but it may be performed simultaneously with the bonding in step (i). Subsequently, all semiconductor chips 10 are bonded to the semiconductor substrate 200 to obtain the semiconductor device 1 shown in Figure 1.

[0045] As described above, a semiconductor device 1 can be obtained in which a plurality of semiconductor chips 10 are electrically and mechanically and precisely positioned on a semiconductor substrate 200. Subsequently, the semiconductor device (CoW) with the configuration shown in Figure 1 may be further fragmented to individually form each semiconductor device, which consists of at least one semiconductor chip 10 and a portion of the semiconductor substrate 200 corresponding to the fragmented semiconductor chip 10.

[0046] As described above, according to the semiconductor device manufacturing method of this embodiment, in steps (e) and (f), the insulating films 102 and 202 are etched by nitrogen plasma such that the surfaces of the insulating films 102 and 202 are closer to the substrate body 101 and 201 than the leading edges of the electrodes 103 and 203. In this case, although nitrogen plasma is irradiated toward both the insulating films 102 and 202 and the electrodes 103 and 203, the amount etched by the nitrogen plasma will differ due to differences in the elastic moduli of the two materials. Therefore, according to this manufacturing method, by changing the conditions of the nitrogen plasma according to the materials of the organic insulating film and the electrodes, or the difference in the elastic moduli of the two materials, it is possible to easily create a desired step D between the surface of the insulating film 202 of the semiconductor substrate 100 and 200 and the leading edges of the electrodes 103 and 203 in a hybrid bonding method using insulating films 102 and 202.

[0047] When etching the insulating films 102 and 202 as described above, argon plasma may be used instead of nitrogen plasma. Even when argon plasma is used to etch the insulating films 102 and 202, the amount etched by the argon plasma will differ due to differences in the elastic modulus of the insulating films 102 and 202 and the electrodes 103 and 203. However, when using argon plasma, the amount etched by electrodes 103 and 203 tends to be smaller compared to nitrogen plasma. Therefore, by etching the insulating films 102 and 202 with nitrogen plasma, the step distance between the surface of the insulating films 102 and 202 and the leading edge of electrodes 103 and 203 can be increased. In other words, under the same plasma irradiation conditions, etching with nitrogen plasma can increase the step D between the surface of the insulating film 202 of the semiconductor substrate 100 and 200 and the leading edge of electrodes 103 and 203 compared to etching with argon plasma.

[0048] When the plasma irradiation conditions are the same, etching with nitrogen plasma can reduce the surface roughness of electrodes 103 and 203 compared to etching with argon plasma. The mechanism is presumed to be as follows, but is not limited to this. Since the mass of nitrogen is smaller than the mass of argon, the energy of the plasma impact on the surface of electrodes 103 and 203 is lower when etching with nitrogen plasma compared to etching with argon plasma. Therefore, the surface of electrodes 103 and 203 is less likely to be abraded when etching with nitrogen plasma compared to etching with argon plasma. As a result, it is presumed that the surface roughness of electrodes 103 and 203 is lower when etching with nitrogen plasma. In addition, a polishing process is performed before the etching process with nitrogen plasma, but since the surface is less likely to be abraded when etching with nitrogen plasma, it is easier to maintain the surface roughness that has been smoothed by polishing.

[0049] In the semiconductor device manufacturing method according to this embodiment, in steps (e) and (f), the flow rate of the plasma gas is 3.38 × 10 －２ Pa・m ３ / sec (20 sccm) to 1.69 Pa·m ３ The flow rate of the plasma gas is 3.38 × 10⁻¹⁰. －２ Pa・m ３ By having a flow rate of 20 sccm or more, etching by nitrogen plasma is promoted, and the step difference D between the surface of the insulating film 102, 202 of the semiconductor substrate 100, 200 and the tip surface of the electrode 103, 203 can be brought to the desired value early on. On the other hand, the flow rate of the plasma gas is 1.69 Pa·m ３ By keeping the pressure below / sec (1000 sccm), surface roughening of the insulating films 102, 202 and electrodes 103, 203 by nitrogen plasma can be suppressed.

[0050] In the semiconductor device manufacturing method according to this embodiment, the plasma output is 10W to 1000W in steps (e) and (f). By setting the plasma output to 10W or more, etching by nitrogen plasma is promoted, and the step difference between the surface of the insulating film 102, 202 of the semiconductor substrate 100, 200 and the leading edge surface of the electrodes 103, 203 can be brought to a desired value at an early stage. On the other hand, by setting the plasma output to 1000W or less, surface roughening of the insulating film 102, 202 and the electrodes 103, 203 by nitrogen plasma can be suppressed.

[0051] In the semiconductor device manufacturing method according to this embodiment, the plasma processing time in steps (e) and (f) is 180 seconds or less. By limiting the plasma processing time to 180 seconds or less, it is possible to suppress surface roughening of the insulating films 102, 202 and electrodes 103, 203 by nitrogen plasma, while creating a desired step D between the surface of the insulating films 102, 202 of the semiconductor substrates 100, 200 and the leading edge surfaces of the electrodes 103, 203.

[0052] In the semiconductor device manufacturing method according to this embodiment, the elastic modulus of the insulating films 102 and 202 is 7.5 GPa or less. In this case, it is possible to easily create a desired step difference between the surface of the insulating films 102 and 202 of the semiconductor substrates 100 and 200 and the leading edge surfaces of the electrodes 103 and 203.

[0053] In the semiconductor device manufacturing method according to this embodiment, in steps (e) and (f), nitrogen plasma is irradiated onto the surfaces of the semiconductor substrates 100 and 200 such that the step distance between the surfaces of the insulating films 102 and 202 and the leading edges of the electrodes 103 and 203 is 15 nm or more and 100 nm or less. In this case, when the semiconductor substrates 100 and 200 are joined to each other, thermal expansion reduces the amount of displacement between the surfaces of the insulating films 102 and 202 and the leading edges of the electrodes 103 and 203, making it possible to join the semiconductor substrates 100 and 200 to each other more reliably.

[0054] The semiconductor device manufacturing method according to this embodiment includes steps (c) and (d), which are steps of polishing insulating films 102, 202 and electrodes 103, 203 provided on one surface of semiconductor substrates 100, 200. Steps (c) and (d) are performed before steps (e) and (f), which are steps of irradiating with nitrogen plasma. By irradiating with nitrogen plasma, the step difference between the surface of the insulating films 102, 202 on the semiconductor substrates 100, 200 and the tip surfaces of the electrodes 103, 203 can be set to a desired value. However, depending on the output conditions of the nitrogen plasma, the surface roughness of the surface of the insulating films 102, 202 or the tip surfaces of the electrodes 103, 203 may be worsened. In hybrid bonding, if the surface roughness of the bonding surface worsens, there is a risk of poor bonding in hybrid bonding. Therefore, in this manufacturing method, the surface roughness of the surface and tip surface that will be roughened by nitrogen plasma irradiation is reduced in advance by polishing. Thus, this manufacturing method makes it possible to reduce bonding defects in hybrid bonding. Furthermore, in steps (c) and (d), it is possible to reduce the surface roughness of the surface of the organic insulating film on the semiconductor substrates 100 and 200 and the tip surface of the electrode, while simultaneously setting the step difference between the surface of the organic insulating film and the tip surface of the electrode to a desired value. However, fine adjustment of the step difference is difficult with polishing. Therefore, if the desired step difference is not obtained in steps (c) and (d), the step difference can be further adjusted by performing steps (e) and (f) after steps (c) and (d).

[0055] In the semiconductor device manufacturing method according to this embodiment, in steps (c) and (d), polishing is performed so that the surface roughness Ra of each surface of the insulating film 102, 202 and the electrodes 103, 203 becomes 2 nm or less. In this case, it is possible to more reliably reduce bonding defects in hybrid bonding.

[0056] The method for manufacturing a semiconductor device according to this embodiment includes the steps of: (a) preparing a semiconductor substrate 100 having a substrate body 101 and an insulating film 102 and an electrode 103 provided on one surface of the substrate body 101; (h) aligning the electrode 103 of the semiconductor substrate 100 with the electrode 203 of the semiconductor substrate 200; and (i) and (j) heating and pressurizing the semiconductor substrate 200 and the semiconductor substrate 100 to bond the insulating film 202 and the insulating film 102 to each other, and to bond the electrode 203 and the electrode 103 to each other. In this case, it is possible to bond the semiconductor substrate 200 and the semiconductor substrate 100 by hybrid bonding.

[0057] Although embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above embodiments and can be applied to various embodiments. For example, in the above, the method for manufacturing a semiconductor device was described using the CoW bonding process as an example of hybrid bonding, but the method for manufacturing a semiconductor device according to the present embodiment may also be applied to the Wafer-to-Wafer (W2W) bonding process. In this case, the semiconductor substrate 100 and the semiconductor substrate 200 that have undergone steps (e) and (f) are joined by hybrid bonding without performing step (g) of dicing the first semiconductor substrate into individual pieces.

[0058] The present invention will be described in more detail below with reference to examples, but the present invention is not limited to these examples. The following examples (experimental examples) involve preparing a semiconductor substrate on which an organic insulating film and an electrode are provided on one surface of the substrate body, and testing whether the step difference between the surface of the organic insulating film and the tip surface of the electrode can be adjusted by irradiating the semiconductor substrate with nitrogen plasma.

[0059] First, a test wafer corresponding to the semiconductor substrate 100 was prepared. In this preparation, a polyimide material was prepared as the organic insulating film material to be used on the test wafer. The above polyimide material has a glass transition temperature of 290°C after curing and a coefficient of linear expansion (CTE) of 100 ppm / °C (10 ―６ The coefficient of linear expansion of the copper used in the electrode was 16.8 ppm / °C (10 ―６The temperature was ( / °C) and the modulus of elasticity was 120 GPa.

[0060] Next, as Experimental Example 1, as shown in Figure 3, numerous electrodes 103, which are copper pillars (Cu) measuring 10 μm square and 6 μm high, were fabricated on a silicon substrate body 101 using a semi-additive method. Subsequently, the polyimide material described above was spin-coated onto the substrate body 101 to cover the electrodes 103, and then baked in a nitrogen atmosphere at 375°C for 2 hours to cure (see Figure 3(a)). After that, the cured semiconductor substrate 100 was placed in a reduced pressure chamber, and nitrogen plasma was irradiated onto the semiconductor substrate 100 under the following plasma conditions (see Figure 3(b)). RF output (plasma output): 500 W (watts) Processing time (plasma processing time): 120 seconds Nitrogen flow rate (plasma gas flow rate): 100 sccm

[0061] After the plasma irradiation was completed, the step height D between the surface of the organic insulating film and the tip surface of the electrode, the surface roughness Ra of the organic insulating film, and the surface roughness Ra, Rz, and Rq of the tip surface of the electrode were measured, and the following results were obtained: Step height D between the surface of the organic insulating film and the tip surface of the electrode: 71.69 nm Surface roughness Ra of the surface of the organic insulating film: 1.78 nm Surface roughness Ra of the tip surface of the electrode: 1.04 nm Surface roughness Rz of the wire end surface of the electrode: 8.69 nm Surface roughness Rq of the tip surface of the electrode: 1.33 nm According to the test under the plasma conditions of Experimental Example 1, it was confirmed that the step height D was in the range of 15 nm to 100 nm, which is the range in which the compression properties of hybrid bonding are good (when the elastic modulus is 2.5 GPa). In addition, it was confirmed that the surface roughness Ra of the organic insulating film and the surface roughness Ra, Rz, and Rq of the electrode were also kept to low values.

[0062] Next, in Experimental Examples 2 to 6, the same polyimide material with an elastic modulus of 2.5 GPa was used, and the plasma was irradiated onto the semiconductor substrate 100 under different plasma conditions. All conditions except for the plasma irradiation conditions were the same as in Experimental Example 1. The plasma conditions and test results for Experimental Examples 2 to 6 are shown in Table 1 below. Note that the evaluation A for bonding performance in Table 1 indicates, as mentioned above, that the step height D was within the range where the bonding performance of the hybrid bonding was good. As shown in Experimental Examples 1 to 6, it was confirmed that the step height D and the surface roughness Ra, Rz, and Rq can be changed (i.e., various adjustments can be made) by changing the plasma irradiation conditions.

[0063] Next, as further experimental examples, Experiments 7 to 11 were conducted. In Experiments 7 to 11, the plasma irradiated onto the semiconductor substrate 100 was changed from nitrogen plasma to argon plasma, and the plasma conditions were also changed when irradiating the semiconductor substrate 100 with plasma. Conditions other than the type of plasma irradiated onto the semiconductor substrate 100 and the plasma irradiation conditions were the same as in Experiment 1. The plasma conditions and test results in Experiments 7 to 11 are shown in Table 2 below. In addition, the evaluation A for the crimping performance in Table 2 indicates that the step D was within the range where the crimping performance of the hybrid bonding was good, as described above.

[0064] As shown in Experimental Examples 7 to 11, even when argon plasma was irradiated onto the semiconductor substrate 100 instead of nitrogen plasma, the evaluation of the bonding performance was still A, and it was confirmed that the step height D was within the range that allows for good bonding performance of hybrid bonding. However, comparing Table 1 and Table 2, it can be seen that the step height D in the experimental examples irradiated with nitrogen plasma is larger than the step height D in the experimental examples irradiated with argon plasma. For example, comparing Experimental Example 1 and Experimental Example 7, where the plasma output and processing time are the same, it was confirmed that the step height D in Experimental Example 1 is larger than the step height D in Experimental Example 7. Similarly, in Experimental Examples 2 and 8, Experimental Examples 3 and 9, Experimental Examples 4 and 10, and Experimental Examples 5 and 11, where the plasma output and processing time are the same, it was confirmed that the step height D in the experimental examples irradiated with nitrogen plasma is larger than the step height D in the experimental examples irradiated with argon plasma.

[0065] Furthermore, as shown in Experimental Examples 7 to 11, it was confirmed that even when argon plasma was irradiated onto the semiconductor substrate 100 instead of nitrogen plasma, the surface roughness Ra of the electrodes could be kept to a low value. However, comparing Table 1 and Table 2, it can be seen that the surface roughness Ra of the electrodes in the experimental examples irradiated with nitrogen plasma is lower than the surface roughness Ra of the electrodes in the experimental examples irradiated with argon plasma. For example, comparing Experimental Example 1 and Experimental Example 7, where the plasma output and processing time are the same, it was confirmed that the surface roughness Ra of the electrodes in Experimental Example 1 is lower than the surface roughness Ra of the electrodes in Experimental Example 7. Similarly, in Experimental Examples 2 and 8, Experimental Examples 3 and 9, Experimental Examples 4 and 10, and Experimental Examples 5 and 11, where the plasma output and processing time are the same, it was confirmed that the surface roughness Ra of the electrodes in the experimental examples irradiated with nitrogen plasma is lower than the surface roughness Ra of the electrodes in the experimental examples irradiated with argon plasma.

[0066] Regarding the electrode surface roughness Rz and Rq, a similar trend can be observed between the experimental examples irradiated with nitrogen plasma and those irradiated with argon plasma. Specifically, the electrode surface roughness Rz and Rq in the experimental examples irradiated with nitrogen plasma are lower than those in the experimental examples irradiated with argon plasma.

[0067] Next, as a further experimental example, Experimental Example 12 was conducted. In Experimental Example 12, the plasma irradiated onto the semiconductor substrate 100 was changed to nitrogen plasma and argon plasma, and the semiconductor substrate 100 was irradiated with the plasma under the following plasma conditions: RF output (plasma output): 500W Processing time (plasma processing time): 120 seconds Nitrogen flow rate (flow rate of gas for nitrogen plasma): 50 sccm Argon flow rate (flow rate of gas for argon plasma): 50 sccm The conditions other than the type of plasma irradiated onto the semiconductor substrate 100 and the plasma irradiation conditions were the same as in Experimental Example 1.

[0068] Furthermore, the test results in Experimental Example 12 were as follows: Step height D between the surface of the organic insulating film and the tip surface of the electrode: 75.35 nm Surface roughness Ra of the surface of the organic insulating film: 2.57 nm Surface roughness Ra of the tip surface of the electrode: 1.90 nm Surface roughness Rz of the wire end surface of the electrode: 16.32 nm Surface roughness Rq of the tip surface of the electrode: 2.57 nm According to the tests under the plasma conditions of Experimental Example 12, it was confirmed that even with etching using nitrogen plasma and argon plasma, the step height D was within the range of 15 nm to 100 nm, which is the range in which the compression adhesion of hybrid bonding is good. It was also confirmed that the surface roughness Ra of the organic insulating film and the surface roughness Ra, Rz, and Rq of the electrode could be kept to low values.

[0069] Based on the above experimental examples, it was confirmed that irradiating both the organic insulating film and the electrode with nitrogen plasma allows for different amounts of etching due to differences in their elastic moduli. Furthermore, it was confirmed that by changing the plasma conditions in such plasma treatment of organic insulating films, etc., according to the materials of the organic insulating film and the electrode, or the difference in their elastic moduli, it is possible to easily create a desired step difference between the surface of the organic insulating film on the semiconductor substrate and the tip surface of the electrode in a hybrid bonding method using an organic insulating film.

[0070] 1... Semiconductor device, 10... Semiconductor chip, 20... Semiconductor substrate, 100, 200... Semiconductor substrate, 101, 201... Substrate body, 101a, 201a... One side, 102, 202... Insulating film, 102a, 202a... Surface, 102b... Insulating film portion, 103, 203... Electrode, 103a, 203a... Tip surface, D... Step.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: preparing a first semiconductor substrate having a first substrate body, a first organic insulating film and a first electrode provided on one surface of the first substrate body; and irradiating the surface of the first semiconductor substrate with nitrogen plasma, wherein in the step of irradiating with nitrogen plasma, at least the first organic insulating film is etched by the nitrogen plasma such that the surface of the first organic insulating film is closer to the first substrate body than the tip surface of the first electrode.

2. In the process of irradiating with nitrogen plasma, the flow rate of the plasma gas is 3.38 × 10 －２ Pa・m ３ / sec (20 sccm) to 1.69 Pa·m ３ A method for manufacturing a semiconductor device according to claim 1, wherein the current is / sec (1000sccm).

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the plasma output in the step of irradiating with nitrogen plasma is 10 W to 1000 W.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the plasma processing time in the step of irradiating with nitrogen plasma is 180 seconds or less.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the elastic modulus of the first organic insulating film is 7.5 GPa or less.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein in the step of irradiating with nitrogen plasma, nitrogen plasma is irradiated onto the surface of the first semiconductor substrate such that the step distance between the surface of the first organic insulating film and the tip surface of the first electrode is 15 nm or more and 100 nm or less.

7. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, further comprising the step of polishing the first organic insulating film and the first electrode provided on one surface of the first semiconductor substrate, wherein the step of polishing the first semiconductor substrate is performed before the step of irradiating with nitrogen plasma.

8. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of polishing the first semiconductor substrate, the polishing is performed so that the surface roughness Ra of each surface of the first organic insulating film and the first electrode becomes 2.0 nm or less.

9. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, further comprising: preparing a second semiconductor substrate having a second substrate body, a second organic insulating film and a second electrode provided on one surface of the second substrate body; aligning the second electrode of the second semiconductor substrate with respect to the first electrode of the first semiconductor substrate; and heating and pressurizing the first semiconductor substrate and the second semiconductor substrate to bond the first organic insulating film and the second organic insulating film to each other, and to bond the first electrode and the second electrode to each other.

10. A method for manufacturing a semiconductor device according to claim 9, further comprising the step of irradiating the surface of the second semiconductor substrate with nitrogen plasma, wherein in the step of irradiating the second semiconductor substrate with nitrogen plasma, at least the second organic insulating film is etched by the nitrogen plasma such that the surface of the second organic insulating film is closer to the main body of the second substrate than the tip surface of the second electrode.

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