Multilevel inverter

Abstract

In the present invention, a voltage drop in a bootstrap circuit can be suppressed, and one period of a carrier signal is set as a control period. In a sixth process, a control device (6) calculates a first total time of a first switching state, a second total time of a second switching state, and a third total time of a third switching state in a prescribed period. In the sixth process, within one period of a carrier signal having a period of the same length as the total time of the first total time, the second total time, and the third total time, a zero vector, a voltage vector having twice the magnitude, a second voltage vector, and a third voltage vector are reordered so as to be in the order of the first switching state, the second switching state, the third switching state, the second switching state, and the first switching state, or in the order of the third switching state, the second switching state, the first switching state, the second switching state, and the third switching state, and time for the same switching state is allocated equally.

Description

Multi-level inverter

[0001] The present disclosure relates to a multi-level inverter, and more particularly to a multi-level inverter provided with a bootstrap circuit.

[0002] Patent Document 1 discloses a multi-level inverter. As an example of the multi-level inverter, Patent Document 1 discloses a T-type three-level three-phase inverter. The multi-level inverter disclosed in Patent Document 1 includes a DC power supply unit, a plurality (for example, three) of inverter circuits, a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, a plurality of second bootstrap circuits, a plurality of third bootstrap circuits, a power supply unit, and a control unit.

[0003] The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control period so that a composite vector of three voltage vectors other than the first voltage vector, a zero vector, and at least one second voltage vector among the plurality of voltage vectors coincides with the command voltage vector.

[0004] In the multi-level inverter disclosed in Patent Document 1, the voltage drop of each of the plurality of first bootstrap circuits and the plurality of second bootstrap circuits can be suppressed. However, in the multi-level inverter disclosed in Patent Document 1, it is necessary to set the control period to two periods of the carrier signal.

[0005] International Publication No. 2024 / 053452

[0006] An object of the present disclosure is to provide a multi-level inverter capable of suppressing a voltage drop in a bootstrap circuit and capable of setting one period of a carrier signal as a control period.

[0007] A multilevel inverter according to one embodiment of the present disclosure comprises a DC power supply unit, a plurality of inverter circuits, and a control system. The DC power supply unit has a positive electrode, a negative electrode, and an intermediate potential point. The plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The control system controls the plurality of inverter circuits. Each of the plurality of inverter circuits has a first switching element, a second switching element, a third switching element, and a fourth switching element, and a first diode, a second diode, a third diode, and a fourth diode connected in antiparallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively. In each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series from the positive electrode side to the negative electrode side in the order of the first switching element and the second switching element, and a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and the output point. The output point is the connection point of the first switching element and the second switching element. The control system includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, a power supply unit, a plurality of second bootstrap circuits, and a control device. The plurality of first gate drivers are connected to a plurality of first switching elements. The plurality of second gate drivers are connected to a plurality of second switching elements. The plurality of third gate drivers are connected to a plurality of third switching elements. The plurality of fourth gate drivers are connected to a plurality of fourth switching elements. The plurality of first bootstrap circuits are connected to the plurality of first gate drivers. The power supply unit supplies voltage to the plurality of second gate drivers. The plurality of second bootstrap circuits are connected to the plurality of third gate drivers and the plurality of fourth gate drivers. The control device stores a group of voltage vectors determined by combinations of potentials of a plurality of output points of the plurality of inverter circuits.The control device controls the plurality of inverter circuits via the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers. When controlling each of the plurality of inverter circuits, the control device performs first, second, third, fourth, fifth, and sixth processing. In the first processing, the control device selects a first voltage vector, a second voltage vector, and a third voltage vector, corresponding to each vertex of an equilateral triangle surrounding the command voltage vector, as a plurality of voltage vectors to be used within half a period of a predetermined period from the group of voltage vectors. In the second processing, the control device determines the first distribution time of the first voltage vector, the second distribution time of the second voltage vector, and the third distribution time of the third voltage vector within half a period of the predetermined period, so that the composite vector of the first voltage vector, the second voltage vector, and the third voltage vector matches the command voltage vector. In the third process, the control device distributes the first distribution time to the first voltage vector based on the number of times the first voltage vector is used within half of the predetermined period, distributes the second distribution time to the second voltage vector based on the number of times the second voltage vector is used within half of the predetermined period, and distributes the third distribution time to the third voltage vector based on the number of times the third voltage vector is used within half of the predetermined period. In the fourth process, the control device selects a voltage vector from among the first, second, and third voltage vectors as the first voltage vector, which has a reference magnitude and is closest to the command voltage vector, and replaces one of the first voltage vectors included in the first voltage vector with a zero vector in which the potential levels of the plurality of output points are all at the potential of the negative electrode, and a voltage vector that is in the same direction as the one first voltage vector and has twice the magnitude of the one first voltage vector.In the fifth process, the control device, with respect to the switching state of each of the plurality of inverter circuits, defines the switching state in which the potential of the output point is the potential of the positive electrode as the first switching state, the switching state in which the potential of the output point is the potential of the intermediate potential point as the second switching state, and the switching state in which the potential of the output point is the potential of the negative electrode as the third switching state, and calculates the first total time of the first switching state, the second total time of the second switching state, and the third total time of the third switching state in the predetermined period. In the sixth process, the control device rearranges the zero vector, the voltage vector with twice the magnitude, the second voltage vector, and the third voltage vector so that within one period of a carrier signal having a period of the same length as the sum of the first total time, the second total time, and the third total time, the switching state is in the order of first switching state, second switching state, third switching state, second switching state, first switching state, or third switching state, second switching state, first switching state, second switching state, third switching state, and distributes the time of the same switching state equally.

[0008] Figure 1 is a circuit diagram of a system equipped with a multilevel inverter according to an embodiment. Figure 2 is an explanatory diagram of the current path when the inverter circuit is in the first switching state in the multilevel inverter. Figure 3 is an explanatory diagram of the discharge and charge paths when the inverter circuit is in the first switching state in the multilevel inverter. Figure 4 is an explanatory diagram of the current path when the inverter circuit is in the second switching state in the multilevel inverter. Figure 5 is an explanatory diagram of the discharge and charge paths when the inverter circuit is in the second switching state in the multilevel inverter. Figure 6 is an explanatory diagram of the current path when the inverter circuit is in the third switching state in the multilevel inverter. Figure 7 is an explanatory diagram of the discharge and charge paths when the inverter circuit is in the third switching state in the multilevel inverter. Figure 8 is an explanatory diagram of the current path when the inverter circuit changes from the third switching state to the second switching state in the multilevel inverter. Figure 9 is an explanatory diagram of the voltage command values ​​of each phase in the multilevel inverter. Figure 10 is a spatial vector modulation diagram for explaining a group of voltage vectors related to the multilevel inverter. Figure 11 is a more detailed spatial vector modulation diagram illustrating a group of voltage vectors relating to the multilevel inverter described above. Figure 12 is a spatial vector modulation diagram illustrating the relationship between the command voltage vector, the first voltage vector, the second voltage vector, and the third voltage vector relating to the multilevel inverter described above. Figure 13 is a time chart of the switching state of each inverter circuit before rearranging the switching states when the voltage vectors are replaced in the control device of the multilevel inverter described above. Figure 14 is a time chart of the switching state of each inverter circuit after rearranging the switching states when the voltage vectors are replaced in the control device of the multilevel inverter described above. Figure 15 is a time chart of the switching state illustrating the formulas for calculating the first total time, second total time, and third total time for an inverter circuit of any X phase among the U phase, V phase, and W phase when the voltage vectors are replaced in the control device of the multilevel inverter described above.Figure 16 is a time chart showing the changes in the switching state of the U-phase inverter circuit and the states of the first to fourth switching elements before rearranging the switching states when the voltage vector is replaced in the control device of the multilevel inverter described above. Figure 17 is a time chart showing the changes in the switching state of the U-phase inverter circuit and the states of the first to fourth switching elements after rearranging the switching states when the voltage vector is replaced in the control device of the multilevel inverter described above. Figure 18 is a time chart showing the changes in the switching state of the V-phase inverter circuit and the states of the first to fourth switching elements before rearranging the switching states when the voltage vector is replaced in the control device of the multilevel inverter described above. Figure 19 is a time chart showing the changes in the switching state of the V-phase inverter circuit and the states of the first to fourth switching elements after rearranging the switching states when the voltage vector is replaced in the control device of the multilevel inverter described above. Figure 20 is a time chart showing the changes in the switching state of the W-phase inverter circuit and the states of the first to fourth switching elements before rearranging the switching states when the voltage vector is replaced in the control device of the multilevel inverter described above. Figure 21 is a time chart showing the switching state of the W-phase inverter circuit and the changes in the state of the first to fourth switching elements after rearranging the switching states when the voltage vector is replaced in the control device of the multilevel inverter described above. Figure 22 is an explanatory diagram of the operation of the multilevel inverter described above, showing the relationship between the duty cycle and output current and phase of the first and fourth control signals generated by the control device. Figure 23 is an explanatory diagram of the operation of the power converter according to Comparative Example 1, showing the relationship between the duty cycle and output current and phase of the first and fourth control signals generated by the control device when the control device performs three-phase modulation. Figure 24 is an explanatory diagram of the operation of the power converter according to Comparative Example 2, showing the relationship between the duty cycle and output current and phase of the first and fourth control signals generated by the control device when the control device performs spatial vector modulation.

[0009] (Embodiment) Below, a multilevel inverter 100 according to an embodiment will be described with reference to Figures 1 to 22.

[0010] (1) Overview The multilevel inverter 100 comprises, for example, a DC power supply unit 3, a plurality (for example, three) inverter circuits 1, and a control system 60, as shown in Figure 1. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The "intermediate potential point M1" is the point where the potential is midway between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The control system 60 controls the plurality of inverter circuits 1.

[0011] The multilevel inverter 100 is a T-type three-level three-phase inverter. In the multilevel inverter 100, each of the multiple inverter circuits 1 has an output terminal 41. In the multilevel inverter 100, an AC load RA1 is connected to the multiple output terminals (AC terminals) 41. The AC load RA1 is, for example, a three-phase servo motor. In the multilevel inverter 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining one is an inverter circuit 1W that outputs a W-phase voltage.

[0012] Each of the multiple inverter circuits 1 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4, and a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are connected in antiparallel to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, respectively. In each of the multiple inverter circuits 1, the first switching element Q1 and the second switching element Q2 are connected in series such that they are arranged in the order of first switching element Q1 and second switching element Q2 from the positive electrode P1 side to the negative electrode N1 side. That is, as shown in Figures 1 and 2, the series circuit of the first switching element Q1 and the second switching element Q2 (first circuit 11) is connected between the positive electrode P1 and the negative electrode N1. In each of the multiple inverter circuits 1, a series circuit (second circuit 12) of a third switching element Q3 and a fourth switching element Q4 is connected between an intermediate potential point M1 and an output point 13. The output point 13 is the connection point between the first switching element Q1 and the second switching element Q2. The second circuit 12 has a bidirectional switch including the third switching element Q3, the fourth switching element Q4, the third diode D3, and the fourth diode D4.

[0013] The control system 60 includes a plurality (for example, three) first gate drivers 61, a plurality (for example, three) second gate drivers 62, a plurality (for example, three) third gate drivers 63, and a plurality (for example, three) fourth gate drivers 64. The control system 60 also includes a plurality (for example, three) bootstrap circuits 71 (hereinafter also referred to as first bootstrap circuits 71), a plurality (for example, three) second bootstrap circuits 72, a power supply unit 9, and a control device 6.

[0014] Multiple first gate drivers 61 drive the first switching elements Q1 of the multiple inverter circuits 1. Multiple second gate drivers 62 drive the second switching elements Q2 of the multiple inverter circuits 1. Multiple third gate drivers 63 drive the third switching elements Q3 of the multiple inverter circuits 1. Multiple fourth gate drivers 64 drive the fourth switching elements Q4 of the multiple inverter circuits 1.

[0015] Multiple first bootstrap circuits 71 correspond one-to-one with multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 supplies voltage to the corresponding first gate driver 61. Multiple second bootstrap circuits 72 correspond to multiple third gate drivers 63 and multiple fourth gate drivers 64. Each of the multiple second bootstrap circuits 72 supplies voltage to the corresponding third gate driver 63 and corresponding fourth gate driver 64. The power supply unit 9 supplies voltage to the multiple second gate drivers 62.

[0016] The control device 6 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64.

[0017] (2) Details of the multilevel inverter The DC power supply unit 3 has a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series. The DC power supply unit 3 further has a first DC terminal 31 connected to the positive terminal P1 and a second DC terminal 32 connected to the negative terminal N1. In the DC power supply unit 3, the first end of the first capacitor C1 is connected to the first DC terminal 31, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the first capacitor C1 and the second capacitor C2 is an intermediate potential point M1. A DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32, for example. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1. "The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" does not mean that the capacitance of the second capacitor C2 is exactly the same as the capacitance of the first capacitor C1, but rather that the capacitance of the second capacitor C2 is within the range of 90% to 110% of the capacitance of the first capacitor C1.

[0018] In the following explanation, for convenience, the output terminal 41 included in inverter circuit 1U will be referred to as output terminal 41U, the output terminal 41 included in inverter circuit 1V will be referred to as output terminal 41V, and the output terminal included in inverter circuit 1W will be referred to as output terminal 41W. Furthermore, in the following explanation, the polarity of the output currents iU, iV, and iW flowing through the U, V, and W phases of the AC load RA1 will be described as positive when flowing in the direction of the arrows in Figure 1, and negative when flowing in the opposite direction to the arrows in Figure 1.

[0019] Each inverter circuit 1 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4, each having a control terminal, a first main terminal, and a second main terminal. Each inverter circuit 1 has an insulated-gate bipolar transistor (IGBT), for example. Therefore, the control terminal, first main terminal, and second main terminal of each of the first switching element Q1, second switching element Q2, third switching element Q3, and fourth switching element Q4 in each inverter circuit 1 are the gate terminal, collector terminal, and emitter terminal, respectively.

[0020] The control terminal of the first switching element Q1 of each inverter circuit 1 is connected to the corresponding first gate driver 61 from among a plurality of first gate drivers 61. The control terminal of the second switching element Q2 of each inverter circuit 1 is connected to the corresponding second gate driver 62 from among a plurality of second gate drivers 62. The control terminal of the third switching element Q3 of each inverter circuit 1 is connected to the corresponding third gate driver 63 from among a plurality of third gate drivers 63. The control terminal of the fourth switching element Q4 of each inverter circuit 1 is connected to the corresponding fourth gate driver 64 from among a plurality of fourth gate drivers 64.

[0021] In each inverter circuit 1, the first main terminal of the first switching element Q1 is connected to the positive terminal P1 of the DC power supply unit 3, and the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2. In addition, in each inverter circuit 1, the second main terminal of the second switching element Q2 is connected to the negative terminal N1 of the DC power supply unit 3.

[0022] Furthermore, in each inverter circuit 1, the first main terminal of the third switching element Q3 is connected to the intermediate potential point M1, the second main terminal of the third switching element Q3 is connected to the second main terminal of the fourth switching element Q4, and the first main terminal of the fourth switching element Q4 is connected to the output point 13. Therefore, the bidirectional switch in the second circuit 12 (see Figure 2) is a common-emitter bidirectional switch in which the second main terminal (emitter terminal) of the third switching element Q3 and the second main terminal (emitter terminal) of the fourth switching element Q4 are connected.

[0023] In inverter circuit 1U, output point 13 (the connection point between the first switching element Q1 and the second switching element Q2) is connected to output terminal 41U. In inverter circuit 1V, output point 13 (the connection point between the first switching element Q1 and the second switching element Q2) is connected to output terminal 41V. In inverter circuit 1W, output point 13 (the connection point between the first switching element Q1 and the second switching element Q2) is connected to output terminal 41W. The output point 13 of inverter circuit 1U is connected to, for example, the U-phase terminal of an AC load RA1 via output terminal 41U. The output point 13 of inverter circuit 1V is connected to, for example, the V-phase terminal of an AC load RA1 via output terminal 41V. The output point 13 of inverter circuit 1W is connected to, for example, the W-phase terminal of an AC load RA1 via output terminal 41W.

[0024] In each inverter circuit 1, the anode of the first diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In addition, in each inverter circuit 1, the anode of the second diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In addition, in each inverter circuit 1, the anode of the third diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. Furthermore, in each inverter circuit 1, the anode of the fourth diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0025] In each inverter circuit 1, the first diode D1 may be replaced with a parasitic diode of the IGBT constituting the first switching element Q1. Also, in each inverter circuit 1, the second diode D2 may be replaced with a parasitic diode of the IGBT constituting the second switching element Q2. Also, in each inverter circuit 1, the third diode D3 may be replaced with a parasitic diode of the IGBT constituting the third switching element Q3. Also, in each inverter circuit 1, the fourth diode D4 may be replaced with a parasitic diode of the IGBT constituting the fourth switching element Q4.

[0026] Multiple first gate drivers 61 correspond one-to-one with multiple first switching elements Q1. Each of the multiple first gate drivers 61 is connected to the control terminal of the corresponding first switching element Q1. Each of the multiple first gate drivers 61 drives the corresponding first switching element Q1. Multiple first gate drivers 61 are connected to a control device 6. The control device 6 outputs multiple first control signals S1 (see Figure 2) that correspond one-to-one with each of the multiple first gate drivers 61. Each of the multiple first gate drivers 61 controls the first switching element Q1 to be on or off based on the given first control signal S1.

[0027] Multiple second gate drivers 62 correspond one-to-one with multiple second switching elements Q2. Each of the multiple second gate drivers 62 is connected to the control terminal of the corresponding second switching element Q2. Each of the multiple second gate drivers 62 drives the corresponding second switching element Q2. Multiple second gate drivers 62 are connected to a control device 6. The control device 6 outputs multiple second control signals S2 (see Figure 2) that correspond one-to-one with the multiple second gate drivers 62. Each of the multiple second gate drivers 62 controls the second switching element Q2 to be on or off based on the given second control signal S2.

[0028] Multiple third gate drivers 63 correspond one-to-one with multiple third switching elements Q3. Each of the multiple third gate drivers 63 is connected to the control terminal of the corresponding third switching element Q3. Each of the multiple third gate drivers 63 drives the corresponding third switching element Q3. The multiple third gate drivers 63 are connected to a control device 6. The control device 6 outputs multiple third control signals S3 (see Figure 2) that correspond one-to-one with the multiple third gate drivers 63. Each of the multiple third gate drivers 63 controls the on / off state of the third switching element Q3 based on the given third control signal S3.

[0029] Multiple fourth gate drivers 64 correspond one-to-one with multiple fourth switching elements Q4. Each of the multiple fourth gate drivers 64 is connected to the control terminal of the corresponding fourth switching element Q4. The multiple fourth gate drivers 64 drive the corresponding fourth switching element Q4. Each of the multiple fourth gate drivers 64 is connected to the control device 6. The control device 6 outputs multiple fourth control signals S4 (see Figure 2) that correspond one-to-one with the multiple fourth gate drivers 64. Each of the multiple fourth gate drivers 64 controls the on / off state of the fourth switching element Q4 based on the given fourth control signal S4.

[0030] Multiple first bootstrap circuits 71 correspond one-to-one with multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 supplies voltage to the corresponding first gate driver 61. Each of the multiple first bootstrap circuits 71 has a diode D17, a resistor R17, and a capacitor C17 (also called a boost capacitor C17), as shown in Figures 1 and 3. In each first bootstrap circuit 71, the anode of diode D17 is connected to the positive terminal of the power supply unit 9, and the cathode of diode D17 is connected to the first terminal of capacitor C17 via resistor R17. The first terminal of capacitor C17 is connected to the high-potential side power supply terminal 61H (see Figure 3) of the first gate driver 61, and the second terminal of capacitor C17 is connected to the low-potential side power supply terminal 61L (see Figure 3) of the first gate driver 61. The first bootstrap circuit 71 supplies the first gate driver 61 with the voltage necessary to turn on the first switching element Q1 in the first gate driver 61. Each of the multiple first bootstrap circuits 71 further has a Zener diode Z17 connected in parallel with the capacitor C17.

[0031] The multiple second bootstrap circuits 72 correspond to the multiple third gate drivers 63 and the multiple fourth gate drivers 64. Each of the multiple second bootstrap circuits 72 supplies voltage to the corresponding third gate driver 63 and the corresponding fourth gate driver 64. Each of the multiple second bootstrap circuits 72 has a diode D27, a resistor R27 and a capacitor C27 (also called a boost capacitor C27). In each second bootstrap circuit 72, the anode of diode D27 is connected to the positive terminal of the power supply unit 9, and the cathode of diode D27 is connected to the first terminal of capacitor C27 via resistor R27. The first terminal of capacitor C27 is connected to the high-potential side power supply terminal 63H of the third gate driver 63 (see Figure 3) and the high-potential side power supply terminal 64H of the fourth gate driver 64 (see Figure 3). The second terminal of capacitor C27 is connected to the low-potential power supply terminal 63L of the third gate driver 63 (see Figure 3) and the low-potential power supply terminal 64L of the fourth gate driver 64 (see Figure 3). Each of the multiple second bootstrap circuits 72 supplies the voltage necessary to turn on the third switching element Q3 in the corresponding third gate driver 63, and supplies the voltage necessary to turn on the fourth switching element Q4 in the corresponding fourth gate driver 64. Each of the multiple second bootstrap circuits 72 further has a Zener diode Z27 connected in parallel with capacitor C27.

[0032] The power supply unit 9 supplies voltage to a plurality (three) of first bootstrap circuits 71, a plurality (three) of second bootstrap circuits 72, and a plurality (three) of second gate drivers 62. The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91. The positive terminal of the power supply unit 9 is connected to the high-potential side power supply terminal 62H (see Figure 3) of each of the plurality of second gate drivers 62, and the negative terminal of the power supply unit 9 is connected to the low-potential side power supply terminal 62L (see Figure 3) of each of the plurality of second gate drivers 62.

[0033] The control device 6 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4 by controlling a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. The execution entity of the control device 6 includes a computer system. The computer system has one or more computers. The computer system mainly consists of a processor and memory as hardware. The function of the control device 6 as the execution entity in this disclosure is realized by the processor executing a program recorded in the memory of the computer system. The program may be pre-recorded in the memory of the computer system, may be provided via a telecommunications line, or may be recorded and provided on a non-temporary recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) that can be read by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The plurality of electronic circuits may be aggregated on a single chip or distributed across multiple chips. Multiple chips may be integrated into a single device, or they may be distributed across multiple devices.

[0034] The control device 6 outputs multiple (three) first control signals S1 (see Figure 2) for controlling multiple (three) first switching elements Q1, multiple (three) second control signals S2 (see Figure 2) for controlling multiple (three) second switching elements Q2, multiple (three) third control signals S3 (see Figure 2) for controlling multiple third switching elements Q3, and multiple (three) fourth control signals S4 for controlling multiple (three) fourth switching elements Q4. Note that in Figure 2, only one of the three inverter circuits 1 is shown, and the remaining two inverter circuits 1 are not shown. Also, in Figure 2, the multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, multiple fourth gate drivers 64, multiple first bootstrap circuits 71, multiple second bootstrap circuits 72, and the power supply unit 9 are not shown. Furthermore, in Figure 3, only one of the three inverter circuits 1 is shown, and the remaining two inverter circuits 1 are omitted from the illustration. Also, in Figure 3, the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, and the two second bootstrap circuits 72 are omitted from the illustration.

[0035] The three first control signals S1 include a first control signal S1U for controlling the first switching element Q1 of the inverter circuit 1U, a first control signal S1V for controlling the first switching element Q1 of the inverter circuit 1V, and a first control signal S1W for controlling the first switching element Q1 of the inverter circuit 1W.

[0036] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the inverter circuit 1U, a second control signal S2V that controls the second switching element Q2 of the inverter circuit 1V, and a second control signal S2W that controls the second switching element Q2 of the inverter circuit 1W.

[0037] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the inverter circuit 1U, a third control signal S3V that controls the third switching element Q3 of the inverter circuit 1V, and a third control signal S3W that controls the third switching element Q3 of the inverter circuit 1W.

[0038] The three fourth control signals S4 include a fourth control signal S4U for controlling the fourth switching element Q4 of the inverter circuit 1U, a fourth control signal S4V for controlling the fourth switching element Q4 of the inverter circuit 1V, and a fourth control signal S4W for controlling the fourth switching element Q4 of the inverter circuit 1W.

[0039] Each of the multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level. The first potential level is, for example, 0V, and the second potential level is a potential level greater than the gate threshold voltage of the IGBT. In other words, in each of the multiple control signals (multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4), the first potential level is the potential level required to turn off the switching element corresponding to that control signal, and the second potential level is the potential level required to turn on the switching element corresponding to that control signal.

[0040] Each of the multiple first switching elements Q1 is turned on when the corresponding first control signal S1 is high level and turned off when it is low level. Each of the multiple second switching elements Q2 is turned on when the corresponding second control signal S2 is high level and turned off when it is low level. Each of the multiple third switching elements Q3 is turned on when the corresponding third control signal S3 is high level and turned off when it is low level. Each of the multiple fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is high level and turned off when it is low level.

[0041] In the multilevel inverter 100, each of the plurality of inverter circuits 1 is controlled to be in the first switching state, the second switching state, or the third switching state. That is, in each of the three inverter circuits 1U, 1V, and 1W of the multilevel inverter 100, the switching state is controlled to be any one of the first switching state, the second switching state, and the third switching state. The first switching state, the second switching state, and the third switching state are different in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the plurality of inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from each other. That is, in each of the plurality of inverter circuits 1, the potential level of the output voltage changes in three levels according to the states of the first to fourth switching elements Q1 to Q4. Regarding the output voltages of the plurality of inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W have different phases from each other.

[0042] The first switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are in the on state, and both the second switching element Q2 and the fourth switching element Q4 are in the off state. Each of the plurality of inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3 when being controlled to be in the first switching state. In the first switching state, in each of the plurality of inverter circuits 1, the potential of the output point 13 becomes the potential level of the positive electrode P1 of the DC power supply unit 3 (for example, Vdc / 2).

[0043] The second switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in an off state, and both the third switching element Q3 and the fourth switching element Q4 are in an on state. When each of the plurality of inverter circuits 1 is controlled to the second switching state, it can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. When each of the plurality of inverter circuits 1 is in the second switching state, the potential of the output point 13 becomes the potential level (for example, 0) of the intermediate potential point M1.

[0044] The third switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are in an off state, and both the second switching element Q2 and the fourth switching element Q4 are in an on state. When each of the plurality of inverter circuits 1 is controlled to the third switching state, it can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. When each of the plurality of inverter circuits 1 is in the third switching state, the potential of the output point 13 becomes the potential level (for example, -Vdc / 2) of the negative electrode N1 of the DC power supply unit 3.

[0045] When the inverter circuit 1 is in the first switching state, as shown in FIG. 2, current flows through the path of the positive electrode P1 of the DC power supply unit 3 - the first switching element Q1 - the output point 13 - the output terminal 41 (see FIG. 1), and the voltage value of the output voltage to the AC load RA1 (see FIG. 1) becomes approximately Vdc / 2.

[0046] Furthermore, when the inverter circuit 1 is in the first switching state, the power supply unit 9 does not charge the capacitor C17 of the first bootstrap circuit 71. Instead, the capacitor C17 of the first bootstrap circuit 71 supplies the voltage necessary for the first gate driver 61 to turn on the first switching element Q1. Consequently, the charge on the capacitor C17 of the first bootstrap circuit 71 is discharged through the discharge path Ru1 of capacitor C17 - high-potential side power supply terminal 61H of the first gate driver 61 - low-potential side power supply terminal 61L of the first gate driver 61 - capacitor C17, as shown in Figure 3. As a result, the voltage across the capacitor C17 in the first bootstrap circuit 71 decreases over time.

[0047] Furthermore, when the inverter circuit 1 is in the first switching state, the power supply unit 9 does not charge the capacitor C27 of the second bootstrap circuit 72. Instead, the capacitor C27 of the second bootstrap circuit 72 supplies the voltage necessary for the third gate driver 63 to turn on the third switching element Q3. Consequently, the charge on the capacitor C27 of the second bootstrap circuit 72 is discharged through the discharge path Ru3, as shown in Figure 3: capacitor C27 - high-potential side power supply terminal 63H of the third gate driver 63 - low-potential side power supply terminal 63L of the third gate driver 63 - capacitor C27. As a result, the voltage across the capacitor C27 in the second bootstrap circuit 72 decreases over time.

[0048] Furthermore, when the inverter circuit 1 is in the second switching state (when it changes from the first switching state to the second switching state), for example, as shown in Figure 4, current flows through the path from the intermediate potential point M1 of the DC power supply unit 3 - the third switching element Q3 - the fourth switching element Q4 - the output point 13 - the output terminal 41 (see Figure 1), and the voltage value of the output voltage to the AC load RA1 becomes approximately Vdc / 2. More specifically, when the inverter circuits 1U, 1V, and 1W are in the second switching state, the third switching state, and the third switching state, respectively, current flows through the path from the intermediate potential point M1 of the DC power supply unit 3 - the third switching element Q3 of the inverter circuit 1U - the fourth switching element Q4 of the inverter circuit 1U - the output point 13 - the output terminal 41U (see Figure 1).

[0049] Furthermore, when the inverter circuit 1 is in the second switching state, the capacitor C27 of the second bootstrap circuit 72 supplies the voltage necessary for the third gate driver 63 to turn on the third switching element Q3. Therefore, as shown in Figure 5, the charge of the capacitor C27 of the second bootstrap circuit 72 is discharged through the discharge path Ru3 of capacitor C27 - high-potential side power supply terminal 63H of the third gate driver 63 - low-potential side power supply terminal 63L of the third gate driver 63 - capacitor C27. Also, when the inverter circuit 1 is in the second switching state, the capacitor C27 of the second bootstrap circuit 72 supplies the voltage necessary for the fourth gate driver 64 to turn on the fourth switching element Q4. Therefore, the charge in capacitor C27 of the second bootstrap circuit 72 is discharged through the discharge path Ru4: capacitor C27 - high-potential power supply terminal 64H of the fourth gate driver 64 - low-potential power supply terminal 64L of the fourth gate driver 64 - capacitor C27.

[0050] Furthermore, when the inverter circuit 1 is in the third switching state, as shown in Figure 6, current flows through the path from the output terminal 41 (see Figure 1) - output point 13 - second switching element Q2 - negative terminal N1 of the DC power supply unit 3, and the output voltage value to the AC load RA1 becomes approximately 0. Also, when the inverter circuit 1 is in the third switching state, the capacitor C17 of the first bootstrap circuit 71 is charged by the power supply unit 9, so the voltage of capacitor C17 rises over time and capacitor C17 becomes fully charged. As shown in Figure 7, the charging path Ru91 for charging capacitor C17 by the power supply unit 9 is the path from the positive terminal of the power supply unit 9 - diode D17 - resistor R17 - capacitor C17 - output point 13 - second switching element Q2 - negative terminal of the power supply unit 9.

[0051] Furthermore, when the inverter circuit 1 is in the third switching state, the power supply unit 9 charges the capacitor C27 of the second bootstrap circuit 72. The charging path Ru92 for charging the capacitor C27 by the power supply unit 9 is the path from the positive terminal of the power supply unit 9 - diode D27 - resistor R27 - capacitor C27 - fourth switching element Q4 - output point 13 - second switching element Q2 - negative terminal of the power supply unit 9.

[0052] Furthermore, when inverter circuit 1 is in the second switching state (when it changes from the third switching state to the second switching state), for example, as shown in Figure 8, current flows through the path from output terminal 41 (see Figure 1) - output point 13 - fourth switching element Q4 - third switching element Q3 - intermediate potential point M1, and the output voltage value to the AC load RA1 becomes approximately 0. More specifically, when inverter circuits 1U, 1V, and 1W are in the second switching state, second switching state, and first switching state, respectively, current flows through the path from output terminal 41 of inverter circuit 1U - output point 13 - fourth switching element Q4 - third switching element Q3 - intermediate potential point M1, and the output voltage value to the AC load RA1 becomes approximately 0.

[0053] Here, when the inverter circuit 1 is in the second switching state, the charge of capacitor C27 is discharged through the discharge paths Ru3 and Ru4 shown in Figure 5 above.

[0054] In the multilevel inverter 100, if the direction of current flow from the output point 13 to the output terminal 41 is defined as positive and the direction of current flow from the output terminal 41 to the output point 13 is defined as negative for each output current of the multiple inverter circuits 1, then the waveforms of the U-phase output current iU, the V-phase output current iV, and the W-phase output current iW will be sinusoidal waveforms. Note that the U-phase output current iU, the V-phase output current iV, and the W-phase output current iW will be sinusoidal currents with, for example, a phase difference of 120° from each other.

[0055] The control device 6 generates first to fourth control signals S1U to S4U, first to fourth control signals S1V to S4V, and first to fourth control signals S1W to S4W based on voltage commands Vu, Vv, and Vw (see Figure 9) relating to the output voltages of the multiple inverter circuits 1U, 1V, and 1W, respectively. The first to fourth control signals S1U to S4U are the first to fourth control signals S1 to S4 for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U. The first to fourth control signals S1V to S4V are the first to fourth control signals S1 to S4 for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V. The first to fourth control signals S1W to S4W are the first to fourth control signals S1 to S4 for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W.

[0056] As shown in Figure 9, the voltage commands Vu, Vv, and Vw are, for example, sinusoidal signals with a phase difference of 120° from each other, and their values ​​(voltage command values) change over time. The length of one period for each of the voltage commands Vu, Vv, and Vw is the same.

[0057] The control device 6 may also perform PI (Proportional Integral) control of the voltage commands Vu, Vv, and Vw based on information output from the detection unit 8 (see Figure 1) which detects the state of the AC load RA1. When the AC load RA1 is a three-phase servo motor, the information output from the detection unit 8 includes, for example, at least one of the following: information from the detection results of multiple current sensors that detect the output currents iU, iV, and iW flowing through the U, V, and W phases of the AC load RA1, respectively, and information from the detection results of an encoder that detects the rotational speed, rotational angle, etc., of the three-phase motor.

[0058] The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with respect to each other.

[0059] The control device 6 controls the multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, and multiple fourth gate drivers 64 by performing the voltage vector control described below.

[0060] The control device 6 stores a group of voltage vectors in advance. Each of the voltage vectors in the group is determined by a combination of potential levels at the output points 13 between the first switching element Q1 and the second switching element Q2 of the plurality of inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the inverter circuit 1U corresponding to the U phase, the switching state of the inverter circuit 1V corresponding to the V phase, and the switching state of the inverter circuit 1W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 3 ３ = 27 items.

[0061] A group of voltage vectors includes three zero vectors V0p, V0n, and V0z, each with a magnitude of zero, as shown in the three-level spatial vector diagram (spatial vector modulation diagram) in Figure 10. Furthermore, a group of voltage vectors also includes vectors with a magnitude of (2 / 3) １／２ It contains six voltage vectors V1, V2, V3, V4, V5, and V6, each with a voltage of 2Vdc and different directions. Furthermore, each group of voltage vectors has a magnitude of (2 / 3). １／２ It includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, where Vdc is. Also, each group of voltage vectors has a magnitude of (2 / 3). １／２ 3 １／２ - Includes six voltage vectors V13, V14, V15, V16, V17, and V18, which are Vdc and have different directions. In this embodiment, (2 / 3) １／２Vdc is used as the reference magnitude. In Figure 10, the angle between any two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between any two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees. Note that Figure 10 is a three-level spatial vector diagram illustrating a group of voltage vectors on an orthogonal α-β coordinate system.

[0062] A group of voltage vectors can be represented as shown in Figure 11, a three-level spatial vector diagram (spatial vector modulation diagram), by expressing the first switching state, second switching state, and third switching state with the symbols "P", "0", and "N", respectively, and listing them in the order of U-phase, V-phase, and W-phase.

[0063] As shown in Figure 11, the three zero vectors V0p, V0z, and V0n can be expressed as V0p[PPP], V0z

[000] , and V0n[NNN], respectively. For example, V0p[PPP] represents that with respect to the zero vector V0p, the switching state of the U-phase inverter circuit 1U is "P", the switching state of the V-phase inverter circuit 1V is "P", and the switching state of the W-phase inverter circuit 1W is "P". Similarly, V0z

[000] represents that with respect to the zero vector V0z, the switching state of the U-phase inverter circuit 1U is "0", the switching state of the V-phase inverter circuit 1V is "0", and the switching state of the W-phase inverter circuit 1W is "0". Furthermore, V0n[NNN] represents that, with respect to the zero vector V0n, the switching state of the U-phase inverter circuit 1U is "N", the switching state of the V-phase inverter circuit 1V is "N", and the switching state of the W-phase inverter circuit 1W is "N". When the switching state of inverter circuit 1 is "P", the potential of the output point 13 in that inverter circuit 1 is the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of inverter circuit 1 is "N", the potential of the output point 13 in that inverter circuit 1 is the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of inverter circuit 1 is "0", the potential of the output point 13 in that inverter circuit 1 is the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0064] Furthermore, voltage vectors denoted with "p," such as V10p, include "P" but do not include "N." This applies to the following as well. Similarly, voltage vectors denoted with "n," such as V10n, include "N" but do not include "P." This also applies to the following as well.

[0065] The six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors like V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], which do not have "p", "n", or "z" appended after the number "V", include "P" and "N" as three-phase switching states. A group of voltage vectors includes six V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], each with a magnitude twice that of the reference magnitude.

[0066] Furthermore, the twelve voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively. Therefore, a group of voltage vectors includes 12 voltage vectors, V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], each of which has a reference magnitude (reference vector).

[0067] Furthermore, the six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0], respectively. A group of voltage vectors has a magnitude of 3 times the reference magnitude. １／２ It includes six voltage vectors of double the magnitude: V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0].

[0068] The control device 6 converts the instantaneous value of the command voltage for each output voltage of the plurality of inverter circuits 1 into a command voltage vector Vref (see Figure 12). If Vα is the α-axis component of the command voltage vector Vref in the orthogonal α-β coordinate system, and Vβ is the β-axis component of the command voltage vector Vref in the orthogonal α-β coordinate system, then the command voltage vector Vref can be obtained using equation (1).

[0069]

[0070] The control device 6 performs the first to sixth processes when controlling each of the multiple inverter circuits 1. The following describes an example of the operation of the control device 6, specifically the case where the command voltage vector Vref is at the position shown in Figure 12.

[0071] In the first process, the control device 6 selects a group of voltage vectors to be used within a period T (see Figure 16) which is half of a predetermined period Ts1. These voltage vectors correspond to the vertices of an equilateral triangle surrounding the command voltage vector Vref, as shown in Figure 12. In the example in Figure 12, the first voltage vector Va includes voltage vectors V7p [P00] and V7n [0NN], the second voltage vector Vb is voltage vector V1 [PNN], and the third voltage vector Vc is voltage vector V13 [P0N]. The period T is the period of the triangular wave carrier signal, and the predetermined period Ts1 is 2 × T.

[0072] In the second process, the control device 6 determines the first distribution time T0 for the first voltage vector Va, the second distribution time T1 for the second voltage vector Vb, and the third distribution time T2 for the third voltage vector Vc in a period T which is half of a predetermined period Ts1, so that the combined vector of the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc matches the command voltage vector Vref.

[0073] The control device 6 determines the first distribution time T0, the second distribution time T1, and the third distribution time T2 such that equations (2) and (3) are satisfied, where V is the magnitude of the command voltage vector Vref and θ is the angle between the command voltage vector Vref and the α-axis. In equation (2), "j" is the imaginary unit. The angle between the first voltage vector Va closest to the command voltage vector Vref and the command voltage vector Vref is less than 30 degrees.

[0074]

[0075]

[0076] In the third process, the control device 6 distributes a first distribution time T0 to each first voltage vector Va based on the number of times the first voltage vector Va is used within one cycle T of the carrier signal, distributes a second distribution time T1 to each second voltage vector Vb based on the number of times the second voltage vector Vb is used within one cycle T of the carrier signal, and distributes a third distribution time T2 to each third voltage vector Vc based on the number of times the third voltage vector Vc is used within one cycle T of the carrier signal.

[0077] In the fourth process, the control device 6 selects a voltage vector from among the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc as the first voltage vector Va, which has a reference magnitude and is closest to the command voltage vector Vref. In a predetermined period Ts1, the control device 6 replaces the first voltage vector VV1, which is the first voltage vector Va, with a zero vector V0n [NNN] which is a combination in which the potential levels of the multiple output points 13 are all at the potential of the negative electrode N1, and a voltage vector VV2 which has the same direction as the first voltage vector VV1 and is twice the magnitude of the first voltage vector VV1.

[0078] In the fourth process, when the control device 6 changes the switching state of two adjacent voltage vectors among the eight voltage vectors arranged in time series within a predetermined period Ts1, it changes the switching state of only one of the U-phase, V-phase, and W-phase between "P" and "0" or between "0" and "N". In the example in Figure 13, the control device 6 uses the voltage vectors in the following order: voltage vector V7n[0NN] → voltage vector V1[PNN] → voltage vector V13[P0N] → voltage vector V1[PNN] → zero vector V0n[NNN] → voltage vector V1[PNN] → voltage vector V13[P0N] → voltage vector V7p[P00]. In the example shown in Figure 13, the control device 6 has a first voltage vector Va that includes voltage vector V7n[0NN] and voltage vector V7p[P00], and replaces the first voltage vector Va with a zero vector V0n[NNN] and voltage vector VV2 (voltage vector V1 in the example shown in Figure 13). The allocation times for the zero vector V0n[NNN] and voltage vector VV2 are the same as the allocation times for the voltage vector V7n[0NN] and voltage vector V7p[P00] before the replacement (T0 / 2 in the example shown in Figure 13).

[0079] In the fifth process, the control device 6 calculates the first total time Txp for the first switching state, the second total time Txz for the second switching state, and the third total time Txn for the third switching state in a predetermined period Ts1. As described above, the first switching state is a switching state in which the potential of the output point 13 is at the potential of the positive electrode P1 for each switching state of the plurality of inverter circuits 1. The second switching state is a switching state in which the potential of the output point 13 is at the potential of the intermediate potential point M1 for each switching state of the plurality of inverter circuits 1. The third switching state is a switching state in which the potential of the output point 13 is at the potential of the negative electrode N1 for each switching state of the plurality of inverter circuits 1. The fifth process in the control device 6 will now be described in more detail. The control device 6 calculates the total time of the first switching state for each of the six types of voltage vectors used in a predetermined period Ts1 as the first total time Txp. Furthermore, the control device 6 calculates the total time of the second switching state for each of the six types of voltage vectors used in a predetermined period Ts1 as the second total time Txz. Furthermore, the control device 6 calculates the total time of the third switching state for each of the six types of voltage vectors used in a predetermined period Ts1 as the third total time Txn. In the example of Figure 15, with respect to the switching state of the inverter circuit 1 of the X phase (the X phase is the U phase, V phase, or W phase), the control device 6 calculates the first total time Txp by, for example, the following equation (4), calculates the second total time Txz by, for example, the following equation (5), and calculates the third total time Txn by, for example, the following equation (6). In equation (4), Tp is the time of the first switching state of the voltage vector in the parentheses immediately following Tp. Tz is the time of the second switching state of the voltage vector in the parentheses following Tz. Tn is the time of the third switching state of the voltage vector in the parentheses following Tn. Furthermore, in equations (4), (5), and (6), Vn represents the voltage vector VV2 obtained by substituting the first voltage vector VV1, and in the examples of Figures 13 and 15, it is the fourth voltage vector V1[PNN].

[0080]

[0081]

[0082]

[0083] The first total time Txp, the second total time Txz, and the third total time Txn are described as the first total time Tup, the second total time Tuz, and the third total time Tun when relating to the first, second, and third switching states of the U-phase inverter circuit 1U. Similarly, the first total time Txp, the second total time Txz, and the third total time Txn are described as the first total time Tvp, the second total time Tvz, and the third total time Tvn when relating to the first, second, and third switching states of the V-phase inverter circuit 1V. Furthermore, the first total time Txp, the second total time Txz, and the third total time Txn are described as the first total time Twp, the second total time Twz, and the third total time Twn when relating to the first, second, and third switching states of the W-phase inverter circuit 1W.

[0084] In the example in Figure 13, the first total time Tup, the second total time Tuz, and the third total time Tun are as follows:

[0085]

[0086]

[0087]

[0088] In the sixth process, the control device 6, within one period Ts2 of a carrier signal having the same length as the sum of the first total time Txp, the second total time Txz, and the third total time Txn, rearranges the control pattern of the switching state of one phase (U phase in the example of Figure 14) of the inverter circuit 1, as shown in Figure 14, so that it is in the order of first switching state ("P"), second switching state ("0"), third switching state ("N"), second switching state ("0"), and first switching state ("P"), and distributes the time of the same switching state evenly. When rearranging the voltage vectors so that they are in the order of first switching state ("P"), second switching state ("0"), third switching state ("N"), second switching state ("0"), and first switching state ("P"), the multiple (for example, nine) voltage vectors arranged in time series within one period Ts2 are rearranged so that the switching state of only one phase among the U-phase, V-phase, and W-phase changes between "P" and "0" or between "0" and "N" for two adjacent voltage vectors. "Evenly distributing the time of the same switching state" means that the time allocated to each of the two first switching states ("P") is half of the first total time Txp (Txp / 2), and the time allocated to each of the two second switching states ("0") is half of the second total time Txz (Txz / 2).

[0089] If the switching states of the U-phase, V-phase, and W-phase inverter circuits 1 generated by the fourth processing result in a control pattern as shown in the example in Figure 13, the control device 6 performs a sixth processing to generate a control pattern as shown in the example in Figure 14 as the control pattern for the switching states of the U-phase, V-phase, and W-phase inverter circuits 1. In the example shown in Figure 14, the voltage vectors are used in the following order: voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V1[PNN] → voltage vector V7n[0NN] → zero vector V0n[NNN] → voltage vector V7n[0NN] → voltage vector V1[PNN] → voltage vector V13[P0N] → voltage vector V7p[P00]. In the example in Figure 14, Txp / 2 is Tup / 2, Txz / 2 is Tuz / 2, and Txn = Tun. In the example shown in Figure 13, the control pattern of the switching state of the U-phase inverter circuit 1U is an asymmetric control pattern with respect to the bisector A1 that passes through half of a predetermined period Ts1, whereas in the example shown in Figure 14, the control pattern is a line-symmetric control pattern with respect to the bisector A2 that passes through half of one period Ts2.

[0090] Figure 14 shows the control patterns of the switching states of the U-phase, V-phase, and W-phase when the control device 6 changes the switching state of the U-phase inverter circuit 1 within one cycle Ts2 as described above. In the example of Figure 14, the switching state of the V-phase inverter circuit 1V is rearranged in the order of second switching state ("0"), third switching state ("N"), and second switching state ("0"). Also in the example of Figure 14, the switching state of the W-phase inverter circuit 1W is rearranged in the order of second switching state ("0"), third switching state ("N"), and second switching state ("0").

[0091] Figure 16 shows the switching state of the U-phase inverter circuit 1U before rearranging the control pattern of the switching state, the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, and the relationship with the carrier signal. In contrast, Figure 17 shows the switching state of the U-phase inverter circuit 1U after rearranging the control pattern of the switching state, the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, and the relationship with the carrier signal. The control device 6 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 within one period Ts2 (where one period Ts2 is the same length as a predetermined period Ts1) so that the composite vector of the voltage vectors used in one period Ts2 matches the command voltage vector Vref. More specifically, the control device 6 generates a first control signal S1U, a second control signal S2U, a third control signal S3U, and a fourth control signal S4U so that the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the U-phase inverter circuit 1U are as shown in Figure 17, and controls the first gate driver 61, the second gate driver 62, the third gate driver 63, and the fourth gate driver 64 corresponding to the U-phase inverter circuit 1U. The control device 6 also generates a first control signal S1V, a second control signal S2V, a third control signal S3V, and a fourth control signal S4V so that the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the V-phase inverter circuit 1V are as shown in Figure 19, and controls the first gate driver 61, the second gate driver 62, the third gate driver 63, and the fourth gate driver 64 corresponding to the V-phase inverter circuit 1V.Furthermore, the control device 6 generates the first control signal S1W, the second control signal S2W, the third control signal S3W, and the fourth control signal S4W so that the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of the W-phase inverter circuit 1W are as shown in Figure 21, thereby controlling the first gate driver 61, the second gate driver 62, the third gate driver 63, and the fourth gate driver 64 corresponding to the W-phase inverter circuit 1W. In Figures 16, 18, and 20, the predetermined period Ts1 is two periods (2T) of the carrier signal. In Figures 17, 19, and 21, one period Ts2 is one period of the carrier signal. In the example of Figure 17, Ts2 = Ts1.

[0092] Figure 18 shows the switching state of the V-phase inverter circuit 1V before rearranging the control pattern of the switching state, the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, and the relationship with the carrier signal. In contrast, Figure 19 shows the switching state of the V-phase inverter circuit 1V after rearranging the control pattern of the switching state, the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, and the relationship with the carrier signal.

[0093] Figure 20 shows the switching state of the W-phase inverter circuit 1W before rearranging the control pattern of the switching state, the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, and the relationship with the carrier signal. In contrast, Figure 21 shows the switching state of the W-phase inverter circuit 1W after rearranging the control pattern of the switching state, the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, and the relationship with the carrier signal.

[0094] In the sixth process of the control device 6, within one cycle Ts2, the control pattern of the switching state of the X-phase inverter circuit 1 may be rearranged so that it is in the order of third switching state ("N"), second switching state ("0"), first switching state ("P"), second switching state ("0"), and third switching state ("N"), and the time of the same switching state may be evenly distributed. In this case, "evenly distributing the time of the same switching state" means that the time allocated to each of the two third switching states ("N") is half of the third total time Txn (Txn / 2), and the time allocated to each of the two second switching states ("0") is half of the second total time Txz (Txz / 2).

[0095] The multilevel inverter 100 according to the embodiment can generate a third switching state in which both the first switching element Q1 and the second switching element Q2 of the inverter circuit 1U are in the off state, and both the third switching element Q3 and the fourth switching element Q4 are in the on state, as shown in Figure 17, for example. Therefore, the multilevel inverter 100 according to the embodiment can suppress the voltage drop of the capacitor C27 of the second bootstrap circuit 72. In addition, in the multilevel inverter 100 according to the embodiment, as shown in Figures 19 and 21, there is a period in which the switching state of the V phase and the switching state of the W phase are "N", so the capacitor C27 of the second bootstrap circuit 72 corresponding to inverter circuits 1V and 1W are charged and maintain their voltage.

[0096] By the way, in the multilevel inverter 100 according to the embodiment, as the control device 6 performs the above-described operation, the duty cycle of the first switching element Q1 and the duty cycle of the second switching element Q2 change, for example, as shown in Figure 22, during one cycle of the U-phase output current iU. In this embodiment, the duty cycle of the first switching element Q1 changes nonlinearly during the half-cycle when the polarity of the U-phase output current iU is positive, and is 0 during the half-cycle when the polarity of the U-phase output current iU is negative. The duty cycle of the first switching element Q1 is discontinuous when the phase is 60°, 120°, and 180°. The duty cycle of the second switching element Q2 changes continuously every 60° during the half-cycle when the polarity of the U-phase output current iU is positive, and changes nonlinearly during the half-cycle when the polarity of the U-phase output current iU is negative. The duty cycle of the second switching element Q2 is discontinuous when the phase is 180°, 240°, and 300°. Furthermore, in this embodiment, the maximum duty cycle of the first switching element Q1 is smaller than the maximum duty cycle of the second switching element Q2, and the minimum duty cycle of the first switching element Q1 is smaller than the minimum duty cycle of the second switching element Q2. In this embodiment, as shown in Figure 22, the duty cycle pattern of the first switching element Q1 and the duty cycle pattern of the second switching element Q2 are asymmetrical with respect to the bisector A3 that passes through the zero-crossing point where the phase of the U-phase output current iU is 180°.

[0097] In contrast, in the multilevel inverter of Comparative Example 1, which is equipped with a control device that performs three-phase modulation instead of the control device 6, the duty cycle of the first switching element and the duty cycle of the second switching element change, for example, as shown in Figure 23, during one period of the U-phase output current. In Comparative Example 1, the duty cycle of the first switching element changes continuously during the half-period when the polarity of the U-phase output current is positive, and is 0 during the half-period when the polarity of the U-phase output current is negative. The duty cycle of the second switching element is 0 during the half-period when the polarity of the U-phase output current is positive, and changes continuously during the half-period when the polarity of the U-phase output current is negative. In Comparative Example 1, as shown in Figure 23, the duty cycle pattern of the first switching element and the duty cycle pattern of the second switching element are symmetrical with respect to the line bisector A3 that passes through the zero-crossing point where the phase of the U-phase output current is 180°.

[0098] Furthermore, in the multilevel inverter of Comparative Example 2, which is equipped with a control device that performs spatial vector modulation instead of control device 6, the duty cycles of the first switching element and the second switching element change, for example, as shown in Figure 24, during one period of the U-phase output current. In Comparative Example 2, the duty cycle of the first switching element changes nonlinearly during the half-period when the polarity of the U-phase output current is positive, and is 0 during the half-period when the polarity of the U-phase output current is negative. The duty cycle of the first switching element is discontinuous when the phase is 60°, 120°, and 180°. The duty cycle of the second switching element is 0 during the half-period when the polarity of the U-phase output current is positive, and changes nonlinearly during the half-period when the polarity of the U-phase output current is negative. The duty cycle of the second switching element is discontinuous when the phase is 180°, 240°, and 300°. Furthermore, in Comparative Example 2, the maximum duty cycle of the first switching element is the same as the maximum duty cycle of the second switching element, and the minimum duty cycle of the first switching element is the same as the minimum duty cycle of the second switching element. In Comparative Example 2, as shown in Figure 24, the duty cycle pattern of the first switching element and the duty cycle pattern of the second switching element are symmetrical with respect to the line bisector A3 that passes through the zero-crossing point where the phase of the U-phase output current is 180°.

[0099] From Figures 22 to 24, it can be seen that by observing the duty cycle of the first switching element Q1 and the second switching element Q2 of the inverter circuit 1U, it is possible to distinguish between the control device 6 of the multilevel inverter 100 in the embodiment and the control devices of the multilevel inverters in Comparative Examples 1 and 2.

[0100] The above examples illustrate the relationship between the U-phase output current iU and the duty cycles of the first switching element Q1 and the second switching element Q2 of the U-phase inverter circuit 1U. The same applies to the relationship between the V-phase output current iV and the duty cycles of the first switching element Q1 and the second switching element Q2 of the V-phase inverter circuit 1V, and also to the relationship between the W-phase output current iW and the duty cycles of the first switching element Q1 and the second switching element Q2 of the W-phase inverter circuit 1W.

[0101] (3) Advantages In the multilevel inverter 100 according to the embodiment, the control device 6 stores a group of voltage vectors determined by combinations of potentials of multiple output points 13 of multiple inverter circuits 1. The control device 6 controls multiple inverter circuits 1 via multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, and multiple fourth gate drivers 64. When controlling each of the multiple inverter circuits 1, the control device 6 performs first, second, third, fourth, fifth, and sixth processing. In the first processing, the control device 6 selects a first voltage vector Va, a second voltage vector Vb, and a third voltage vector Vc from the group of voltage vectors to be used within a period T which is half of a predetermined period Ts1, corresponding to each vertex of an equilateral triangle surrounding the command voltage vector Vref. In the second process, the control device 6 determines the first allocation time T0 for the first voltage vector Va, the second allocation time T1 for the second voltage vector Vb, and the third voltage vector Vc in a period T that is half of a predetermined period Ts1, so that the combined vector of the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc matches the command voltage vector Vref. In the third process, the control device 6 distributes the first allocation time T0 to each first voltage vector Va based on the number of times the first voltage vector Va is used within a period T that is half of a predetermined period Ts1, distributes the second allocation time T1 to each second voltage vector Vb based on the number of times the second voltage vector Vb is used within a period T that is half of a predetermined period Ts1, and distributes the third allocation time T2 to each third voltage vector Vc based on the number of times the third voltage vector Vc is used within a period T that is half of a predetermined period Ts1. In the fourth process, the control device 6 selects a voltage vector from among the first voltage vector Va, the second voltage vector Vb, and the third voltage vector Vc as the first voltage vector Va, which has a magnitude that is the reference magnitude and is closest to the command voltage vector Vref, and replaces one first voltage vector VV1 included in the first voltage vector Va with a zero vector V0n [NNN] which is a combination in which the potential levels of multiple output points 13 are all at the potential of the negative electrode N1, and a voltage vector VV2 which has the same direction as the one first voltage vector VV1 and is twice the magnitude of the one first voltage vector VV1.In the fifth process, the control device 6, with respect to the switching state of each of the multiple inverter circuits 1, defines the switching state in which the potential of the output point 13 is at the potential of the positive electrode P1 as the first switching state ("P"), the switching state in which the potential of the output point 13 is at the potential of the intermediate potential point M1 as the second switching state ("0"), and the switching state in which the potential of the output point 13 is at the potential of the negative electrode N1 as the third switching state ("N"), and calculates the first total time Txp for the first switching state, the second total time Txz for the second switching state, and the third total time Txn for the third switching state in a predetermined period Ts1. In the sixth process, the control device 6 rearranges the zero vector V0n[NNN], the voltage vector VV2 (twice the magnitude), the second voltage vector Vb, and the third voltage vector Vc so that within one period Ts2 of a carrier signal having a period of the same length as the sum of the first total time Txp, the second total time Txz, and the third total time Txn, the sequence is either first switching state, second switching state, third switching state, second switching state, first switching state, or third switching state, second switching state, first switching state, second switching state, third switching state, and also distributes the time of the same switching state equally.

[0102] According to the above configuration, it is possible to suppress voltage drops in the bootstrap circuits (multiple first bootstrap circuits 71 and multiple second bootstrap circuits 72), and it is possible to set one period Ts2 of the carrier signal as the control period. In the multilevel inverter 100 according to this embodiment, by allowing one period Ts2 of the carrier signal to be set as the control period in the control device 6, it is possible to increase the time that can be used for calculations in the control device 6, and thus it is possible to increase the frequency of the carrier signal.

[0103] Furthermore, in the multilevel inverter 100 according to this embodiment, the DC-DC converter 91 included in the power supply unit 9 supplies voltage to a plurality of second gate drivers 62, a plurality of first bootstrap circuits 71, and a plurality of second bootstrap circuits 72.

[0104] The above configuration makes it possible to miniaturize the device.

[0105] (Modifications) The above embodiments are merely one of many embodiments of the present disclosure. The above embodiments can be modified in various ways depending on the design, etc., as long as the objectives of the present disclosure are achieved.

[0106] For example, each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 is not limited to IGBTs, but may be a MOSFET. In this case, the control terminal, first main terminal, and second main terminal of each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 are the gate terminal, drain terminal, and source terminal, respectively. In each inverter circuit 1, the MOSFETs constituting each of the first switching element Q1, second switching element Q2, third switching element Q3, and fourth switching element Q4 are, for example, normally-off n-channel MOSFETs. Note that the MOSFETs are Si-based MOSFETs, but are not limited to Si-based MOSFETs; for example, they may be SiC-based MOSFETs.

[0107] Furthermore, each of the multiple first bootstrap circuits 71 includes a resistor R17, but may also be configured without a resistor R17. Similarly, each of the multiple second bootstrap circuits 72 includes a resistor R27, but may also be configured without a resistor R27.

[0108] Furthermore, each of the multiple first bootstrap circuits 71 includes a Zener diode Z17, but may also be configured without a Zener diode Z17. Similarly, each of the multiple second bootstrap circuits 72 includes a Zener diode Z27, but may also be configured without a Zener diode Z27.

[0109] (Aspects) The following aspects are disclosed herein.

[0110] The multilevel inverter (100) according to the first embodiment comprises a DC power supply unit (3), a plurality of inverter circuits (1), and a control system (60). The DC power supply unit (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The plurality of inverter circuits (1) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The control system (60) controls the plurality of inverter circuits (1). Each of the plurality of inverter circuits (1) has a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4), and a first diode (D1), a second diode (D2), a third diode (D3), and a fourth diode (D4) connected in antiparallel to the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4), respectively. In each of the multiple inverter circuits (1), a first switching element (Q1) and a second switching element (Q2) are connected in series from the positive terminal (P1) side to the negative terminal (N1) side in the order of the first switching element (Q1) and the second switching element (Q2). A series circuit of a third switching element (Q3) and a fourth switching element (Q4) is connected between an intermediate potential point (M1) and an output point (13). The output point (13) is the connection point between the first switching element (Q1) and the second switching element (Q2). The control system (60) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a power supply unit (9), a plurality of second bootstrap circuits (72), and a control device (6). Multiple first gate drivers (61) are connected to multiple first switching elements (Q1). Multiple second gate drivers (62) are connected to multiple second switching elements (Q2). Multiple third gate drivers (63) are connected to multiple third switching elements (Q3). Multiple fourth gate drivers (64) are connected to multiple fourth switching elements (Q4). Multiple first bootstrap circuits (71) are connected to multiple first gate drivers (61).The power supply unit (9) supplies voltage to a plurality of second gate drivers (62). The plurality of second bootstrap circuits (72) are connected to a plurality of third gate drivers (63) and a plurality of fourth gate drivers (64). The control device (6) stores a set of voltage vectors determined by combinations of potentials of a plurality of output points (13), including the output points (13) of the plurality of inverter circuits (1). The control device (6) controls the plurality of inverter circuits (1) via a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64). When controlling each of the plurality of inverter circuits (1), the control device (6) performs first, second, third, fourth, fifth, and sixth processing. In the first process, the control device (6) selects a first voltage vector (Va), a second voltage vector (Vb), and a third voltage vector (Vc) from a group of voltage vectors to be used within half a period (T) of a predetermined period (Ts1), with each corresponding to a vertex of an equilateral triangle surrounding the command voltage vector (Vref). In the second process, the control device (6) determines the first allocation time (T0) for the first voltage vector (Va), the second allocation time (T1) for the second voltage vector (Vb), and the third voltage vector (Vc) during half a period (T) of the predetermined period (Ts1), so that the combined vector of the first voltage vector (Va), the second voltage vector (Vb), and the third voltage vector (Vc) matches the command voltage vector (Vref). In the third process, the control device (6) distributes a first distribution time (T0) to each first voltage vector (Va) based on the number of times the first voltage vector (Va) is used within half a period (T) of a predetermined period (Ts1), distributes a second distribution time (T1) to each second voltage vector (Vb) based on the number of times the second voltage vector (Vb) is used within half a period (T) of a predetermined period (Ts1), and distributes a third distribution time (T2) to each third voltage vector (Vc) based on the number of times the third voltage vector (Vc) is used within half a period (T) of a predetermined period (Ts1).In the fourth process, the control device (6) selects a voltage vector from among the first voltage vector (Va), the second voltage vector (Vb), and the third voltage vector (Vc) that has a magnitude that is the reference magnitude and is closest to the command voltage vector (Vref) as the first voltage vector (Va), and replaces one first voltage vector (VV1) included in the first voltage vector (Va) with a zero vector (V0n [NNN]) which is a combination in which the potential levels of multiple output points (13) are all at the potential of the negative electrode (N1), and a voltage vector (VV2) which has the same direction as the first first voltage vector (VV1) and twice the magnitude of the first first voltage vector (VV1). In the fifth process, the control device (6) determines the switching state of each of the multiple inverter circuits (1) by defining the switching state in which the potential of the output point (13) is equal to the potential of the positive electrode (P1) as the first switching state ("P"), the switching state in which the potential of the output point (13) is equal to the potential of the intermediate potential point (M1) as the second switching state ("0"), and the switching state in which the potential of the output point (13) is equal to the potential of the negative electrode (N1) as the third switching state ("N"), and calculates the first total time (Txp) of the first switching state, the second total time (Txz) of the second switching state, and the third total time (Txn) of the third switching state in a predetermined period (Ts1). In the sixth process, the control device (6) rearranges the zero vector (V0n [NNN]), the voltage vector twice the magnitude (VV2), the second voltage vector (Vb), and the third voltage vector (Vc) within one period (Ts2) of a carrier signal having a period of the same length as the sum of the first total time (Txp), the second total time (Txz), and the third total time (Txn), so that the sequence is either first switching state, second switching state, third switching state, second switching state, first switching state, or third switching state, second switching state, first switching state, second switching state, third switching state, and also distributes the time of the same switching state equally.

[0111] According to this embodiment, it is possible to suppress voltage drops in the multiple first bootstrap circuits (71) and the multiple second bootstrap circuits (72), and it is possible to set one period (Ts2) of the carrier signal as the control period.

[0112] In the multilevel inverter (100) according to the second embodiment, in the first embodiment, the control device (6) sets the length of the ON period of the second switching element (Q2) to a length of 90% or more and 110% or less of the CR time constant of the corresponding first bootstrap circuit (71) among the plurality of first bootstrap circuits (71).

[0113] According to this embodiment, it becomes possible to miniaturize the first gate driver (61).

[0114] In the third embodiment of the multilevel inverter (100), in the first or second embodiment, the first bootstrap circuit (71) that supplies voltage to the first gate driver (61) includes a capacitor (C17) and a diode (D17) connected in series with the capacitor (C17).

[0115] In the fourth embodiment, the multilevel inverter (100) further includes, in the third embodiment, a first bootstrap circuit (71) that supplies voltage to a first gate driver (61), a resistor (R17) connected in series with a capacitor (C17).

[0116] In the multilevel inverter (100) according to the fifth embodiment, in any one of the first to fourth embodiments, the power supply unit (9) includes a DC-DC converter (91).

[0117] 1 Inverter circuit 3 DC power supply unit 6 Control device 61 First gate driver 62 Second gate driver 63 Third gate driver 64 Fourth gate driver 9 Power supply unit 91 DC-DC converter 13 Output point 71 First bootstrap circuit 72 Second bootstrap circuit 100 Multilevel inverter C17, C27 Capacitors D1 First diode D2 Second diode D3 Third diode D4 Fourth diode D17, D27 Diodes P1 Positive electrode Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element M1 Intermediate potential point N1 Negative electrode R17, R27 Resistors T Period Ts1 Determined period Ts2 1 period Tup, Txp First total time Tuz, Txz Second total time Tun, Txn Third total time Va First voltage vector Vb, second voltage vector Vc, third voltage vector VV1, first voltage vector VV2, voltage vectors V0-V18, voltage vector Vref, command voltage vector

Claims

1. A DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point; a plurality of inverter circuits connected between the positive electrode and the negative electrode of the DC power supply unit; and a control system for controlling the plurality of inverter circuits, each of the plurality of inverter circuits having a first switching element, a second switching element, a third switching element, and a fourth switching element, and a first diode, a second diode, a third diode, and a fourth diode connected in antiparallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively; in each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series from the positive electrode side to the negative electrode side in the order of the first switching element and the second switching element; a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and the output point; the output point is the connection point between the first switching element and the second switching element; and the control system comprises a plurality of first gate drivers connected to the plurality of first switching elements, and a plurality of second gate drivers connected to the plurality of second switching elements. The inverter circuit includes: a plurality of third gate drivers connected to a plurality of third switching elements; a plurality of fourth gate drivers connected to a plurality of fourth switching elements; a plurality of first bootstrap circuits connected to a plurality of first gate drivers; a power supply unit that supplies voltage to a plurality of second gate drivers; a plurality of second bootstrap circuits connected to the plurality of third gate drivers and the plurality of fourth gate drivers; and a control device that stores a group of voltage vectors determined by a combination of the potentials of a plurality of output points of the plurality of inverter circuits, and controls the plurality of inverter circuits via the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers and the plurality of fourth gate drivers, wherein the control device controls each of the plurality of inverter circuits,A first process is performed to select a first voltage vector, a second voltage vector, and a third voltage vector, corresponding to each vertex of an equilateral triangle surrounding a command voltage vector, as a plurality of voltage vectors to be used within half a period of a predetermined period from the group of voltage vectors. A second process is performed to determine the first allocation time for the first voltage vector, the second allocation time for the second voltage vector, and the third allocation time for the third voltage vector within half a period of the predetermined period, so that the composite vector of the first voltage vector, the second voltage vector, and the third voltage vector matches the command voltage vector. A third process is performed to distribute the first allocation time to the first voltage vector based on the number of times the first voltage vector is used within half a period of the predetermined period, distribute the second allocation time to the second voltage vector based on the number of times the second voltage vector is used within half a period of the predetermined period, and distribute the third allocation time to the third voltage vector based on the number of times the third voltage vector is used within half a period of the predetermined period. A fourth process is performed in which, among the first voltage vector, the second voltage vector, and the third voltage vector, a voltage vector is selected as the first voltage vector whose magnitude is a reference magnitude and is closest to the command voltage vector, and one first voltage vector included in the first voltage vector is replaced with a zero vector which is a combination in which the potential levels of the plurality of output points are all at the potential of the negative electrode, and a voltage vector which is in the same direction as the one first voltage vector and has twice the magnitude of the one first voltage vector, and with respect to the switching state of each of the plurality of inverter circuits, a switching state in which the potential of the output point is at the potential of the positive electrode is defined as the first switching state, a switching state in which the potential of the output point is at the potential of the intermediate potential point is defined as the second switching state, and a switching state in which the potential of the output point is at the potential of the negative electrode is defined as the third switching state, and a fifth process is performed in which the first total time of the first switching state, the second total time of the second switching state, and the third total time of the third switching state in the predetermined period are calculated,A multilevel inverter that performs a sixth process in which, within one cycle of a carrier signal having a period of the same length as the sum of the first total time, the second total time, and the third total time, the zero vector, the voltage vector of twice the magnitude, the second voltage vector, and the third voltage vector are rearranged so that the sequence is either first switching state, second switching state, third switching state, second switching state, first switching state, third switching state, or third switching state, second switching state, first switching state, second switching state, third switching state, and the time of the same switching state is equally distributed.

2. The multilevel inverter according to claim 1, wherein the control device sets the length of the ON period of the second switching element to a length of 90% or more and 110% or less of the CR time constant of the corresponding first bootstrap circuit among the plurality of first bootstrap circuits.

3. The multilevel inverter according to claim 1 or 2, wherein each of the plurality of first bootstrap circuits includes a capacitor and a diode connected in series with the capacitor.

4. The multilevel inverter according to claim 3, wherein each of the plurality of first bootstrap circuits further includes a resistor connected in series with the capacitor.

5. The power supply unit includes a DC-DC converter, as described in any one of claims 1 to 4.

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