Display panel and display apparatus

Abstract

A display panel (100) and a display apparatus. The display panel (100) comprises a substrate (10), a plurality of data lines (110), a plurality of gate lines (120), and a plurality of fan-out lines (130), wherein the plurality of fan-out lines (130) are correspondingly connected to at least some of the plurality of data lines (110); among at least some of the plurality of fan-out lines (130), each fan-out line (130) comprises a connection sub-segment (134) and a plurality of extension sub-segments (135), adjacent extension sub-segments (135) are connected by means of the connection sub-segment (134), and the plurality of extension sub-segments (135) comprise a first extension sub-segment (1351) and a second extension sub-segment (1352); and in the same refresh cycle, the display panel satisfies at least one of the following situations: at least one voltage jump moment of a pulse of a signal on at least one gate line (120) adjacent to the first extension sub-segment (1351) is different from a voltage jump moment of a pulse of a signal on a gate line (120) adjacent to the second extension sub-segment (1352), or an amplitude polarity of a pulse of a signal on at least one gate line (120) adjacent to the first extension sub-segment (1351) is different from an amplitude polarity of a pulse of a signal on a gate line adjacent to the second extension sub-segment (1352).

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411466356.4, filed on October 21, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0004] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Compared to liquid crystal displays, OLED technology offers advantages such as lower energy consumption, lower cost, self-emissiveness, wide viewing angles, and faster response times. However, the brightness uniformity of display panels created using these technologies is relatively poor. Summary of the Invention

[0005] Therefore, it is necessary to provide a display panel and display device that can improve brightness uniformity.

[0006] In a first aspect, embodiments of this application provide a display panel, comprising: a substrate, a plurality of data lines, a plurality of gate lines, and a plurality of fan-out lines. The plurality of data lines are disposed on the substrate. The plurality of gate lines are disposed on the substrate. The plurality of fan-out lines are disposed on the substrate and are electrically connected to at least a portion of the data lines. Each fan-out line includes a sub-connection segment and a plurality of sub-extension segments, with adjacent sub-extension segments connected via the sub-connection segment. The plurality of sub-extension segments include a first sub-extension segment and a second sub-extension segment. Within the same refresh cycle, the display panel satisfies at least one of the following conditions: at least one voltage transition time of a pulse on at least one gate line adjacent to the first sub-extension segment is different from the voltage transition time of a pulse on a gate line adjacent to the second sub-extension segment; or the amplitude polarity of a pulse on at least one gate line adjacent to the first sub-extension segment is different from the amplitude polarity of a pulse on a gate line adjacent to the second sub-extension segment.

[0007] In the display panel provided in this application embodiment, in each of at least a portion of the fan-out lines, the at least one gate line adjacent to the first sub-extension segment can affect the signal voltage of the first sub-extension segment at its voltage transition moment, but has essentially no effect on the signal voltage of the second sub-extension segment. The parasitic capacitance between the at least one gate line and the fan-out line is equal to the parasitic capacitance generated by the mutual coupling between the first sub-extension segment and the at least one gate line. This application embodiment can shorten the coupling length between the at least one gate line and the fan-out line, thereby reducing the degree of coupling between the at least one gate line and the fan-out line and reducing the parasitic capacitance between the at least one gate line and the fan-out line. Alternatively, the signal of the gate line adjacent to the second sub-extension segment can affect the signal voltage of the second sub-extension segment, which can partially or completely offset the effect of the at least one gate line adjacent to the first sub-extension segment on the signal voltage of the first sub-extension segment at its voltage transition moment, thereby improving the uniformity of the display brightness of the display panel.

[0008] In one embodiment, the orthographic projection of the first sub-extension on the substrate is a first orthographic projection, the orthographic projection of the second sub-extension on the substrate is a second orthographic projection, and the orthographic projection of the gate line on the substrate is a third orthographic projection. In each fan-out line, at least two third orthographic projections are provided between the first and second orthographic projections of the first and second sub-extensions.

[0009] In one embodiment, the plurality of gate lines includes at least one of a first gate line and a second gate line, and at least one of a third gate line and a fourth gate line. In each fan-out line, a first sub-extension segment is adjacent to a first gate line; a second sub-extension segment is adjacent to a third gate line, and the signal of the first gate line adjacent to the first sub-extension segment is different from the signal of the third gate line adjacent to the second sub-extension segment. Alternatively, in each outgoing line, the first sub-extension segment is adjacent to the first gate line and the second gate line, respectively, and the first orthographic projection is located between the orthographic projection of the first gate line adjacent to the first sub-extension segment on the substrate and the orthographic projection of the second gate line adjacent to the first sub-extension segment on the substrate; the second sub-extension segment is adjacent to the third gate line and the fourth gate line, respectively, and the second orthographic projection is located between the orthographic projection of the third gate line adjacent to the second sub-extension segment on the substrate and the orthographic projection of the fourth gate line adjacent to the second sub-extension segment on the substrate; the signal of the first gate line adjacent to the first sub-extension segment is different from the signals of the third and fourth gate lines adjacent to the second sub-extension segment; the signal of the second gate line adjacent to the first sub-extension segment is different from the signals of the third and fourth gate lines adjacent to the second sub-extension segment.

[0010] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array, with gate lines extending along the row direction of the array and data lines extending along the column direction of the array. In each fan-out line, a first orthographic projection of a first sub-extension segment and a second sub-extension segment lies between the orthographic projections on the substrate of adjacent first and second gate lines electrically connected to the corresponding pixel circuits in the same row; a second orthographic projection lies between the orthographic projections on the substrate of adjacent third and fourth gate lines electrically connected to the corresponding pixel circuits in the same row. The column direction is parallel to a first direction, and the row direction is parallel to a second direction.

[0011] In one embodiment, the orthographic projections of the first and second sub-extensions in each fan-out line onto the substrate are located between the orthographic projections of the first, second, third, and fourth gate lines electrically connected to the corresponding pixel circuits in the same row onto the substrate.

[0012] In one embodiment, in each sector of the first sub-extension segment and the second sub-extension segment, the first gate line, the second gate line adjacent to the first sub-extension segment, the third gate line, and the fourth gate line adjacent to the second sub-extension segment are electrically connected to the corresponding pixel circuit in the same row.

[0013] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array, with gate lines extending along the row direction of the array and data lines extending along the column direction of the array. In each fan-out line, in the first and second sub-extension segments, a first orthographic projection is located between the orthographic projections on the substrate of the adjacent first and second gate lines of the first sub-extension segment; a second orthographic projection is located between the orthographic projections on the substrate of the adjacent third and fourth gate lines of the second sub-extension segment; the orthographic projections on the substrate of the adjacent second and third gate lines of the first and second sub-extension segments are located between the orthographic projections on the substrate of the adjacent first and fourth gate lines of the first and second sub-extension segments; the adjacent second and third gate lines of the first and second sub-extension segments are electrically connected to pixel circuits in the same row; the adjacent first and fourth gate lines of the first and second sub-extension segments are electrically connected to pixel circuits in different rows. The column direction is parallel to the first direction, and the row direction is parallel to the second direction.

[0014] In one embodiment, the display panel satisfies at least one of the following conditions: any two of the first gate line, second gate line, third gate line, and fourth gate line have different signals; the first gate line, second gate line, third gate line, and fourth gate line are used to transmit signals with different functions; the display panel includes a plurality of pixel circuits arranged in an array, the pixel circuits include a plurality of transistors with different functions, the gate lines extend along the row direction of the array, and the data lines extend along the column direction of the array; the first gate line, second gate line, third gate line, and fourth gate line are electrically connected to transistors with different functions; or, any two of the first gate line, second gate line, third gate line, and fourth gate line are alternately arranged along a first direction.

[0015] In one embodiment, the plurality of gate lines include a plurality of gate line groups, each gate line group including a first gate line and a second gate line. In each fan-out line, the first sub-extension segment is adjacent to the first gate line and the second gate line in the corresponding gate line group, and the first orthographic projection is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate in the corresponding gate line group; the second sub-extension segment is adjacent to the first gate line and the second gate line in the corresponding other gate line group, and the second orthographic projection is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate in the corresponding other gate line group.

[0016] In one embodiment, the display panel satisfies at least one of the following conditions: in each of the first and second sub-extension segments of the fan-out line, the signal timing of the first gate line adjacent to the first sub-extension segment is different from the signal timing of the first gate line adjacent to the second sub-extension segment; the signal timing of the second gate line adjacent to the first sub-extension segment is different from the signal timing of the second gate line adjacent to the second sub-extension segment; the first gate line and the second gate line are used to transmit different functional signals; or the first gate line and the second gate line are alternately arranged along a first direction.

[0017] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array, with gate lines extending along the row direction of the array and data lines extending along the column direction of the array. In each fan-out line, in a first sub-extension segment and a second sub-extension segment, a first gate line and a second gate line in a gate line group adjacent to the first sub-extension segment are electrically connected to pixel circuits in different rows; or, a first gate line and a second gate line in another gate line group adjacent to the second sub-extension segment are electrically connected to pixel circuits in different rows. The column direction is parallel to a first direction, and the row direction is parallel to a second direction.

[0018] In one embodiment, the display panel includes a first gate driving circuit, which includes cascaded multi-stage first shift registers electrically connected to corresponding first gate lines. In each sector of the display panel, in the first sub-extension and the second sub-extension, the first gate line adjacent to the first sub-extension and the first gate line adjacent to the second sub-extension are electrically connected to the outputs of different first shift registers. The display panel also includes a second gate driving circuit, which includes cascaded multi-stage second shift registers electrically connected to corresponding second gate lines. In each sector of the display panel, in the first sub-extension and the second sub-extension, the second gate line adjacent to the first sub-extension and the second gate line adjacent to the second sub-extension are electrically connected to the outputs of different second shift registers.

[0019] In one embodiment, the output of each stage of the first shift register is electrically connected to N corresponding first gate lines, where N is a positive integer. The output of each stage of the second shift register is electrically connected to M corresponding second gate lines, where M is a positive integer. In each sector of the first and second sub-extensions, the length of the sub-connection segment connecting the first and second sub-extensions along the first direction is greater than or equal to K times the first distance, and / or the distance between the first and second sub-extensions along the first direction is greater than or equal to K times the first distance, where K = max(M, N), and the first distance is the distance between two adjacent first gate lines along the first direction. At least one of N and M is 1, or at least one of N and M is greater than or equal to 2.

[0020] In one embodiment, the display panel satisfies at least one of the following conditions: the display panel includes a plurality of pixel circuits arranged in an array, each pixel circuit including a plurality of transistors with different functions; a first gate line in a different group of gate lines is electrically connected to a transistor with the same function in a pixel circuit in a different row; a second gate line in a different group of gate lines is electrically connected to a transistor with the same function in a pixel circuit in a different row; or, a first gate line and a second gate line are electrically connected to transistors with different functions in the pixel circuit. The display panel satisfies at least one of the following conditions: the pixel circuit includes a driving transistor and a first initialization transistor, the first initialization transistor being connected between a first initialization signal line and a first electrode or a second electrode of the driving transistor, and a first gate line being electrically connected to the gate of the first initialization transistor; the pixel circuit includes a second initialization transistor, the second initialization transistor being connected between a second initialization signal line and the gate or a second electrode of the driving transistor, and a second gate line being electrically connected to the gate of the second initialization transistor; or the pixel circuit includes a third initialization transistor, the third initialization transistor being connected between a third initialization signal line and a first electrode of a light-emitting unit, and a first gate line being electrically connected to the gate of the third initialization transistor.

[0021] In one embodiment, first gate lines in different gate line groups are used to transmit signals with the same function; second gate lines in different gate line groups are used to transmit signals with the same function. The output of each stage of the first shift register is electrically connected to N corresponding first gate lines, where N is a positive integer. The output of each stage of the second shift register is electrically connected to M corresponding second gate lines, where M is a positive integer. In each sector of the first and second sub-extensions, the length of the sub-connection segment connecting adjacent first and second sub-extensions along the first direction is greater than or equal to K times the first distance, where K = max(M, N), and the first distance is the distance between two adjacent first gate lines along the first direction; the data line extends along the first direction. At least one of N and M is greater than or equal to 2.

[0022] In one embodiment, the plurality of fan-out lines include a plurality of first fan-out lines, and the plurality of sub-extension segments in each first fan-out line include a first sub-extension segment and a second sub-extension segment. The display panel satisfies at least one of the following conditions: the extension length of the second sub-extension segment in the plurality of first fan-out lines gradually decreases along a first direction; the extension length of the first sub-extension segments in the plurality of first fan-out lines is equal; or, the extension length of the sub-connection segments in the plurality of first fan-out lines is equal.

[0023] In one embodiment, the display panel satisfies at least one of the following conditions: second sub-extension segments of a plurality of first fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; first sub-extension segments of at least a portion of adjacent first fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; the distance between first sub-extension segments of two adjacent first fan-out lines is less than or equal to the distance between the first and second sub-extension segments of each first fan-out line along the first direction; the distance between first sub-extension segments of two adjacent first fan-out lines is less than or equal to the extension length of a sub-connecting segment; the distance between second sub-extension segments of two adjacent first fan-out lines is less than or equal to the distance between the first and second sub-extension segments of each of the two adjacent first fan-out lines along the first direction; the distance between second sub-extension segments of two adjacent first fan-out lines is less than or equal to the extension length of a sub-connecting segment; or, the distance between first sub-extension segments of two adjacent first fan-out lines is equal to the distance between the second sub-extension segments of the two adjacent first fan-out lines.

[0024] In one embodiment, the extension length of the second sub-extension segment with the largest extension length among the plurality of first fan-outlines is equal to the extension length of the first sub-extension segment among the plurality of first fan-outlines.

[0025] In one embodiment, the display panel satisfies at least one of the following conditions: first sub-extension segments of at least a portion of adjacent first fan-out lines are partially opposite and partially misaligned along a first direction; or, sub-connecting segments of at least a portion of adjacent first fan-out lines are partially opposite and partially misaligned along a second direction.

[0026] In one embodiment, the display panel satisfies at least one of the following conditions: among the plurality of first fan-outlines, the misalignment distances of adjacent first sub-extensions are equal; or, among the plurality of first fan-outlines, the misalignment distances of adjacent sub-connection segments are equal.

[0027] In one embodiment, in each outgoing line, the second sub-extension is connected between the first sub-extension and the corresponding data line.

[0028] In one embodiment, the display panel includes a display area and a first non-display area, the first non-display area being located on one side of the display area along a first direction, and data lines, gate lines, and fan-out lines are at least partially located in the display area; the data lines extend along the first direction. The display panel satisfies at least one of the following conditions: the extension length of the second sub-extension segment among the plurality of first fan-out lines gradually decreases along the direction from the display area to the first non-display area; the first fan-out lines are connected to the corresponding data lines through a first electrical connection node, and the extension lengths of the plurality of sub-extension segments among the first fan-out lines corresponding to the first electrical connection node furthest from the first non-display area along the first direction are equal; or, the extension length of the second sub-extension segment is the largest.

[0029] In one embodiment, the first non-display area includes a bonding area, the bonding pins of which are electrically connected to the fan-out line.

[0030] In one embodiment, the difference in the extension length of the second sub-extension of two adjacent first fan-outlines is twice the second distance.

[0031] In one embodiment, the extension length of the second sub-extension segment with the smallest extension length among the plurality of first fan-outlines is greater than or equal to twice the second distance.

[0032] In one embodiment, the distance between each pair of adjacent data lines is the same, and is the second distance.

[0033] In one embodiment, among three adjacent data lines, the distance between the middle data line and the data line on one side is different from the distance between the middle data line and the data line on the other side; half the distance between the data line on one side and the data line on the other side is the second distance.

[0034] In one embodiment, in each first sector outgoing line, the distance between the second sub-extension segment and the first non-display area along the first direction is greater than the distance between the first sub-extension segment and the first non-display area along the first direction.

[0035] In one embodiment, the plurality of fan-out lines further include a plurality of second fan-out lines, wherein the number of sub-extensions in each second fan-out line is greater than the number of sub-extensions in each first fan-out line. In each second fan-out line, the plurality of sub-extensions include a first sub-extension, a second sub-extension, and a third sub-extension, the third sub-extension being connected between the second sub-extension and a corresponding data line. In each second fan-out line, the signal of at least one gate line adjacent to the third sub-extension is different from the signal of the gate line adjacent to the second sub-extension. The display panel satisfies at least one of the following conditions: the extension length of the third sub-extension in the plurality of second fan-out lines gradually decreases along a first direction; the extension lengths of the first sub-extensions in the plurality of second fan-out lines are equal; the extension lengths of the second sub-extensions in the plurality of second fan-out lines are equal; the extension lengths of the first sub-extension and the second sub-extension in each second fan-out line are equal; or, the extension lengths of the first sub-extension in the second fan-out line and the first sub-extension in the first fan-out line are equal. The display panel satisfies at least one of the following conditions: third sub-extension segments of a plurality of second fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; first sub-extension segments of at least a portion of adjacent second fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; second sub-extension segments of at least a portion of second fan-out lines and first sub-extension segments of at least a portion of first fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; second sub-extension segments of at least a portion of second fan-out lines and first sub-extension segments of at least a portion of first fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; The second sub-extension segments in the line are arranged at equal or unequal intervals along the first direction and extend along the second direction; the extension length of the sub-connecting segments in the second fan-out line is equal to the extension length of the sub-connecting segments in the first fan-out line; the extension length of the third sub-extension segment with the longest extension length among the multiple second fan-out lines is equal to the extension length of the first sub-extension segment in the first fan-out line; or, the extension length of the first sub-connecting segment in the second fan-out line is equal to the extension length of the second sub-connecting segment in the second fan-out line; the first sub-connecting segment is connected between the first sub-extension segment and the second sub-extension segment, the second sub-connecting segment is connected between the second sub-extension segment and the third sub-extension segment, and the extension length of the third sub-extension segment among the multiple second fan-out lines gradually decreases along the direction from the display area to the first non-display area.

[0036] In one embodiment, the display panel includes a first display area and a second display area, the second display area being located on opposite sides of the first display area along a second direction. Multiple data lines include multiple first data lines located in the second display area, and the multiple first data lines are electrically connected to multiple first fan-out lines. The second display area includes a first sub-region and a second sub-region, the first sub-region being located on a side of the second sub-region away from the first display area, and the first data lines being located in the first sub-region. The multiple data lines also include multiple second data lines located in the second sub-region. The multiple fan-out lines include multiple auxiliary fan-out lines, and the multiple auxiliary fan-out lines are electrically connected to the multiple second data lines. Each auxiliary fan-out line includes a first sub-extension segment, and the number of sub-extension segments in each auxiliary fan-out line is less than the number of sub-extension segments in each first fan-out line. The display panel satisfies at least one of the following conditions: the first sub-extension segments of the multiple auxiliary fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; or, at least a portion of the first sub-extension segments of the first fan-out lines and at least a portion of the first sub-extension segments of the auxiliary fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction. The display panel satisfies at least one of the following conditions: the extension length of the first sub-extension segment with the longest extension among the plurality of auxiliary fan-out lines is equal to the extension length of the first sub-extension segment among the first fan-out lines; or, the distance between the first sub-extension segments of adjacent first fan-out lines along the first direction is equal to the distance between the first sub-extension segments of adjacent auxiliary fan-out lines along the first direction. The extension length of the first sub-extension segments of the plurality of auxiliary fan-out lines gradually decreases along the first direction. The first sub-extension segment of the first fan-out line is located on the side of the first sub-extension segment of the auxiliary fan-out line away from the first non-display area. The difference in extension length between the first sub-extension segments of two adjacent auxiliary fan-out lines is twice the second distance. The fan-out lines of the two second display areas located on opposite sides of the first display area along the second direction are symmetrically arranged. The plurality of data lines also include a third data line located in the first display area, the third data line being electrically connected to the bonding pin of the bonding area. In each fan-out line, the fan-out line also includes an auxiliary sub-connection segment electrically connected between the first sub-extension segment and the bonding pin of the bonding area of ​​the display panel. The plurality of auxiliary sub-connection segments are arranged along the second direction and extend along the first direction. In at least a portion of the fan-out lines, the distance between two adjacent auxiliary sub-connecting segments is an integer multiple of the second distance.

[0037] In one embodiment, the display panel satisfies at least one of the following conditions: the extension length of the first sub-extension segment in each fan-out line is less than, greater than, or equal to the extension length of the second sub-extension segment; in a portion of the fan-out lines, the extension lengths of the first sub-extension segment and the second sub-extension segment in each fan-out line are equal; in a portion of the fan-out lines, the extension length of the first sub-extension segment in each fan-out line is greater than the extension length of the second sub-extension segment; in at least a portion of the fan-out lines, the number of sub-extension segments in each fan-out line is at least 3; a plurality of data lines extend along a first direction and are arranged along a second direction, the first direction and the second direction intersect; a plurality of gate lines are arranged along a first direction and extend along a second direction; in each fan-out line, adjacent sub-connections... The extension directions of the connecting segment and the sub-extension segment intersect; the sub-extension segment extends along a second direction; the sub-connecting segment extends along a first direction, or the extension direction of the gate line intersects with the extension direction of the sub-connecting segment; the display panel includes a display area and a first non-display area, the first non-display area being located on one side of the display area along the first direction, and the data line, gate line, and fan-out line are all at least partially located in the display area; the data line extends along the first direction; the first non-display area includes a bonding area, the bonding pins of the bonding area being electrically connected to the fan-out line; among at least a portion of the fan-out lines, the farther the distance between the electrical connection node of the fan-out line and the corresponding data line and the first non-display area along the first direction, the more sub-extension segments there are in the fan-out line, the more sub-connecting segments there are in the fan-out line, and the more sub-extension segments there are in the fan-out line. The greater the sum of the extension lengths; the data lines and sub-extensions are arranged on different layers; adjacent data lines and sub-extensions are connected through vias; the conductive layer where the data line is located is on the side of the conductive layer where the sub-extension is located that is away from or close to the substrate; an insulating layer is provided between the conductive layer where the data line is located and the conductive layer where the sub-extension is located; sub-connection segments and sub-extensions are arranged on different layers; adjacent sub-connection segments and sub-extensions are connected through vias; the conductive layer where the sub-connection segment is located is on the side of the conductive layer where the sub-extension is located that is away from or close to the substrate; an insulating layer is provided between the conductive layer where the sub-connection segment is located and the conductive layer where the sub-extension is located; sub-connection segments and data lines are arranged on the same layer or on different layers; within the same refresh cycle, the first voltage transition of the pulse of the signal on at least one gate line adjacent to the first sub-extension. The timing of the voltage transition of the signal pulse on the gate line adjacent to the second sub-extension is different from the timing of the voltage transition of the signal pulse on the gate line adjacent to the first sub-extension in each sector; within the same refresh cycle, the pulse of the signal on at least one gate line adjacent to the first sub-extension does not overlap with the pulse of the signal on the gate line adjacent to the second sub-extension in each sector; within the same refresh cycle, the pulse of the signal on at least one gate line adjacent to the first sub-extension is asynchronous with the pulse of the signal on the gate line adjacent to the second sub-extension in each sector; within the same refresh cycle, the timing of the pulse of the signal on at least one gate line adjacent to the first sub-extension transitioning to its own effective level is different from the timing of the pulse of the signal on the gate line adjacent to the second sub-extension transitioning to its own effective level in each sector.Alternatively, within the same refresh cycle, in each sector, the moment when the pulse of the signal on each gate line adjacent to the first sub-extension changes to its own effective level differs from the moment when the pulse of the signal on the gate line adjacent to the second sub-extension changes to its own effective level.

[0038] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array, each pixel circuit including a plurality of transistors with different functions. A plurality of gate lines include a first scan line, and a plurality of transistors include a driving transistor and a first initialization transistor. The first initialization transistor is connected between a first initialization signal line and a first or second electrode of the driving transistor, and the first scan line is electrically connected to the gate of the first initialization transistor. A plurality of gate lines include a second scan line, and a plurality of transistors include a second initialization transistor. The second initialization transistor is connected between a second initialization signal line and the gate or second electrode of the driving transistor, and the second scan line is electrically connected to the gate of the second initialization transistor. A plurality of transistors includes a third initialization transistor, which is connected between a third initialization signal line and a first electrode of a light-emitting unit, and the first scan line is electrically connected to the gate of the third initialization transistor. A plurality of gate lines include a third scan line, and a plurality of transistors include a write transistor, which is connected between a data line and a first electrode of the driving transistor; the third scan line is electrically connected to the gate of the write transistor. A plurality of gate lines include a fourth scan line, and a plurality of transistors include a threshold compensation transistor, which is connected between the gate and a second electrode of the driving transistor; the fourth scan line is electrically connected to the gate of the threshold compensation transistor. Multiple gate lines include light-emitting control lines, and multiple transistors include at least one of a first light-emitting control transistor or a second light-emitting control transistor. The first light-emitting control transistor is connected between a first power supply line and a first electrode of a driving transistor, and the second light-emitting control transistor is connected between a second electrode of a driving transistor and a first electrode of a light-emitting unit. The light-emitting control lines are electrically connected to at least one of the gates of the corresponding first or second light-emitting control transistors. Second scan lines, third scan lines, fourth scan lines, light-emitting control lines, and first scan lines electrically connected to the same row of pixel circuits are arranged sequentially along a first direction. In the first and second sub-extension segments of the same fan-out line, the first sub-extension segment is located between two adjacent second scan lines, third scan lines, fourth scan lines, light-emitting control lines, and first scan lines; the second sub-extension segment is located between another two adjacent second scan lines, third scan lines, fourth scan lines, light-emitting control lines, and first scan lines.

[0039] In one embodiment, the display panel includes one or more gate driving circuits. The gate driving circuit includes cascaded multi-stage shift registers electrically connected to corresponding gate lines. In each fan-out line, the first sub-extension segment is located between two adjacent second scan lines, third scan lines, fourth scan lines, light emission control lines, and first scan lines. The gate lines adjacent to the first and second sub-extension segments have the same function but different signal timing and are electrically connected to different shift registers.

[0040] Secondly, embodiments of this application provide a display panel, including: a substrate, a plurality of data lines, a plurality of gate lines, a plurality of fan-out lines, and one or more gate driving circuits. The plurality of data lines are disposed on the substrate. The plurality of gate lines are disposed on the substrate. The plurality of fan-out lines are disposed on the substrate, and are electrically connected to at least a portion of the data lines. The gate driving circuit includes cascaded multi-stage shift registers, the output terminals of which are electrically connected to corresponding gate lines. Each of the at least a portion of the plurality of fan-out lines includes a sub-connection segment and a plurality of sub-extension segments. Adjacent sub-extension segments are connected via the sub-connection segment. The plurality of sub-extension segments include a first sub-extension segment and a second sub-extension segment. At least one gate line adjacent to the first sub-extension segment and a gate line adjacent to the second sub-extension segment are electrically connected to the output terminals of different shift registers.

[0041] Thirdly, embodiments of this application provide a display panel, comprising: a substrate, a plurality of data lines, a plurality of gate lines, a plurality of fan-out lines, and a plurality of pixel circuits arranged in an array. The plurality of data lines are disposed on the substrate. The plurality of gate lines are disposed on the substrate. The plurality of fan-out lines are disposed on the substrate and are electrically connected to at least a portion of the data lines. The plurality of pixel circuits arranged in an array are electrically connected to corresponding gate lines and data lines, and each pixel circuit includes a plurality of transistors with different functions. Among the at least a portion of the fan-out lines, each fan-out line includes a sub-connection segment and a plurality of sub-extension segments. Adjacent sub-extension segments are connected by the sub-connection segment. The plurality of sub-extension segments include a first sub-extension segment and a second sub-extension segment. The transistor electrically connected to at least one gate line adjacent to the first sub-extension segment has a different function than the transistor electrically connected to the gate line adjacent to the second sub-extension segment.

[0042] Fourthly, embodiments of this application provide a display device, including a driver chip and a display panel of any one of the first to third aspects described above, wherein the driver chip is electrically connected to the plurality of fan-out lines.

[0043] The display device provided in this application includes a display panel. At least one gate line adjacent to a first sub-extension can affect the signal voltage of the first sub-extension at its voltage transition moment, but has basically no effect on the signal voltage of the second sub-extension. The parasitic capacitance between the at least one gate line and the fan-out line is equal to the parasitic capacitance generated by the mutual coupling between the first sub-extension and the at least one gate line, which shortens the coupling length between the at least one gate line and the fan-out line, thereby reducing the coupling degree between the at least one gate line and the fan-out line and reducing the parasitic capacitance between the at least one gate line and the fan-out line. Alternatively, the signal of the gate line adjacent to the second sub-extension affects the signal voltage of the second sub-extension, which can partially or completely offset the influence of the at least one gate line adjacent to the first sub-extension on the signal voltage of the first sub-extension at its voltage transition moment, thereby improving the uniformity of the display brightness of the display panel. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 is a top view of the display panel provided in an embodiment of this application.

[0046] Figure 2 is a top view of the data line, first gate line, and fan-out line provided in an embodiment of this application.

[0047] Figure 3 is another top view of the data line, first gate line, and fan-out line provided in an embodiment of this application.

[0048] Figure 4 is a top view of the gate line set and pixel circuit provided in an embodiment of this application.

[0049] Figure 5 is a top view of a fan-out line and a gate line provided in an embodiment of this application.

[0050] Figure 6a is another top view of a fan-out line and a gate line provided in an embodiment of this application.

[0051] Figure 6b is a top view of a fan-out line, gate line, and gate drive circuit provided in an embodiment of this application.

[0052] Figure 6c is another top view of a fan-out line, gate line, and gate drive circuit provided in an embodiment of this application.

[0053] Figure 7 is a top view of a fan-out line, gate line, and row pixel circuit provided in an embodiment of this application.

[0054] Figure 8a is another top view of a fan-out line, gate line, and pixel circuit provided in an embodiment of this application.

[0055] Figure 8b is another top view of a fan-out line, gate line, and pixel circuit provided in an embodiment of this application.

[0056] Figure 8c is another top view of a fan-out line, gate line, and pixel circuit provided in an embodiment of this application.

[0057] Figure 9 is a top view of a fan-out line, gate line, pixel circuit, and gate driving circuit provided in an embodiment of this application.

[0058] Figure 10 is another top view of a fan-out line, gate line, pixel circuit, and gate driving circuit provided in an embodiment of this application.

[0059] Figure 11a is another top view of a fan-out line, gate line, pixel circuit, and gate driving circuit provided in an embodiment of this application.

[0060] Figure 11b is another top view of a fan-out line, gate line, pixel circuit, and gate driving circuit provided in an embodiment of this application.

[0061] Figure 11c is another top view of a fan-out line, gate line, pixel circuit, and gate driving circuit provided in an embodiment of this application.

[0062] Figure 12 is an equivalent circuit diagram of the pixel circuit, light-emitting unit and each signal line provided in the embodiment of this application.

[0063] Figure 13 is another equivalent circuit diagram of the pixel circuit, light-emitting unit and signal lines provided in the embodiment of this application.

[0064] Figure 14a is another top view of a fan-out line, gate line, and pixel circuit provided in an embodiment of this application.

[0065] Figure 14b is another top view of a fan-out line, gate line, and pixel circuit provided in an embodiment of this application.

[0066] Figure 15 is a top view of the data line group and pixel circuit provided in an embodiment of this application.

[0067] Figure 16 is a timing diagram of the pixel circuit provided in an embodiment of this application.

[0068] Figure 17 is a timing diagram of the gate line adjacent to the first sub-extension and the gate line adjacent to the second sub-extension provided in an embodiment of this application.

[0069] Figure 18 is another timing diagram of the gate line adjacent to the first sub-extension and the gate line adjacent to the second sub-extension provided in an embodiment of this application.

[0070] Figure 19 is another timing diagram of the gate line adjacent to the first sub-extension and the gate line adjacent to the second sub-extension provided in an embodiment of this application.

[0071] Figure 20 is another timing diagram of the gate line adjacent to the first sub-extension and the gate line adjacent to the second sub-extension provided in an embodiment of this application.

[0072] Explanation of reference numerals in the attached drawings: 100, Display panel; 100a, Display area; 101a, First display area; 102a, Second display area; 102a1, First sub-area; 102a2, Second sub-area; 100b, Non-display area; 101b, First non-display area; 102b, Second non-display area; 110, Data line; 110a, Data line group; 111, First data line; 112, Second data line; 113, Third data line; 120, Gate line; 120a, Gate line set; 120b, Gate line group; Sa, First gate line; Sb, Second gate line; Sc, Third gate line; Sd, Fourth gate line; Se, Fifth gate line; 130, Fan-out line; 131, First fan-out line; 132, ... Second fan-out line; 133, Auxiliary fan-out line; 134, Sub-connection segment; 1341, First sub-connection segment; 1342, Second sub-connection segment; 135, Sub-extension segment; 1351, First sub-extension segment; 1352, Second sub-extension segment; 1353, Third sub-extension segment; 136, Electrical connection node; 1361, First electrical connection node; 1362, Second electrical connection node; 137, Auxiliary sub-connection segment; 140, Gate drive circuit; 140a, Shift register; 141, First gate drive circuit; 1411, First shift register; 142, Second gate drive circuit; 1422, Second shift register; 151, Pixel circuit; 161, Driver chip; 162, Bonding pin. Detailed Implementation

[0073] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0074] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0076] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Compared to liquid crystal displays, OLED technology offers advantages such as lower energy consumption, lower cost, self-emissiveness, wide viewing angles, and faster response times. However, the brightness uniformity of display panels created using these technologies is relatively poor.

[0077] In the process of developing this application, the inventors discovered the following problems in the related technology: A display panel includes a substrate, on which multiple gate lines, multiple data lines, and multiple fan-out lines are disposed. The multiple data lines extend along the column direction and are spaced apart along the row direction. The multiple gate lines extend along the row direction and are spaced apart along the column direction. Some or all of the data lines are correspondingly connected to the fan-out lines, and at least a portion of the fan-out lines is located in the display area. Each fan-out line includes a first sub-fan-out line extending along the row direction and a second sub-fan-out line extending along the column direction. The first sub-fan-out line is connected between the corresponding data line and the second sub-fan-out line. The first sub-fan-out line may be located in the display area, and at least a portion of the second sub-fan-out line is located in the display area.

[0078] However, there is a parasitic capacitance between the first sub-fan-out line and the adjacent gate line. The first sub-fan-out line has a large extension length along the row direction, resulting in a large parasitic capacitance between the first sub-fan-out line and the adjacent gate line. This causes the signal voltage of the adjacent fan-out line and the data line connected to the fan-out line to be coupled and pulled when the gate line signal changes. Ultimately, this causes the data signal voltage written to the pixel corresponding to this column of data lines at this moment to be inconsistent with that of other rows in the same column. Consequently, the brightness of the pixel differs from that of other pixels. That is, among the multiple light-emitting units corresponding to this column of data lines, the brightness of the light-emitting unit near the gate line is different from that of other light-emitting units. This results in poor uniformity of display brightness on the display panel, and the display panel is prone to diagonal uneven areas or dark spots.

[0079] In view of at least one of the above problems, embodiments of this application provide a display panel and a display device that can improve the brightness uniformity of the display panel and alleviate the appearance of diagonal uneven areas or dark spots on the display panel.

[0080] The display panel and display device provided in the embodiments of this application will be described below with reference to Figures 1-20.

[0081] This application provides a display device, which may include a display panel 100. The display device may be an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart bracelet, smartwatch, supercomputer, navigator, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, clock, calculator, television monitor, computer monitor, automotive display (e.g., odometer display), cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic billboard or sign, projector, and other mobile or fixed terminals.

[0082] For example, the display panel can be an organic light-emitting diode (OLED) display panel, a micro organic light-emitting diode (Micro OLED) display panel, a light-emitting diode (LED) display panel, a quantum dot light-emitting diode (QLED) display panel, a mini light-emitting diode (MiniLED) display panel, a micro light-emitting diode (Micro LED) display panel, or a liquid crystal display (LCD) display panel, etc. This application uses an OLED display panel as an example for illustration.

[0083] For example, referring to Figure 1, the display panel 100 may have a first direction A, a second direction B, and a third direction, all of which are different. The first direction A and the second direction B can be any two different directions parallel to the display panel 100, and the third direction can be any direction intersecting a plane parallel to the display panel 100. For example, the first direction A, the second direction B, and the third direction can be perpendicular to each other. For example, the first direction A can be the length direction of the display panel 100, the second direction B can be the width direction of the display panel 100, and the third direction can be the thickness direction of the display panel 100. The length, width, and thickness in the embodiments of this application are merely for descriptive convenience and do not imply any limitation on the dimensions. For example, the width can be greater than, equal to, or less than the length. The orientation of the display panel 100 can be consistent with the orientation of the substrate or other film layers.

[0084] The display panel 100 provided in the embodiments of this application will be described below.

[0085] In some embodiments, referring to FIG1, the display panel 100 includes a display area 100a and a non-display area 100b, the non-display area 100b being disposed adjacent to the display area 100a. For example, the non-display area 100b may surround the outer periphery of the display area 100a.

[0086] For example, referring to FIG1, the non-display area 100b includes a first non-display area 101b, which is located on one side of the display area 100a along the first direction A.

[0087] For example, referring to FIG1, the non-display area 100b includes a second non-display area 102b, which is located on both sides of the display area 100a along the second direction B.

[0088] For example, referring to FIG1, the display area 100a includes a first display area 101a and a second display area 102a, the second display area 102a being located on opposite sides of the first display area 101a along the second direction B.

[0089] For example, referring to FIG2, the second display area 102a includes a first sub-region 102a1 and a second sub-region 102a2, wherein the first sub-region 102a1 is located on the side of the second sub-region 102a2 opposite to the first display area 101a.

[0090] In some embodiments, the display panel 100 may include a substrate 10. The substrate 10 may provide support for subsequent layers of film.

[0091] In some embodiments, referring to FIG2, the display panel 100 may include a plurality of data lines 110 disposed on the substrate 10. For example, the plurality of data lines 110 all extend along a first direction A, and the plurality of data lines 110 are arranged at intervals along a second direction B. The plurality of data lines 110 in FIG2 may be D1, D2, D3, D4, D5...Dn respectively.

[0092] Referring to Figure 2, the display panel 100 may include a plurality of gate lines 120, which are disposed on the substrate 10. The gate lines 120 are spaced apart along a first direction A and extend along a second direction B. The orthographic projections of the gate lines 120 on the substrate 10 and the orthographic projections of the data lines 110 on the substrate 10 are interleaved. The gate lines 120 shown in Figure 2 are all first gate lines Sa; the other gate lines 120 are not shown. The plurality of first gate lines Sa can be first gate lines Sa-1, Sa-2, Sa-3, Sa-4, Sa-5, Sa-6...Sa-n.

[0093] Referring to Figure 2, the display panel 100 may include a plurality of fan-out lines 130 disposed on the substrate 10, and the plurality of fan-out lines 130 are electrically connected to at least a portion of the data lines 110. For example, the first non-display area 101b includes a bonding area, in which bonding pins 162 (Figure 1) are disposed, one end of the fan-out line 130 is electrically connected to the corresponding data line, and the bonding pin 162 is electrically connected to the other end of the fan-out line 130. The plurality of fan-out lines 130 shown in Figure 2 are F1, F2, F3, F4, F5, F6, F7, F8, and F9. Among them, F1, F2, F3, F4, and F5 are all first fan-out lines 131, and F6, F7, F8, and F9 are all auxiliary fan-out lines 133. At least a portion may include some or all of them.

[0094] For example, the data line 110, the gate line 120, and the fan-out line 130 are all at least partially located in the display area 100a.

[0095] For example, referring to Figure 2, in at least a portion of the fan-out lines 130, each fan-out line 130 includes a sub-connecting segment 134 and a plurality of sub-extension segments 135. Adjacent sub-extension segments 135 are connected by a sub-connecting segment 134. For example, the extension directions of adjacent sub-connecting segments 134 and the extension directions of sub-extension segments 135 intersect. In this at least a portion of the fan-out lines 130, the number of sub-extension segments 135 in each fan-out line 130 can be any number of two, three, four, or more than four.

[0096] For example, sub-extension 135 intersects the extension direction of data line 110. For example, referring to FIG2, sub-extension 135 extends along a second direction B. For example, sub-connection 134 intersects the extension direction of gate line 120. For example, referring to FIG2, sub-connection 134 extends along a first direction A.

[0097] For example, the extension direction of gate line 120 intersects with the extension direction of sub-connection segment 134.

[0098] In one embodiment, the sub-extension 135 and / or sub-connection 134 may also extend in other directions.

[0099] For example, in the at least a portion of the fan-out lines 130, the number of sub-extensions 135 in any two fan-out lines 130 may be the same or different.

[0100] For example, referring to Figures 1 and 3, in at least a portion of the fan-out lines 130, the greater the distance between the electrical connection node 136 of the fan-out line 130 and the corresponding data line 110 and the first non-display area 101b along the first direction A, the more sub-extension segments 135 in the fan-out line 130, the more sub-connection segments 134 in the fan-out line 130, and the greater the sum of the extension lengths of the sub-extension segments 135 in the fan-out line 130. For example, the distance between the second electrical connection node 1362 of the second fan-out line 132 and the corresponding data line 110 and the first non-display area 101b along the first direction A is greater than the distance between the first electrical connection node 1361 of the first fan-out line 131 and the corresponding data line 110 and the first non-display area 101b along the first direction A; the number of sub-extension segments 135 in the second fan-out line 132 is greater than the number of sub-extension segments 135 in the first fan-out line 131; the number of sub-connection segments 134 in the second fan-out line 132 is greater than the number of sub-connection segments 134 in the first fan-out line 131; and the sum of the extension lengths of the multiple sub-extension segments 135 in the second fan-out line 132 is greater than the sum of the extension lengths of the multiple sub-extension segments 135 in the first fan-out line 131. Since the number of sub-extension segments 135 in the second fan-out line 132 is greater than the number of sub-extension segments 135 in the first fan-out line 131, it has a better effect on reducing parasitic capacitance and is more conducive to improving the pixel density of the display panel 100.

[0101] Referring to Figures 17 and 18, the signal of at least one (e.g., multiple, partially or all) gate line 120 adjacent to the first sub-extension 1351 is different from the signal of the gate line 120 adjacent to the second sub-extension 1352. The signal difference may include one or more differences in the pulse width, transition timing, amplitude polarity, phase, frequency, function, etc.

[0102] For example, within the same refresh cycle, at least one (e.g., multiple, partial, or all) voltage transition time of the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension 1351 differs from the voltage transition time of the pulse of the signal on the gate line 120 adjacent to the second sub-extension 1352. For example, the amplitude polarity (e.g., negative or positive pulse) of the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension 1351 may be the same as or different from the amplitude polarity of the pulse of the signal on the gate line 120 adjacent to the second sub-extension 1352. Wherein, Sa-1 can be a gate line 120 adjacent to the first sub-extension 1351, Sa-2 can be a gate line 120 adjacent to the second sub-extension 1352, and Sa-1 and Sa-2 have the same function. Alternatively, Sa can be a gate line 120 adjacent to the first sub-extension 1351, and Sc can be a gate line 120 adjacent to the second sub-extension 1352, and Sa and Sc have different functions. Taking Sa and Sc as examples, as shown in Figure 17, the pulses of the signals on Sa and Sc are negative pulses, and the pulses do not overlap, resulting in a delay. As shown in Figure 18, the pulses of the signals on Sa and Sc are positive pulses, and the pulses partially overlap, resulting in a delay.

[0103] For example, referring to Figures 19 and 20, the amplitude polarity (e.g., negative or positive pulse) of the pulse on at least one gate line 120 adjacent to the first sub-extension 1351 is different from the amplitude polarity (e.g., positive or negative pulse) of the pulse on the gate line 120 adjacent to the second sub-extension 1352. For example, the voltage transition time of the pulse on at least one gate line 120 adjacent to the first sub-extension 1351 and the voltage transition time of the pulse on the gate line 120 adjacent to the second sub-extension 1352 may be the same or different. Here, Sa can be a gate line 120 adjacent to the first sub-extension 1351, and Sc can be a gate line 120 adjacent to the second sub-extension 1352; Sa and Sc have different functions. The pulse on Sa is a negative pulse, and the pulse on Sc is a positive pulse. Referring to Figure 19, the pulse amplitude polarities of Sa and Sc are different, and their voltage transition times are different. Referring to Figure 20, Sa and Sc have different pulse amplitude polarities, but the voltage transition times are the same.

[0104] For example, within the same refresh cycle, the first voltage transition time of the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension 1351 is different from the voltage transition time of the pulse of the signal on the gate line 120 adjacent to the second sub-extension 1352.

[0105] For example, within the same refresh cycle, in each sector 130, the pulses of the signal on at least one gate line 120 adjacent to the first sub-extension 1351 do not overlap with the pulses of the signal on the gate line adjacent to the second sub-extension 1352.

[0106] For example, within the same refresh cycle, in each sector 130, the pulses of the signal on at least one gate line 120 adjacent to the first sub-extension 1351 are out of sync with the pulses of the signal on the gate line 120 adjacent to the second sub-extension 1352, for example, there is a delay.

[0107] For example, within the same refresh cycle, in each sector 130, the moment when the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension 1351 transitions to its own effective level (which may be the level after the first voltage transition) is different from the moment when the pulse of the signal on the gate line 120 adjacent to the second sub-extension 1352 transitions to its own effective level. The effective level can be high or low. The effective level can be on or off.

[0108] For example, within the same refresh cycle, in each sector 130, the moment when the pulse of the signal on each gate line 120 adjacent to the first sub-extension 1351 transitions to its own effective level is different from the moment when the pulse of the signal on the gate line 120 adjacent to the second sub-extension 1352 transitions to its own effective level.

[0109] Referring to Figure 2, in at least a portion of the fan-out lines 130, each fan-out line 130 includes multiple sub-extensions 135, each including a first sub-extension 1351 and a second sub-extension 1352. The signal voltage of the first sub-extension 1351 is primarily affected by the gate line 120 adjacent to it, and the signal voltage of the second sub-extension 1352 is primarily affected by the gate line 120 adjacent to it. At least one gate line adjacent to the first sub-extension 1351... The signal of gate line 120 is different from the signal of gate line 120 adjacent to the second sub-extension 1352. Thus, at least one gate line 120 adjacent to the first sub-extension 1351 is not adjacent to the second sub-extension 1352, for example, it is separated by other gate lines. This at least one gate line 120 adjacent to the first sub-extension 1351 can affect the signal voltage of the first sub-extension 1351 at its signal transition time, for example, by influencing the pull-up or pull-down voltage, while essentially having no effect on the signal voltage of the second sub-extension 1352. The signal voltage is affected. Since the signal of the gate line 120 adjacent to the second sub-extension 1352 is different from the signal of the at least one gate line 120, the signal of the gate line 120 adjacent to the second sub-extension 1352 will not change at this moment, and the signal of the gate line 120 adjacent to the second sub-extension 1352 will not affect the signal voltage of the second sub-extension 1352. The parasitic capacitance between the at least one gate line 120 and the fan-out line 130 is equal to the parasitic capacitance generated by the mutual coupling between the first sub-extension 1351 and the at least one gate line 120, which shortens the coupling length between the at least one gate line 120 and the fan-out line 130, thereby reducing the coupling degree between the at least one gate line 120 and the fan-out line 130, reducing the parasitic capacitance between the at least one gate line 120 and the fan-out line 130, reducing the influence of the at least one gate line 120 on the signal voltage of the fan-out line 130 at the moment of its signal change, thereby improving the uniformity of the display brightness of the display panel 100. Since the signal of the gate line 120 adjacent to the second sub-extension 1352 is different from the signal of the at least one gate line 120, the signal of the gate line 120 adjacent to the second sub-extension 1352 changes in the opposite direction at this moment. The signal of the gate line 120 adjacent to the second sub-extension 1352 affects the signal voltage of the second sub-extension 1352, which can partially or completely cancel the influence of the at least one gate line 120 adjacent to the first sub-extension 1351 on the signal voltage of the first sub-extension 1351 at the time of its signal change, thereby improving the uniformity of the display brightness of the display panel 100.

[0110] Therefore, in the embodiments of this application, in each fan-out line 130, by dividing the portion of the fan-out line 130 extending along the second direction B into multiple sub-extension segments 135, the length of each sub-extension segment 135 is reduced, which can reduce the coupling length between the sub-extension segment 135 and the adjacent gate line 120, thereby reducing the parasitic capacitance between the sub-extension segment 135 and the adjacent gate line 120, thereby alleviating the oblique uneven area or dark spot caused by uneven display brightness, making the parasitic capacitance design requirements within a single pixel lower, which is beneficial to improving pixel density.

[0111] The different signals of the two gate lines 120 can mean either that the two gate lines 120 are used to transmit different functional signals, or that the two gate lines 120 are used to transmit the same functional signal, but their timing is different, for example, there is a delay in the pulse signals on the two gate lines 120. The two gate lines 120 can be electrically connected to the outputs of different shift registers 140a to make their signals different. Alternatively, the two gate lines 120 can be electrically connected to transistors with different functions, in which case they are used to transmit different functional signals.

[0112] For example, in each outgoing line 130, the first sub-extension 1351 and the second sub-extension 1352 may be arranged adjacent to each other or not adjacent to each other.

[0113] For example, referring to Figure 2, the extension length of the first sub-extension 1351 in each fan-out line 130 is less than, greater than, or equal to the extension length of the second sub-extension 1352. This results in a smaller parasitic capacitance between the gate line 120 adjacent to the second sub-extension 1352 and the second sub-extension 1352, which is beneficial for improving the uniformity of the display brightness of the display panel 100. For example, in a portion of the fan-out lines 130, the extension length of the first sub-extension 1351 in each fan-out line 130 is greater than the extension length of the second sub-extension 1352. The longest sub-extension 135 in each fan-out line 130 has the largest coupling capacitance with the adjacent gate line. Therefore, dividing the longest fan-out line into multiple sub-extensions 135 with equal extension lengths helps to reduce the maximum value of the coupling capacitance between the fan-out line 130 and the adjacent gate line.

[0114] In other examples, the extension length of the first sub-extension 1351 in each outgoing line 130 may be less than the extension length of the second sub-extension 1352.

[0115] For example, in a number of fan-out lines 130, the first sub-extension segment 1351 and the second sub-extension segment 1352 in each fan-out line 130 have the same extension length, thereby reducing the difficulty of setting up the first sub-extension segment 1351 and the second sub-extension segment 1352 of the fan-out line 130.

[0116] For example, in each of the first sub-extensions 1351 and the second sub-extensions 1352 of each outgoing line 130, the number of gate lines 120 disposed adjacent to the first sub-extension 1351 can be one or more, and the number of gate lines 120 disposed adjacent to the second sub-extension 1352 can be one or more.

[0117] In this context, the adjacent arrangement of the sub-extension segment 135 and the gate line 120 can mean the following: In embodiments where the sub-extension segment 135 and the adjacent gate line 120 do not overlap along the thickness direction of the substrate 10, there are no other gate lines 120 projected onto the substrate 10 between the orthogonal projection of the sub-extension segment 135 on the substrate 10 and the orthogonal projection of the adjacent gate line 120 on the substrate 10. In embodiments where the sub-extension segment 135 and the adjacent gate line 120 at least partially overlap along the thickness direction of the substrate 10, no other gate lines 120 are provided between the sub-extension segment 135 and the adjacent gate line 120 along the thickness direction of the substrate. Furthermore, no other gate lines, power lines, DC potential lines, or shielding lines are provided between the sub-extension segment 135 and the gate lines 120 adjacent to it.

[0118] In some embodiments, the orthographic projection of the first sub-extension 1351 on the substrate 10 is a first orthographic projection, the orthographic projection of the second sub-extension 1352 on the substrate 10 is a second orthographic projection, and the orthographic projection of the gate line 120 on the substrate 10 is a third orthographic projection. In each fan-out line 130, at least two third orthographic projections are disposed between the first and second orthographic projections of the first sub-extension 1351 and the second sub-extension 1352, such that at least two gate lines 120 are disposed between the first sub-extension 1351 and the second sub-extension 1352 along the first direction A, and so on. 2. Adjacent to different gate lines 120, to avoid the situation where only one gate line 120 is provided between the first sub-extension 1351 and the second sub-extension 1352. If the first sub-extension 1351 and the second sub-extension 1352 are adjacent to the same gate line 120, the gate line 120 will affect the signal voltage of the first sub-extension 1351 and the second sub-extension 1352 at the time of signal transition. The parasitic capacitance between the gate line 120 and the fan-out line 130 is equal to the sum of the parasitic capacitances generated by the mutual coupling between the first sub-extension 1351, the second sub-extension 1352, and the gate line 120, which in turn leads to display defects. In the at least two gate lines 120, the gate line 120 corresponding to the third orthographic projection adjacent to the first orthographic projection is arranged adjacent to the first sub-extension 1351, and the gate line 120 corresponding to the third orthographic projection adjacent to the second orthographic projection is arranged adjacent to the second sub-extension 1352.

[0119] In some embodiments, referring to FIG5, the plurality of gate lines 120 include at least one of a first gate line Sa and a second gate line Sb, and at least one of a third gate line Sc and a fourth gate line Sd. In each fan-out line 130, in the first sub-extension 1351 and the second sub-extension 1352, the first sub-extension 1351 is adjacent to at least one of the first gate line Sa and the second gate line Sb, and the second sub-extension 1352 is adjacent to at least one of the third gate line Sc and the fourth gate line Sd.

[0120] In some embodiments, referring to FIG5, in each sector 130, the first sub-extension 1351 and the second sub-extension 1352 are each adjacent to a gate line 120. For example, the first sub-extension 1351 is adjacent to a first gate line Sa or a second gate line Sb (taking the first gate line Sa as an example), and the second sub-extension 1352 is adjacent to a third gate line Sc or a fourth gate line Sd (taking the third gate line Sc as an example). The signal of the first gate line Sa adjacent to the first sub-extension 1351 is different from the signal of the third gate line Sc adjacent to the second sub-extension 1352. Thus, the first sub-extension 1351... The signal transition time of the first gate line Sa adjacent to 351 is different from the signal transition time of the third gate line Sc adjacent to the second sub-extension 1352. The influence of the signal transition of the first gate line Sa on the signal voltage of the fan-out line 130 is mainly related to the parasitic capacitance between the first gate line Sa and the first sub-extension 1351. The parasitic capacitance between the first gate line Sa and the fan-out line 130 is mainly formed by the coupling between the first sub-extension 1351 and the first gate line Sa, thereby reducing the coupling degree between the first gate line Sa and the fan-out line 130 and reducing the parasitic capacitance between the first gate line Sa and the fan-out line 130, thereby improving the uniformity of the display brightness of the display panel 100. The impact of the signal transition of the third gate line Sc on the signal voltage of the fan-out line 130 is mainly related to the parasitic capacitance between the third gate line Sc and the second sub-extension 1352. This parasitic capacitance is primarily formed by the coupling between the second sub-extension 1352 and the third gate line Sc. Therefore, the coupling degree between the third gate line Sc and the fan-out line 130 can be reduced, thus reducing the parasitic capacitance between them and improving the uniformity of the display brightness of the display panel 100. Furthermore, in embodiments where the first gate line Sa and the third gate line Sc are located between the first sub-extension 1351 and the second sub-extension 1352, the different signals of the first gate line Sa and the third gate line Sc can isolate the first sub-extension 1351 and the second sub-extension 1352 from each other, so that the first sub-extension 1351 is only affected by the first gate line Sa, and the second sub-extension 1352 is only affected by the third gate line Sc.

[0121] In other embodiments, referring to FIG6a, in each sector 130, the first sub-extension 1351 and the second sub-extension 1352 are each provided with at least two gate lines 120 adjacent to each other. For example, the first sub-extension 1351 is adjacent to the first gate line Sa and the second gate line Sb, respectively. The first orthographic projection is located between the orthographic projection of the first gate line Sa adjacent to the first sub-extension 1351 on the substrate 10 and the orthographic projection of the second gate line Sb adjacent to the first sub-extension 1351 on the substrate 10. The second sub-extension 1352 is adjacent to the third gate line Sc and the fourth gate line Sd, respectively. The second orthographic projection is located between the orthographic projection of the third gate line Sc adjacent to the second sub-extension 1352 on the substrate 10 and the orthographic projection of the fourth gate line Sd adjacent to the second sub-extension 1352 on the substrate 10. The signal of the first gate line Sa adjacent to the first sub-extension 1351 is different from the signals of the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension 1352, and the signal of the second gate line Sb adjacent to the first sub-extension 1351 is different from the signals of the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension 1352. For example, the signals of any two of the first gate line Sa and the second gate line Sb adjacent to the first sub-extension 1351, and the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension 1352 are different. In this way, the parasitic capacitance between the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd and the fan-out line 130 can be reduced, thereby improving the uniformity of the display brightness of the display panel 100. The difference in the gate line signals may be due to different pulse transition times and / or different pulse amplitude polarities.

[0122] In some embodiments, referring to FIG4, the display panel 100 includes a plurality of pixel circuits 151 arranged in an array. Gate lines 120 extend along the row direction of the array (e.g., parallel to the second direction B), and data lines 110 extend along the column direction of the array (e.g., parallel to the first direction A). The plurality of data lines 110 are electrically connected to corresponding columns of pixel circuits 151. This embodiment of the application describes an example where one column of pixel circuits 151 is correspondingly configured with one data line 110. The data line 110 is electrically connected to the corresponding column of pixel circuits 151.

[0123] In this embodiment, the correspondence between A and B can refer to either one A corresponding to at least one B, or one B corresponding to at least one A. This embodiment uses the example of one A corresponding to one B for illustration.

[0124] For example, pixel circuit 151 includes a plurality of transistors with different functions. In at least a portion of the fan-out lines 130, in each fan-out line 130, the function of at least one (e.g., multiple or partially or all) gate line 120 adjacent to the first sub-extension 1351 is different from the function of the transistors electrically connected to the gate line 120 adjacent to the second sub-extension 1352.

[0125] Referring, as exemplarily to Figures 12 and 13, the plurality of gate lines 120 include a first scan line S1. For example, the first scan line S1 can be used to transmit a scan signal that controls the initialization of the first or second terminal of the drive transistor T1. The plurality of transistors include a drive transistor T1 and a first initialization transistor T8. The first initialization transistor T8 is connected between the first initialization signal line Verf1 and the first or second terminal of the drive transistor T1. The first scan line S1 is electrically connected to the gate of the first initialization transistor T8 and is used to control the on / off state of the first initialization transistor T8. When the first scan line S1 controls the first initialization transistor T8 to be turned on, the first initialization transistor T8 can transmit the signal from the first initialization signal line Verf1 to the first or second terminal of the drive transistor T1. The first initialization transistor T8 may include an N-type transistor or a P-type transistor.

[0126] In one embodiment, one of the first and second terminals of the transistor can be the source of the transistor, and the other of the first and second terminals of the transistor can be the drain of the transistor.

[0127] Referring, as exemplarily to Figures 12 and 13, the plurality of gate lines 120 include a second scan line S2. For example, the second scan line S2 can be used to transmit a scan signal that initializes the gate or second electrode of the driving transistor T1. The plurality of transistors include a second initialization transistor T4, which is connected between the second initialization signal line Verf2 and the gate or second electrode of the driving transistor T1. The second scan line S2 is electrically connected to the gate of the second initialization transistor T4, and the second scan line S2 is used to control the on / off state of the second initialization transistor T4. When the second scan line S2 controls the second initialization transistor T4 to be turned on, the second initialization transistor T4 can transmit the signal from the second initialization signal line Verf2 to the gate or second electrode of the driving transistor T1. The second initialization transistor T4 may include an N-type transistor or a P-type transistor.

[0128] Referring, as exemplarily to Figures 12 and 13, a plurality of transistors include a third initialization transistor T7, which is connected between a third initialization signal line Verf3 and the first electrode of the light-emitting unit OLED. A first scan line S1 is electrically connected to the gate of the third initialization transistor T7, and the first scan line S1 controls the on / off state of the third initialization transistor T7. When the first scan line S1 controls the third initialization transistor T7 to be turned on, the third initialization transistor T7 can transmit the signal from the third initialization signal line Verf3 to the first electrode of the light-emitting unit OLED. For example, the first scan line S1 can be used to transmit a scan signal controlling the initialization of the first electrode of the light-emitting unit OLED. The third initialization transistor T7 may include an N-type transistor or a P-type transistor.

[0129] In some embodiments, the gates of the second initialization transistor T4 and the third initialization transistor T7 may be connected to the same scan line, such as the second scan line S2. In other embodiments, the gates of the second initialization transistor T4 and the third initialization transistor T7 may be connected to different scan lines.

[0130] Referring, as exemplarily to Figures 12 and 13, the plurality of gate lines 120 include a third scan line S3, which may be used to transmit a scan signal controlling data writing. The plurality of transistors include a write transistor T2 connected between the data line 110 and the first terminal of the drive transistor T1. The third scan line S3 is electrically connected to the gate of the write transistor T2 and can control the on / off state of the write transistor T2. When the third scan line S3 controls the write transistor T2 to be turned on, the write transistor T2 can transmit the data voltage of the data line 110 to the first terminal of the drive transistor T1. The write transistor T2 may include an N-type transistor or a P-type transistor. Referring, as exemplarily to Figures 12 and 13, the plurality of gate lines 120 include a fourth scan line S4, which may be used to transmit a scan signal controlling threshold compensation. Multiple transistors include a threshold compensation transistor T3, which is connected between the gate and the second terminal of the driving transistor T1. A fourth scan line S4 is electrically connected to the gate of the threshold compensation transistor T3 and can control the on / off state of the threshold compensation transistor T3. When the fourth scan line S4 controls the threshold compensation transistor T3 to be turned on, the threshold compensation transistor T3 can conduct between the gate and the second terminal of the driving transistor T1, thereby compensating the threshold voltage of the driving transistor T1 to the voltage value obtained by the data voltage and transmitting it to the gate of the driving transistor T1.

[0131] In some embodiments, the gate of the write transistor T2 and the gate of the threshold compensation transistor T3 may be connected to the same scan line, that is, the third scan line S3 is multiplexed as the fourth scan line S4. In other embodiments, the gate of the write transistor T2 and the gate of the threshold compensation transistor T3 may be connected to different scan lines, that is, the third scan line S3 and the fourth scan line S4 are different scan lines. The threshold compensation transistor T3 may include an N-type transistor or a P-type transistor.

[0132] For example, referring to Figures 12 and 13, multiple gate lines 120 include light-emitting control lines EM, which can be used to transmit light-emitting control signals. Multiple transistors include a first light-emitting control transistor T5 and / or a second light-emitting control transistor T6. The first light-emitting control transistor T5 is connected between a first power supply line ELVDD and the first electrode of a driving transistor T1. The second light-emitting control transistor T6 is connected between the second electrode of the driving transistor T1 and the first electrode of the light-emitting unit OLED. The light-emitting control line EM is electrically connected to the gate of the corresponding first light-emitting control transistor T5 and / or the gate of the corresponding second light-emitting control transistor T6. The light-emitting control line EM can control the on / off state of the corresponding first light-emitting control transistor T5 and / or the second light-emitting control transistor T6. When the first light-emitting control transistor T5 and / or the second light-emitting control transistor T6 corresponding to the light-emitting control line EM are turned on, the first light-emitting control transistor T5 can transmit the signal from the first power line ELVDD to the first electrode of the driving transistor T1, and the second light-emitting control transistor T6 can connect the second electrode of the driving transistor T1 and the first electrode of the light-emitting unit OLED. The driving transistor T1 generates a driving current according to the voltage between its gate and the first electrode, driving the light-emitting unit OLED to emit light. The second electrode of the light-emitting unit OLED can be electrically connected to the second power line ELVSS. One of the first electrode and the second electrode of the light-emitting unit OLED can be an anode, and the other can be a cathode. For example, the first electrode of the light-emitting unit OLED can be an anode. The second electrode of the light-emitting unit OLED can be a cathode. The first light-emitting control transistor T5 can include an N-type transistor or a P-type transistor. The second light-emitting control transistor T6 can include an N-type transistor or a P-type transistor.

[0133] In some embodiments, pixel circuit 151 may include a first initialization transistor T8. In other embodiments, pixel circuit 151 may not include the first initialization transistor T8. Pixel circuit 151 may include some or all of transistors T1 to T8.

[0134] In some embodiments, referring to Figures 13 and 16, during the first initialization phase (t1), a signal on the second scan line S2 controls the conduction of the second initialization transistor T4. During the data writing and threshold compensation phase (t2), a signal on the third scan line S3 controls the conduction of the writing transistor T2, and a signal on the fourth scan line S4 controls the conduction of the threshold compensation transistor T3. During the second initialization phase (t3), a signal on the first scan line S1 controls the conduction of the third initialization transistor T7, and a signal on the first scan line S1 controls the conduction of the first initialization transistor T8. During the light emission phase (t4), a signal on the light emission control line EM controls the conduction of the corresponding first light emission control transistor T5 and / or second light emission control transistor T6.

[0135] The following describes the gate line set 120a provided in the embodiments of this application.

[0136] In some embodiments, referring to FIG4, the display panel 100 includes a plurality of gate line sets 120a, which are arranged along a first direction A. The plurality of gate line sets 120a are correspondingly configured with multiple rows of pixel circuits 151. This embodiment of the application describes an example of one gate line set 120a corresponding to one row of pixel circuits 151. The gate line set 120a is electrically connected to the corresponding row of pixel circuits 151.

[0137] For example, referring to Figure 4, each gate line set 120a includes a plurality of gate lines 120, and the number of gate lines 120 in each gate line set 120a can be any number of 2, 3, 4, or 5 or more. This embodiment of the application illustrates the example with 5 gate lines 120 in each gate line set 120a.

[0138] For example, each gate line set 120a includes at least one of a first gate line Sa, a second gate line Sb, a third gate line Sc, a fourth gate line Sd, and a fifth gate line Se. This application embodiment illustrates an example where each gate line set 120a includes a first gate line Sa, a second gate line Sb, a third gate line Sc, a fourth gate line Sd, and a fifth gate line Se. "At least one" may include one or more of these. "At least one" may include one or more of these.

[0139] For example, one of the first gate line Sa, the second gate line Sb, the third gate line Sc, the fourth gate line Sd, and the fifth gate line Se can be one of the first scan line S1, the second scan line S2, the third scan line S3, the fourth scan line S4, and the light emission control line EM. The first scan line S1, the second scan line S2, the third scan line S3, the fourth scan line S4, and the light emission control line EM are used to classify the multiple gate lines 120 according to their functions.

[0140] For example, the first gate line Sa can be the first scan line S1, that is, the first gate line Sa is electrically connected to the gate of the first initialization transistor T8, and the first gate line Sa is electrically connected to the gate of the third initialization transistor T7.

[0141] For example, the second gate line Sb can be the second scan line S2, that is, the second gate line Sb is electrically connected to the gate of the second initialization transistor T4.

[0142] For example, the arrangement order of the multiple gate lines 120 in any two gate line sets 120a may be the same or different. This application embodiment is illustrated by taking the example that the arrangement order of the multiple gate lines 120 in any two gate line sets 120a is the same.

[0143] For example, any two of the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd are arranged alternately along the first direction A, thereby reducing the difficulty of arranging these two lines. For instance, the first gate line Sa and the second gate line Sb are arranged alternately along the first direction A.

[0144] For example, referring to Figures 14a and 14b, the second scan line S2, the third scan line S3, the fourth scan line S4, the light emission control line EM, and the first scan line S1, which are electrically connected to the pixel circuit 151 in the same row, are arranged sequentially along the first direction A. This is equivalent to the second scan line S2, the third scan line S3, the fourth scan line S4, the light emission control line EM, and the first scan line S1 being arranged sequentially along the first direction A in the same gate line set 120a.

[0145] For example, the signals of any two of the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd are different. For instance, the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd can be used to transmit different functional signals, so that the signals of any two of the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd are different. In embodiments where the pixel circuit 151 includes a plurality of transistors with different functions, the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd are electrically connected to transistors with different functions.

[0146] The first distance L1 and the second distance L2 provided in the embodiments of this application will be described below.

[0147] For example, the distance between functionally identical gate lines 120 in two adjacent gate line sets 120a along the first direction A can be a first distance L1 (FIG. 2). For instance, taking a first gate line Sa as an example, the first distance L1 is the distance between two adjacent first gate lines Sa along the first direction A. Wherein, the first distance L1 is the size of a pixel along the first direction A.

[0148] In some embodiments, a column of pixel circuits 151 is correspondingly arranged with a data line 110, and the distance between each pair of adjacent data lines 110 is the same, and the distance between each pair of adjacent data lines 110 is a second distance L2 (FIG. 2). The second distance L2 can be the dimension of the pixel circuit 151 along the second direction B.

[0149] In some embodiments, among three adjacent data lines 110, the distance between the middle data line 110 and the data line 110 on one side is different from the distance between the middle data line 110 and the data line 110 on the other side. Half of the distance between the data line 110 on one side and the data line 110 on the other side is the second distance L2. For example, referring to FIG15, a plurality of pixel circuits 151 form a plurality of columns of pixel circuits 151 (taking four columns of pixel circuits 151 as an example). The plurality of columns of pixel circuits 151 are arranged along the second direction B. A plurality of data lines 110 form a plurality of data line groups 110a. The plurality of data line groups 110a are arranged along the second direction B. Each data line group 110a includes two data lines 110. A data line group 110a is correspondingly connected to two columns of pixel circuits 151. In the corresponding two columns of pixel circuits 151 and data line groups 110a, the orthographic projection of the two data lines 110 on the substrate 10 is at least partially located between the orthographic projections of the two columns of pixel circuits 151 on the substrate 10. Define two adjacent data line groups 110a as the first data line group and the second data line group, respectively. The second distance L2 is half the distance between a data line 110 in the first data line group that is closer to the second data line group and a data line 110 in the second data line group that is farther away from the first data line group.

[0150] The gate driving circuit 140 provided in the embodiments of this application will be described below.

[0151] In some embodiments, referring to FIG11a, the display panel 100 includes at least one (e.g., one or more) gate driving circuits 140. A gate driving circuit 140 can be electrically connected to gate lines 120 of the same function (i.e., transmitting the same functional signal) in each gate line set 120a. Alternatively, a gate driving circuit 140 can be electrically connected to gate lines 120 of different functions (i.e., transmitting different functional signals) in each gate line set 120a, which is equivalent to at least two types of gate lines with different functions sharing a gate driving circuit. A gate driving circuit 140 includes cascaded multi-stage shift registers 140a, and the shift registers 140a are electrically connected to corresponding gate lines 120. In the correspondingly configured gate driving circuits 140 and gate lines 120, a single-stage shift register 140a can be correspondingly configured with at least one gate line 120.

[0152] For example, the display panel 100 includes one or more gate drive circuits 140, the gate drive circuit 140 includes cascaded multi-stage shift registers 140a, and in at least a portion of the fan-out lines 130, in each fan-out line 130, at least one (e.g., multiple or partially or all) gate line 120 adjacent to the first sub-extension 1351 and the gate line 120 adjacent to the second sub-extension 1352 are electrically connected to the output of different shift registers 140a.

[0153] In embodiments where each gate line set 120a includes five gate lines 120, there can be five gate drive circuits 140. The gate lines 120 corresponding to different gate drive circuits 140 are used to transmit signals with different functions. Within the same gate drive circuit 140, the outputs of shift registers 140a at different stages are used to output signals with different timing sequences. For example, within the same gate drive circuit 140, shift registers 140a at different stages are used to transmit signals with the same function but different timing sequences (e.g., pulse phase delay). The electrical connection between the shift register 140a and the gate line 120 can mean that the output of the shift register 140a is electrically connected to the gate line 120.

[0154] In some embodiments, gate lines transmitting signals with different functions can be connected to the same gate drive circuit, that is, share a gate drive circuit.

[0155] For example, referring to FIG11a, the display panel 100 includes a first gate driving circuit 141, which includes cascaded multi-stage first shift registers 1411. The output terminal of the first shift register 1411 is electrically connected to the corresponding first gate line Sa. The output terminal of the first-stage first shift register 1411 can be electrically connected to at least one or at least two first gate lines Sa, and is electrically connected to the pixel circuit 151 of the corresponding row through the first gate line Sa. In this embodiment, the output terminal of the first-stage first shift register 1411 is electrically connected to two first gate lines Sa as an example. At least one may include one or more or at least two, etc. The output terminal of the first-stage first shift register 1411 can be electrically connected to at least one row or at least two rows of pixel circuits. One stage can be each stage or one of the stages.

[0156] For example, referring to FIG11a, the display panel 100 includes a second gate driving circuit 142, which includes cascaded multi-stage second shift registers 1422. The output terminal of the second shift register 1422 is electrically connected to the corresponding second gate line Sb. The output terminal of the first-stage second shift register 1422 can be electrically connected to at least one or at least two second gate lines Sb, and is electrically connected to the pixel circuit 151 of the corresponding row through the second gate line Sb. In this embodiment, the first-stage second shift register 1422 is electrically connected to one second gate line Sb as an example. The output terminal of the first-stage second shift register 1422 can be electrically connected to at least one row or at least two rows of pixel circuits.

[0157] For example, the display panel 100 includes a third gate driving circuit, which includes cascaded multi-stage third shift registers. The output of each third shift register is electrically connected to a corresponding third gate line Sc. The output of a first-stage third shift register can be electrically connected to at least one or at least two third gate lines Sc, and is electrically connected to the pixel circuit 151 of the corresponding row through the third gate line Sc. The output of the first-stage third shift register can be electrically connected to at least one or at least two rows of pixel circuits.

[0158] For example, the display panel 100 includes a fourth gate driving circuit, which includes cascaded multi-stage fourth shift registers. The output of each fourth shift register is electrically connected to a corresponding fourth gate line Sd. The output of a first-stage fourth shift register can be electrically connected to at least one or at least two fourth gate lines Sd, and is electrically connected to the pixel circuit 151 of the corresponding row through the fourth gate lines Sd. The output of a first-stage fourth shift register can be electrically connected to at least one or at least two rows of pixel circuits.

[0159] For example, the display panel 100 includes a fifth gate driving circuit, which includes cascaded multi-stage fifth shift registers. The output of each fifth shift register is electrically connected to a corresponding fifth gate line Se. The output of a first-stage fifth shift register can be electrically connected to at least one or at least two fifth gate lines Se, and is electrically connected to the pixel circuit 151 of the corresponding row via the fifth gate line Se. The output of the first-stage fifth shift register can be electrically connected to at least one or at least two rows of pixel circuits.

[0160] In each gate drive circuit, the stage pass signal terminal of the preceding shift register can be electrically connected to the input terminal of the following shift register in two adjacent shift register stages. For example, the stage pass signal terminal and the output terminal of the same shift register can be the same signal terminal or different signal terminals. For example, in the same gate drive circuit, the output terminals of two adjacent shift register stages have the same pulse width, but there is a phase delay.

[0161] Referring to Figures 6a-8c, the following description will be given regarding each sector 130, where the first sub-extension 1351 is adjacent to the first gate line Sa and the second gate line Sb, and the second sub-extension 1352 is adjacent to the third gate line Sc and the fourth gate line Sd.

[0162] In some embodiments, referring to FIG6a, in the first sub-extension 1351 and the second sub-extension 1352 of each fan-out line 130, the first orthographic projection is located between the orthographic projections of the adjacent first gate line Sa and the second gate line Sb electrically connected to the corresponding same row pixel circuit 151 on the substrate 10, and the second orthographic projection is located between the orthographic projections of the adjacent third gate line Sc and the fourth gate line Sd electrically connected to the corresponding same row pixel circuit 151 on the substrate 10.

[0163] In some embodiments, referring to FIG7, in the first sub-extension 1351 and the second sub-extension 1352 of each fan-out line 130, the first gate line Sa and the second gate line Sb adjacent to the first sub-extension 1351, and the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension 1352 are all electrically connected to the corresponding pixel circuit 151 in the same row. The orthographic projection of the first sub-extension 1351 and the second sub-extension 1352 in each fan-out line 130 on the substrate 10 is located between the orthographic projections of the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd electrically connected to the corresponding pixel circuit 151 in the same row on the substrate 10. This arrangement makes the distance between the first sub-extension 1351 and the second sub-extension 1352 along the first direction A relatively small, which is beneficial to increase the number of fan-out lines 130, increase the wiring density of fan-out lines 130, and / or reduce the overall space occupied by fan-out lines 130.

[0164] In an embodiment where the second scan line S2, the third scan line S3, the fourth scan line S4, the light emission control line EM, and the first scan line S1 are arranged sequentially along the first direction A in the same gate line set 120a, in each fan-out line 130, the first sub-extension segment 1351 is located between two adjacent pairs of the second scan line S2, the third scan line S3, the fourth scan line S4, the light emission control line EM, and the first scan line S1, and the second sub-extension segment 1352 is located between another two adjacent pairs of the second scan line S2, the third scan line S3, the fourth scan line S4, the light emission control line EM, and the first scan line S1.

[0165] In some embodiments, referring to FIG8a, in the first sub-extension 1351 and the second sub-extension 1352 of each fan-out line 130, the first gate line Sa and the second gate line Sb adjacent to the first sub-extension 1351 are electrically connected to a row of pixel circuits 151, and the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension 1352 are electrically connected to another row of pixel circuits 151. The first orthographic projection is located between the orthographic projections of the adjacent first gate line Sa and the second gate line Sb electrically connected to the corresponding row of pixel circuits 151 on the substrate 10, and the second orthographic projection is located between the orthographic projections of the adjacent first gate line Sa and the second gate line Sb electrically connected to the corresponding row of pixel circuits 151 ... adjacent first gate line Sa and the second gate line Sb electrically connected to the corresponding row of pixel circuits 151 and the second gate line Sd. A row of pixel circuit 151 is electrically connected between the orthogonal projections of adjacent third gate line Sc and fourth gate line Sd on substrate 10. This arrangement makes the distance between the first sub-extension 1351 and the second sub-extension 1352 along the first direction A larger. This is beneficial to increase the number of gate lines 120 between the second gate line Sb adjacent to the first sub-extension 1351 and the third gate line Sc adjacent to the second sub-extension 1352, and better avoids the influence of the second gate line Sb on the second sub-extension 1352, and better avoids the influence of the third gate line Sc on the first sub-extension 1351.

[0166] In some embodiments, referring to Figures 8b and 8c, in each sector 130, the second gate line Sb adjacent to the first sub-extension 1351 and the third gate line Sc adjacent to the second sub-extension 1352 are electrically connected to the same row pixel circuit 151, and the first gate line Sa adjacent to the first sub-extension 1351 and the fourth gate line Sd adjacent to the second sub-extension 1352 are electrically connected to different row pixel circuits 151. For example, referring to Figure 8b, in each sector 130, the second gate line Sb adjacent to the first sub-extension 1351, the third gate line Sc adjacent to the second sub-extension 1352, and the fourth gate line Sd are all electrically connected to the same row pixel circuit 151, and the first gate line Sa adjacent to the first sub-extension 1351 is electrically connected to another row pixel circuit 151. Alternatively, referring to Figure 8c, in each sub-extension 1351 and sub-extension 1352 of each sector 130, the first gate line Sa and the second gate line Sb adjacent to the first sub-extension 1351, and the third gate line Sc adjacent to the second sub-extension 1352 are all electrically connected to the same row of pixel circuits 151, and the fourth gate line Sd adjacent to the second sub-extension 1352 is electrically connected to another row of pixel circuits 151.

[0167] In some embodiments, in each sub-extension 1351 and second sub-extension 1352 of each outgoing line 130, the first gate line Sa and the second gate line Sb adjacent to the first sub-extension 1351 are electrically connected to different shift registers 140a, for example, electrically connected to different gate drive circuits 140 (see FIG. 6b), or electrically connected to the output terminals of different shift registers 140a of the same gate drive circuit 140 (see FIG. 6b). The third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension 1352 are electrically connected to different shift registers 140a, for example, electrically connected to different gate drive circuits 140 (see FIG. 6b), or electrically connected to the output terminals of different shift registers 140a of the same gate drive circuit 140 (see FIG. 6c). The shift register 140a electrically connected to the adjacent first gate line Sa and second gate line Sb is different from the shift register 140a electrically connected to the third gate line Sc and fourth gate line Sd adjacent to the second sub-extension 1352. For example, the first gate line Sa and second gate line Sb adjacent to the first sub-extension 1351, and the third gate line Sc and fourth gate line Sd adjacent to the second sub-extension 1352 are electrically connected to different gate drive circuits, or they are electrically connected to the output terminals of different shift registers of the same gate drive circuit. For example, any two of the first gate line Sa and second gate line Sb adjacent to the first sub-extension 1351, and the third gate line Sc and fourth gate line Sd adjacent to the second sub-extension 1352 are electrically connected to different shift registers 140a, so that the signals of these two are different.

[0168] Referring to Figures 9-10, the following description will be given regarding each gate line 130, where the first sub-extension 1351 is adjacent to the first gate line Sa and the second gate line Sb of a gate line group 120b, and the second sub-extension 1352 is adjacent to the first gate line Sa and the second gate line Sb of another gate line group 120b.

[0169] In some embodiments, the plurality of gate lines 120 include a plurality of gate line groups 120b, each gate line group 120b including a first gate line Sa and a second gate line Sb. The first gate line Sa and the second gate line Sb in the same gate line group 120b may be located in the same gate line set 120a. In this case, the first gate line Sa and the second gate line Sb in the same gate line group 120b may be electrically connected to the same row of pixel circuits 151. For example, the orthographic projections of the first gate line Sa and the second gate line Sb in the same gate line group 120b on the substrate 10 overlap with the orthographic projections of the same row of pixel circuits 151 on the substrate 10. Alternatively, the first gate line Sa and the second gate line Sb in the same gate line group 120b can be located in two different gate line sets 120a. In this case, the first gate line Sa and the second gate line Sb in the same gate line group 120b can be electrically connected to different row pixel circuits 151. For example, the orthographic projection of the first gate line Sa and the second gate line Sb in the same gate line group 120b on the substrate 10 overlaps with the orthographic projection of the different row pixel circuits 151 on the substrate 10.

[0170] In some embodiments, first gate lines Sa in different gate line groups 120b are electrically connected to transistors with the same function in pixel circuits 151 in different rows. And / or, second gate lines Sa in different gate line groups 120b are electrically connected to transistors with the same function in pixel circuits 151 in different rows. And / or, first gate lines Sa and second gate lines Sb are electrically connected to transistors with different functions in pixel circuits 151. For example, first gate lines Sa in different gate line groups are used to transmit signals with the same function; second gate lines Sb in different gate line groups are used to transmit signals with the same function.

[0171] Referring to Figures 9 and 10, in each gate line 130, the first sub-extension 1351 and the second sub-extension 1352 are adjacent to the first gate line Sa and the second gate line Sb in a corresponding gate line group 120b. The first orthographic projection is located between the orthographic projection of the first gate line Sa and the second gate line Sb in the corresponding gate line group 120b on the substrate 10. The second sub-extension 1352 is adjacent to the first gate line Sa and the second gate line Sb in another corresponding gate line group 120b. The second orthographic projection is located between the orthographic projection of the first gate line Sa and the second gate line Sb in the corresponding other gate line group 120b on the substrate 10. With this configuration, the two gate lines 120 adjacent to the first sub-extension segment 1351 and the second sub-extension segment 1352 in each gate line 130 have the same function, making the arrangement of the first sub-extension segment 1351 and the second sub-extension segment 1352 in each gate line 130 more regular. This helps to reduce the difficulty of arranging the first sub-extension segment 1351 and the second sub-extension segment 1352 in each gate line 130, improve the uniformity of the screen-off display, and reduce the risk of uneven screen-off display (mura) due to the irregular arrangement of the first sub-extension segment 1351 and the second sub-extension segment 1352.

[0172] In some embodiments, in each sub-extension 1351 and the second sub-extension 1352 of each outgoing line 130, the first gate line Sa adjacent to the first sub-extension 1351 and the first gate line Sa adjacent to the second sub-extension 1352 can be electrically connected to a gate drive circuit 140 or the output of a shift register 140a (e.g., the first shift register 1411) of a different stage of the first gate drive circuit, so that the signal timing of the first gate line Sa adjacent to the first sub-extension 1351 is different from the signal timing of the first gate line Sa adjacent to the second sub-extension 1352, so that the signal of the first gate line Sa adjacent to the first sub-extension 1351 is different from that of the second sub-extension 1352. The signal of the first gate line Sa adjacent to 1352, and the second gate line Sb adjacent to the first sub-extension 1351 and the second gate line Sb adjacent to the second sub-extension 1352 can be electrically connected to the output of a shift register 140a (e.g., the second shift register 1422) of a different stage of another gate drive circuit 140 or the second gate drive circuit, so that the signal timing of the second gate line Sb adjacent to the first sub-extension 1351 is different from the signal timing of the second gate line Sb adjacent to the second sub-extension 1352.

[0173] In an embodiment where the second scan line S2, third scan line S3, fourth scan line S4, light emission control line EM, and first scan line S1 are arranged sequentially along the first direction A in the same gate line set 120a, in each fan-out line 130, the first sub-extension segment 1351 is located between two adjacent segments of the second scan line S2, third scan line S3, fourth scan line S4, light emission control line EM, and first scan line S1. The gate line 120 adjacent to the first sub-extension segment 1351 and the second sub-extension segment 1352 has the same function but different signal timing and is electrically connected to different shift registers 140a. In this case, the first gate line Sa and the second gate line Sb in the same gate line group 120b can be two adjacent segments of the second scan line S2, third scan line S3, fourth scan line S4, light emission control line EM, and first scan line S1. Taking the first gate line Sa and the second gate line Sb in the same gate line group 120b as the second scan line S2 and the third scan line S3 respectively, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in each fan-out line 130, the first sub-extension segment 1351 is arranged adjacent to the second scan line S2 and the third scan line S3 of a gate line set 120a, and the second sub-extension segment 1352 is arranged adjacent to the second scan line S2 and the third scan line S3 of another gate line set 120a. The second scan line S2 adjacent to the first sub-extension segment 1351 and the second scan line S2 adjacent to the second sub-extension segment 1352 are electrically connected to different levels of second shift registers 1422, and the third scan line S3 adjacent to the first sub-extension segment 1351 and the third scan line S3 adjacent to the second sub-extension segment 1352 are electrically connected to different levels of third shift registers.

[0174] For example, referring to FIG10, in the first sub-extension 1351 and the second sub-extension 1352 of each sector 130, the first gate line Sa and the second gate line Sb in a gate line group 120b adjacent to the first sub-extension 1351 are electrically connected to pixel circuits 151 in different rows. The first gate line Sa and the second gate line Sb in a gate line group 120b adjacent to the first sub-extension 1351 are respectively located in different gate line sets 120a, and / or, the first gate line Sa and the second gate line Sb in another gate line group 120b adjacent to the second sub-extension 1352 are electrically connected to different In the pixel circuit 151 of the row, at least one of the first sub-extension segment 1351 and the second sub-extension segment 1352 in each fan-out line 130 is arranged adjacently. The two first gate lines Sa and the second gate lines Sb are respectively located in different gate line sets 120a. The orthographic projection of the first sub-extension segment 1351 and / or the second sub-extension segment 1352 on the substrate 10 can be located between the orthographic projections of two adjacent gate line sets 120a on the substrate 10. In this way, it is beneficial to reduce the interference of the first sub-extension segment 1351 and / or the second sub-extension segment 1352 on the arrangement of multiple gate lines 120 in the gate line set 120a.

[0175] In some embodiments, referring to Figures 11a-11c, each stage of the first shift register 1411 is electrically connected to N corresponding first gate lines Sa, where N is a positive integer. For example, N can be any number of 1, 2, 3, or greater than 3. Each stage of the second shift register 1422 is electrically connected to M corresponding second gate lines Sb, where M is a positive integer, and M can be any number of 1, 2, 3, or greater than 3. The output of each stage of the first shift register 1411 is electrically connected to N rows of pixel circuits via the first gate line Sa. The output of each stage of the second shift register 1422 is electrically connected to M rows of pixel circuits via the second gate line Sb.

[0176] For example, in each of the first sub-extension segments 1351 and 1352 of each outgoing line 130, at least K first gate lines Sa are provided between the first orthographic projection and the second orthographic projection on the substrate 10, where K = max(M, N), and K takes the larger of M and N. For example, when M = N, K = M = N; when M is greater than N, K = M; and when M is less than N, K = N. This makes it easier to provide at least K first gate lines Sa between the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A. One of the first sub-extensions 1351 is connected to a first-stage first shift register 1411, and one of the at least K first gate lines Sa that is closest to the second sub-extension 1352 is connected to another first-stage first shift register 1411. This makes the timing signals of the at least K first gate lines Sa that are closest to the first sub-extension 1351 and the one that is closest to the second sub-extension 1352 different. This helps to reduce the influence of the parasitic capacitance between the at least K first gate lines Sa and the fan-out line 130 on the signal voltage of the fan-out line, thereby improving the uniformity of the display brightness of the display panel 100. And / or, in each fan-out line 130, in the first sub-extension 1351 and the second sub-extension 1352, at least K second gate lines Sb are provided on the substrate 10 between the first orthographic projection and the second orthographic projection, where K = max(M, N). This helps to reduce the influence of the parasitic capacitance between the at least K second gate lines Sb and the fan-out line 130 on the signal voltage of the fan-out line, thereby improving the uniformity of the display brightness of the display panel 100. The principle has been explained and will not be repeated here.

[0177] For example, at least one of N and M is 1.

[0178] For example, at least one of N and M is greater than or equal to 2. Taking the first-level first shift register 1411 electrically connected to two first gate lines Sa as an example, the number of first shift registers 1411 can be reduced, which is beneficial to reducing the bezel width of the display panel 100.

[0179] In some embodiments, in each of the first sub-extension segments 1351 and the second sub-extension segments 1352 of each outgoing line 130, the length of the sub-connecting segment 134 connecting the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is greater than or equal to K times the first distance L1 (FIG. 2), and / or, in each of the first sub-extension segments 1351 and the second sub-extension segments 1352 of each outgoing line 130, the distance between the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is greater than or equal to K times the first distance L1, where K = max(M, N). For example, the distance between adjacent first sub-extension segments 1351 and the second sub-extension segments 1352 along the first direction A is greater than or equal to K times the first distance L1, so as to realize that in each of the first sub-extension segments 1351 and the second sub-extension segments 1352 of each outgoing line 130, at least K first gate lines Sa and at least K second gate lines Sb are provided on the substrate 10 for orthogonal projection between the first orthogonal projection and the second orthogonal projection.

[0180] For example, referring to Figure 2, in each outgoing line 130, the length of the sub-connecting segment 134 connecting the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is an integer multiple of the first distance L1, and / or the distance between the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is an integer multiple of the first distance L1. This setting makes the setting of the length of the sub-connecting segment 134 along the first direction A simpler, reduces the difficulty of setting the sub-connecting segment 134, and also makes the arrangement of the first sub-extension segment 1351 and the second sub-extension segment 1352 more regular.

[0181] For example, referring to Figure 2, among at least a portion of the adjacent fan-out lines 130, the distance between adjacent first sub-extension segments 1351 along the first direction A is an integer multiple of the first distance L1. This makes it easier to set the distance between the first sub-extension segments 1351 of the multiple fan-out lines 130 along the first direction A, reduces the difficulty of arranging each first sub-extension segment 1351, and makes the arrangement of each first sub-extension segment 1351 along the first direction A more regular.

[0182] For example, referring to Figure 2, among at least a portion of the adjacent fan-out lines 130, the distance between adjacent second sub-extension segments 1352 along the first direction A is an integer multiple of the first distance L1. This makes it easier to set the distance between the second sub-extension segments 1352 of the multiple fan-out lines 130 along the first direction A, reduces the difficulty of arranging each second sub-extension segment 1352, and makes the arrangement of each second sub-extension segment 1352 along the first direction A more regular.

[0183] For example, referring to Figure 2, among at least a portion of the adjacent fan-out lines 130, the distance between adjacent first sub-extension segments 1351 along the first direction A is equal to the distance between adjacent second sub-extension segments 1352 along the first direction A. This makes the arrangement of the first sub-extension segments 1351 and second sub-extension segments 1352 of each fan-out line 130 more regular, which helps to reduce the difficulty of arranging the first sub-extension segments 1351 and second sub-extension segments 1352 of each fan-out line 130.

[0184] For example, referring to Figure 2, among at least a portion of the adjacent fan-out lines 130, the distance between adjacent first sub-extension segments 1351 along the first direction A is less than or equal to the length of sub-connection segments 134 along the first direction A. The distance between adjacent first sub-extension segments 1351 along the first direction A can be set to be smaller so that more fan-out lines 130 can be set, and / or the space occupied by the fan-out lines can be reduced. In addition, the length of sub-connection segments 134 along the first direction A can be set to be larger, which is beneficial for setting more gate lines 120 with different signals between the first sub-extension segments 1351 and the second sub-extension segments 1352 along the first direction A, thereby better reducing the influence of parasitic capacitance between the gate lines 120 adjacent to the fan-out line 130 and the fan-out line 130 on the signal voltage of the fan-out line, so as to improve the uniformity of the display brightness of the display panel 100.

[0185] For example, referring to Figure 2, if the distance between adjacent second sub-extensions 1352 along the first direction A is less than or equal to the length of the sub-connection segment 134 along the first direction A among at least a portion of the adjacent fan-out lines 130, the distance between adjacent second sub-extensions 1352 along the first direction A can be set to be smaller so that more fan-out lines 130 can be set, and / or, the space occupied by the fan-out lines can be reduced.

[0186] The first outgoing line 131 provided in the embodiments of this application will be described below.

[0187] Referring to Figure 2, the plurality of fan-out lines 130 include a plurality of first fan-out lines 131. Each first fan-out line 131 contains a plurality of sub-extension segments 135, including a first sub-extension segment 1351 and a second sub-extension segment 1352. For example, the number of sub-extension segments 135 in the first fan-out line 131 can be any number of two, three, four, or more. This embodiment of the application uses two sub-extension segments 135 in the first fan-out line 131 as an example for illustration. The first sub-extension segment 1351 and the corresponding data line 110 are connected through the second sub-extension segment 1352.

[0188] For example, referring to Figure 2, the extension length of the second sub-extension segment 1352 in the plurality of first fan-outgoing lines 131 gradually decreases along the first direction A, making the arrangement of the second sub-extension segment 1352 in the plurality of first fan-outgoing lines 131 more regular. This can reduce the difficulty of setting up the second sub-extension segment 1352 in the plurality of first fan-outgoing lines 131, and also facilitate the connection of the second sub-extension segment 1352 in the plurality of first fan-outgoing lines 131 to the corresponding data line 110. For example, the extension length of the second sub-extension segment 1352 in the plurality of first fan-outgoing lines 131 gradually decreases along the direction from the display area 100a (Figure 1) to the first non-display area 101b (Figure 1).

[0189] For example, the first sub-extensions 1351 of the plurality of first fan-outlines 131 have equal extension lengths, thereby reducing the difficulty of setting up the first sub-extensions 1351 of the plurality of first fan-outlines 131, and / or making the extension lengths of the sub-extensions with the longest extension lengths among the plurality of first fan-outlines 131 equal, and the maximum parasitic capacitances between each first fan-outline and the adjacent gate line equal or approximately equal, so as to improve the uniformity of the display brightness of the display panel 100. The first sub-extension 1351 may be the sub-extension with the longest extension length among the first fan-outlines 131.

[0190] For example, the extension lengths of the sub-connection segments 134 in the multiple first-fan outgoing lines 131 are equal, which can better reduce the difficulty of setting up the sub-connection segments 134 in the multiple first-fan outgoing lines 131.

[0191] For example, at least one of the first sub-extension 1351 and the second sub-extension 1352 can extend along the second direction B. Taking the second sub-extension 1352 as an example, the second sub-extension 1352 extends along the second direction B, and the extension direction of the second sub-extension 1352 can be the same as the extension direction of the gate line 120. This can avoid the second sub-extension 1352 being too close to the adjacent gate line 120 along the first direction A, which helps to reduce the parasitic capacitance between the second sub-extension 1352 and the adjacent gate line 120. In addition, it can reduce the difficulty of setting the second sub-extension 1352.

[0192] For example, the second sub-extension segments 1352 of the multiple first fan-outgoing lines 131 are arranged at equal or unequal intervals along the first direction A, thereby allowing for a variety of arrangement methods for the second sub-extension segments 1352 of the multiple first fan-outgoing lines 131, which can be applied to more arrangement scenarios. For example, the arrangement of the second sub-extension segments 1352 of the multiple first fan-outgoing lines 131 at equal intervals along the first direction A is beneficial to improving the display effect.

[0193] For example, the first sub-extension segments 1351 of at least a portion of the adjacent first fan-outgoing lines 131 are arranged at equal or unequal intervals along the first direction A, thereby allowing for a greater variety of arrangement methods for the first sub-extension segments 1351 of the at least a portion of the first fan-outgoing lines 131, which can be applied to more arrangement scenarios. For instance, the arrangement of the first sub-extension segments 1351 of at least a portion of the adjacent first fan-outgoing lines 131 at equal intervals along the first direction A is beneficial for improving the display effect.

[0194] For example, referring to Figure 2, the distance L3 between the first sub-extension segments 1351 in two adjacent first sector outgoing lines 131 is less than or equal to the distance L4 between the first sub-extension segments 1351 and the second sub-extension segments 1352 in each first sector outgoing line 131 along the first direction A, and / or, the distance between the first sub-extension segments 1351 in two adjacent first sector outgoing lines 131 is less than or equal to the extension length of the sub-connecting segment 134. This allows the distance between the first sub-extension segments 1351 in two adjacent first sector outgoing lines 131 to be closer, which is beneficial for setting a larger number of first sub-extension segments 1351, thus facilitating the setting of more sectors. The outgoing line 130, and / or, reduces the space occupied by the fan-outgoing line. In addition, the distance between the first sub-extension segment 1351 and the second sub-extension segment 1352 in each first fan-outgoing line 131 along the first direction A is larger, and / or the extension length of the sub-connection segment 134 is set to be larger. This is beneficial to set more gate lines 120 with different signals between the first sub-extension segment 1351 and the second sub-extension segment 1352 in each first fan-outgoing line 131 along the first direction A, thereby better reducing the parasitic capacitance between the gate line 120 adjacent to the fan-outgoing line 130 and the fan-outgoing line 130, so as to improve the uniformity of the display brightness of the display panel 100.

[0195] For example, referring to Figure 2, the distance L5 between the second sub-extension segments 1352 in two adjacent first fan-out lines 131 is less than or equal to the distance L4 between the first sub-extension segments 1351 and the second sub-extension segments 1352 in each first fan-out line 131 along the first direction A; and / or, the distance between the second sub-extension segments 1352 in two adjacent first fan-out lines 131 is less than or equal to the extension length of the sub-connection segment 134, thereby facilitating the setting of a larger number of fan-out lines 130, and / or reducing the space occupied by the fan-out lines, and also better reducing the parasitic capacitance between the gate line 120 adjacent to the fan-out line 130 and the fan-out line 130, so as to improve the uniformity of the display brightness of the display panel 100. The principle has been explained and will not be repeated here.

[0196] For example, referring to Figure 2, the distance between the first sub-extension segment 1351 in two adjacent first fan-outgoing lines 131 is equal to the distance between the second sub-extension segment 1352 in two adjacent first fan-outgoing lines 131, so that the first sub-extension segment 1351 and the second sub-extension segment 1352 in multiple first fan-outgoing lines 131 are arranged in a more regular manner, which helps to reduce the difficulty of setting up.

[0197] For example, referring to FIG2, the extension length of the second sub-extension segment 1352 with the largest extension length among the plurality of first fan-out lines 131 is equal to the extension length of the first sub-extension segment 1351 among the plurality of first fan-out lines 131. This allows the extension length of the sub-extension segments 135 of all first fan-out lines 131 to be set to be relatively small, which is beneficial to reduce the parasitic capacitance between each sub-extension segment 135 and the adjacent gate line 120, thereby improving the uniformity of the display brightness of the display panel 100.

[0198] For example, referring to FIG2, the first fan-out line 131 is connected to the corresponding data line 110 through a first electrical connection node 1361 (a via can be provided here). The extension lengths of multiple sub-extension segments 135 in the first fan-out line 131 (F1 in FIG2) corresponding to the first electrical connection node 1361 that is furthest from the first non-display area 101b (FIG2) along the first direction A are equal. This allows the extension lengths of multiple sub-extension segments 135 in the first fan-out line 131 to be set to be relatively short, so that the parasitic capacitances between the multiple sub-extension segments 135 in the first fan-out line 131 and the corresponding adjacent gate line 120 are relatively small, which is beneficial to improving the uniformity of the display brightness of the display panel 100. Among all the sub-extensions 135 of the first fan-out line 131, the second sub-extension 1352 of the first fan-out line 131 corresponding to the first electrical connection node 1361 that is furthest from the first non-display area 101b along the first direction A has the largest extension length. This makes the extension length of the sub-extensions 135 of the longest first fan-out line 131 set to be relatively small, which is beneficial to improving the uniformity of the display brightness of the display panel 100.

[0199] For example, in related technologies, in each fan-out line, the portion of the fan-out line extending along the second direction B is not divided into multiple sub-extension segments, resulting in a large parasitic capacitance between the portion of the fan-out line extending along the second direction B and the adjacent gate line. In this application, in the first sub-extension segment 1351 and the second sub-extension segment 1352 of the first fan-out line 131 corresponding to the first electrical connection node 1361 that is furthest from the first non-display area 101b along the first direction A, the parasitic capacitance of the first sub-extension segment 1351 and the adjacent gate line 120, and the parasitic capacitance of the second sub-extension segment 1352 and the adjacent gate line 120 are both halved. The second sub-extension segment 1352 in the first fan-out line 131 corresponding to the first electrical connection node 1361 that is farthest from the first non-display area 101b along the first direction A has the largest extension length. If the parasitic capacitance between the second sub-extension segment 1352 with the largest extension length and the adjacent gate line 120 is E, then the parasitic capacitance between all other sub-extension segments 135 and the adjacent gate line 120 can be less than or equal to E, so that the effect of improving parasitic capacitance is the best and the design is optimal.

[0200] For example, referring to Figure 2, the first sub-extension segments 1351 of at least a portion of the adjacent first fan-out lines 131 are partially opposite and partially misaligned along the first direction A. In this way, by setting them to be partially opposite, the total extension length of the display panel 100 along the second direction B occupied by the first sub-extension segments 1351 of at least a portion of the first fan-out lines 131 can be reduced, which is beneficial for setting up a larger number of fan-out lines 130 and / or reducing the space occupied by the fan-out lines. In addition, by setting them to be partially misaligned, the layout of the first sub-extension segments 1351 among the at least a portion of the first fan-out lines 131 can be prevented from interfering with each other.

[0201] For example, referring to Figure 2, among the multiple first-fan outgoing lines 131, the misalignment distance L6 of adjacent first sub-extension segments 1351 is equal, which makes the arrangement of the first sub-extension segments 1351 among the multiple first-fan outgoing lines 131 more regular, which helps to reduce the difficulty of setting up the first sub-extension segments 1351 among the multiple first-fan outgoing lines 131.

[0202] For example, referring to Figure 2, the sub-connecting segments 134 in at least a portion of the adjacent first fan-out lines 131 are partially opposite and partially misaligned along the second direction B. In this way, by setting them to be partially opposite, the total extension length of the display panel 100 along the first direction A occupied by the sub-connecting segments 134 in at least a portion of the first fan-out lines 131 can be reduced, which is beneficial for setting up a larger number of fan-out lines 130 and / or reducing the space occupied by the fan-out lines. In addition, by setting them to be partially misaligned, the layout of the sub-connecting segments 134 in at least a portion of the first fan-out lines 131 can be prevented from interfering with each other.

[0203] For example, referring to Figure 2, in the multiple first-fan outgoing lines 131, the misalignment distance L5 of adjacent sub-connecting segments 134 is equal, which makes the setting of sub-connecting segments 134 in the multiple first-fan outgoing lines 131 more regular, which helps to reduce the difficulty of setting sub-connecting segments 134 in the multiple first-fan outgoing lines 131.

[0204] For example, referring to Figure 2, the difference in the extension length of the second sub-extension segment 1352 of two adjacent first fan-outgoing lines 131 is twice the second distance L2, which can reduce the difficulty of setting the second sub-extension segment 1352 in each first fan-outgoing line 131, and also facilitates the connection of the second sub-extension segment 1352 of the first fan-outgoing line 131 with the corresponding data line 110.

[0205] For example, referring to Figure 2, the extension length of the second sub-extension segment 1352 with the smallest extension length among the multiple first fan-outgoing lines 131 is greater than or equal to twice the second distance L2, thereby avoiding the extension length of the second sub-extension segment 1352 being too short and reducing the difficulty of setting up the second sub-extension segment 1352.

[0206] For example, referring to Figure 2, in each first sector output line 131, the distance between the second sub-extension segment 1352 and the first non-display area 101b along the first direction A is greater than the distance between the first sub-extension segment 1351 and the first non-display area 101b (Figure 1) along the first direction A. This makes the distance between the first sub-extension segment 1351 and the first non-display area 101b along the first direction A closer, which is beneficial to shorten the extension length of the auxiliary sub-connection segment 137, thereby reducing the mutual interference between the auxiliary sub-connection segment 137 and other signal lines, and also reducing the difficulty of setting up the auxiliary sub-connection segment 137.

[0207] The second outgoing line 132 provided in the embodiments of this application will be described below.

[0208] In some embodiments, referring to FIG3, the plurality of fan-out lines 130 further include a plurality of second fan-out lines 132, wherein the number of sub-extension segments 135 in each second fan-out line 132 is greater than the number of sub-extension segments 135 in each first fan-out line 131. For example, the number of sub-extension segments 135 in each second fan-out line 132 can be any number of 3, 4, or greater than 4. In this embodiment, the number of sub-extension segments 135 in each second fan-out line 132 is described as 3.

[0209] For example, referring to Figure 3, each second fan-out line 132 includes multiple sub-extensions 135, including a first sub-extension 1351, a second sub-extension 1352, and a third sub-extension 1353. The third sub-extension 1353 is connected between the second sub-extension 1352 and the corresponding data line 110. For instance, in each second fan-out line 132, the signal of at least one gate line 120 adjacent to the third sub-extension 1353 is different from the signal of the gate line 120 adjacent to the second sub-extension 1352. This can reduce the influence of the at least one gate line 120 on the signal voltage of the second fan-out line 132 at its signal transition time, thereby improving the uniformity of the display brightness of the display panel 100. The principle is similar to that of the first sub-extension 1351 and the second sub-extension 1352, and will not be described again.

[0210] For example, referring to Figure 3, the extension length of the third sub-extension segment 1353 in the plurality of second fan-outgoing lines 132 gradually decreases along the first direction A, making the arrangement of the third sub-extension segment 1353 in the plurality of second fan-outgoing lines 132 more regular. This can reduce the difficulty of setting up the third sub-extension segment 1353 in the plurality of second fan-outgoing lines 132, and also facilitate the connection of the third sub-extension segment 1353 in the plurality of second fan-outgoing lines 132 with the corresponding data. For example, the extension length of the third sub-extension segment 1353 in the plurality of second fan-outgoing lines 132 gradually decreases along the direction from the display area 100a to the first non-display area 101b (Figure 1).

[0211] For example, referring to Figure 3, the extension lengths of the first sub-extensions 1351 in the plurality of second fan-out lines 132 are equal, and / or the extension lengths of the second sub-extensions 1352 in the plurality of second fan-out lines 132 are equal, thereby better reducing the difficulty of setting the first sub-extensions 1351 and / or the second sub-extensions 1352 in the plurality of second fan-out lines 132, and / or making the parasitic capacitance between the first sub-extension of each second fan-out line and the adjacent gate line equal or approximately equal, and making the parasitic capacitance between the second sub-extension of each second fan-out line and the adjacent gate line equal or approximately equal, so as to improve the uniformity of the display brightness of the display panel 100.

[0212] For example, referring to FIG3, the extension lengths of the first sub-extension segment 1351 and the second sub-extension segment 1352 in each second fan-out line 132 are equal, thereby reducing the difficulty of setting the first sub-extension segment 1351 and the second sub-extension segment 1352 in each second fan-out line 132, and / or making the parasitic capacitance between the first sub-extension segment and the adjacent gate line, and the parasitic capacitance between the second sub-extension segment and the adjacent gate line equal or approximately equal, so as to improve the uniformity of the display brightness of the display panel 100.

[0213] For example, referring to Figure 3, the extension lengths of the first sub-extension segment 1351 in the second fan-out line 132 and the first sub-extension segment 1351 in the first fan-out line 131 are equal. This helps to reduce the difficulty of setting up the first sub-extension segment 1351 in the first fan-out line 131 and the second fan-out line 132, and / or makes the parasitic capacitance between the first sub-extension segment in the second fan-out line 132 and the adjacent gate line, and the parasitic capacitance between the first sub-extension segment 1351 in the first fan-out line 131 and the adjacent gate line equal or approximately equal, so as to improve the uniformity of the display brightness of the display panel 100.

[0214] For example, referring to FIG3, the third sub-extension 1353 extends along the second direction B, which can avoid the third sub-extension 1353 being too close to the adjacent gate line 120 along the first direction A, which helps to reduce the parasitic capacitance between the third sub-extension 1353 and the adjacent gate line 120. In addition, it can reduce the difficulty of setting the third sub-extension 1353.

[0215] The extension directions of the first sub-extension segment 1351 of the first outgoing line 131 and the first sub-extension segment 1351 of the second outgoing line 132 may be the same or different. The extension directions of the second sub-extension segment 1352 of the first outgoing line 131 and the second sub-extension segment 1352 of the second outgoing line 132 may be the same or different.

[0216] For example, the third sub-extension segments 1353 of multiple second fan-outgoing lines 132 are arranged at equal or unequal intervals along the first direction A, and / or, at least a portion of the first sub-extension segments 1351 of adjacent second fan-outgoing lines 132 are arranged at equal or unequal intervals along the first direction A, and / or, at least a portion of the second sub-extension segments 1352 of adjacent second fan-outgoing lines 132 are arranged at equal or unequal intervals along the first direction A. This allows for a greater variety of arrangement methods for the sub-extension segments 135 of multiple second fan-outgoing lines 132, making them applicable to more layout scenarios. The principle has already been explained and will not be repeated here. Equal interval arrangement is beneficial for improving display effects and / or reducing design complexity.

[0217] For example, at least a portion of the first sub-extension segments 1351 in the second fan-outgoing lines 132 and at least a portion of the first sub-extension segments 1351 in the first fan-outgoing lines 131 are arranged at equal or unequal intervals along the first direction A; and / or, at least a portion of the second sub-extension segments 1352 in the second fan-outgoing lines 132 and at least a portion of the second sub-extension segments 1352 in the first fan-outgoing lines 131 are arranged at equal or unequal intervals along the first direction A, thereby allowing for more arrangement methods of at least a portion of the first fan-outgoing lines 131 and the sub-extension segments 135 in the second fan-outgoing lines 132, which can be applied to more arrangement scenarios. The principle has been explained and will not be repeated here.

[0218] For example, referring to Figure 3, the extension length of the sub-connection segment 134 in the second fan-out line 132 is equal to the extension length of the sub-connection segment 134 in the first fan-out line 131, thereby reducing the difficulty of setting up the sub-connection segment 134 of the first fan-out line 131 and the second fan-out line 132.

[0219] For example, referring to Figure 3, the extension length of the third sub-extension segment 1353, which has the longest extension length among the plurality of second-fan outgoing lines 132, is equal to the extension length of the first sub-extension segment 1351 among the plurality of first-fan outgoing lines 131. The extension length of the third sub-extension segment 1353, which has the longest extension length among the plurality of second-fan outgoing lines 132, is equal to the extension length of the second sub-extension segment 1352, which has the longest extension length among the plurality of first-fan outgoing lines 131.

[0220] For example, referring to Figure 3, the extension length of the third sub-extension segment 1353, which has the longest extension length among the plurality of second-outgoing lines 132, is equal to the extension length of the first sub-extension segment 1351 among the second-outgoing lines 132. The extension length of the third sub-extension segment 1353, which has the longest extension length among the plurality of second-outgoing lines 132, is equal to the extension length of the second sub-extension segment 1352 among the second-outgoing lines 132.

[0221] For example, referring to Figure 3, in each second outgoing line 132, the sub-connecting segment 134 includes a first sub-connecting segment 1341 and a second sub-connecting segment 1342. The first sub-connecting segment 1341 is connected between the first sub-extension segment 1351 and the second sub-extension segment 1352, and the second sub-connecting segment 1342 is connected between the second sub-extension segment 1352 and the third sub-extension segment 1353. The extension length of the first sub-connecting segment 1341 in the second outgoing line 132 is equal to the extension length of the second sub-connecting segment 1342 in the second outgoing line 132, which helps to reduce the difficulty of setting up the first sub-connecting segment 1341 and the second sub-connecting segment 1342 in the second outgoing line 132.

[0222] For example, referring to Figure 3, the extension length of the second sub-extension 1352 in each second sector 132 is greater than or equal to the extension length of the third sub-extension 1353.

[0223] For example, referring to Figure 3, in a portion of the second sector outlets 132, the extension lengths of the second sub-extension 1352 and the third sub-extension 1353 in each second sector outlet 132 are equal.

[0224] For example, referring to Figure 3, in a portion of the second sector outlets 132, the extension length of the second sub-extension segment 1352 in each second sector outlet 132 is greater than the extension length of the third sub-extension segment 1353.

[0225] For example, referring to Figure 3, the difference in the extension length of the third sub-extension segment 1353 of two adjacent second fan-outgoing lines 132 is twice the second distance L2, which can reduce the difficulty of setting the third sub-extension segment 1353 in each second fan-outgoing line 132, and also facilitates the connection between the second fan-outgoing line 132 and the corresponding data line 110. The principle has been explained and will not be repeated here.

[0226] For example, at least a portion of the first sub-extensions 1351 of adjacent second fan-outgoing lines 132 are partially opposite and partially misaligned along the first direction A; and / or, at least a portion of the second sub-extensions 1352 of adjacent second fan-outgoing lines 132 are partially opposite and partially misaligned along the first direction A; at least a portion of the first sub-extensions 1351 of the first fan-outgoing lines 131 are partially opposite and partially misaligned with the first sub-extensions 1351 of the second fan-outgoing lines 132 along the first direction A; and / or At least a portion of the second sub-extension segments 1352 in the first fan-out line 131 are partially opposite to and partially misaligned with the second sub-extension segments 1352 in the second fan-out line 132 along the first direction A. This facilitates the installation of a larger number of fan-out lines 130 and / or reduces the space occupied by the fan-out lines. It also avoids mutual interference in the layout between the first sub-extension segments 1351 of adjacent fan-out lines 130 and between the second sub-extension segments 1352 of adjacent fan-out lines 130. The principle has been explained and will not be repeated here.

[0227] For example, referring to Figure 3, in the plurality of second-fan outgoing lines 132 and / or the plurality of first-fan outgoing lines 131, the stagger distance of adjacent first sub-extension segments 1351 is equal, thereby making the arrangement of the first sub-extension segments 1351 in the plurality of second-fan outgoing lines 132 and / or the plurality of first-fan outgoing lines 131 more regular, which helps to reduce the difficulty of setting the first sub-extension segments 1351 in the plurality of second-fan outgoing lines 132 and / or the plurality of first-fan outgoing lines 131.

[0228] For example, referring to Figure 3, among the multiple second-fan outgoing lines 132, the stagger distance of adjacent second sub-extension segments 1352 is equal, which makes the arrangement of the second sub-extension segments 1352 of the multiple second-fan outgoing lines 132 more regular, which helps to reduce the difficulty of setting the second sub-extension segments 1352 of the multiple second-fan outgoing lines 132.

[0229] For example, the first sub-connecting segments 1341 of at least a portion of the adjacent second fan-out lines 132 are partially opposite to each other along the second direction B and partially misaligned. This is beneficial for setting up a larger number of second fan-out lines 132 and / or reducing the space occupied by the fan-out lines. It can also avoid mutual interference in the layout of the first sub-connecting segments 1341 of adjacent second fan-out lines 132. The principle has been explained and will not be repeated here.

[0230] For example, the second sub-connecting segments 1342 of at least a portion of the adjacent second fan-out lines 132 are partially opposite to each other along the second direction B and partially misaligned. This is beneficial for setting up a larger number of second fan-out lines 132 and / or reducing the space occupied by the fan-out lines. It can also avoid mutual interference between the layouts of the second sub-connecting segments 1342 of adjacent second fan-out lines 132. The principle has been explained and will not be repeated here.

[0231] For example, in a plurality of second outgoing lines 132 and / or a plurality of first outgoing lines 131, the offset distance of adjacent first sub-connecting segments 1341 is equal; and / or, in a plurality of second outgoing lines 132, the offset distance of adjacent second sub-connecting segments 1342 is equal, thereby helping to reduce the difficulty of setting up the second outgoing lines 132 and / or the first outgoing lines 131. The principle has been explained and will not be repeated here.

[0232] For example, at least a portion of the first sub-connecting segments 1341 in the first fan-outgoing lines 131 are partially opposite to, and partially misaligned with, the second sub-connecting segments 1342 in at least a portion of the second fan-outgoing lines 132 along the second direction B. The principle of this has been explained and will not be repeated here.

[0233] For example, among the multiple second-fan outgoing lines 132, the misalignment distance of adjacent second sub-extension segments 1352 is equal to the misalignment distance of adjacent first sub-extension segments 1351, which helps to reduce the difficulty of setting up the second-fan outgoing lines 132. The principle has been explained and will not be repeated here.

[0234] For example, referring to Figure 3, the second fan-out line 132 is connected to the corresponding data line 110 through a second electrical connection node 1362 (a via can be provided here). The extension lengths of multiple sub-extension segments 135 in the second fan-out line 132 (F1 in Figure 3) corresponding to the second electrical connection node 1362 that is furthest from the first non-display area 101b along the first direction A are equal. This allows the extension lengths of multiple sub-extension segments 135 in the second fan-out line 132 to be set to be relatively short, resulting in smaller parasitic capacitances between the multiple sub-extension segments 135 in the second fan-out line 132 and the corresponding adjacent gate line 120. This is beneficial for improving the uniformity of the display brightness of the display panel 100. Among all the sub-extensions 135 of the second fan-out line 132, the third sub-extension 1353 of the second fan-out line 132 corresponding to the second electrical connection node 1362 that is furthest from the first non-display area 101b along the first direction A has the largest extension length. This makes the extension length of the sub-extensions 135 of all the second fan-out lines 132 set to be relatively small, which is beneficial to improving the uniformity of the display brightness of the display panel 100.

[0235] For example, referring to Figure 3, in each second fan-out line 132, the distance between the third sub-extension segment 1353 and the first non-display area 101b along the first direction A is greater than the distance between the second sub-extension segment 1352 and the first non-display area 101b along the first direction A. The distance between the second sub-extension segment 1352 and the first non-display area 101b along the first direction A is greater than the distance between the first sub-extension segment 1351 and the first non-display area 101b along the first direction A. This makes the distance between the first sub-extension segment 1351 and the first non-display area 101b along the first direction A closer, which is beneficial to shorten the extension length of the auxiliary sub-connection segment 137, thereby reducing the mutual interference between the auxiliary sub-connection segment 137 and other signal lines, and also reducing the difficulty of setting up the auxiliary sub-connection segment 137.

[0236] For example, referring to Figure 3, the first sub-extension 1351 of the second fan-out line 132 is located on the side of the first sub-extension 1351 of the first fan-out line 131 away from the first non-display area 101b, and the second sub-extension 1352 of the second fan-out line 132 is located on the side of the second sub-extension 1352 of the first fan-out line 131 away from the first non-display area 101b. This is so that the second fan-out line 132, which has a longer total extension length along the second direction B, is located on the side of the first fan-out line 131 away from the first non-display area 101b, which helps to avoid layout interference caused by the second fan-out line 132 and the first fan-out line 131 crossing each other.

[0237] For example, referring to FIG3, the data line 110 electrically connected to the second fan-out line 132 is located between the data line 110 electrically connected to the first fan-out line 131 and the frame of the display panel 100 extending along the first direction A. That is, the data line 110 electrically connected to the second fan-out line 132 is located between the data line 110 electrically connected to the first fan-out line 131 and the second non-display area 102b (FIG2).

[0238] The auxiliary fan-out line 133 provided in the embodiments of this application will be described below.

[0239] In some embodiments, referring to FIG2, the plurality of data lines 110 include a plurality of first data lines 111 located in the second display area 102a, and the plurality of first data lines 111 are electrically connected to a plurality of first fan-out lines 131.

[0240] For example, referring to Figure 2, the first data line 111 is located in the first sub-region 102a1, and the multiple data lines 110 also include multiple second data lines 112 located in the second sub-region 102a2. The multiple fan-out lines 130 include multiple auxiliary fan-out lines 133, and the multiple auxiliary fan-out lines 133 are electrically connected to the multiple second data lines 112. Each auxiliary fan-out line 133 includes a first sub-extension segment 1351. The number of sub-extension segments 135 in each auxiliary fan-out line 133 is less than the number of sub-extension segments 135 in each first fan-out line 131, thereby reducing the number of sub-extension segments 135 in each auxiliary fan-out line 133, which simplifies the structure of the auxiliary fan-out line 133 and reduces the fabrication difficulty of each auxiliary fan-out line 133.

[0241] In one embodiment, each auxiliary fan-out line 133 may include one sub-extension segment 135.

[0242] For example, referring to FIG2, the first sub-extension 1351 of the auxiliary fan-out line 133 can extend along the second direction B, which can avoid the first sub-extension 1351 being too close to the adjacent gate line 120 along the first direction A, which helps to reduce the parasitic capacitance between the first sub-extension 1351 and the adjacent gate line 120. In addition, it can reduce the difficulty of setting the first sub-extension 1351.

[0243] For example, the first sub-extension segments 1351 in a plurality of auxiliary fan-out lines 133 are arranged at equal or unequal intervals along the first direction A, and / or, at least a portion of the first sub-extension segments 1351 in the first fan-out lines 131 and at least a portion of the first sub-extension segments 1351 in the auxiliary fan-out lines 133 are arranged at equal or unequal intervals along the first direction A, thereby enabling a greater variety of arrangement methods for the first sub-extension segments 1351 and making them applicable to more arrangement scenarios. The principle of this has been explained and will not be repeated here.

[0244] For example, referring to Figure 2, the length of the first sub-extension segment 1351 with the longest extension among the multiple auxiliary fan-out lines 133 is equal to the length of the first sub-extension segment 1351 in the first fan-out line 131. This makes the first sub-extension segment 1351 of each auxiliary fan-out line 133 smaller, which helps to reduce the parasitic capacitance between the first sub-extension segment 1351 of each auxiliary fan-out line 133 and the corresponding adjacent gate line 120, and helps to improve the uniformity of the display brightness of the display panel 100.

[0245] For example, referring to Figure 2, the distance of the first sub-extension segment 1351 in the adjacent first fan-out line 131 along the first direction A is equal to the distance of the first sub-extension segment 1351 in the adjacent auxiliary fan-out line 133 along the first direction A. This makes the arrangement of the first sub-extension segment 1351 in the first fan-out line 131 and the auxiliary fan-out line 133 more regular, which helps to reduce the difficulty of setting up the first sub-extension segment 1351 in the first fan-out line 131 and the auxiliary fan-out line 133.

[0246] For example, referring to Figure 2, the extension length of the first sub-extension segment 1351 of the plurality of auxiliary fan-out lines 133 gradually decreases along the first direction A, making the arrangement of the first sub-extension segment 1351 of the plurality of auxiliary fan-out lines 133 more regular. This can reduce the difficulty of setting the first sub-extension segment 1351 of the plurality of auxiliary fan-out lines 133, and also facilitate the connection of the first sub-extension segment 1351 of the plurality of auxiliary fan-out lines 133 to the corresponding second data line 112. For example, the extension length of the first sub-extension segment 1351 of the plurality of auxiliary fan-out lines 133 gradually decreases along the direction from the display area 100a to the first non-display area 101b.

[0247] For example, referring to Figure 2, the first sub-extension 1351 of the first fan-out line 131 is located on the side of the first sub-extension 1351 of the auxiliary fan-out line 133 away from the first non-display area 101b, which helps to avoid layout interference caused by the first fan-out line 131 and the auxiliary fan-out line 133 crossing each other.

[0248] For example, referring to Figure 2, the difference in the extension length of the first sub-extension segment 1351 of two adjacent auxiliary fan-out lines 133 is twice the second distance L2, which can reduce the difficulty of setting the first sub-extension segment 1351 in each auxiliary fan-out line 133, and also facilitates the connection of the auxiliary fan-out line 133 with the corresponding second data line 112.

[0249] In some embodiments, the fan-out lines 130 of the two second display areas 102a located on opposite sides of the first display area 101a along the second direction B are symmetrically arranged, thereby reducing the difficulty of setting the fan-out lines 130.

[0250] In some embodiments, the plurality of data lines 110 further include a third data line 113 located in the first display area 101a, the third data line 113 being electrically connected to the bonding pin 162 (FIG. 1) of the bonding area.

[0251] The auxiliary sub-connection segment 137 provided in the embodiments of this application will be described below.

[0252] Referring to Figure 2, in each fan-out line 130, the fan-out line 130 also includes an auxiliary sub-connection segment 137, which is electrically connected between the first sub-extension segment 1351 and the bonding pin 162 (Figure 1) of the bonding area. The bonding pin 162 (Figure 1) can be electrically connected to the driver chip 161 (Figure 1).

[0253] For example, a plurality of auxiliary sub-connection segments 137 are arranged along the second direction B, and the plurality of auxiliary sub-connection segments 137 extend along the first direction A.

[0254] For example, in at least a portion of the fan-out lines 130, the distance between two adjacent auxiliary sub-connecting segments 137 is an integer multiple of the second distance L2, which makes it easier to set the distance of multiple auxiliary sub-connecting segments 137 along the second direction B, reduces the difficulty of arranging each auxiliary sub-connecting segment 137, and makes the arrangement of each auxiliary sub-connecting segment 137 along the second direction B more regular.

[0255] In some embodiments, the display panel 100 includes a plurality of conductive layers located on the substrate 10, with an insulating layer disposed between adjacent conductive layers, and at least one of the plurality of conductive layers may be a metal layer. Any one of the data line 110, fan-out line 130, and gate line 120 may be disposed on at least one of the plurality of conductive layers.

[0256] For example, the data line 110 and the sub-extension 135 are disposed on different layers, and adjacent data lines 110 and sub-extensions 135 are connected by vias. The data lines 110 and sub-extensions 135 are located on different conductive layers, thereby preventing them from intersecting and short-circuiting.

[0257] For example, the conductive layer (which may include a metal layer or a transparent conductive layer) where the data line 110 is located is on the side of the conductive layer (which may include a metal layer or a transparent conductive layer) where the sub-extension 135 is located, away from or close to the substrate 10.

[0258] For example, the sub-connection segment 134 and the sub-extension segment 135 are configured on different layers, and adjacent sub-connection segments 134 and sub-extension segments 135 are connected by vias, which helps to improve the configuration flexibility of the sub-connection segment 134 and sub-extension segment 135 and avoids short circuits caused by the fan-out line 130 intersecting with adjacent signal lines.

[0259] For example, the conductive layer (which may include a metal layer or a transparent conductive layer) where the sub-connection segment 134 is located is on the side of the conductive layer where the sub-extension segment 135 is located that is away from or close to the substrate 10.

[0260] For example, the sub-connection segment 134 and the data line 110 can be set on the same layer or on different layers. There are many ways to set the sub-connection segment 134, which can be applied to many scenarios.

[0261] For example, sub-extension 135 and some or all of gate line 120 are disposed on different layers. For example, sub-extension 135 and some or all of gate line 120 are disposed on the same layer. For example, sub-connection segment 134 and gate line 120 are disposed on different layers. For example, data line 110 and gate line 120 are disposed on different layers. For example, data line 110 and gate line 120 are insulated and cross-connected.

[0262] Multiple structures set in the same layer can be obtained by patterning the same film layer, thus simplifying the process.

[0263] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0264] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0265] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, comprising: substrate; Multiple data lines are disposed on the substrate; Multiple gate lines are disposed on the substrate; Multiple fan-out lines are disposed on the substrate, and the multiple fan-out lines are electrically connected to at least a portion of the data lines; In this configuration, at least a portion of the plurality of fan-out lines, each fan-out line includes a sub-connection segment and a plurality of sub-extension segments, with adjacent sub-extension segments connected by the sub-connection segment. The plurality of sub-extension segments include a first sub-extension segment and a second sub-extension segment. Within the same refresh cycle, the display panel satisfies at least one of the following conditions: at least one voltage transition time of the pulse of the signal on at least one gate line adjacent to the first sub-extension segment is different from the voltage transition time of the pulse of the signal on the gate line adjacent to the second sub-extension segment; or, the amplitude polarity of the pulse of the signal on at least one gate line adjacent to the first sub-extension segment is different from the amplitude polarity of the pulse of the signal on the gate line adjacent to the second sub-extension segment.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the first sub-extension on the substrate is a first orthographic projection, the orthographic projection of the second sub-extension on the substrate is a second orthographic projection, and the orthographic projection of the gate line on the substrate is a third orthographic projection. In each of the first and second sub-extension segments of each outgoing line, at least two third orthographic projections are provided between the first orthographic projection and the second orthographic projection.

3. The display panel according to claim 2, characterized in that, The plurality of gate lines include at least one of a first gate line and a second gate line, and at least one of a third gate line and a fourth gate line. In each outgoing line, the first sub-extension segment is adjacent to the first gate line; the second sub-extension segment is adjacent to the third gate line, and the signal of the first gate line adjacent to the first sub-extension segment is different from the signal of the third gate line adjacent to the second sub-extension segment. or In each outgoing line, the first sub-extension segment and the second sub-extension segment are respectively adjacent to the first gate line and the second gate line. The first orthographic projection is located between the orthographic projection of the first gate line adjacent to the first sub-extension segment on the substrate and the orthographic projection of the second gate line adjacent to the first sub-extension segment on the substrate. The second sub-extension segment is respectively adjacent to the third gate line and the fourth gate line. The second orthographic projection is located between the orthographic projection of the third gate line adjacent to the second sub-extension segment on the substrate and the orthographic projection of the fourth gate line adjacent to the second sub-extension segment on the substrate. The signal of the first gate line adjacent to the first sub-extension segment is different from the signals of the third and fourth gate lines adjacent to the second sub-extension segment. The signal of the second gate line adjacent to the first sub-extension segment is different from the signals of the third and fourth gate lines adjacent to the second sub-extension segment.

4. The display panel according to claim 3, characterized in that, The display panel includes a plurality of pixel circuits arranged in an array, the gate lines extending along the row direction of the array, and the data lines extending along the column direction of the array; In each of the first and second sub-extension segments of the outgoing line, the first orthographic projection is located between the orthographic projections of the adjacent first gate line and second gate line electrically connected to the corresponding pixel circuit in the same row on the substrate; the second orthographic projection is located between the orthographic projections of the adjacent third gate line and fourth gate line electrically connected to the corresponding pixel circuit in the same row on the substrate. The column direction is parallel to the first direction, and the row direction is parallel to the second direction.

5. The display panel according to claim 4, characterized in that, The orthographic projections of the first sub-extension segment and the second sub-extension segment in each fan-out line on the substrate are located between the orthographic projections of the first gate line, the second gate line, the third gate line and the fourth gate line electrically connected to the corresponding pixel circuit in the same row on the substrate. or In each sector of the first sub-extension segment and the second sub-extension segment, the first gate line, the second gate line adjacent to the first sub-extension segment, and the third gate line and the fourth gate line adjacent to the second sub-extension segment are electrically connected to the corresponding pixel circuit in the same row.

6. The display panel according to claim 3, characterized in that, The display panel includes a plurality of pixel circuits arranged in an array, the gate lines extending along the row direction of the array, and the data lines extending along the column direction of the array; In each of the first and second sub-extension segments of the outgoing line, the first orthographic projection is located between the orthographic projections of the first gate line and the second gate line adjacent to the first sub-extension segment on the substrate; the second orthographic projection is located between the orthographic projections of the third gate line and the fourth gate line adjacent to the second sub-extension segment on the substrate. The orthographic projections of the second gate line adjacent to the first sub-extension and the third gate line adjacent to the second sub-extension on the substrate are located between the orthographic projections of the first gate line adjacent to the first sub-extension and the fourth gate line adjacent to the second sub-extension on the substrate; the second gate line adjacent to the first sub-extension and the third gate line adjacent to the second sub-extension are electrically connected to the pixel circuit in the same row; the first gate line adjacent to the first sub-extension and the fourth gate line adjacent to the second sub-extension are electrically connected to the pixel circuit in a different row. The column direction is parallel to the first direction, and the row direction is parallel to the second direction.

7. The display panel according to claim 3, characterized in that, The display panel satisfies at least one of the following conditions: The signals of any two of the first gate line, the second gate line, the third gate line, and the fourth gate line are different; The first gate line, the second gate line, the third gate line, and the fourth gate line are used to transmit different functional signals; The display panel includes multiple pixel circuits arranged in an array, each pixel circuit including multiple transistors with different functions. Gate lines extend along the row direction of the array, and data lines extend along the column direction of the array. The first gate line, second gate line, third gate line, and fourth gate line are electrically connected to the transistors with different functions; or Any two of the first gate line, the second gate line, the third gate line, and the fourth gate line are arranged alternately along the first direction.

8. The display panel according to claim 2, characterized in that, The plurality of gate lines include a plurality of gate line groups, and each gate line group includes a first gate line and a second gate line; In each of the first and second sub-extension segments of the outgoing line, the first sub-extension segment is adjacent to the first gate line and the second gate line in a corresponding gate line group, and the first orthographic projection is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate in the corresponding gate line group; the second sub-extension segment is adjacent to the first gate line and the second gate line in another corresponding gate line group, and the second orthographic projection is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate in the other corresponding gate line group.

9. The display panel according to claim 8, characterized in that, The display panel satisfies at least one of the following conditions: In each outgoing line, the signal timing of the first gate line adjacent to the first sub-extension segment and the signal timing of the second gate line adjacent to the second sub-extension segment are different from the signal timing of the first gate line adjacent to the second sub-extension segment; the signal timing of the second gate line adjacent to the first sub-extension segment is different from the signal timing of the second gate line adjacent to the second sub-extension segment. The first gate line and the second gate line are used to transmit different functional signals; or The first gate line and the second gate line are arranged alternately along the first direction.

10. The display panel according to claim 8, characterized in that, The display panel includes a plurality of pixel circuits arranged in an array, the gate lines extending along the row direction of the array, and the data lines extending along the column direction of the array; In each of the first and second sub-extension segments of the outgoing line, the first gate line and the second gate line in a gate line group adjacent to the first sub-extension segment are electrically connected to the pixel circuits in different rows, or the first gate line and the second gate line in another gate line group adjacent to the second sub-extension segment are electrically connected to the pixel circuits in different rows. and The column direction is parallel to the first direction, and the row direction is parallel to the second direction.

11. The display panel according to claim 8, characterized in that, The display panel includes a first gate driving circuit, which includes cascaded multi-stage first shift registers electrically connected to corresponding first gate lines. In each of the first and second sub-extension segments of the outgoing line, the first gate line adjacent to the first sub-extension segment and the first gate line adjacent to the second sub-extension segment are electrically connected to the output terminals of different first shift registers. The display panel includes a second gate driving circuit, which includes cascaded multi-stage second shift registers electrically connected to the corresponding second gate lines. In each sector of the first sub-extension segment and the second sub-extension segment, the second gate line adjacent to the first sub-extension segment and the second gate line adjacent to the second sub-extension segment are electrically connected to the output terminals of different second shift registers.

12. The display panel according to claim 11, characterized in that, The output of the first shift register in each stage is electrically connected to N corresponding first gate lines, where N is a positive integer; The output of each stage of the second shift register is electrically connected to M corresponding second gate lines, where M is a positive integer; In each outgoing line, the length of the sub-connection segment connecting the first sub-extension segment and the second sub-extension segment along the first direction is greater than or equal to K times the first distance, or the distance between the first sub-extension segment and the second sub-extension segment along the first direction is greater than or equal to K times the first distance, where K = max(M, N), and the first distance is the distance between two adjacent first gate lines along the first direction. At least one of N and M is 1, or at least one of N and M is greater than or equal to 2.

13. The display panel according to any one of claims 8-12, characterized in that, The display panel satisfies at least one of the following conditions: The display panel includes a plurality of pixel circuits arranged in an array, each pixel circuit including a plurality of transistors with different functions, and the first gate line in different gate line groups is electrically connected to transistors with the same function in different rows of pixel circuits. The second gate line in different gate line groups is electrically connected to transistors of the same function in different rows of pixel circuits; or The first gate line and the second gate line are electrically connected to transistors with different functions in the pixel circuit; and The display panel satisfies at least one of the following conditions: The pixel circuit includes: a driving transistor and a first initialization transistor, wherein the first initialization transistor is connected between a first initialization signal line and a first or second terminal of the driving transistor, and the first gate line is electrically connected to the gate of the first initialization transistor. The pixel circuit includes: a second initialization transistor, the second initialization transistor being connected between a second initialization signal line and the gate or second electrode of the driving transistor, the second gate line being electrically connected to the gate of the second initialization transistor; or The pixel circuit includes: a third initialization transistor, which is connected between a third initialization signal line and a first electrode of a light-emitting unit, and the first gate line is electrically connected to the gate of the third initialization transistor.

14. The display panel according to claim 11, characterized in that, The first gate line in different gate line groups is used to transmit signals with the same function; the second gate line in different gate line groups is used to transmit signals with the same function. The output of the first shift register in each stage is electrically connected to N corresponding first gate lines, where N is a positive integer; The output of each stage of the second shift register is electrically connected to M corresponding second gate lines, where M is a positive integer; In each outgoing line, the length of the sub-connection segment connecting adjacent first and second sub-extension segments along the first direction is greater than or equal to K times the first distance, where K = max(M, N), and the first distance is the distance between two adjacent first gate lines along the first direction; the data line extends along the first direction. At least one of N and M is greater than or equal to 2.

15. The display panel according to claim 1, characterized in that, The plurality of fan-out lines include a plurality of first fan-out lines, and each first fan-out line has a plurality of sub-extension segments including a first sub-extension segment and a second sub-extension segment; and The display panel satisfies at least one of the following conditions: the extension length of the second sub-extension segment in the plurality of first fan-outlines gradually decreases along a first direction; or, the extension lengths of the first sub-extension segments in the plurality of first fan-outlines are equal; or, the extension lengths of the sub-connecting segments in the plurality of first fan-outlines are equal; or The display panel satisfies at least one of the following conditions: the second sub-extension segments of the plurality of first fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; the first sub-extension segments of at least a portion of adjacent first fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; the distance between the first sub-extension segments of two adjacent first fan-out lines is less than or equal to the distance between the first sub-extension segment and the second sub-extension segment of each first fan-out line along the first direction; the distance between the first sub-extension segments of two adjacent first fan-out lines is less than or equal to the extension length of the sub-connecting segment. The distance between the second sub-extension segments of two adjacent first fan-out lines is less than or equal to the distance between the first and second sub-extension segments of each of the two adjacent first fan-out lines along the first direction; the distance between the second sub-extension segments of two adjacent first fan-out lines is less than or equal to the extension length of the sub-connecting segment; or the distance between the first sub-extension segments of two adjacent first fan-out lines is equal to the distance between the second sub-extension segments of the two adjacent first fan-out lines; or The extension length of the second sub-extension segment with the longest extension length among the plurality of first fan outgoing lines is equal to the extension length of the first sub-extension segment among the plurality of first fan outgoing lines; or The display panel satisfies at least one of the following conditions: the first sub-extension segments of at least a portion of adjacent first fan-out lines are partially opposite and partially misaligned along the first direction; or, the sub-connecting segments of at least a portion of adjacent first fan-out lines are partially opposite and partially misaligned along the second direction; or The display panel satisfies at least one of the following conditions: the misalignment distance of adjacent first sub-extension segments is equal among the plurality of first fan-outlines; or, the misalignment distance of adjacent sub-connection segments is equal among the plurality of first fan-outlines; or In each outgoing line, the second sub-extension segment is connected between the first sub-extension segment and the corresponding data line; or The display panel includes a display area and a first non-display area, the first non-display area being located on one side of the display area along a first direction, and the data line, the gate line, and the fan-out line all being at least partially located in the display area; the data line extends along the first direction; the display panel satisfies at least one of the following conditions: the extension length of the second sub-extension segment among the plurality of first fan-out lines gradually decreases along the direction from the display area to the first non-display area; the first fan-out line is connected to the corresponding data line through a first electrical connection node, and the extension lengths of the plurality of sub-extension segments among the first fan-out lines corresponding to the first electrical connection node farthest from the first non-display area along the first direction are equal; or, the extension length of the second sub-extension segment is the largest; or The first non-display area includes a bonding area, wherein the bonding pins of the bonding area are electrically connected to the fan-out line; or The difference in extension length between the second sub-extension segments of two adjacent first fan-out lines is twice the second distance; or The extension length of the second sub-extension segment with the smallest extension length among the plurality of first fan outgoing lines is greater than or equal to twice the second distance; or The distance between any two adjacent data lines is the same, and is the second distance, or Of the three adjacent data lines, the distance between the middle data line and the data line on one side is different from the distance between the middle data line and the data line on the other side; half the distance between the data line on one side and the data line on the other side is the second distance; or In each first fan-out line, the distance between the second sub-extension segment and the first non-display area along the first direction is greater than the distance between the first sub-extension segment and the first non-display area along the first direction.

16. The display panel according to claim 15, characterized in that, The plurality of fan-out lines also include a plurality of second fan-out lines, wherein the number of sub-extension segments in each second fan-out line is greater than the number of sub-extension segments in each first fan-out line; in each second fan-out line, the plurality of sub-extension segments include a first sub-extension segment, a second sub-extension segment and a third sub-extension segment, wherein the third sub-extension segment is connected between the second sub-extension segment and the corresponding data line; In each second sector line, the signal of at least one gate line adjacent to the third sub-extension is different from the signal of the gate line adjacent to the second sub-extension. The display panel satisfies at least one of the following conditions: the extension length of the third sub-extension segment in the plurality of second fan-outlines gradually decreases along a first direction; the extension lengths of the first sub-extension segments in the plurality of second fan-outlines are equal; the extension lengths of the second sub-extension segments in the plurality of second fan-outlines are equal; the extension lengths of the first sub-extension segment and the second sub-extension segment in each second fan-outline are equal; or the extension lengths of the first sub-extension segment in each second fan-outline and the first sub-extension segment in each first fan-outline are equal. The display panel satisfies at least one of the following conditions: the third sub-extension segments of the plurality of second fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; the first sub-extension segments of at least a portion of adjacent second fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; the second sub-extension segments of at least a portion of adjacent second fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; the first sub-extension segments of at least a portion of the second fan-out lines and the first sub-extension segments of at least a portion of the first fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; the second sub-extension segments of at least a portion of the second fan-out lines and the second sub-extension segments of at least a portion of the first fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; The segments are arranged at equal or unequal intervals along a first direction and extend along a second direction; the extension length of the sub-connecting segment in the second fan-out line is equal to the extension length of the sub-connecting segment in the first fan-out line; the extension length of the third sub-extending segment with the longest extension length among the plurality of second fan-out lines is equal to the extension length of the first sub-extending segment in the first fan-out line; or the extension length of the first sub-connecting segment in the second fan-out line is equal to the extension length of the second sub-connecting segment in the second fan-out line; the first sub-connecting segment is connected between the first sub-extending segment and the second sub-extending segment, the second sub-connecting segment is connected between the second sub-extending segment and the third sub-extending segment, and the extension length of the third sub-extending segment among the plurality of second fan-out lines gradually decreases along the direction from the display area to the first non-display area.

17. The display panel according to claim 15, characterized in that, The display panel includes a first display area and a second display area, the second display area being located on opposite sides of the first display area along a second direction, and the plurality of data lines including a plurality of first data lines located in the second display area, the plurality of first data lines being electrically connected to the plurality of first fan-out lines. The second display area includes a first sub-area and a second sub-area. The first sub-area is located on the side of the second sub-area opposite to the first display area, and the first data line is located in the first sub-area. The plurality of data lines also include a plurality of second data lines located in the second sub-area. The plurality of fan-out lines include a plurality of auxiliary fan-out lines, and the plurality of auxiliary fan-out lines are electrically connected to the plurality of second data lines. Each auxiliary fan-out line includes a first sub-extension segment, and the number of said sub-extension segments in each auxiliary fan-out line is less than the number of said sub-extension segments in each first fan-out line; The display panel satisfies at least one of the following conditions: the first sub-extension segments of the plurality of auxiliary fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction; or, at least a portion of the first sub-extension segments of the first fan-out lines and at least a portion of the first sub-extension segments of the auxiliary fan-out lines are arranged at equal or unequal intervals along a first direction and extend along a second direction. The display panel satisfies at least one of the following conditions: the extension length of the first sub-extension segment with the longest extension length among the plurality of auxiliary fan-out lines is equal to the extension length of the first sub-extension segment among the first fan-out lines; or, the distance between the first sub-extension segments in adjacent first fan-out lines along the first direction is equal to the distance between the first sub-extension segments in adjacent auxiliary fan-out lines along the first direction. The extension length of the first sub-extension segment of the plurality of auxiliary fan-outlines gradually decreases along the first direction; The first sub-extension of the first fan-out line is located on the side of the first sub-extension of the auxiliary fan-out line that is away from the first non-display area; The difference in the extension length of the first sub-extension segment of two adjacent auxiliary fan-out lines is twice the second distance; The fan-out lines of the two second display areas located on opposite sides of the first display area along the second direction are symmetrically arranged; The plurality of data lines also includes a third data line located in the first display area, the third data line being electrically connected to the bonding pin of the bonding area; Each outgoing line also includes an auxiliary sub-connection section, which is electrically connected between the first sub-extension section and the bonding pin of the bonding area of ​​the display panel; The plurality of auxiliary sub-connecting segments are arranged along the second direction and extend along the first direction; In at least a portion of the fan-out lines, the distance between two adjacent auxiliary sub-connecting segments is an integer multiple of the second distance.

18. The display panel according to claim 1, characterized in that, The display panel satisfies at least one of the following conditions: The extension length of the first sub-extension segment in each outgoing line is less than, greater than, or equal to the extension length of the second sub-extension segment. In a subset of the plurality of fan-out lines, the first sub-extension segment and the second sub-extension segment in each fan-out line have equal extension lengths; In a subset of the plurality of fan-out lines, the extension length of the first sub-extension segment in each fan-out line is greater than the extension length of the second sub-extension segment. In at least a portion of the plurality of fan-out lines, the number of sub-extension segments in each fan-out line is at least 3; The plurality of data lines extend along a first direction and are arranged along a second direction, wherein the first direction and the second direction intersect. The plurality of gate lines are arranged along the first direction and extend along the second direction; In each outgoing line, the extension directions of adjacent sub-connecting segments and sub-extension segments intersect; The sub-extension segment extends along the second direction; The sub-connection segment extends along the first direction, or the extension direction of the gate line intersects with the extension direction of the sub-connection segment; The display panel includes a display area and a first non-display area, the first non-display area being located on one side of the display area along a first direction, the data line, the gate line, and the fan-out line all being at least partially located in the display area; the data line extends along the first direction; the first non-display area includes a bonding area, the bonding pins of the bonding area being electrically connected to the fan-out line; among at least a portion of the fan-out lines, the greater the distance between the electrical connection node of the fan-out line and the corresponding data line and the first non-display area along the first direction, the greater the number of sub-extension segments in the fan-out line, the greater the number of sub-connection segments in the fan-out line, and the greater the sum of the extension lengths of the sub-extension segments in the fan-out line; The data line and the sub-extension are disposed on different layers; adjacent data lines and sub-extensions are connected by vias; The conductive layer containing the data line is located on the side of the conductive layer containing the sub-extension segment that is away from or close to the substrate; an insulating layer is provided between the conductive layer containing the data line and the conductive layer containing the sub-extension segment. The sub-connecting segment and the sub-extension segment are disposed in different layers; adjacent sub-connecting segments and sub-extension segments are connected by vias; The conductive layer containing the sub-connection segment is located on the side of the conductive layer containing the sub-extension segment that is away from or close to the substrate; an insulating layer is provided between the conductive layer containing the sub-connection segment and the conductive layer containing the sub-extension segment. The sub-connection segment and the data line can be arranged on the same layer or on different layers; Within the same refresh cycle, the first voltage transition time of the pulse of the signal on at least one gate line adjacent to the first sub-extension is different from the voltage transition time of the pulse of the signal on the gate line adjacent to the second sub-extension. Within the same refresh cycle, in each sector, the pulses of the signal on at least one gate line adjacent to the first sub-extension do not overlap with the pulses of the signal on the gate line adjacent to the second sub-extension. Within the same refresh cycle, in each sector, the pulses of the signal on at least one gate line adjacent to the first sub-extension are out of sync with the pulses of the signal on the gate line adjacent to the second sub-extension. Within the same refresh cycle, in each sector, the moment when the pulse of the signal on at least one gate line adjacent to the first sub-extension transitions to its own effective level is different from the moment when the pulse of the signal on the gate line adjacent to the second sub-extension transitions to its own effective level; or Within the same refresh cycle, in each sector, the moment when the pulse of the signal on each gate line adjacent to the first sub-extension transitions to its own effective level is different from the moment when the pulse of the signal on the gate line adjacent to the second sub-extension transitions to its own effective level.

19. The display panel according to claim 1, characterized in that, The display panel includes multiple pixel circuits arranged in an array, and each pixel circuit includes multiple transistors with different functions; The plurality of gate lines include a first scan line, the plurality of transistors include a driving transistor and a first initialization transistor, the first initialization transistor is connected between a first initialization signal line and a first or second terminal of the driving transistor, and the first scan line is electrically connected to the gate of the first initialization transistor. The plurality of gate lines include a second scan line, the plurality of transistors include a second initialization transistor, the second initialization transistor is connected between the second initialization signal line and the gate or second electrode of the driving transistor, and the second scan line is electrically connected to the gate of the second initialization transistor; The plurality of transistors includes a third initialization transistor, which is connected between a third initialization signal line and a first electrode of a light-emitting unit, and the first scan line is electrically connected to the gate of the third initialization transistor. The plurality of gate lines include a third scan line, and the plurality of transistors include a write transistor, the write transistor being connected between the data line and the first terminal of the drive transistor; the third scan line is electrically connected to the gate of the write transistor; The plurality of gate lines include a fourth scan line, and the plurality of transistors include a threshold compensation transistor, the threshold compensation transistor being connected between the gate and the second terminal of the driving transistor; the fourth scan line is electrically connected to the gate of the threshold compensation transistor. The plurality of gate lines include light-emitting control lines, and the plurality of transistors include at least one of a first light-emitting control transistor or a second light-emitting control transistor. The first light-emitting control transistor is connected between a first power supply line and a first electrode of the driving transistor, and the second light-emitting control transistor is connected between a second electrode of the driving transistor and a first electrode of the light-emitting unit. The light-emitting control lines are electrically connected to at least one of the gates of the corresponding first light-emitting control transistor or the gate of the corresponding second light-emitting control transistor. The second scan line, the third scan line, the fourth scan line, the light emission control line, and the first scan line, which are electrically connected to the pixel circuit in the same row, are arranged sequentially along a first direction; In each outgoing line, the first sub-extension segment is located between two adjacent scan lines (the second, third, fourth, and light-emitting control lines) and the second sub-extension segment is located between another two adjacent scan lines (the second, third, fourth, and light-emitting control lines). Alternatively, the display panel includes one or more gate driving circuits, each including cascaded multi-stage shift registers electrically connected to the corresponding gate lines. In each outgoing line, the first sub-extension segment is located between two adjacent scan lines (the second, third, fourth, and light-emitting control lines). The gate lines adjacent to the first and second sub-extension segments have the same function but different signal timing and are electrically connected to different shift registers.

20. A display panel, characterized in that, include: substrate; Multiple data lines are disposed on the substrate; Multiple gate lines are disposed on the substrate; Multiple fan-out lines are disposed on the substrate, and the multiple fan-out lines are electrically connected to at least a portion of the multiple data lines; One or more gate driving circuits, the gate driving circuits including cascaded multi-stage shift registers, the output of the shift registers being electrically connected to the corresponding gate lines; Multiple pixel circuits arranged in an array are electrically connected to the corresponding gate lines and data lines, and each pixel circuit includes multiple transistors with different functions. Among them, in at least a portion of the plurality of fan-out lines, each fan-out line includes a sub-connecting segment and a plurality of sub-extension segments, and two adjacent sub-extension segments are connected by the sub-connecting segment. The plurality of sub-extension segments include a first sub-extension segment and a second sub-extension segment. Wherein, at least one gate line adjacent to the first sub-extension and the gate line adjacent to the second sub-extension are electrically connected to the output terminals of different shift registers, or the transistors electrically connected to at least one gate line adjacent to the first sub-extension and the transistors electrically connected to the gate line adjacent to the second sub-extension have different functions.

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