Method for producing three-dimensional semiconductor nanoparticles from self-assembling metal nanoparticles

Abstract

The present invention relates to a method for producing three-dimensional semiconductor nanoparticles from self-assembling metal nanoparticles. The method combines the deposition of a metal on a semiconductor substrate using physical deposition techniques with reactive-ion plasma attacks on the metal-semiconductor assembly. The method is simple, fast and economical and dispenses with the need for lithographic processes.

Description

[0001] Procedure for producing three-dimensional semiconductor nanoparticles from self-assembled metallic nanoparticles.

[0002] DESCRIPTION

[0003] TECHNICAL SECTOR

[0004] The present invention relates to the fabrication of semiconductor nanostructures using an innovative selective etching method on pre-deposited, self-assembled metallic nanoparticles. This method is applicable to various technical sectors where semiconductor nanostructures are essential, such as nanophotonics and nanoelectronics. The nanostructures obtained through this process can be used in a wide variety of applications, including solar cells (as an active or antireflective layer), light emitters, lasers, nonlinear optics, terahertz antennas, and biosensing, among others.

[0005] BACKGROUND OF THE INVENTION

[0006] Over the past few decades, numerous methods have emerged for fabricating semiconductor nanostructures. These can be classified according to their formation strategy as "top-down" or "bottom-up" methods. The former involves removing different parts of a material to generate the required nanostructures from them. On the other hand, the "bottom-up" approach involves assembling individual atoms and molecules into larger structures. This latter method results in much more precise size control of nanostructures than that obtained by the "top-down" approach. In this method, atoms are typically deposited by physical methods such as thermal evaporation, molecular beam epitaxy (MBE), or metal-organic chemical vapor deposition (MOCVD).Generally, and by default, materials deposited using any of these techniques result in the growth of continuous thin layers. Therefore, concepts such as self-assembly are necessary for these two-dimensional thin layers to transform into three-dimensional nanostructures. An example of self-assembly that achieves a high degree of control in the formation of three-dimensional nanostructures is the growth of semiconductor quantum dots (QDs) using the Stranski-Krastanov method. These QDs form through the epitaxial growth of one semiconductor onto another after reaching a critical layer thickness, which depends on the strain and chemical potential of the deposited film. Growth continues through nucleation and coalescence, resulting in isolated quantum dots.This method, although highly efficient and high-resolution, requires complex equipment and the combination of different materials, making it impossible to obtain three-dimensional nanostructures on the same material.

[0007] Top-down methods, on the other hand, do not have this limitation, as the nanostructure is produced by decomposing or removing the original material. Among these methods, lithography stands out. It consists of transferring or etching a pattern drawn on a mask onto a desired substrate or material. This transfer can be performed in different ways, with photolithography, which uses light to transfer the pattern, being the most widely used today and, as such, the most established microfabrication method. The sizes of the structures that can be produced (i.e., the pattern resolution) are determined by the wavelength of the light used. Consequently, smaller structures require high-energy (ultraviolet) radiation and, therefore, complex and expensive facilities and technologies. For all these reasons, it is not a viable technique for producing nanostructures.

[0008] Given this disadvantage, many alternative "top-down" techniques have been developed to fabricate nanoscale structures. One example is electron beam lithography (EBL), which, limited by the wavelength of electrons, is capable of fabricating designs with a resolution of <10 nanometers. Furthermore, it has a high level of tolerance for application in more sophisticated devices where cost is not critical, but it is even more limited in terms of speed and surface coverage. Focused ion beam lithography (FIB), on the other hand, has similar advantages and disadvantages, but allows for pattern transfer without the use of a resin or mask.However, while these techniques, EBL and FIB, offer higher spatial resolution than photolithography, enabling the fabrication of smaller nanostructures, they also present other challenges such as higher cost, low surface coverage, slower manufacturing rates, and the requirement for highly sophisticated equipment. Finally, all the lithographic techniques mentioned so far share another major drawback: they require a post-lithography procedure to modify the shape of the nanostructure as needed. This post-lithography procedure can range from chemically assisted etching (such as that described in US RE48).407 E), inductively coupled reactive ion plasma etching (RIE-ICP) (US 9,627,199 B2), or even a combination of lithographic and reactive ion plasma etching (RIE) processes (US 9,120,669 B2). Of particular note is a method that shares similarities with this invention (US 6242326 B1), which uses gallium (Ga) droplets, among many other processes, to produce gallium arsenide (GaAs) semiconductor nanostructures. Specifically, this method involves processes such as: different dielectric deposition, photolithographic methods, thermal alloying, sacrificial and barrier layer deposition, Ga droplet deposition, and desorption processes that ultimately result in semiconductor nanostructures.

[0009] All the disadvantages of these complex processes continue to motivate research into unconventional soft lithography manufacturing techniques that avoid the use of hard masks, thus eliminating the need for radiation and simplifying the process while simultaneously reducing costs. Among these methods, colloidal lithography stands out. This technique, which uses a soft mask, has garnered attention in the field of nanotechnology because (1) it can be used on a wider range of surfaces, increasing the range of permissible materials, (2) it allows for larger-scale patterning, and, most importantly, (3) it employs industrially attractive manufacturing methods due to their ease of use and low cost. Its resolution depends solely on the sizes of the colloidal particles that can be deposited, allowing for nanoscale pattern control.Furthermore, nanostructures of different shapes, such as cones and nanowires (CN 105957801 A, WO 2016 / 205610 A1), can be obtained without any further processing. However, this method has a clear drawback: the smaller the deposited particles that act as a mask, the more affected they are by destabilizing Brownian forces, which prevent their ordered arrangement during self-assembly. Consequently, to date, the minimum feasible resolution of colloidal lithography ranges from 50 to 200 nm, which is comparable to that of more advanced (and more expensive) hard lithography systems, such as photolithography (determined by the UV diffraction limit), but not as low as the resolution of EBL or FIB lithography (on the order of a few nanometers).

[0010] DESCRIPTION OF THE INVENTION

[0011] In order to achieve the objectives and avoid the drawbacks mentioned in the preceding sections, the invention proposes a new method for obtaining three-dimensional semiconductor nanostructures from the controlled deposition of self-assembled metallic nanoparticles. This method has several advantages:

[0012] 1. Avoids lithographic processes: It does not require the use of any prefabricated mask (soft or hard), nor radiation that may limit the size of the nanostructures obtained.

[0013] 2. Reduces costs: By avoiding the processes mentioned, the cost associated with manufacturing is reduced.

[0014] 3. Simplicity and speed: The method consists of only two processes.

[0015] The procedure consists of two main processes:

[0016] 1. Metal deposition: First, a metal is deposited onto a semiconductor surface using physical deposition techniques. This process achieves the self-assembled formation of semi-spherical metallic nanoparticles with a controllable size.

[0017] 2. Physical-chemical etching process: Subsequently, a reactive ion plasma etching is performed on the metal-semiconductor assembly. The metallic nanoparticles are removed, simultaneously eroding the semiconductor surface. During the process, the metallic nanoparticles act as a mask.

[0018] Thus, in a first aspect, the invention relates to a procedure for producing three-dimensional semiconductor nanoparticles, comprising the following steps:

[0019] a) provide a substrate comprising a semiconductor material;

[0020] b) depositing a metal with a sufficiently low surface tension so that it forms self-assembled metallic nanoparticles when the metal is deposited onto the substrate using physical deposition techniques, obtaining a substrate at least partially coated with self-assembled metallic nanoparticles; and

[0021] c) attack the substrate coated at least partially with metallic nanoparticles using Reactive Ion Etching (RIE) techniques, obtaining three-dimensional semiconductor nanoparticles deposited on the substrate.

[0022] In a second aspect, the invention relates to the self-assembled metallic nanoparticles obtained from step b) of the above procedure. These nanoparticles are approximately hemispherical and are deposited on the semiconductor substrate, having a radius of approximately 10 to 500 nm.

[0023] In a third aspect, the invention relates to the three-dimensional semiconductor nanoparticles obtained according to the aforementioned procedure, which are also deposited on the semiconductor substrate. These particles have an approximately conical shape and a radius of approximately 10 to 500 nm.

[0024] The result of this method is semiconductor nanostructures with adjustable characteristics. The size, shape, and surface coverage percentage of these nanostructures can be modified by varying the initial size of the metallic nanoparticles and the parameters of the plasma etching process.

[0025] This method is distinguished by being efficient in terms of cost and time, as well as allowing precise control over the characteristics of the nanostructures formed, making it suitable for advanced applications in the semiconductor and nanomaterials industry.

[0026] A substantial feature of the invention is the selection of the material such that, thanks to its low surface tension / energy, after deposition it forms self-assembled nanostructures on the surface of the semiconductor material, i.e., without any external agent or additional prior or subsequent procedures. This characteristic is essential to avoid lithographic processes, but it is also a unique feature of certain metals. Those skilled in the art know, or can deduce by simple trial and error, which of these metals have a sufficiently low surface tension to form self-assembled metallic nanoparticles when deposited on a substrate using physical deposition techniques, given the limited number of metals in the Periodic Table. The preferred metals possessing this characteristic are gallium (Ga), indium (In), and bismuth (Bi).Physical deposition can be carried out by techniques such as thermal evaporation (by joule effect or with electron gun), MOCVD or MBE.

[0027] The invention further comprises a second process using Reactive Ion Etching (RIE), where the previously formed metallic nanostructures act as a mask. For this, the entire material (semiconductor-metal) is exposed to an ion plasma which, under predetermined conditions of pressure, gases, power, and time, produces their progressive and selective removal. Once all the metallic nanostructures have been removed, the result is a three-dimensional nanostructured surface of the semiconductor. In one particular embodiment, the RIE technique used is Inductively Coupled Plasma Reactive Ion Etching (RIE-ICP).

[0028] An important parameter is the response of both materials to ion attack. Depending on the RIE conditions used, a greater directionality of attack can be selected, resulting in greater selectivity of the attack on either the semiconductor material or the metal. These parameters will determine the size, shape, and final surface coverage percentage of the resulting semiconductor nanostructures.

[0029] BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The description is supplemented, for ease of understanding, by Figure 1, which illustrates the method of this invention for illustrative purposes only and is not intended to be limiting. In addition, five further figures are included showing a preferred embodiment.

[0031] Figure 1 shows a schematic illustration of the method of this invention, where three different stages are observed: Stage 1, which consists of a semiconductor surface; Stage 2, which consists of self-assembled metallic nanoparticles on the substrate of Stage 1; and Stage 3, which consists of three-dimensional semiconductor nanostructures on the surface of the substrate of Stage 1. A list of the various elements represented in Figure 1 that comprise the invention is provided below:

[0032] 1 = Semiconductor surface

[0033] 2=Metallic nanoparticles

[0034] 3=Native metallic oxide

[0035] 4=Semiconductor nanostructures

[0036] Figure 2 shows Transmission Electron Microscopy (TEM) images corresponding to steps 2 and 3 of Figure 1. The portion marked a1) in Figure 2 shows hemispherical Ga metallic nanoparticles deposited on a gallium arsenide (GaAs) substrate, while the portion marked a2) shows a high-magnification section of the area in section a1) marked with a black box. The corresponding Fast Fourier Transforms (FFTs) of the black box (Ga nanoparticle area) and the white box (GaAs substrate) are also included. The portion marked b1) in Figure 2 shows GaAs semiconductor nanostructures on a GaAs substrate, while the portion marked b2) shows a high-magnification section and its corresponding FFTs of the black and white boxes.

[0037] Figure 3 shows the compositional analysis by Energy Dispersive X-ray Spectroscopy (EDX) of steps 2 and 3 from Figure 1. The portion marked a) in Figure 3 shows hemispherical Ga metallic nanoparticles deposited on a GaAs substrate, while portion b) shows GaAs semiconductor nanostructures on a GaAs substrate. In the compositional maps, Ga content is associated with light gray, oxygen (O) with white, and arsenic (As) with dark gray.

[0038] Figure 4 shows the calibration of the RIE-ICP etching rate using argon (Ar) plasma on stage 1, which consists of a GaAs substrate. Additionally, the depth of etching data obtained from TEM images of the Ga nanoparticles are included.

[0039] Figure 5 shows two overhead Scanning Electron Microscopy (SEM) images of stages 2 and 3 of Figure 1 where a decrease in the percentage of surface coverage of the nanostructures is observed due to the RIE-ICP etching process.

[0040] Figure 6 shows a SEM cross-sectional view of steps 2 and 3 of Figure 1, corresponding to nanostructures hundreds of nanometers in size, larger than those observed in Figures 2 and 3, demonstrating the high size control of the method of this invention. DESCRIPTION OF A PREFERRED EMBODIMENT

[0041] In view of the aforementioned figures, and in accordance with the numbering adopted, an example of a preferred embodiment of the invention is presented, which comprises the characteristics and procedures that are outlined in Figure 1 and described in detail below.

[0042] The method of this invention begins in step 1, which consists of a semiconductor material that acts as a substrate for the metallic nanostructures of step 2 and is a constituent of the semiconductor nanostructures of step 3. The crystalline quality of step 3 will be conditioned by the crystalline quality of the substrate of step 1. In this preferred embodiment, flat GaAs (001 ) n substrates have been used. + This method can be extrapolated to other semiconductor substrates.

[0043] Step 2 is achieved by depositing a metallic material onto the substrate, resulting in metallic nanoparticles. In this preferred embodiment, Ga has been chosen because, due to the reduction of surface tension with the substrate, it readily forms self-assembled nanoparticles on a multitude of substrates such as silicon, glass, aluminum (Al), sapphire (Al₂O₃), polymers, copper (Cu), etc. However, the invention is not limited to Ga; it could also be carried out with other metals that have similar surface tension / energy relaxation properties with the semiconductor surface interface, such as indium (In) or bismuth (Bi). The shape of the Ga nanoparticles depends intrinsically on the wetting angle with the substrate, which is a function of the surface tension. In this preferred embodiment of the invention, hemispherical nanoparticles with contact angles of 100° are typically obtained. eWhen the substrate is GaAs, the physical deposition of metallic Ga can be carried out using different techniques such as MOCVD, MBE, or thermal evaporation. In this preferred embodiment, Joule heating was used because it is a simple, economical method commonly used in the semiconductor industry. The deposition process was performed in a vacuum chamber at a working pressure of 1.5–10' 5At mbar, applying 50 W to a tungsten filament causes the evaporation of Ga, which is deposited onto a GaAs substrate located 200 mm away. The final size of the nanoparticles is determined by the amount of material evaporated. After deposition, when the nanoparticles are exposed to air, the chemical reactivity of Ga with oxygen leads to the formation of a self-limiting, passivating, amorphous Ga oxide (GaxOy) crust, resulting in a core-shell structure represented in stage 2 of Figure 1. The core of the nanoparticles consists of a subcooled liquid of metallic Ga, as evidenced by TEM characterization. As shown in section a1) of Figure 2, the hemispherical nanoparticles obtained under these conditions have an aspect ratio (height / width) of 0.44 ± 0.02 with radii less than 50 nm.The corresponding FFTs (section a2 of Figure 2) demonstrate the amorphous nature of the Ga core (liquid phase) in addition to the monocrystalline nature of the substrate. The compositional characterization, presented in Figure 3a), highlights the absence of As in the nanoparticles at this stage 2.

[0044] Step 3 is obtained by ICP-RIE etching the metallic nanoparticles from Step 2, resulting in semiconductor nanostructures. The ICP-RIE ion plasma etches not only the Ga nanoparticles but also the semiconductor substrate between them. The GaAs substrate beneath the nanoparticles is protected, with the nanoparticles acting as a mask. This is similar to the colloidal lithography method for creating semiconductor nanostructures using silica (SiO2) or polystyrene (PS) spheres, which has the drawbacks described earlier in the Background section. In this preferred embodiment, argon (Ar) is used as the plasma gas, producing a purely physical etching of the nanoparticle-substrate assembly (Step 2). However, other gases could also be used, such as noble gases (He), diatomic molecules (O2, Cl2, H2...), hydrocarbons (CH4, C2H6...), chlorinated and / or fluorinated compounds (CHF3, SiCk, CCk, SFe, BOH, CF2Cl2...) or a combination thereof, although a new calibration of the etching process would be necessary for each gas. The etching process was carried out at a working pressure of 66.66 mbar, under an Ar flow of 30 cm. 3Standard per minute, applying a radio frequency (RF) power of 220 W and an inductively coupled pulse (ICP) power of 100 W. After a certain time and once all the metallic nanoparticles have been removed, three-dimensional semiconductor nanostructures are obtained. The technical characteristics of stage 3 have been demonstrated by TEM characterization, as shown in Figure 2b). The nanostructures exhibit a conical shape in cross-section with an aspect ratio (height / width) of 0.77 ± 0.05 and radii less than 30 nm. Crystallographic analysis (Figure 2b2) using FFT imaging shows that they are monocrystalline, exhibiting coherence with the GaAs substrate. The compositional characterization by EDX is presented in Figure 3b), where it can be observed that the resulting nanostructures are composed of GaAs with no metallic Ga present within them.

[0045] A characteristic property of this method, and of any other ICP-RIE etching, is the control over the etching rate of the materials present, a factor that determines the size and shape of the final semiconductor nanostructures obtained. Thus, physical etching with Ar by RIE-ICP does not produce a significant etching of PS or SiU2 (nano)particles in colloidal lithography, which in most cases necessitates an additional procedure to remove the excess mask material (see, for example, patent documents CN105957801 A, TW201922901 A, and WO2016 / 205610A1). In the preferred embodiment of this invention, this procedure is not necessary because Ga is a mask with some reactivity to Ar plasma. Figure 4 shows the calibration of the Ar plasma attack rate on GaAs substrates for the RIE-ICP conditions that give rise to the semiconductor nanostructures of Figure 2 b) and 3 b).This calibration was performed by etching at different times. For this purpose, resin was deposited using photolithography with a thickness greater than 2.5 pm, leaving an area of ​​the GaAs substrate unetched. Both areas were etched, and the remaining resin was removed with acetone. The resulting step between the unetched area beneath the resin and the etched area of ​​GaAs was measured using atomic force microscopy (AFM) for the different etching times. According to the calibration in Figure 4 for the etching conditions described above, an etching rate of 0.69 ± 0.02 nm / s was obtained. This figure also includes the etching rate on the Ga nanoparticles obtained from TEM images for two intermediate times before the complete removal of the metallic Ga nanoparticles deposited on the GaAs in Figure 2a).According to these data, the attack rate of the Ar plasma on the GaAs substrate is higher than on the metallic nanoparticles. This selectivity between GaAs and Ga results in an increased aspect ratio between the Ga nanoparticles and the conical GaAs nanostructures. It is important to emphasize the need to perform this calibration if the material used in the substrate or in the nanoparticles differs from that of this preferred embodiment, or if the RIE etching process conditions differ from those employed in this invention.

[0046] A direct consequence of the higher attack rate of the ICP-RIE process on GaAs surfaces compared to Ga nanoparticles is the ability to control the surface coverage percentage. Ga nanoparticles cover approximately 50% of the total surface area on most substrates where they are physically deposited. This percentage depends on the diffusion of Ga on the respective surface, which determines the coalescence, size, and final coverage percentage of the nanoparticles. In the preferred embodiment of this invention, they cover 40% on flat GaAs substrates, as shown in the top view of the SEM image in Figure 5a). However, after ICP-RIE etching (Figure 5b), this percentage is reduced to 13% after the Ar plasma etching process, which results in the semiconductor nanostructures shown in Figures 2 and 3.

[0047] It is worth noting that both the shape of the resulting semiconductor nanostructures and their total coating percentage can be adjusted by modifying the RIE-ICP physical etching conditions. Parameters such as ICP and / or RF power, chamber pressure, or a higher gas flow rate can increase the selectivity for etching one of the materials present. This versatility can be very interesting from a design perspective in the search for new applications of these nanostructures.

[0048] In addition to the method's flexibility in obtaining different shapes in the semiconductor nanostructure, it is important to highlight the possibility of obtaining a wide range of sizes. As an example, Figure 6 illustrates the application of the method to obtain semiconductor nanostructures larger than those shown in Figures 2 and 3. This is achieved by depositing hemispherical Ga nanoparticles with radii greater than 250 nm (Figure 6a)) simply by evaporating a larger quantity of material. Subsequently, RIE-ICP etching is carried out under the conditions described previously, resulting in larger GaAs semiconductor nanostructures (Figure 6b)) while maintaining the same technical characteristics mentioned above.

[0049] INDUSTRIAL APPLICATION

[0050] The method reported in this invention is applicable in industrial sectors where semiconductor nanostructures are used. Some of these are briefly described below.

[0051] One of the applications where semiconductors are most integrated is in the manufacture of solar cells for photovoltaic energy generation. In this sector, semiconductors are essential and can play different roles depending on their position within the cell. For example, if the semiconductor is located inside the solar cell structure, it can act as a photon-absorbing material or active layer. The form in which the semiconductor is presented depends on the technology used. In this regard, in first- and second-generation solar cells, semiconductors were used in the form of a thin film. However, in third- and fourth-generation solar cells, nanostructures, such as semiconductor quantum dots, are included in the active layers and can be manufactured using the method of this invention.

[0052] At the same time, semiconductors are also used in the top layer of solar cells to reduce the reflection of sunlight on the surface. These optical losses have been addressed technologically and historically by incorporating an antireflective coating (ARC) with a refractive index intermediate between that of the solar cell's top material and that of air. In commercial solar cells, it is typical to use a combination of several layers of dielectric materials such as TiOx, Al₂O₃, MgF₂, ZnS, or SiO₂. However, depositing these materials in multilayers typically requires expensive techniques such as atomic-phase deposition or sputtering.Despite the great effort made by the scientific community in the design of multilayer ARCs, solar cells with these ARCs still do not sufficiently reduce the reflection of light on their surface to produce the short-circuit current expected by the theoretical Shockley-Queisser limit, achieving increases of 30% at best.

[0053] In the last decade, the use of nanostructures for ARCs has gained significant importance for better coupling light to solar cells. The concept is based on two effects. The first is that when a nanostructure is placed near the interface between two dielectrics, light is preferentially scattered by the dielectric with the higher permittivity through Rayleigh scattering. The scattered light then acquires a scattering angle that increases the optical path length, thus improving the amount of light captured and the efficiency of the solar cell. The second effect is the grading of the refractive index. Each nanostructure can be treated vertically as a multilayered partition using the effective medium approximation. Due to the shape of the nanostructure, each layer will have a different amount of material and therefore a different effective refractive index.This gradual refractive index profile, unlike the abrupt profile of thin layers, prevents excessive light reflection at the surface (WO2019 / 075215A1). Among gradual refractive index profiles, those obtained by conical nanostructures are particularly desirable compared to more spherical or truncated shapes, which are those obtained in this invention.

[0054] To date, only two nanostructure-based systems have yielded solar cell current enhancements comparable to those obtained with multilayers: TiO2 and Al nanostructures, achieving a 26% increase (“Efficiency improvement of III–V GaAs solar cells using biomimetic TiO2 subwavelength structures with wide-angle and broadband antireflection properties,” Solar Energy Materials and Solar Cells, 127, 43–49 (2014)) and a 22% increase (“Loss mitigation in plasmonic solar cells: aluminum nanoparticles for broadband photocurrent enhancements in GaAs photodiodes,” Scientific Reports, 3, 2874 (2013)), respectively. Unfortunately, both scenarios require complex lithography-based manufacturing processes. Therefore, while the use of nanostructures is promising, they must simplify current multilayer deposition methods.In this sense, this invention could meet the necessary requirements of simplicity and effectiveness while also not significantly increasing the cost.

[0055] Another potential application for this invention lies in the field of sensors. In recent decades, the capacity of semiconductor nanostructures for the development of environmental detection devices or sensors has been demonstrated. Simple contact of nanostructures with the atmosphere produces significant changes in the physical properties of their surface. A strong correlation has been found between external environmental conditions and the optical properties of surface quantum dots of III-V materials, which have been attributed to confined surface states. Luminescence intensity decreases under high vacuum and dry environments, while it remains constant in atmospheres containing water vapor. It has been suggested that certain characteristics of the molecules in the environment, such as molecular weight, polarity, and size, among others, could be responsible for similar effects.In this sense, this correlation has been demonstrated in the electrical properties of surface quantum dots of III-V materials, to manufacture humidity sensors from the measurement of conductivity in quantum dots of III-V materials, achieving high sensitivity.

[0056] Finally, it is important to highlight the significance of semiconductor nanostructures in light-emitting devices, including diodes, lasers, and single-photon emitters. Semiconductor nanostructures, and quantum dots in particular, have the ability to tune their emission energy from the ultraviolet to the near-infrared by varying the size and composition of the semiconductor material and / or its impurities or dopants. This aspect is particularly interesting for their application in classical communications with continuous light through optical fibers or in quantum communications with single-photon emitters. Both approaches require nanometric heterostructures typically composed of elements from the same family (III-V, for example), such that the active (emitting) semiconductor layer is covered on both sides by another semiconductor material with a higher band gap energy.Thus, the carriers in the active layer will be confined, increasing the probability of recombination and, consequently, photon emission. The method reported in this invention makes the fabrication of this type of semiconductor heterostructure viable. Heterostructures of similar size to those obtained in Figures 2, 3, and 5 could be obtained if the initial step 1 (semiconductor surface) consists of suitable two-dimensional thin layers. Especially important for this application is the versatility of this method, which allows for modification of both the shape / size of the resulting semiconductor nanostructures and the total surface coverage percentage by altering the conditions of the RIE physical etching process.

Claims

CLAIMS 1. A process for producing three-dimensional semiconductor nanoparticles, comprising the following steps: a) providing a substrate comprising a semiconductor material; b) depositing a metal with a sufficiently low surface tension to form self-assembled metallic nanoparticles when said metal is deposited onto the substrate by physical deposition techniques, obtaining a substrate at least partially coated with self-assembled metallic nanoparticles; and c) attack the substrate coated at least partially with metallic nanoparticles using Reactive Ion Etching (RIE) techniques, obtaining three-dimensional semiconductor nanoparticles deposited on the substrate.

2. The process of claim 1, wherein the semiconductor substrate material of step a) is GaAs.

3. The process of claim 1 or 2, wherein the metal in step b) is selected from gallium, indium and bismuth, alone or in any combination thereof.

4. The process of any of claims 1 to 3 above, wherein the physical deposition technique used in step b) is selected from thermal evaporation techniques, either by Joule effect or with electron gun, Metal-Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE).

5. The process of claim 4, wherein the physical deposition technique is thermal evaporation by Joule effect.

6. The process of claim 5 wherein Ga is used as a semiconductor metal and GaAs as a substrate, and the deposition is carried out in a chamber from vacuum to a pressure of 1.5-10' 5mbar, applying 50 W to a tungsten filament, which causes the Ga to evaporate, which is then deposited onto the GaAs substrate.

7. The process of claim 6 wherein, after step b), when the self-assembled metallic nanoparticles are exposed to air, a 2-3 nanometer amorphous Ga oxide (GaxOy) crust is formed on them.

8. The process of any of the preceding claims, wherein the self-assembled metallic nanoparticles cover between 40% and 50% of the substrate surface.

9. The process of any of the preceding claims, wherein the Reactive Ion Etching (RIE) technique of step c) is Inductively Coupled Plasma Reactive Ion Etching (RIE-ICP).

10. The process of claim 9, wherein the reactive ion plasma is a plasma of noble gases, diatomic molecules, hydrocarbons, chlorinated and / or fluorinated compounds, or a combination thereof.

11. The process of claim 10, wherein the reactive ion plasma is an Ar plasma.

12. The process of any of claims 9-11 above, wherein the ICP-RIE reactive ion plasma attacks both the self-assembled metallic nanoparticles and the uncoated semiconductor substrate between nanoparticles.

13. The method of any of claims 9-12 above wherein the ICP-RIE attack is carried out under an Ar flux of 30 cm 3 standard per minute, at a pressure of 66.66 mbar, applying a radiofrequency power of 220 W and an ICP power of 100 W.

14. The process of any of claims 9-13 above, wherein both the shape of the resulting semiconductor nanoparticles and the percentage of substrate coverage thereof are regulated by modifying the parameters of the ICP-RIE etching such as the ICP and / or RF power, the pressure in the chamber, or the flow of introduced gas.

15. The process of any of the preceding claims, wherein the size of the resulting semiconductor nanoparticles is regulated by adjusting the amount of metal that is evaporated.

16. Self-assembled metallic nanoparticles obtained from step b) of the procedure of any of claims 1 to 15 above.

17. Self-assembled metallic nanoparticles according to claim 16, having a height / width aspect ratio of approximately 0.

44.

18. Self-assembled metallic nanoparticles according to claim 16 or 17, which are hemispherical and have a radius between 10 and 500 nm.

19. Three-dimensional semiconductor nanoparticles obtained according to the procedure of any of claims 1 to 15 above.

20. Three-dimensional semiconductor nanoparticles according to claim 19, having an approximately conical shape.

21. Three-dimensional semiconductor nanoparticles according to claims 19 or 20, having a size between 10 and 500 nm.

22. Three-dimensional semiconductor nanoparticles according to any of claims 19 to 21 having a height / width aspect ratio of 0.77 and a radius less than 30 nm.

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