Photodetector and electronic equipment

Abstract

In an embodiment, this photodetector (1) comprises: a light reception unit (13) that generates carriers through photoelectric conversion; and a multiplication unit (14) that increases the carriers generated by the light reception unit (13) by avalanche multiplication. The multiplication unit (14) has a plurality of multiplication regions for increasing the carriers, and the plurality of multiplication regions are provided at opposing positions.

Description

Optical Detection Device and Electronic Device

[0001] The present disclosure relates to an optical detection device and an electronic device.

[0002] An optical detection device using an avalanche photodiode has been developed (see, for example, Patent Document 1). In this optical detection device, there is a rapid change in potential in an avalanche multiplication region such as a PN junction, and a strong electric field of about 50 V / μm is generated. In the avalanche multiplication region, when the generated electrons reach the multiplication operation (for example, Geiger mode), the electrons are counted by the detection circuit.

[0003] Japanese Patent Application Laid-Open No. 2022-186423

[0004] However, the probability that the generated electrons reach the multiplication operation (for example, Geiger mode), that is, the multiplication probability may be low. Therefore, an improvement in the multiplication probability is required.

[0005] Therefore, the present disclosure provides an optical detection device and an electronic device capable of improving the multiplication probability.

[0006] The optical detection device according to an embodiment includes a light receiving unit that generates carriers by photoelectric conversion, and a multiplication unit that multiplies the carriers generated by the light receiving unit by avalanche multiplication. The multiplication unit has a plurality of multiplication regions for multiplying the carriers, and the plurality of multiplication regions are provided at opposing positions.

[0007] The electronic device according to an embodiment includes an optical detection device. The optical detection device includes a light receiving unit that generates carriers by photoelectric conversion, and a multiplication unit that multiplies the carriers generated by the light receiving unit by avalanche multiplication. The multiplication unit has a plurality of multiplication regions for multiplying the carriers, and the plurality of multiplication regions are provided at opposing positions.

[0008] This is a diagram showing an example configuration of a photodetector according to the first embodiment. This is a diagram showing an example configuration of a unit pixel according to the first embodiment. This is a cross-sectional view showing a partial configuration example of a photodetector according to the first embodiment. This is a plan view showing a partial surface of a semiconductor substrate according to the first embodiment. This is a cross-sectional view showing a partial configuration example of a semiconductor substrate according to the first embodiment. This is a graph showing the potential and electric field strength of the multiplication unit according to the first embodiment. This is a plan view showing a partial surface of a semiconductor substrate according to the second embodiment. This is a cross-sectional view showing a partial configuration example of a semiconductor substrate according to the second embodiment. This is a graph showing the potential and electric field strength of the multiplication unit according to the second embodiment. This is a diagram for explaining the multiplication operation of the multiplication unit according to the second embodiment. This is a graph for explaining the multiplication operation of the multiplication unit according to the second embodiment. This is a cross-sectional view showing a partial configuration example of a semiconductor substrate of a comparative example according to the second embodiment. This is a diagram for explaining the multiplication operation of the multiplication unit of a comparative example according to the second embodiment. This is a graph showing the potential and electric field strength of the multiplication unit of a comparative example according to the second embodiment. This is a cross-sectional view showing a partial configuration example of a semiconductor substrate of modified example 1 according to the second embodiment. This is a cross-sectional view showing an example of anode wiring configuration of modified example 1 according to the second embodiment. This is a cross-sectional view showing a partial configuration example of a semiconductor substrate of modified example 2 according to the second embodiment. This is a graph showing the potential and electric field strength of the amplification section of modified example 2 according to the second embodiment. This is a cross-sectional view showing a partial configuration example of the semiconductor substrate of modified example 3 according to the second embodiment. This is a cross-sectional view showing a partial configuration example of the semiconductor substrate of modified example 4 according to the second embodiment. This is a cross-sectional view showing a partial configuration example of the semiconductor substrate of modified example 5 according to the second embodiment. This is a cross-sectional view showing a partial configuration example of the semiconductor substrate of modified example 6 according to the second embodiment. This is a cross-sectional view showing a partial configuration example of the semiconductor substrate of modified example 7 according to the second embodiment. This is a cross-sectional view showing a partial configuration example of the semiconductor substrate of modified example 8 according to the second embodiment. This is a plan view showing a partial surface of the semiconductor substrate of modified example 9 according to the second embodiment. This is a cross-sectional view showing a partial configuration example of the semiconductor substrate of modified example 9 according to the second embodiment. This is a diagram showing an application example of the photodetector according to the above-described embodiment. This is a diagram showing an example of the configuration of the imaging device according to the application example. This is a diagram showing an example of the configuration of the distance measuring device according to the application example.

[0009] Embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments include examples and modifications. However, the technology relating to this disclosure is not limited by the embodiments. In addition, in the following embodiments, the same reference numerals are used for essentially the same parts to omit redundant explanations.

[0010] This disclosure will be described in the following order of items: 1. First Embodiment 1-1. Example of the configuration of the light detection device 1-2. Example of a part of the configuration of the light detection device 2. Second Embodiment 2-1. Example of a part of the configuration of the light detection device 2-2. Comparative example 2-3. Modification 3. Operation and effect of each embodiment 4. Other embodiments 5. Application examples 5-1. Various devices 5-2. Imaging device 5-3. Distancing device 6. Notes

[0011] <1. First Embodiment> <1-1. Example of Light Detection Device Configuration> An example of the configuration of the light detection device 1 according to the first embodiment will be described with reference to Figures 1 and 2. Figure 1 is a diagram showing an example of the configuration of the light detection device 1 according to the first embodiment. Figure 2 is a diagram showing an example of the configuration of the unit pixel 101 according to the first embodiment.

[0012] As shown in Figure 1, the light detection device 1 according to the first embodiment includes a pixel array section 100 and a bias voltage application section 110. This light detection device 1 can be applied to, for example, a distance image sensor that measures distance using the Time-of-Flight (ToF) method, or an image sensor that captures images. In the example shown in Figure 1, the bias voltage application section 110 is located around the pixel array section 100 in a plan view, but this is not limited to that. For example, the bias voltage application section 110 may be stacked on top of the pixel array section 100.

[0013] The pixel array section 100 has a plurality of unit pixels 101. These unit pixels 101 are arranged in an array, for example, in the row and column directions. The unit pixels 101 are formed, for example, in a polygonal or circular shape in a plan view. Note that a single unit pixel 101 may be used as one pixel, or a plurality of unit pixels 101 may be used as a single pixel.

[0014] The bias voltage application unit 110 applies a bias voltage to each unit pixel 101 of the pixel array unit 100. In the first embodiment, the case in which electrons are read out as signal charges (carriers) will be described.

[0015] As shown in Figure 2, the unit pixel 101 comprises a light-receiving element 12, a quenching resistor element 120, and an inverter 130. For example, a p-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used as the quenching resistor element 120. For example, a complementary type MOSFET is used as the inverter 130.

[0016] The light-receiving element 12 converts incident light into an electrical signal by photoelectric conversion and outputs it. For example, the light-receiving element 12 converts incident light (photons: hv) into an electrical signal by photoelectric conversion and outputs a pulse corresponding to the incident photon. As the light-receiving element 12, for example, a photoelectric conversion element such as a SPAD (Single Photon Avalanche Diode) element is used. A SPAD element has the characteristic that, for example, electrons or holes generated in response to the incident of one photon increase by avalanche multiplication, and a large current flows. In the light-receiving element 12, for example, the anode is connected to the bias voltage application unit 110 and the cathode is connected to the source terminal of the quenching resistor element 120. A bias voltage is applied to the anode of the light-receiving element 12 from the bias voltage application unit 110.

[0017] The quenching resistor element 120 is connected in series with the photodetector element 12, with its source terminal connected to the cathode of the photodetector element 12 and its drain terminal connected to a power supply (not shown). An excitation voltage V is supplied from the power supply to the drain terminal of the quenching resistor element 120. Ｅ A voltage is applied. The quenching resistor element 120 receives a negative voltage V due to the voltage generated by electrons avalanche multiplied by the light-receiving element 12. ＢＤ When it reaches this point, the photodetector 12 emits electrons that have been multiplied, and recharges the voltage back to its initial voltage.

[0018] The inverter 130 is connected to the photodetector 12 and the quenching resistor 120. Its input terminal is connected to the cathode of the photodetector 12 and the source terminal of the quenching resistor 120, and its output terminal is connected to a subsequent arithmetic processing unit (not shown). The inverter 130 outputs a photodetection signal based on the carriers (signal charges) multiplied by the photodetector 12. More specifically, the inverter 130 shapes the voltage generated by the electrons multiplied by the photodetector 12. The inverter 130 then outputs a photodetection signal (APD OUT) to the arithmetic processing unit, starting from the arrival time of one photon, generating, for example, the pulse waveform shown in Figure 2.

[0019] For example, the arithmetic processing unit calculates the distance to the subject based on the timing of the pulse indicating the arrival time of one photon in each received light signal, and calculates the distance for each unit pixel 101. Then, based on these distances, a distance image is generated in which the distances to the subject detected by multiple unit pixels 101 are arranged in a planar manner. The arithmetic processing unit may also have, for example, a histogram generation unit that generates a histogram representing the time spectrum.

[0020] <1-2. Partial Configuration Example of the Photodetector> Partial configuration examples of the photodetector 1 according to the first embodiment will be described with reference to Figures 3 to 6. Figure 3 is a cross-sectional view showing a partial configuration example of the photodetector 1 according to the first embodiment. Figure 4 is a plan view showing a part of the surface of the semiconductor substrate 11 according to the first embodiment. Figure 5 is a cross-sectional view (cross-sectional view along line A1-A1 in Figure 4) showing a partial configuration example of the semiconductor substrate 11 according to the first embodiment.

[0021] As shown in Figure 3, the photodetector 1 has a sensor substrate 10 and a logic substrate 20. For example, the logic substrate 20 is laminated on the front side of the sensor substrate 10 (for example, the first surface 11S1 side, which is the front surface of the semiconductor substrate 11 that constitutes the sensor substrate 10). The photodetector 1 is a back-illuminated type photodetector that receives light from the back side of the sensor substrate 10 (for example, the second surface 11S2, which is the back surface of the semiconductor substrate 11 that constitutes the sensor substrate 10).

[0022] The light detection device 1 has a light-receiving element 12 for each unit pixel 101. The light-receiving element 12 includes a light-receiving section 13 and a multiplier section 14. The light-receiving section 13 and the multiplier section 14 are, for example, embedded in a semiconductor substrate 11. The semiconductor substrate 11 is also provided with a pixel separation section 17. The pixel separation section 17 is provided around the unit pixel 101 so as to extend between the first surface 11S1 and the second surface 11S2 of the semiconductor substrate 11, and electrically separates adjacent unit pixels 101.

[0023] As shown in Figures 4 and 5, each of the multiple unit pixels 101 is independently provided with multiple anode electrodes 15 and multiple cathode electrodes 16. In the example in Figure 4, each unit pixel 101 is formed in a rectangular shape in plan view, and each unit pixel 101 is provided with six anode electrodes 15 and two cathode electrodes 16. Each anode electrode 15 and each cathode electrode 16 are arranged, for example, on the outer periphery of the unit pixel 101. Specifically, three anode electrodes 15 are provided on two sides of the outer periphery of the unit pixel 101. One cathode electrode 16 is provided on two sides of the outer periphery of the unit pixel 101.

[0024] The pixel separation section 17 electrically separates adjacent unit pixels 101 and is provided, for example, to surround each of a plurality of unit pixels 101 in a plan view. Specifically, it is provided to surround the periphery of a unit pixel 101 having a rectangular shape. The pixel separation section 17 extends between the first surface 11S1 and the second surface 11S2 of the semiconductor substrate 11 and penetrates the semiconductor substrate 11, for example. The pixel separation section 17 is formed using an insulating film, for example, a silicon oxide (SiOx) film. The pixel separation section 17 may also have, for example, a light-shielding film. In this case, optical crosstalk can be suppressed. The light-shielding film is provided, for example, inside the pixel separation section 17. As an example, a metal material is embedded inside the pixel separation section 17 and the light-shielding film is formed inside the pixel separation section 17.

[0025] Each anode electrode 15 and each cathode electrode 16 are provided, for example, on the first surface 11S1 side of the semiconductor substrate 11. Specifically, each anode electrode 15 and each cathode electrode 16 are formed by being embedded in the first surface 11S1 of the semiconductor substrate 11. Also, for example, each anode electrode 15 is electrically connected to the light receiving unit 13, and the cathode electrode 16 is electrically connected to each anode electrode 15 and the multiplier unit 14. The anode electrode 15 is an example of a first electrode, and the cathode electrode 16 is an example of a second electrode.

[0026] In Figure 5, the symbols "p" and "n" represent the p-type semiconductor region and the n-type semiconductor region, respectively. For example, the "+" or "-" at the end of "p" both represent the impurity concentration in the p-type semiconductor region. Similarly, the "+" or "-" at the end of "n" both represent the impurity concentration in the n-type semiconductor region. Here, a larger number of "+" signs indicates a higher impurity concentration, and a larger number of "-" signs indicates a lower impurity concentration. This is also true for the other figures.

[0027] As shown in Figures 3 to 5, the sensor substrate 10 includes a semiconductor substrate 11. The semiconductor substrate 11 is made of, for example, a silicon substrate. This semiconductor substrate 11 has a first surface 11S1 and a second surface 11S2 that face each other. For each unit pixel 101, the semiconductor substrate 11 is provided with a semiconductor region 112 including, for example, an n-type semiconductor region (n-) 111 whose impurity concentration is controlled to be n-type. The semiconductor region 112 constitutes the light-receiving section 13. In addition, a p-type semiconductor region (p) 14X1, an n-type semiconductor region (n+) 14Y, and a p-type semiconductor region (p) 14X2 are provided on the first surface 11S1 side of the semiconductor substrate 11. The p-type semiconductor region 14X1, the n-type semiconductor region 14Y, and the p-type semiconductor region 14X2 constitute the multiplication section 14.

[0028] The p-type semiconductor region 14X1 is formed to extend, for example, in a planar direction (X-axis and Y-axis direction) to contact the side surface of the pixel separation portion 17, and to extend along that side surface toward the second surface 11S2 of the semiconductor substrate 11 in the stacking direction (Z-axis direction). Similarly, the p-type semiconductor region 14X2 is also formed to extend, for example, in a planar direction (X-axis and Y-axis direction) to contact the side surface of the pixel separation portion 17, and to extend along that side surface toward the second surface 11S2 of the semiconductor substrate 11 in the stacking direction (Z-axis direction). Furthermore, parts of both the p-type semiconductor region 14X1 and the p-type semiconductor region 14X2 are integrated directly below the n-type semiconductor region (n+) 14Y and extend toward the second surface 11S2 of the semiconductor substrate 11 to the central part of the semiconductor region 112. For example, the semiconductor region 112 is surrounded by a p-type semiconductor region 14X1 and a p-type semiconductor region 14X2, and the n-type semiconductor region 111 is separated by the aforementioned extension formed by the p-type semiconductor region 14X1 and the p-type semiconductor region 14X2.

[0029] The light-receiving element 12 is composed of a light-receiving section 13 and a multiplication section 14. This light-receiving element 12 is a SPAD element that can increase the electrons or holes generated by the incidence of one photon by avalanche multiplication, for example, by applying a positive voltage to the cathode electrode 16 and a negative voltage to the anode electrode 15.

[0030] The light-receiving unit 13 is a photoelectric conversion unit that absorbs light incident from the second surface 11S2 side of the semiconductor substrate 11 and generates carriers according to the amount of light received. The light-receiving unit 13 is configured to include an n-type semiconductor region 111 in which the impurity concentration is controlled to be n-type. The carriers (electrons) generated in the light-receiving unit 13 are transferred to the multiplier unit 14 by a potential gradient.

[0031] The multiplication unit 14 increases the carriers (in this case, electrons) generated in the light-receiving unit 13 by avalanche multiplication. The multiplication unit 14 is composed of, for example, a p-type semiconductor region 14X1, an n-type semiconductor region 14Y, and a p-type semiconductor region 14X2. Specifically, the p-type semiconductor region 14X1, the n-type semiconductor region 14Y, and the p-type semiconductor region 14X2 are arranged in the planar direction X-axis, forming a PNP junction. This multiplication unit 14 includes a plurality of multiplication regions, for example, two multiplication regions 14a and 14b (see Figure 5). These multiplication regions 14a and 14b are separated by a predetermined distance and face each other. Each of the multiplication regions 14a and 14b is an avalanche multiplication region (avalanche unit) that increases carriers by avalanche multiplication due to a high electric field region.

[0032] Here, the p-type semiconductor region 14X1 is an example of a first semiconductor region, the n-type semiconductor region 14Y is an example of a second semiconductor region, and the p-type semiconductor region 14X2 is an example of a third semiconductor region. The p-type is an example of a first conductivity type, and the n-type is an example of a second conductivity type.

[0033] In the photodetector 12, the junction between the p-type semiconductor region 14X1 and the n-type semiconductor region 14Y functions as a multiplication region 14a, and the junction between the p-type semiconductor region 14X2 and the n-type semiconductor region 14Y functions as a multiplication region 14b. Each of the multiplication regions 14a and 14b includes a high-electric-field region (depletion layer) formed at the interface of the junction by a large negative voltage applied to the cathode. In each of the multiplication regions 14a and 14b, the electrons (e-) generated by one photon incident on the photodetector 12 increase due to avalanche multiplication.

[0034] The photodetector 12 has an anode electrode 15 and a cathode electrode 16. The anode electrode 15 is composed of a p-type semiconductor region (p++). This p-type semiconductor region (p++) is electrically connected to the n-type semiconductor region 111 via a p-type semiconductor region 14X1 (or p-type semiconductor region 14X1). The cathode electrode 16 is composed of an n-type semiconductor region (n++). This n-type semiconductor region (n++) is electrically connected to the n-type semiconductor region 14Y. Each anode electrode 15 is connected to, for example, an anode wiring. Each cathode electrode 16 is electrically connected to, for example, a circuit such as a quenching resistor element 120 or an inverter 130.

[0035] As shown in Figure 3, a multilayer wiring layer 19 is provided on the first surface 11S1 side of the semiconductor substrate 11. In the multilayer wiring layer 19, a wiring layer 192 consisting of one or more wirings is formed within the interlayer insulating layer 193. The wiring layer 192 is used, for example, to supply a voltage to be applied to the semiconductor substrate 11 or the photodetector 12, or to extract carriers generated in the photodetector 12. Some of the wiring in the wiring layer 192 is electrically connected to an anode electrode 15, a cathode electrode 16, etc. Multiple pad electrodes 194 are embedded on the surface of the interlayer insulating layer 193 opposite to the semiconductor substrate 11 side (the surface 19S1 of the multilayer wiring layer 19). The multiple pad electrodes 194 are electrically connected to some of the wiring in the wiring layer 192 via vias V1 and V2. Note that a wiring layer that electrically connects each anode electrode 15 to each other may also be provided within the multilayer wiring layer 19.

[0036] The wiring layer 192 is formed using, for example, aluminum (Al), copper (Cu), or tungsten (W). The interlayer insulating layer 193 is composed of a single layer film made of one of the following: silicon oxide (SiOx), TEOS, silicon nitride (SiNx), and silicon oxynitride (SiOxNy), or a multilayer film made of two or more of these. The pad electrode 194 is exposed on the bonding surface with the logic substrate 20 (the surface 19S1 of the multilayer wiring layer 19) and is used, for example, for connection with the logic substrate 20. The pad electrode 194 is formed using, for example, copper (Cu). In the example shown in Figure 3, a wiring layer 192 is formed within the multilayer wiring layer 19, but the total number of wiring layers within the multilayer wiring layer 19 is not limited.

[0037] The logic board 20 includes, for example, a semiconductor substrate 21 made of a silicon substrate and a multilayer wiring layer 22. The logic board 20 is provided with logic circuits including a bias voltage application unit 110, a readout circuit that outputs a pixel signal based on the charge output from the unit pixel 101 of the pixel array unit 100, a vertical drive circuit, a column signal processing circuit, a horizontal drive circuit, and an output circuit.

[0038] The multilayer wiring layer 22 is constructed by stacking, for example, the gate wiring 221 of a transistor constituting a readout circuit and each wiring layer 222, 223, 224, 225, which contains one or more wirings, in order from the semiconductor substrate 21 side (for example, the first surface 21S1 side of the semiconductor substrate 21), with an interlayer insulating layer 226 in between. Multiple pad electrodes 227 are embedded in the surface of the interlayer insulating layer 226 opposite to the semiconductor substrate 21 side (the surface 22S1 of the multilayer wiring layer 22). The multiple pad electrodes 227 are electrically connected to some of the wirings of the wiring layer 225 via vias V3.

[0039] The interlayer insulating layer 117, like the interlayer insulating layer 193, is composed of a single layer film made of one of the following materials: silicon oxide (SiOx), TEOS, silicon nitride (SiNx), and silicon oxynitride (SiOxNy), or a laminated layer made of two or more of these materials. The gate wiring 221 and each wiring layer 222, 223, 224, 225, and 228 are formed using materials such as aluminum (Al), copper (Cu), or tungsten (W), similar to each wiring layer 192 and 195.

[0040] The pad electrode 227 is exposed on the bonding surface with the sensor substrate 10 (the surface 22S1 of the multilayer wiring layer 22) and is used, for example, for connection with the sensor substrate 10. The pad electrode 227, like the pad electrode 194, is formed using, for example, copper (Cu). In the photodetector 1, a CuCu junction is made between the pad electrode 194 and the pad electrode 227. As a result, the cathode of the photodetector 12 is electrically connected to the quenching resistor element 120 provided on the logic substrate 20 side, and the anode of the photodetector 12 is electrically connected to the bias voltage application unit 110.

[0041] On the light-receiving surface (second surface 11S2) side of the semiconductor substrate 11, an on-chip lens 33 is provided, for example, for each unit pixel 101 via a protective layer 31 and a color filter 32. The on-chip lens 33 focuses light incident from above onto the light-receiving element 12 and is formed using, for example, silicon oxide (SiOx).

[0042] Figure 6 is a graph showing the potential and electric field strength of the multiplier unit 14 according to the first embodiment. In the example of Figure 6, the vertical axis represents the potential or electric field strength, the horizontal axis represents the position in the -Z direction (position in the Z-axis direction), and the potential waveform (potential distribution) P1 and the electric field strength waveform (electric field strength distribution) E1 are shown. The potential waveform P1 is the waveform of the potential on which electrons, which are carriers, move. The position in the -Z direction is the position from the first surface 11S1 of the semiconductor substrate 11 (depth from the surface). This is the same for other graphs as well.

[0043] As shown in FIG. 6, electrons swing through the potential waveform P1 (for example, the trough portion of the potential waveform P1) and are finally emitted from the cathode electrode 16 (details will be described later). From the electric field strength waveform E1, it can be seen that there is a strong electric field with an electric field strength of 50 V / μm. That is, since there are two multiplication regions 14a and 14b, only the multiplication probability of electrons (for example, the ignition probability) increases. For example, the multiplication probability is about 100% - (40% × 40% × √2 (for the establishment of only electrons)) = 80%.

[0044] The multiplication section 14 is formed in a shape having at least one trough in the potential shape, like the aforementioned potential waveform P1. That is, each multiplication region (each avalanche section) 14a and 14b is provided so as to have a potential shape having at least one trough. Note that the number of troughs is not limited.

[0045] Thus, according to the photodetector 1, for example, P / N / P (p-type semiconductor region 14X1, n-type semiconductor region 14Y, and p-type semiconductor region 14X2) is arranged in the Si of the semiconductor substrate 11, and two PN junctions are formed, thereby forming two multiplication regions 14a and 14b. As a result, the region related to avalanche multiplication increases, so that an improvement in the multiplication probability can be realized.

[0046] <2. Second Embodiment> <2-1. Configuration Example of a Part of the Photodetector> A configuration example of a part of the photodetector 1 according to the second embodiment will be described with reference to FIGS. 7 to 11. FIG. 7 is a plan view showing a part of the surface of the semiconductor substrate 11 according to the second embodiment. FIG. 8 is a cross-sectional view (a cross-sectional view taken along line A2-A2 in FIG. 7) showing a configuration example of a part of the semiconductor substrate 11 according to the second embodiment.

[0047] As shown in FIG. 7, in the second embodiment, a plurality of unit pixels 101 each have an octagonal shape. An anode electrode 15 and a cathode electrode 16 are provided for each of the unit pixels 101. In the example of FIG. 7, one anode electrode 15 and one cathode electrode 16 are provided for each unit pixel 101.

[0048] The anode electrode 15 is positioned approximately in the center of the unit pixel 101, and the cathode electrode 16 is positioned diagonally from the center of the unit pixel 101. Specifically, the anode electrode 15 is positioned approximately in the center of the octagonal unit pixel 101. The cathode electrode 16 is positioned in the gap between adjacent unit pixels 101 that are positioned diagonally (for example, at a 45° angle) due to the matrix arrangement of the octagonal unit pixels 101.

[0049] The pixel separation unit 17 is formed to surround the periphery of the octagonal unit pixel 101 (light receiving unit 13) in a plan view, and the cathode electrode 16 which is positioned in the gap between adjacent unit pixels 101 that are positioned at an oblique angle (for example, at a 45° angle) to the unit pixel 101.

[0050] For example, each cathode electrode 16 is positioned between adjacent anode electrodes 15 in a matrix of unit pixels 101 that are positioned diagonally (for example, at a 45° angle). Furthermore, each cathode electrode 16 is positioned such that the distance between adjacent diagonally positioned anode electrodes 15 is equal to the distance between adjacent diagonally positioned cathode electrodes 16. Also, each cathode electrode 16 is positioned such that the distance between adjacent anode electrodes 15 in the row direction (X-axis direction) and column direction (Y-axis direction) is equal to the distance between adjacent cathode electrodes 16 in the row direction (X-axis direction) and column direction (Y-axis direction).

[0051] As shown in Figure 8, the multiplication section 14 is constructed by stacking a p-type semiconductor region 14X1, an n-type semiconductor region 14Y, and a p-type semiconductor region 14X2. In the example in Figure 8, the p-type semiconductor region 14X1, the n-type semiconductor region 14Y, and the p-type semiconductor region 14X2 are stacked in the Z-axis direction from the first surface 11S1 side of the semiconductor substrate 11 in the order of p-type semiconductor region 14X1, n-type semiconductor region 14Y, and p-type semiconductor region 14X2. The two multiplication sections 14a and 14b are separated by a predetermined distance and face each other.

[0052] The n-type semiconductor region 14Y is formed to extend in the planar direction (X-axis and Y-axis direction), then contact the side surface of the pixel separation portion 17, and then extend along the side surface of the pixel separation portion 17 toward the first surface 11S1 of the semiconductor substrate 11 in the Z-axis direction, so as to contact the cathode electrode 16.

[0053] The p-type semiconductor region 14X1 and the p-type semiconductor region 14X2 are formed so as to be in contact with and sandwiching the n-type semiconductor region 14Y. For example, the p-type semiconductor region 14X1 and the p-type semiconductor region 14X2 are formed so as to be located on the same straight line as the anode electrode 15 (for example, on a straight line extending in the Z-axis direction).

[0054] The semiconductor region 112 includes a p-type semiconductor region 111A. The p-type semiconductor region 111A is formed to surround the p-type semiconductor regions 14X1 and 14X2 while in contact with them. For example, the side of the p-type semiconductor region 14X1 opposite to the n-type semiconductor region 14Y is in contact with the p-type semiconductor region 111A, and similarly, the side of the p-type semiconductor region 14X2 opposite to the n-type semiconductor region 14Y is in contact with the p-type semiconductor region 111A. Furthermore, the p-type semiconductor region 111A is formed to be in contact with the anode electrode 15. In other words, a part of the p-type semiconductor region 111A is provided between the anode electrode 15 and the p-type semiconductor region 14X1, and is in contact with the anode electrode 15 and the p-type semiconductor region 14X1. The p-type semiconductor region 111A is an example of a fourth semiconductor region.

[0055] Figure 9 is a graph showing the potential and electric field strength of the multiplier unit 14 according to the second embodiment. In the example of Figure 9, similar to Figure 6, the vertical axis represents the potential or electric field strength, the horizontal axis represents the position in the -Z direction (position in the Z-axis direction), and the potential waveform P2 and electric field strength waveform E2 are shown.

[0056] As shown in Figure 9, electrons, similar to those in Figure 6, swing along the potential waveform P2 (for example, the trough portion of the potential waveform P2) and are ultimately ejected from the cathode electrode 16 (details will be described later). In the example in Figure 9, the electric field strength waveform E2 shows that there are two strong electric fields with an electric field strength of 50 V / um. That is, since there are two multiplication regions 14a and 14b, the multiplication probability (for example, the firing probability) of electrons increases. For example, the multiplication probability increases to about 100% - (40% × 40% × √2 (for the probability of electrons only)) = 80%.

[0057] As described above, with the photodetector 1, for example, P / N / P (p-type semiconductor region 14X1, n-type semiconductor region 14Y, and p-type semiconductor region 14X2) are arranged in the Si of the semiconductor substrate 11, and two PN junctions are created, forming two multiplication regions 14a and 14b. As a result, the region involved in avalanche multiplication increases, and thus an improvement in multiplication probability can be achieved.

[0058] (Multiplication Operation) Figure 10 is a diagram illustrating the multiplication operation of the multiplication unit 14 according to the second embodiment. Figure 11 is a graph illustrating the multiplication operation of the multiplication unit 14 according to the second embodiment. In the example of Figure 11, as in Figure 6, the vertical axis represents potential or electric field strength, the horizontal axis represents position in the -Z direction (position in the Z-axis direction), and the potential waveform P3 and electric field strength waveform E3 are shown.

[0059] In the example in Figure 10, the left and center figures show cases where multiplication does not occur, while the right figure shows cases where multiplication occurs. In the left figure, the electron (e) initially generated by photoelectric conversion does not increase in the multiplication unit 14 (unignited). In the center figure, the first electron increases (ignited), but the next hole (h) does not increase (unignited). In the right figure, the electron and hole continue to multiply, and the operation reaches the Geiger mode.

[0060] As shown in Figures 10 and 11, initially the number of electrons does not increase (unfired), but because the electrons possess kinetic energy, they ascend the potential gradient on the first surface 11S1 side (surface side) of the semiconductor substrate 11 (see the left diagram in Figure 11). Once the electrons have ascended the potential gradient to a certain extent, their kinetic energy is converted into potential energy. Now, the electrons begin to move along the potential gradient and acquire kinetic energy. While this swinging motion is occurring, the electrons ignite probabilistically (see the right diagram in Figure 11). This increases the number of electron and hole pairs, leading to multiplication operations such as Geiger mode.

[0061] <2-2. Comparative Example> A partial configuration example of the photodetector (semiconductor substrate 11A) of the comparative example according to the second embodiment will be described with reference to Figures 12 to 14. Figure 12 is a cross-sectional view showing a partial configuration example of the semiconductor substrate 11A of the comparative example according to the second embodiment.

[0062] As shown in Figure 12, in the comparative example, the multiplication section 14A is constructed by stacking a p-type semiconductor region 14X and an n-type semiconductor region 14Y. In the example in Figure 12, the p-type semiconductor region 14X and the n-type semiconductor region 14Y are stacked in the Z-axis direction from the first surface 11S1 side of the semiconductor substrate 11 in the order of p-type semiconductor region 14X and n-type semiconductor region 14Y. A cathode electrode 16 is stacked on the p-type semiconductor region 14X. In other words, in the comparative example, the positions of the cathode electrode 16 and the anode electrode 15 are swapped.

[0063] The p-type semiconductor region 111A is formed to be in contact with the n-type semiconductor region 14Y and the anode electrode 15. For example, the side of the n-type semiconductor region 14Y opposite to the p-type semiconductor region 14X is in contact with the p-type semiconductor region 111A.

[0064] In a comparative example of such a configuration, for example, a P / N (p-type semiconductor region 14X and n-type semiconductor region 14Y) is arranged in the Si of the semiconductor substrate 11, and one PN junction is formed, thereby creating one multiplication region 14a. When only this one multiplication region 14a exists, the region involved in avalanche multiplication becomes narrower compared to when the two multiplication regions 14a and 14b mentioned above are present, so the multiplication probability becomes lower.

[0065] (Multiplication Operation) Figure 13 is a diagram illustrating the multiplication operation of the multiplication unit 14A of the comparative example according to the second embodiment. Figure 14 is a graph showing the potential and electric field strength of the multiplication unit 14A of the comparative example according to the second embodiment. In the example of Figure 14, as in Figure 6, the vertical axis is the potential or electric field strength, the horizontal axis is the position in the -Z direction (position in the Z-axis direction), and the potential waveform P4 and electric field strength waveform E4 are shown.

[0066] In the example in Figure 13, the left and center figures show cases where multiplication does not occur, while the right figure shows cases where multiplication occurs. In the left figure, the electron (e) initially generated by photoelectric conversion does not increase in the multiplication unit 14A (unignited). In the center figure, the first electron increases (ignited), but the next hole (h) does not increase (unignited). For example, even after increasing several to several dozen times, not all of the generated electrons and holes may be multiplied, the multiplication may stop, and the operation may not reach Geiger mode. In the right figure, electrons and holes continue to multiply, and the operation reaches Geiger mode.

[0067] Increasing the electric field strength increases the multiplication probability, but it exponentially increases the probability of electron generation due to crystal defects (TAT), leading to an increase in DC resistance (DCR). For example, an electric field strength of 60 V / μm is the limit of acceptable DCR. Therefore, there are limits to how much the electric field strength can be increased.

[0068] As shown in Figure 14, when we look at the potential waveform P4 and the electric field strength waveform E4, we see that there is a rapid change in potential at the multiplication section 14A, i.e., the PN junction, and a strong electric field (approximately 50 V / μm) is generated. In this section, electrons generated by discharge conversion reach the Geiger mode. The probability that these electrons reach the Geiger mode, i.e., the multiplication probability, is approximately 60% when the electric field strength is 50 V / μm.

[0069] On the other hand, according to the second embodiment, as described above, two strong electric fields (approximately 50 V / um) are generated (see Figure 9), and two multiplication regions 14a and 14b exist, so the multiplication probability of electrons only (for example, the probability of firing) increases. For example, the multiplication probability increases from the aforementioned 60% to about 80%. In this case, the multiplication section 14 is constructed by stacking a p-type semiconductor region 14X1, an n-type semiconductor region 14Y, and a p-type semiconductor region 14X2. As a result, two PN junctions are created, and two multiplication regions 14a and 14b are formed. Therefore, the area related to avalanche multiplication increases, and an improvement in the multiplication probability can be achieved.

[0070] In the second embodiment, the anode electrode 15 is independently positioned approximately in the center of each of the multiple unit pixels 101 arranged in an array in the matrix direction, and the cathode electrode 16 is positioned diagonally from the center of the unit pixel 101 (for example, at a 45° angle) (see Figure 7). This will be explained below.

[0071] An avalanche photodiode is a SPAD (Semiconductor Application Diode) element that amplifies one electron to tens of thousands of electrons by applying a high electric field to a semiconductor. For example, in silicon (Si), an electric field of 0.4 to 0.6 MV / cm is applied to the avalanche photodiode. In a typical photodetector, multiple rectangular pixels are arranged in an array in the row and column directions. In this typical photodetector, the avalanche photodiodes arranged for each pixel have a rectangular shape similar to the pixels, with, for example, a cathode or anode located approximately in the center of the pixel, and anodes or cathodes located between adjacent pixels in the row and column directions, and at the four corners of the rectangle.

[0072] A reverse bias voltage difference of 20V to 30V is applied to the anode (p++) and cathode (n++) of an avalanche photodiode. Since almost no current flows before avalanche multiplication occurs, this voltage difference is applied to the regions outside the p-type and n-type avalanche multiplication regions (neutral regions). This voltage difference is applied to the short depletion layer of the high-concentration n-type and p-type semiconductor regions (p+ / n+) that constitute the avalanche multiplication region, resulting in a high electric field of 0.4MV / cm to 0.6MV / cm. When considering miniaturization of avalanche photodiodes, for example, to reduce the size from about 10μm per side to, for example, 1 / 4 size (about 2.5μm per side), each structure would need to be reduced to 1 / 4.

[0073] However, for example, it is not possible to reduce the avalanche electric field between 0.4 MV / cm and 0.6 MV / cm, nor is it possible to reduce the voltage difference between 20V and 30V. When a rectangular avalanche photodiode like the one described above is miniaturized to one-quarter of its size, the lateral electric field becomes four times stronger. For example, if the lateral electric field of an avalanche photodiode with sides of 10 μm is 0.1 MV / cm to 0.2 MV / cm, the lateral electric field of an avalanche photodiode with sides of 2.5 μm will be 0.4 MV / cm to 0.8 MV / cm, which is equivalent to or greater than the avalanche electric field, raising concerns about edge breakdown.

[0074] In contrast, in the second embodiment, as described above, the anode electrode 15 is independently positioned approximately in the center of each of the multiple unit pixels 101 arranged in an array in the matrix direction, and the cathode electrode 16 is positioned diagonally from the center of the unit pixel 101 (for example, at a 45° angle). As a result, the distance between the anode electrode 15 and the cathode electrode 16 can be secured to be √2 times the pixel pitch, compared to a rectangular avalanche photodiode. Therefore, the lateral electric field can be made smaller than, for example, the avalanche electric field. Consequently, the photodetector 1 of the second embodiment can reduce the occurrence of edge breakdown.

[0075] <2-3. Modified Examples> An example of the configuration of the semiconductor substrate 11 according to the second embodiment will be described with reference to Figures 15 to 26.

[0076] (Modification 1) Figure 15 is a cross-sectional view showing a partial configuration example of the semiconductor substrate 11 of Modification 1 according to the second embodiment. Figure 16 is a cross-sectional view showing a configuration example of the anode wiring (Anode1 wiring 151, Anode2 wiring 152) of Modification 1 according to the second embodiment.

[0077] As shown in Figure 15, the anode electrode 15 is provided on the first surface 11S1 of the semiconductor substrate 11 as well as on the second surface 11S2 of the semiconductor substrate 11. For example, the anode electrode 15 is embedded in the second surface 11S2 of the semiconductor substrate 11. The anode electrode 15 on the second surface 11S2 side of the semiconductor substrate 11 is an example of a third electrode.

[0078] The presence of the anode electrode 15 on the second surface 11S2 side of the semiconductor substrate 11 allows for the rapid discharge of holes moving towards the second surface 11S2 side. To prevent through-current between the anode electrode 15 on the first surface 11S1 side (front side) and the anode electrode 15 on the second surface 11S2 side (back side) of the semiconductor substrate 11, for example, the potential of the anode electrode 15 on the first surface 11S1 side and the anode electrode 15 on the second surface 11S2 side of the semiconductor substrate 11 are made the same.

[0079] The anode electrode 15 on the first surface 11S1 side of the semiconductor substrate 11 is electrically connected to Anode1 wiring 151. The anode electrode 15 on the second surface 11S2 side of the semiconductor substrate 11 is electrically connected to Anode2 wiring 152.

[0080] As shown in Figure 16, the Anode1 wiring 151 is electrically connected to the Anode1 power supply 155. Also, the Anode2 wiring 152 is electrically connected to the Anode2 power supply 156. In the example in Figure 16, the Anode1 wiring 151 and Anode2 wiring 152 in the pixel array section 100 are shown.

[0081] Note that Anode1 wiring 151 may be, for example, logic wiring within the logic board 20. Also, Anode2 wiring 152 may be connected to, for example, a light-shielding metal such as the pixel separation unit 17, or it may be electrically connected to wiring outside the pixel array unit 100.

[0082] (Modification 2) Figure 17 is a cross-sectional view showing a partial configuration example of the semiconductor substrate 11 of Modification 2 according to the second embodiment.

[0083] As shown in Figure 17, the p-type semiconductor region 111A is separated by the n-type semiconductor region 14Y. That is, the n-type semiconductor region 14Y extends in the planar direction (X-axis direction and Y-axis direction) and is in contact with the side surface of the pixel separation portion 17. As a result, the p-type semiconductor region 111A is separated by the n-type semiconductor region 14Y, so that the potential of the anode electrode 15 on the first surface 11S1 side of the semiconductor substrate 11 and the potential of the anode electrode 15 on the second surface 11S2 side of the semiconductor substrate 11 can be made different.

[0084] In other words, in the aforementioned modified example 1, the potential of the anode electrode 15 on the first surface 11S1 side of the semiconductor substrate 11 and the potential of the anode electrode 15 on the second surface 11S2 side of the semiconductor substrate 11 are the same. However, as in modified example 2, the potential of the anode electrode 15 on the first surface 11S1 side of the semiconductor substrate 11 and the potential of the anode electrode 15 on the second surface 11S2 side of the semiconductor substrate 11 may be different. For example, each anode voltage may be varied independently.

[0085] Figure 18 is a graph showing the potential and electric field strength of the amplification unit 14 in modified example 2 according to the second embodiment. In the example of Figure 18, similar to Figure 6, the vertical axis represents the potential or electric field strength, the horizontal axis represents the position in the -Z direction (position in the Z-axis direction), and the potential waveform P5 and electric field strength waveform E5 are shown.

[0086] In the example shown in Figure 18, the left figure shows the state before the voltage is lowered, and the right figure shows the state after the voltage is increased. In the left figure, when the anode voltage to the anode electrode 15 on the first surface 11S1 side (front side) of the semiconductor substrate 11 is lowered, the electric field strength on the first surface 11S1 side of the semiconductor substrate 11 decreases from approximately 50 V / μm to approximately 40 V / μm, as shown in the right figure. In this way, by applying different voltages to the anode electrode 15 on the first surface 11S1 side (front side) and the anode electrode 15 on the second surface 11S2 side (back side) of the semiconductor substrate 11, the electric field strength (for example, the depth of the trough in the potential waveform P5) can be adjusted as appropriate.

[0087] Here, the multiplication probability, TAT, and DCR are proportional to the electric field strength. Increasing the electric field strength to increase the multiplication probability also increases TAT ​​and DCR. In particular, TAT is highly temperature-dependent, and DCR worsens at lower temperatures. Crystal defects, which are the cause of TAT, are numerous on the first surface 11S1 side of the semiconductor substrate 11. At low temperatures, the voltage (absolute value) on the first surface 11S1 side of the semiconductor substrate 11 can be lowered to reduce the electric field on the first surface 11S1 side of the semiconductor substrate 11, thereby suppressing DCR. This is just one example, and the optimal multiplication probability and DCR can be set depending on the application.

[0088] Furthermore, in order to apply different voltages to the anode electrode 15 on the first surface 11S1 side and the anode electrode 15 on the second surface 11S2 side of the semiconductor substrate 11, the p-type semiconductor region 111A must be completely separated by the n-type semiconductor region 14Y midway. If this separation is not achieved, a through-current will flow. In addition, if necessary, for example, the density of the conductivity types of the aforementioned regions may be changed, the thickness of the aforementioned regions may be changed, or the aforementioned regions may be separated by distance.

[0089] (Modification 3) Figure 19 is a cross-sectional view showing a partial configuration example of the semiconductor substrate 11 of Modification 3 according to the second embodiment.

[0090] As shown in Figure 19, in Modification 3, the first surface 11S1 side of the semiconductor substrate 11 is formed by a p-type semiconductor region 111A. As a result, the first surface 11S1 side of the semiconductor substrate 11 becomes pwell, making it possible to reduce the electron generation probability on the first surface 11S1 side of the semiconductor substrate 11. Therefore, it is possible to suppress the generation of electrons due to crystal defects and the like. In the second embodiment, the initial ignition is by an electron. For this reason, it is desirable to suppress the generation of electrons due to crystal defects and the like.

[0091] (Modification 4) Figure 20 is a cross-sectional view showing a partial configuration example of the semiconductor substrate 11 of Modification 4 according to the second embodiment.

[0092] As shown in Figure 20, in Modification 4, the second surface 11S2 side of the semiconductor substrate 11 is formed by a p-type semiconductor region 111A. As a result, the second surface 11S2 side of the semiconductor substrate 11 becomes pwell, making it possible to reduce the electron generation probability on the second surface 11S2 side of the semiconductor substrate 11. Therefore, it is possible to suppress electron generation due to crystal defects and the like.

[0093] (Modification 5) Figure 21 is a cross-sectional view showing a partial configuration example of the semiconductor substrate 11 of Modification 5 according to the second embodiment.

[0094] As shown in Figure 21, in Modification 5, both the first surface 11S1 and the second surface 11S2 of the semiconductor substrate 11 are formed by p-type semiconductor regions 111A. As a result, both the first surface 11S1 and the second surface 11S2 of the semiconductor substrate 11 become pwell, making it possible to reduce the electron generation probability on both sides of the semiconductor substrate 11. Therefore, it is possible to suppress electron generation due to crystal defects and the like.

[0095] (Modification 6) Figure 22 is a cross-sectional view showing a partial configuration example of the semiconductor substrate 11 of Modification 6 according to the second embodiment.

[0096] As shown in Figure 22, in Modification 6, in addition to the configuration of Modification 5, a p-type semiconductor region (p+) 161 is embedded in the first surface 11S1 of the semiconductor substrate 11, and a p-type semiconductor region (p+) 162 is embedded in the second surface 11S2 of the semiconductor substrate 11. As a result, the first surface 11S1 and the second surface 11S2 of the semiconductor substrate 11 are pinned with p+. The p-type semiconductor region 161 is an example of a fifth semiconductor region, and the p-type semiconductor region 162 is an example of a sixth semiconductor region.

[0097] A cathode electrode 16 is present on the first surface 11S1 side of the semiconductor substrate 11. To suppress the generation of a strong electric field between the cathode electrode 16 and the p-type semiconductor region 161, a separation portion 163 is provided between the cathode electrode 16 and the p-type semiconductor region 161. For example, the separation portion 163 extends in the Z-axis direction. A dielectric material such as an oxide film can be used as the separation portion 163. The separation portion 163 can, for example, return photoelectrically converted electrons to the multiplier portion 14, and also contributes to improving sensitivity.

[0098] (Modification 7) Figure 23 is a cross-sectional view showing a partial configuration example of the semiconductor substrate 11 of Modification 7 according to the second embodiment.

[0099] As shown in Figure 23, in Modification 7, in addition to the configuration of Modification 6, a plurality of relaxation regions 164, 165, and 166 are provided. These relaxation regions 164, 165, and 166 are composed of, for example, n-type semiconductor regions (n-). Each relaxation region 164, 165, and 166 is provided to suppress unwanted electron generation.

[0100] The relaxation region 164 is inserted between the n-type semiconductor region 14Y and the isolation region 163, for example, to suppress the DCR generated from the interface between Si and the dielectric. This relaxes the electric field, thereby suppressing unwanted electron generation.

[0101] The relaxation region 165 is inserted between the n-type semiconductor region 14Y and the p-type semiconductor region 111A, for example, to suppress the electric field caused by contact between the n-type semiconductor region 14Y and the p-type semiconductor region 111A. As a result, the electric field is suppressed, and thus electron generation caused by TAT can be suppressed.

[0102] The relaxation region 166, like the relaxation region 164, is inserted between the n-type semiconductor region 14Y and the pixel separation region 17, for example, to suppress DCR generated from the interface between Si and the dielectric. This relaxes the electric field, thereby suppressing unwanted electron generation.

[0103] (Modification 8) Figure 24 is a cross-sectional view showing a partial configuration example of the semiconductor substrate 11 of Modification 8 according to the second embodiment.

[0104] As shown in Figure 24, in the modified example 8, the multiplication section 14 is constructed by stacking a p-type semiconductor region 14X1, an n-type semiconductor region 14Y, a p-type semiconductor region 14X2, a p-type semiconductor region 14X1, an n-type semiconductor region 14Y, and a p-type semiconductor region 14X2. In the example in Figure 24, the p-type semiconductor region 14X1, an n-type semiconductor region 14Y, a p-type semiconductor region 14X2, a p-type semiconductor region 14X1, an n-type semiconductor region 14Y, and a p-type semiconductor region 14X2 are stacked in the Z-axis direction from the first surface 11S1 side of the semiconductor substrate 11 in the order they are described. The multiplication section 14 includes two multiplication regions 14a and two multiplication regions 14b, that is, four multiplication regions 14a, 14b.

[0105] As described above, according to Modification 8, for example, P / N / P and P / N / P (p-type semiconductor region 14X1, n-type semiconductor region 14Y, p-type semiconductor region 14X2, p-type semiconductor region 14X1, n-type semiconductor region 14Y, and p-type semiconductor region 14X2) are arranged in the Si of the semiconductor substrate 11, and four PN junctions are created, thereby forming four multiplication regions 14a and 14b. As a result, the region involved in avalanche multiplication increases, and an improvement in multiplication probability can be achieved.

[0106] (Modification 9) Figure 25 is a plan view showing a part of the surface of the semiconductor substrate 11 of Modification 9 according to the second embodiment. Figure 26 is a cross-sectional view (cross-sectional view along line A3-A3 in Figure 25) showing an example of a part of the configuration of the semiconductor substrate 11 of Modification 9 according to the second embodiment.

[0107] As shown in Figure 25, in Modification 9, each of the multiple unit pixels 101 has a rectangular shape. Each unit pixel 101 is provided with an anode electrode 15 and multiple cathode electrodes 16. In the example in Figure 25, each unit pixel 101 is provided with one anode electrode 15 and eight cathode electrodes 16.

[0108] As shown in Figure 26, the first surface 11S1 of the semiconductor substrate 11 is provided with multiple cathode electrodes 16 in addition to the anode electrode 15. Furthermore, the second surface 11S2 of the semiconductor substrate 11 is also provided with multiple anode electrodes 15. This arrangement promotes carrier discharge and improves the reliability of the device compared to cases where there is only one cathode electrode 16 or one anode electrode 15.

[0109] The n-type semiconductor region 14Y1, which is in contact with the n-type semiconductor region 14Y, extends in the planar direction (X-axis and Y-axis direction) to contact the side surface of the pixel separation portion 17, and extends along that side surface toward the first surface 11S1 of the semiconductor substrate 11 in the stacking direction (Z-axis direction), and is formed to contact each cathode electrode 16. The p-type semiconductor region 111A extends in the planar direction (X-axis and Y-axis direction) to contact the side surface of the pixel separation portion 17, and extends along that side surface toward the second surface 11S2 of the semiconductor substrate 11 in the stacking direction (Z-axis direction), and is formed to contact each anode electrode 15.

[0110] <3. Operation and Effects of Each Embodiment> As described above, the photodetector 1 according to the embodiment comprises a light receiving unit 13 that generates carriers by photoelectric conversion, and a multiplication unit 14 that increases the carriers generated by the light receiving unit 13 by avalanche multiplication. The multiplication unit 14 has a plurality of multiplication regions 14a and 14b that increase the carriers, and the plurality of multiplication regions 14a and 14b are provided at opposing positions (see Figures 3 to 11, etc.). As a result, there are two multiplication regions 14a and 14b, and the area involved in avalanche multiplication is increased, so an improvement in the multiplication probability can be achieved.

[0111] Furthermore, the multiple multiplication regions 14a and 14b may face each other with a common semiconductor region (for example, an n-type semiconductor region 14Y) in between (see Figures 3 to 11, etc.). This allows the size of the multiplication section 14 to be reduced because it includes a common semiconductor region.

[0112] Furthermore, the multiple multiplication regions 14a and 14b may be aligned in the stacking direction (Z-axis direction) (see Figures 7 to 11, etc.). This makes it possible to reduce the size of the multiplication section 14 in the planar direction (X-axis direction and Y-axis direction).

[0113] Furthermore, the multiple multiplication regions 14a and 14b may be arranged such that the potential shape has at least one valley (see Figures 3 to 11, etc.). This ensures that the multiplication probability is improved.

[0114] Furthermore, the multiple multiplication regions 14a and 14b are composed of a first semiconductor region of a first conductivity type (e.g., a p-type semiconductor region 14X1), a second semiconductor region of a second conductivity type different from the first conductivity type (e.g., an n-type semiconductor region 14Y), and a third semiconductor region of the first conductivity type (e.g., a p-type semiconductor region 14X2), and the second semiconductor region may be sandwiched between the first and third semiconductor regions (see Figures 3 to 11, etc.). This ensures that the multiplication probability is improved.

[0115] Furthermore, the first semiconductor region (e.g., p-type semiconductor region 14X1), the second semiconductor region (e.g., n-type semiconductor region 14Y), and the third semiconductor region (e.g., p-type semiconductor region 14X2) may be aligned in the stacking direction (Z-axis direction) (see Figures 7 to 11, etc.). This makes it possible to reduce the size of each multiplication region 14a, 14b in the planar direction (X-axis direction and Y-axis direction).

[0116] Furthermore, the photodetector 1 may further include a semiconductor substrate 11 including a light receiving unit 13 and a multiplier unit 14, a first electrode (for example, an anode electrode 15) provided on the first surface 11S1 of the semiconductor substrate 11 for the multiplier unit 14, and a second electrode (for example, a cathode electrode 16) provided on the first surface 11S1 for the multiplier unit 14 (see Figures 3 to 11, etc.). Even with such a configuration, an improvement in multiplication probability can be reliably achieved.

[0117] Furthermore, the semiconductor substrate 11 includes a light-receiving section 13 and a multiplier section 14 for each unit pixel 101, and one or both of the first electrode (e.g., anode electrode 15) and the second electrode (e.g., cathode electrode 16) may be provided in multiple quantities for each unit pixel 101 (see Figures 3 to 5, 25, 26, etc.). This promotes carrier discharge and improves device reliability compared to the case where there is only one first electrode or one second electrode.

[0118] Furthermore, the semiconductor substrate 11 includes a light-receiving section 13 and a multiplier section 14 for each unit pixel 101, and the first electrode (for example, an anode electrode 15) is provided in the center of each unit pixel 101 in a plan view, while the second electrode (for example, a cathode electrode 16) may be provided at a position away from the center of each unit pixel 101 in a plan view (for example, at an angle of 45°) (see Figure 7). This reduces the occurrence of edge breakdown.

[0119] Furthermore, the photodetector 1 is provided on the second surface 11S2, which is the opposite surface of the first surface 11S1 on the semiconductor substrate 11, and may further include a third electrode (for example, an anode electrode 15) for the multiplication unit 14 (see Figures 15, 16, 25, 26, etc.). This can promote the discharge of carriers.

[0120] Furthermore, the semiconductor substrate 11 includes a light-receiving section 13 and a multiplication section 14 for each unit pixel 101, and multiple third electrodes (for example, anode electrodes 15) may be provided for each unit pixel 101 (see Figures 25, 26, etc.). This promotes carrier discharge and improves the reliability of the device compared to the case where there is only one third electrode.

[0121] Furthermore, the multiple multiplication regions 14a and 14b are constructed by stacking a first semiconductor region of a first conductivity type (e.g., a p-type semiconductor region 14X1), a second semiconductor region of a second conductivity type different from the first conductivity type (e.g., an n-type semiconductor region 14Y), and a third semiconductor region of the first conductivity type (e.g., a p-type semiconductor region 14X2) (see Figures 7 to 9, etc.). This ensures that the multiplication probability is reliably improved.

[0122] Furthermore, the photodetector 1 is provided on the semiconductor substrate 11 and further comprises a fourth semiconductor region of a first conductivity type (e.g., a p-type semiconductor region 111A) that contacts a first semiconductor region (e.g., a p-type semiconductor region 14X1) and a third semiconductor region (e.g., a p-type semiconductor region 14X2), and the fourth semiconductor region may be separated by a second semiconductor region (e.g., an n-type semiconductor region 14Y) (see Figures 17 and 18). This makes it possible to suppress the generation of through-current.

[0123] Furthermore, the photodetector 1 may also include a fifth semiconductor region of a first conductivity type (for example, a p-type semiconductor region 161) provided on the first surface 11S1 of the semiconductor substrate 11 (see Figures 22 and 23). This allows the first surface 11S1 of the semiconductor substrate 11 to be pinned with the first conductivity type.

[0124] Furthermore, the photodetector 1 may also include a separation section 163 provided between the fifth semiconductor region (for example, the p-type semiconductor region 161) and the second electrode (for example, the cathode electrode 16) (see Figures 22 and 23). This makes it possible to suppress the generation of a strong electric field between the fifth semiconductor region and the second electrode.

[0125] Furthermore, the photodetector 1 may also include a relaxation region 164 provided between the separation section 163 and the second semiconductor region (for example, the n-type semiconductor region 14Y) (see Figure 23). This relaxes the electric field, thereby suppressing unwanted electron generation.

[0126] Furthermore, the photodetector 1 may also include a sixth semiconductor region of the first conductivity type (for example, a p-type semiconductor region 162) provided on the second surface 11S2, which is the opposite surface of the first surface 11S1 on the semiconductor substrate 11 (see Figures 22 and 23). This allows the second surface 11S2 of the semiconductor substrate 11 to be pinned with the first conductivity type.

[0127] Furthermore, the photodetector 1 may further include a seventh semiconductor region of a first conductivity type (e.g., a p-type semiconductor region 111A) provided between a sixth semiconductor region (e.g., a p-type semiconductor region 162) and a second semiconductor region (e.g., an n-type semiconductor region 14Y), and a relaxation region 165 provided between the seventh semiconductor region and the second semiconductor region (see Figure 23). This relaxes the electric field, thereby suppressing electron generation caused by TAT.

[0128] Furthermore, the semiconductor substrate 11 includes a light-receiving section 13 and a multiplier section 14 for each unit pixel 101, and the photodetector 1 may further include a pixel separation section 17 for separating the unit pixels 101, and a relaxation section 166 provided between the pixel separation section 17 and a second semiconductor region (for example, an n-type semiconductor region 14Y) (see Figure 23). This relaxes the electric field, thereby suppressing the generation of unwanted electrons.

[0129] <4. Other Embodiments> The configurations and processes described in the above-described embodiments (including examples and modifications) may be implemented in various other forms besides those described above. For example, the configurations and processes may be in various forms, not limited to the examples described above. Also, for example, the configurations, processing procedures, specific names, and information including various data and parameters shown in the above document and drawings may be changed at will unless otherwise specified.

[0130] Furthermore, the configurations and processes described in the above-mentioned embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the figures. In other words, the specific forms of distribution or integration of each configuration and process are not limited to those shown in the figures, and all or part of them may be functionally or physically distributed or integrated in any unit depending on various loads and usage conditions.

[0131] Furthermore, the various configurations and processes described in the above-mentioned embodiments (including examples and modifications) may be combined as appropriate. For example, at least a part of one embodiment may be combined with at least a part of another embodiment as appropriate. Also, the effects described in the embodiments are merely illustrative and not limiting, and other effects may also occur.

[0132] <5. Application Examples> <5-1. Various Devices> Application examples of the photodetector 1 according to the above-described embodiment (including examples and modified versions) will be explained with reference to Figure 27. Figure 27 is a diagram showing an application example of the photodetector 1 according to the above-described embodiment.

[0133] The light detection device 1 according to the above embodiment may be applied to various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows. For example, the light detection device 1 may be applied to various devices (electronic devices) or electronic devices mounted on various devices, as shown below.

[0134] As shown in Figure 27, the light detection device 1 according to the above embodiment can be used in, for example, "devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions," "devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles," "devices used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and perform device operations according to those gestures," "devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography by receiving infrared light," "devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition," "devices used for beauty purposes, such as skin measuring devices that capture images of the skin and microscopes that capture images of the scalp," "devices used for sports purposes, such as action cameras and wearable cameras for sports use," and "devices used for agriculture, such as cameras for monitoring the condition of fields and crops."

[0135] Furthermore, the technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as electronic equipment mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors). Alternatively, for example, the technology disclosed herein may be implemented as electronic equipment mounted on endoscopic surgical systems or microsurgical systems.

[0136] <5-2. Imaging Device> The imaging device 300 according to the application example will be described with reference to Figure 28. Figure 28 is a diagram showing an example configuration of the imaging device 300 according to the application example. This imaging device 300 is an example of an electronic device to which the light detection device 1 according to the above-described embodiment is applied. Examples of imaging devices 300 include digital still cameras, video cameras, smartphones and mobile phones with imaging functions, and other electronic devices.

[0137] As shown in Figure 28, the imaging device 300 includes an optical system 301, a shutter device 302, an image sensor (solid-state imager) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. This imaging device 300 is capable of capturing both still and moving images.

[0138] The optical system 301 has one or more lenses. This optical system 301 guides light from the subject (incident light) to the image sensor 303 and forms an image on the light-receiving surface of the image sensor 303.

[0139] The shutter device 302 is positioned between the optical system 301 and the image sensor 303. The shutter device 302 controls the light illumination period and the light shielding period for the image sensor 303 according to the control of the control circuit 304.

[0140] The image sensor 303 accumulates signal charge for a certain period of time in response to light that is imaged onto the light-receiving surface via the optical system 301 and shutter device 302. The signal charge accumulated in the image sensor 303 is transferred according to a drive signal (timing signal) supplied from the control circuit 304. As the image sensor 303, for example, the light detection device 1 according to the above embodiment is used.

[0141] The control circuit 304 drives the image sensor 303 and the shutter device 302 by outputting drive signals that control the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302.

[0142] The signal processing circuit 305 performs various signal processing operations on the signal charge output from the image sensor 303. The image (image data) obtained by the signal processing circuit 305 is supplied to the monitor 306 and also to the memory 307.

[0143] The monitor 306 displays video or still images captured by the image sensor 303 based on image data supplied from the signal processing circuit 305. For example, the monitor 306 may be a panel-type display device such as a liquid crystal panel or an organic EL (Electro-Luminescence) panel.

[0144] The memory 307 stores image data supplied from the signal processing circuit 305, that is, image data of moving or still images captured by the image sensor 303. Various types of storage devices can be used as the memory 307.

[0145] Even in the imaging device 300 configured in this way, the same effects as in the above-described embodiment can be obtained by applying the light detection device 1 according to the above-described embodiment as the image sensor 303.

[0146] <5-3. Distance Measuring Device> The distance measuring device 400 according to the application example will be described with reference to Figure 29. Figure 29 is a diagram showing an example of the configuration of the distance measuring device 400 according to the application example. This distance measuring device 400 is an example of an electronic device to which the optical detection device 1 according to the above-described embodiment is applied.

[0147] As shown in Figure 29, the distance measuring device (distance image sensor) 400 comprises a light source unit 401, an optical system 402, an image sensor (solid-state imager) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. This distance measuring device 400 can acquire a distance image corresponding to the distance to the subject by projecting light from the light source unit 401 toward the subject and receiving the light (modulated light or pulsed light) reflected from the surface of the subject.

[0148] The light source unit 401 projects light toward the subject. The light source unit 401 can be, for example, a vertical cavity surface-emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the arrangement of the laser diodes.

[0149] The optical system 402 has one or more lenses. This optical system 402 guides light from the subject (incident light) to the image sensor 403 and forms an image on the light-receiving surface (sensor part) of the image sensor 403.

[0150] The image sensor 403 accumulates signal charge in response to light formed on the light-receiving surface via the optical system 402. A distance signal indicating the distance, determined from the light-receiving signal (APD OUT) output from the image sensor 403, is supplied to the signal processing circuit 405. As the image sensor 403, for example, the light detection device 1 according to the above embodiment is used.

[0151] The control circuit 404 outputs drive signals (control signals) that control the operation of the light source unit 401 and the image sensor 403, and drives the light source unit 401 and the image sensor 403.

[0152] The signal processing circuit 405 performs various signal processing operations on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing and peak detection processing) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing circuit 405 is supplied to the monitor 406 and also to the memory 407.

[0153] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. For example, a panel-type display device such as a liquid crystal panel or an organic EL panel can be used as the monitor 406.

[0154] The memory 407 stores image data supplied from the signal processing circuit 405, that is, image data of the distance image captured by the image sensor 403. Various types of storage devices can be used as the memory 407.

[0155] Even in the distance measuring device 400 configured in this way, the same effects as in the above-described embodiment can be obtained by applying the light detection device 1 according to the above-described embodiment as the image sensor 403.

[0156] As described above, the light detection device 1 according to the above embodiment can be implemented in various electronic devices. For example, in addition to the imaging device 300 and the distance measuring device 400, the light detection device 1 according to the above embodiment may be installed in various electronic devices such as HDDs (hard disk drives), notebook PCs (personal computers), mobile devices (e.g., smartphones and tablet PCs), PDAs (personal digital assistants), wearable devices, game consoles, and music players.

[0157] <6. Addendum> The technology can also be configured as follows: (1) A photodetector comprising: a light receiving unit that generates carriers by photoelectric conversion; and a multiplier unit that increases the carriers generated by the light receiving unit by avalanche multiplication, wherein the multiplier unit has a plurality of multiplier regions that increase the carriers, and the plurality of multiplier regions are provided at opposing positions. (2) The photodetector according to (1), wherein the plurality of multiplier regions are facing each other with a common semiconductor region in between. (3) The photodetector according to (1), wherein the plurality of multiplier regions are arranged in the stacking direction. (4) The photodetector according to (1), wherein the plurality of multiplier regions are provided so that the potential shape has at least one valley. (5) The photodetector according to (1), wherein the plurality of multiplication regions are composed of a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type different from the first conductivity type, and a third semiconductor region of the first conductivity type, and the second semiconductor region is sandwiched between the first semiconductor region and the third semiconductor region. (6) The photodetector according to (5), wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in the stacking direction. (7) The photodetector according to (1), further comprising: a semiconductor substrate including the light-receiving portion and the multiplication portion; a first electrode provided on the first surface of the semiconductor substrate for the multiplication portion; and a second electrode provided on the first surface for the multiplication portion. (8) The photodetector according to (7), wherein the semiconductor substrate includes the light-receiving portion and the multiplication portion for each pixel, and one or both of the first electrode and the second electrode are provided in multiples for each pixel. (9) The light detection device according to (7), wherein the semiconductor substrate includes the light receiving portion and the multiplier portion for each pixel, the first electrode is provided in the center of the pixel in a plan view for each pixel, and the second electrode is provided in a position at an oblique angle away from the center in a plan view for each pixel. (10) The light detection device according to (7), further comprising a third electrode provided on a second surface which is the opposite surface of the first surface of the semiconductor substrate, and relating to the multiplier portion.(11) The photodetector according to (10), wherein the semiconductor substrate includes the light-receiving portion and the multiplication portion for each pixel, and a plurality of the third electrodes are provided for each pixel. (12) The photodetector according to (7), wherein the plurality of multiplication regions are constructed by stacking a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type different from the first conductivity type, and a third semiconductor region of the first conductivity type. (13) The photodetector according to (12), further comprising a fourth semiconductor region of a first conductivity type provided on the semiconductor substrate and in contact with the first semiconductor region and the third semiconductor region, wherein the fourth semiconductor region is separated by the second semiconductor region. (14) The photodetector according to (12), further comprising a fifth semiconductor region of a first conductivity type provided on the first surface. (15) The photodetector according to (14), further comprising a separation portion provided between the fifth semiconductor region and the second electrode. (16) The photodetector according to (15), further comprising a relaxation region provided between the separation portion and the second semiconductor region. (17) The photodetector according to (12), further comprising a sixth semiconductor region of a first conductivity type provided on the second surface of the semiconductor substrate which is the opposite surface to the first surface. (18) The photodetector according to (17), further comprising a seventh semiconductor region of a first conductivity type provided between the sixth semiconductor region and the second semiconductor region, and a relaxation region provided between the seventh semiconductor region and the second semiconductor region. (19) The photodetector according to (12), wherein the semiconductor substrate includes the light receiving portion and the multiplier portion for each pixel, and further comprises a pixel separation portion for separating the pixels, and a relaxation region provided between the pixel separation portion and the second semiconductor region. (20) Electronic device comprising a photodetector, the photodetector comprising: a light receiving unit that generates carriers by photoelectric conversion; and a multiplier unit that increases the carriers generated by the light receiving unit by avalanche multiplication, the multiplier unit having a plurality of multiplier regions that increase the carriers, and the plurality of multiplier regions being provided at opposing positions. (21) Electronic device comprising a photodetector according to any one of (1) to (19).

[0158] 1. Light detection device 10. Sensor substrate 11. Semiconductor substrate 11S1 First surface 11S2 Second surface 12. Light receiving element 13. Light receiving section 14. Multiplier section 14a Multiplier region 14A Multiplier section 14b Multiplier region 14X p-type semiconductor region 14X1 p-type semiconductor region 14X2 p-type semiconductor region 14Y n-type semiconductor region 15. Anode electrode 16. Cathode electrode 17. Pixel separation section 19. Multilayer wiring layer 19S1 Surface 20. Logic substrate 21. Semiconductor substrate 22. Multilayer wiring layer 22S1 Surface 31. Protective layer 32. Color filter 33. On-chip lens 100. Pixel array section 101 Unit pixel 110. Bias voltage application section 111 n-type semiconductor region 111A p-type semiconductor region 112. Semiconductor region 117 Interlayer insulation layer 120 Quenching resistor element 130 Inverter 151 Anode1 wiring 152 Anode2 wiring 155 Anode1 power supply 156 Anode2 power supply 161 p-type semiconductor region 162 p-type semiconductor region 163 Isolation region 164 Relaxation region 165 Relaxation region 166 Relaxation region 192 Wiring layer 193 Interlayer insulation layer 194 Pad electrode 195 Wiring layer 221 Gate wiring 222 Wiring layer 223 Wiring layer 224 Wiring layer 225 Wiring layer 226 Interlayer insulation layer 227 Pad electrode 228 Wiring layer 300 Imaging device 400 Distance measuring device V1 Via V2 Via V3 Via

Claims

1. A light detection device comprising: a light receiving unit that generates carriers by photoelectric conversion; and a multiplier unit that increases the carriers generated by the light receiving unit by avalanche multiplication, wherein the multiplier unit has a plurality of multiplier regions that increase the carriers, and the plurality of multiplier regions are provided at opposing positions.

2. The photodetector according to claim 1, wherein the plurality of multiplication regions are opposite each other with a common semiconductor region in between.

3. The photodetector according to claim 1, wherein the plurality of multiplication regions are arranged in the stacking direction.

4. The photodetector according to claim 1, wherein the plurality of multiplication regions are arranged such that the potential shape has at least one valley.

5. The photodetector according to claim 1, wherein the plurality of multiplication regions are composed of a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type different from the first conductivity type, and a third semiconductor region of the first conductivity type, and the second semiconductor region is sandwiched between the first semiconductor region and the third semiconductor region.

6. The photodetector according to claim 5, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in the stacking direction.

7. The photodetector according to claim 1, further comprising: a semiconductor substrate including the light receiving portion and the light multiplier portion; a first electrode provided on the first surface of the semiconductor substrate and relating to the light multiplier portion; and a second electrode provided on the first surface and relating to the light multiplier portion.

8. The photodetector according to claim 7, wherein the semiconductor substrate includes the light-receiving portion and the multiplier portion for each pixel, and one or both of the first electrode and the second electrode are provided in multiple quantities for each pixel.

9. The light detection device according to claim 7, wherein the semiconductor substrate includes the light receiving portion and the multiplier portion for each pixel, the first electrode is provided in the center of the pixel in a plan view for each pixel, and the second electrode is provided in a position at an oblique angle away from the center for each pixel in a plan view.

10. The photodetector according to claim 7, further comprising a third electrode provided on a second surface which is the opposite surface of the first surface of the semiconductor substrate, and relating to the multiplication portion.

11. The photodetector according to claim 10, wherein the semiconductor substrate includes the light-receiving portion and the multiplier portion for each pixel, and a plurality of the third electrodes are provided for each pixel.

12. The photodetector according to claim 7, wherein the plurality of multiplication regions are configured by stacking a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type different from the first conductivity type, and a third semiconductor region of the first conductivity type.

13. The photodetector according to claim 12, further comprising a fourth semiconductor region of a first conductivity type provided on the semiconductor substrate and in contact with the first semiconductor region and the third semiconductor region, wherein the fourth semiconductor region is separated by the second semiconductor region.

14. The photodetector according to claim 12, further comprising a fifth semiconductor region of a first conductivity type provided on the first surface.

15. The photodetector according to claim 14, further comprising a separation portion provided between the fifth semiconductor region and the second electrode.

16. The photodetector according to claim 15, further comprising a relaxation region provided between the separation portion and the second semiconductor region.

17. The photodetector according to claim 12, further comprising a sixth semiconductor region of a first conductivity type provided on a second surface which is the opposite surface of the first surface of the semiconductor substrate.

18. The photodetector according to claim 17, further comprising: a seventh semiconductor region of a first conductivity type provided between the sixth semiconductor region and the second semiconductor region; and a relaxation region provided between the seventh semiconductor region and the second semiconductor region.

19. The photodetector according to claim 12, wherein the semiconductor substrate includes the light-receiving portion and the multiplier portion for each pixel, and further comprises a pixel separation portion for separating the pixels, and a relaxation region provided between the pixel separation portion and the second semiconductor region.

20. An electronic device comprising a light detection device, the light detection device comprising: a light receiving unit that generates carriers by photoelectric conversion; and a multiplier unit that increases the carriers generated by the light receiving unit by avalanche multiplication, the multiplier unit having a plurality of multiplier regions that increase the carriers, and the plurality of multiplier regions being provided at opposing positions.

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