Instruction buffer for nested loop, and processor

Abstract

The present application relates to an instruction buffer for a nested loop, and a processor. The processor comprises an instruction dispatch unit, a control status register, and a processing engine. The instruction buffer for a nested loop is configured to: acquire an instruction from the instruction dispatch unit; decode the instruction to acquire one or more total loop count indices respectively associated with one or more nested loops in the instruction; acquire from the control status register one or more total loop counts respectively associated with the one or more total loop count indices; and on the basis of the one or more total loop counts respectively associated with the one or more total loop count indices, send the one or more nested loops to the processing engine.

Description

Instruction buffers and processors for nested loops Technical Field

[0001] This disclosure relates generally to the field of computers, and more particularly to an instruction buffer and processor for nested loops. Background Technology

[0002] With the development of artificial intelligence (AI) technology, AI accelerators are being used more and more. Developers can use AI accelerators to quickly build and train their own deep learning models and apply them to various real-world scenarios, including image recognition, speech recognition, natural language processing, and recommendation systems. Summary of the Invention

[0003] An instruction buffer for nested loops according to an embodiment of the present disclosure is used in a processor including an instruction dispatch unit, a control status register, and a processing engine. It is configured to obtain instructions from the instruction dispatch unit, obtain one or more loop count indices respectively associated with one or more nested loops in the instructions by decoding the instructions, obtain one or more loop counts respectively associated with one or more loop count indices from the control status register, and send one or more nested loops to the processing engine based on one or more loop counts respectively associated with one or more loop count indices.

[0004] The processor according to an embodiment of the present invention includes an instruction dispatch unit, a control status register, a processing engine, and the aforementioned instruction buffer for nested loops.

[0005] These and other features of the processor core disclosed herein, as well as the operation, functionality, and economics of manufacture of related structural elements and combinations thereof, will become more apparent upon consideration of the following description and appended claims with reference to the accompanying drawings (all of which form a part of this specification, wherein like reference numerals designate corresponding portions in the drawings). However, it should be clearly understood that the drawings are for illustrative and descriptive purposes only and not for limiting purposes. Attached Figure Description

[0006] Figure 1 is a schematic block diagram illustrating an example internal structure of a processor in which an instruction buffer is used according to an embodiment of the present disclosure.

[0007] Figure 2 is a schematic block diagram illustrating an example internal structure of the instruction buffer shown in Figure 1.

[0008] Figure 3 is a schematic diagram illustrating an example process of caching and retrieving instructions, including nested loops, from the instruction buffer shown in Figure 1.

[0009] Figure 4 is a schematic diagram illustrating an example of the read pointer change process when the instruction buffer shown in Figure 1 reads instructions including nested loops.

[0010] Figure 5 is a schematic block diagram illustrating an example hardware implementation of the instruction buffer shown in Figure 2.

[0011] Figure 6 is a schematic block diagram illustrating the internal structure of an example computing device in which a processor core according to an embodiment of the present disclosure can be used. Detailed Implementation

[0012] Neural networks are a hot research topic in the field of AI. They primarily mimic the working principle of the human brain, learning and processing data through connections and information transmission between neurons. This ability to learn and process data has enabled neural networks to demonstrate enormous potential in various fields, such as image recognition, speech recognition, and natural language processing. Of course, the development of neural networks is inseparable from the support of computer technology. At the same time, the development of technologies such as cloud computing and big data has provided more convenient and efficient platforms for the training and application of neural networks.

[0013] Since most of the data in a neural network is represented as a multidimensional tensor, and processing multidimensional tensors typically involves iterations across different dimensions, the operations performed by a processor when executing a neural network usually require nested loops to segment and process the data.

[0014] In view of the above, an instruction buffer for nested loops according to embodiments of the present disclosure is proposed, which can efficiently manage nested loops related to neural networks, thereby enabling the processor to execute neural networks with minimal overhead.

[0015] Figure 1 is a schematic block diagram illustrating an example internal structure of a processor in which an instruction buffer is used according to an embodiment of the present disclosure. As shown in Figure 1, the processor 100 includes a fifth-generation Reduced Instruction Set Computing-five (RISC-V) Vector (RVV) core 102, a Control and Status Register (CSR) 104, an instruction buffer 106, a processing engine 108, and an Instruction Dispatch Unit (IDU) 110, wherein: the RVV core 102 is configured to set a loop count index associated with nested loops in an instruction, and a loop count, source tensor address, destination tensor address, source address jump step, and destination address jump step associated with the loop count index, and send them to the CSR 104; the CSR 104 is configured to store the loop count index and the associated loop count, source tensor address, destination tensor address, source address jump step, and destination address jump step, send the loop count associated with the loop count index to instruction buffer 106, and send the associated source tensor address, destination tensor address, source address jump step, and destination address jump step to processing engine 108; instruction buffer 106 is configured to retrieve data from IDU. 110 retrieves instructions, decodes the instructions to obtain the loop count index and / or loop count associated with each nested loop in the instructions, and sends the corresponding nested loop to the processing engine 108 based on the loop count index and / or loop count associated with each nested loop; the processing engine 108 is configured to retrieve input tensors from the data storage device based on the source tensor address and source address jump step size associated with the loop count index, process the input tensors based on the nested loops associated with the loop count index to generate output tensors, and store the output tensors in the data storage device based on the destination tensor address and destination address jump step size associated with the loop count index; IDU 110 is configured to send instructions to the instruction buffer 106.

[0016] In some embodiments, any nested loop in the instructions begins with a Loop Start (LPS) instruction or a Loop Start and Immediate (LPSI) instruction and ends with a Loop End (LPE) instruction. The LPS and LPE instructions contain a loop identifier associated with the nested loop, and the LPSI instruction contains a loop identifier and a loop count associated with the nested loop. In this case, the instruction buffer 106 can be configured to obtain the loop count index and / or loop count associated with each nested loop by decoding one or more of the LPS, LPSI, and LPE instructions.

[0017] Figure 2 is a schematic block diagram illustrating an example internal structure of the instruction buffer shown in Figure 1. As shown in Figure 2, in some embodiments, the instruction buffer 106 includes a buffer 1062, a pre-decoding unit 1064, and a control unit 1066, wherein: the buffer 1062 is configured to receive and buffer instructions from IDU 110; the pre-decoding unit 1064 is configured to extract instructions from the buffer 1062, decode the instructions to obtain one or more loop count indices associated with one or more nested loops in the instructions (e.g., one or more nested loops including LPS instructions and LPE instructions), and provide these loop count indices to the control unit 1066; the control unit 1066 is configured to obtain one or more loop counts associated with one or more loop count indices from CSR 104, and control the buffer 1062 to send one or more nested loops to the processing engine 108 based on these loop counts.

[0018] As shown in Figure 2, in some embodiments, the pre-decoding unit 1064 may be further configured to obtain one or more total loop counts associated with one or more nested loops in the instructions (e.g., one or more nested loops including LPSI instructions and LPE instructions) by decoding the instructions, and provide these total loop counts to the control unit 1066; the control unit 1066 may be further configured to control the buffer 1062 to send one or more nested loops to the processing engine 108 based on the one or more total loop counts from the pre-decoding unit 1064.

[0019] In some embodiments, the pre-decoding unit 1064 may be further configured to use a loop level register to record the loop level of each nested loop in the instruction as their total loop count index. For example, the loop level of the outermost nested loop may be recorded as 0 and the loop level of the innermost nested loop may be recorded as N (N is an integer greater than 0), and the loop level of the nested loops may be incremented by a predetermined step size in order from the outside to the inside.

[0020] As shown in Figure 2, in some embodiments, the control unit 1066 may be further configured to send a buffer empty state indication to the IDU 110 when the unoccupied buffer space in the buffer 1062 is greater than the buffer empty state threshold, so that the IDU 110 sends an instruction to the buffer 1062 in response to the buffer empty state indication.

[0021] As shown in Figure 2, in some embodiments, the control unit 1066 may be further configured to receive an engine full status indication from the processing engine 108 indicating that the unoccupied buffer space in the processing engine 108 is less than the engine full status threshold, and to control the buffer 1062 to stop sending instructions to the processing engine 108 in response to the engine full status indication.

[0022] As shown in Figure 2, in some embodiments, the control unit 1066 may be further configured to count the number of reads experienced by any nested loop in the instructions and control the buffer 1062 to exit the nested loop when the number of reads experienced by the nested loop reaches the total number of loops associated with the nested loop (i.e., stop reading and sending the nested loop to the processing engine 108 so that the processing engine 108 exits the execution of the nested loop).

[0023] Figure 3 is a schematic diagram illustrating an example process of caching and retrieving instructions including nested loops using the instruction buffer shown in Figure 1. As shown in Figure 3, in some embodiments, the instruction buffer 106 may be further configured to cache instructions in the form of a stack, and the write pointer wr_ptr is incremented by 1 each time an entry is written to the stack. It should be noted that, initially, the write pointer wr_ptr and the read pointer rd_ptr are equal, and the number of entries in the stack cnt is 0.

[0024] As shown in Figure 3, in some embodiments, the instruction buffer 106 may be further configured to increment the read pointer rd_ptr by 1 whenever an entry is read from the stack if the outermost nested loop LPS or LPSI instruction in the instruction has not yet been read, and to calculate the number of entries in the stack cnt based on the read pointer rd_ptr and the write pointer wr_ptr (i.e., cnt = wr_ptr - rd_ptr).

[0025] As shown in Figure 3, in some embodiments, the instruction buffer 106 can be further configured to, after reading the LPS or LPSI instruction of the outermost nested loop in the instruction, cause the read pointer rd_ptr to cycle between the pointer value corresponding to the LPS or LPSI instruction of the outermost nested loop and the pointer value corresponding to the LPE instruction of the outermost nested loop, and calculate the number of entries cnt in the stack based on the read pointer wr_ptr and the pointer value loop_start_ptr corresponding to the LPS or LPSI instruction of the outermost nested loop (i.e., cnt = wr_ptr - loop_start_ptr). In this case, the instruction buffer 106 can be further configured to continue writing entries to the stack until the number of entries cnt in the stack reaches the buffer full threshold.

[0026] Figure 4 is a schematic diagram illustrating an example of the read pointer change process when the instruction buffer shown in Figure 1 reads instructions including nested loops. As shown in Figure 4, in some embodiments, the instruction buffer 106 may be further configured to perform the following processing for any nested loop in the instruction: when the total number of loops associated with the nested loop is greater than 1, when the LPE instruction of the nested loop is read for the first time, the read pointer rd_ptr jumps back to the pointer value corresponding to the LPS or LPSI instruction of the nested loop and increments by 1; when the number of reads experienced by the nested loop has not yet reached the total number of loops associated with the nested loop, when the LPE instruction of the nested loop corresponding to the next read entry is predicted based on the current pointer value of the read pointer rd_ptr and the pointer value corresponding to the LPE instruction of the nested loop, the read pointer rd_ptr jumps back to the pointer value corresponding to the LPS or LPSI instruction of the nested loop and increments by 1; when the number of reads experienced by the nested loop has reached the total number of loops associated with the nested loop, when the LPE instruction of the nested loop corresponding to the next read entry is predicted based on the current pointer value of the read pointer rd_ptr and the pointer value corresponding to the LPE instruction of the nested loop, the read pointer rd_ptr increments by 2.

[0027] In some embodiments, the instruction buffer 106 may be further configured to increment the read pointer rd_ptr by 1 when the LPE instruction of the nested loop is read, provided that the total number of loops associated with the nested loop is equal to 1.

[0028] In some embodiments, the instructions from IDU 110 also include an operation end (OPEND) instruction, and the instruction buffer 106 may be further configured to cause the read pointer rd_ptr to jump to the next aligned address (i.e., to the next line) when the OPEND instruction is read.

[0029] Figure 5 is a schematic block diagram illustrating an example hardware implementation of the instruction buffer shown in Figure 2. As shown in Figure 5, in some embodiments, the instruction buffer 106 includes a dual-port static random access memory (SRAM) 502, a decoder 504, and a loop predictor 506, wherein: the dual-port SRAM 502 is configured to implement the buffer 1062 shown in Figure 2; the decoder 504 is configured to implement the pre-decoding unit 1064 shown in Figure 2; and the loop predictor 506 is configured to implement the control unit 1066 shown in Figure 2.

[0030] As shown in Figure 5, in some embodiments, the decoder 504 is configured to obtain the loop identifier and loop count associated with the nested loop by decoding the LPSI instruction, to obtain the loop identifier associated with the nested loop by decoding the LPS or LPE instruction, or to obtain information for controlling the read pointer jump by decoding the OPEND instruction.

[0031] As shown in Figure 5, in some embodiments, in the loop predictor 506: the loop level and loop identifier obtained by the decoder 504 from decoding the LPS or LPSI instruction and the LPE instruction are stored in a hash table last-in-first-out (LIFO) in the form of key-value pairs, where the key is the loop level and the value is the loop identifier. The hash table LIFO outputs the loop identifier of the innermost loop. The loop count array and the maximum loop count array store the current loop count and the maximum loop count (i.e., the total number of loops) of each nested loop, respectively, and find the current loop count and the maximum loop count of the innermost loop based on the loop identifier of the innermost loop. The current loop count is updated when the decoder 504 decodes the LPS or LPSI instruction and / or the LPE instruction. The pointer controller determines the next jump direction of the read pointer based on the following information: ① the loop count array and the maximum loop count array are output. The values ​​are equal; ② Processing engine 108 request, the read pointer has not caught up with the write pointer; ③ Predict the next instruction is an LPE instruction; ④ The current instruction is an LPE instruction; ⑤ The OPEND instruction has a jump. Priority order: If ④ is present, jump to the pointer value corresponding to the LPS or LPSI instruction of the current innermost loop + 1; if ③ and ① are present, jump to the pointer value corresponding to the LPE instruction of the current innermost loop + 1; if ③ is present but ① is absent, jump to the pointer value corresponding to the LPS or LPSI instruction of the current innermost loop + 1; if ⑤ is present, jump to the next line; if ② is present, increment normally by 1; otherwise, keep the read pointer unchanged. The loop exit position of the current innermost loop and the pointer value corresponding to the LPS instruction of the current innermost loop + 1 will be obtained by the loop exit address controller and the loop start address controller based on the loop identifier of the current innermost loop and the loop identifier of the outermost loop (i.e., the top-level loop). Furthermore, the loop predictor 506 also includes a prediction flushing controller, used to automatically roll back the state and correct it to the correct state when loop prediction or calculation fails.

[0032] Figure 6 is a schematic block diagram illustrating the internal structure of an example computing device in which a processor according to an embodiment of the present disclosure may be used. As shown in Figure 6, the computing device 600 may include a bus 602 or other communication mechanism for transmitting information and one or more hardware processors 604 coupled to the bus 602 for processing information. The one or more hardware processors 604 may include, for example, one or more general-purpose microprocessors and / or one or more processors according to embodiments of the present disclosure.

[0033] As shown in Figure 6, in some embodiments, computing device 600 may further include main memory 606 coupled to bus 602 for storing information and instructions executed by one or more processors 604, such as random access memory (RAM), cache, and / or other dynamic storage devices. Main memory 606 may also be used to store temporary variables or other intermediate information during the execution of instructions executed by one or more processors 604. These instructions, when stored in storage media accessible to one or more processors 604, can cause computing device 600 to become a dedicated machine customized to perform the operations specified in the instructions. Main memory 606 may include non-volatile and / or volatile storage media. Non-volatile storage media may include, for example, optical discs or magnetic disks. Volatile storage media may include dynamic memory. Common forms of storage media may include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape, or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, DRAM, PROM, and EPROM, FLASH-EPROM, NVRAM, any other memory chip or cartridge, or their networking versions.

[0034] As shown in Figure 6, in some embodiments, the computing device 600 may further include a communication interface 610 coupled to the bus 602. The communication interface 610 may provide bidirectional data communication coupling to one or more network links connected to one or more networks. As another example, the communication interface 610 may be a local area network (LAN) card to provide data communication connectivity to a LAN-compatible (or WAN component communicating with a WAN) network. A wireless link may also be implemented.

[0035] The execution of certain operations can be distributed across processors rather than residing within a single machine, but rather deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0036] Each of the processes, methods, and algorithms described in the preceding sections may be embodied in code modules executed by one or more computer systems or computer processors including computer hardware, and may be fully or partially automated by these code modules. The processes and algorithms may be implemented, partially or fully, in dedicated circuit systems.

[0037] When the functions disclosed herein are implemented as software functional units and sold or used as standalone products, they may be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, may be embodied in the form of a software product. The software product may be stored in a storage medium and includes several instructions that cause a computing device (which may be a personal computer, server, network device, etc.) to perform all or some steps of the methods of the embodiments of this application. The storage medium may include a flash drive, portable hard disk drive, ROM, RAM, magnetic disk, optical disk, other media operable to store program code, or any combination thereof.

[0038] Specific embodiments further provide a system including a processor and a non-transitory computer-readable storage medium storing instructions executable by the processor to cause the system to perform operations corresponding to steps in any method of the embodiments disclosed above. Specific embodiments further provide a non-transitory computer-readable storage medium storing instructions executable by one or more processors to cause the one or more processors to perform operations corresponding to steps in any method of the embodiments disclosed above.

[0039] The embodiments disclosed herein can be implemented via a cloud platform, server, or server cluster (collectively referred to below as the "Service System") that interacts with a client. The client can be a terminal device or a client registered by a user at the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can have the platform application installed.

[0040] The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Additionally, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and their associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in an order other than that specifically disclosed, or multiple blocks or states may be combined into a single block or state. Example blocks or states may be executed sequentially, in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments. The exemplary systems and components described herein may be configured differently than described. For example, components may be added to, removed from, or rearranged compared to the disclosed example embodiments.

[0041] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. The algorithm may be included in program code or instructions stored in memory (e.g., the aforementioned non-transitory computer-readable storage medium). This algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not explicitly refer to the computer as performing the function but may learn from training data to generate a predictive model of the function.

[0042] The various operations of the exemplary methods described herein can be performed, at least in part, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, these processors can constitute an engine of processor implementation that operates to perform one or more of the operations or functions described herein.

[0043] Similarly, the methods described herein may be implemented at least in part by a processor, wherein one or more specific processors are instances of hardware. For example, at least some operations of the methods may be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors may also be operable to support the execution of related operations in a “cloud computing” environment or as the execution of related operations in a “Software as a Service” (SaaS) context. For example, at least some operations may be performed by a group of computers (as an example of a machine containing processors), wherein these operations are accessible via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0044] The execution of certain operations can be distributed across processors rather than residing within a single machine, and can be deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0045] Throughout this specification, multiple instances may be implemented as components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of these individual operations may be performed simultaneously, and not necessarily in the order illustrated. Structures and functions presented as separate components in the example configuration may be implemented as composite structures or components. Similarly, structures and functions presented as single components may be implemented as single components. These and other variations, modifications, additions, and improvements fall within the scope of this document.

[0046] As used herein, "or" is inclusive rather than exclusive unless explicitly indicated by the context. Therefore, in this document, "A, B, or C" means "A, B, A and B, A and C, B and C, or A, B, and C" unless explicitly indicated by the context. Furthermore, "and" is combined and separate unless explicitly indicated by the context. Therefore, in this document, "A and B" means "A and B, combined or separate" unless explicitly indicated by the context. Additionally, multiple instances of resources, operations, or structures described herein may be provided as a single instance. Furthermore, the boundaries between various resources, operations, engines, and data storage devices are somewhat arbitrary and specific operations are illustrated within the context of a particular illustrative configuration. Other functional assignments are foreseeable and fall within the scope of various embodiments of this disclosure. Generally, structures and functions presented as individual resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functions presented as single resources may be implemented as single resources. These and other changes, modifications, additions, and improvements fall within the scope of the embodiments of this disclosure as expressed in the appended claims. Therefore, this specification and drawings should be considered illustrative rather than restrictive.

[0047] The terms “comprising” or “including” are used to indicate the presence of a subsequently claimed feature, but do not preclude the addition of other features. Unless otherwise specifically stated or otherwise understood in the context in which they are used, conditional language such as “may,” “can,” “may,” and “can” is generally intended to convey that certain embodiments include certain features, components, and / or steps that are not included in other embodiments. Therefore, this conditional language is generally not intended to imply that one or more embodiments require features, components, and / or steps in any way, or that one or more embodiments must include logic for determining whether such features, components, and / or steps are included in or performed in any particular embodiment, with or without user input or prompts.

[0048] Although the general outline of the subject matter has been described with reference to specific exemplary embodiments, various modifications and changes may be made to these embodiments without departing from the broad scope of embodiments of this disclosure. Where more than one embodiment is disclosed, these embodiments of the subject matter may be referred to individually or collectively herein as the term "invention," this is for convenience only and is not intended to automatically limit the scope of this application to any single disclosure or concept.

[0049] The embodiments illustrated herein have been described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. Therefore, the term "implementation" is not intended to be limiting, and the scope of the various embodiments is defined only by the appended claims and their full scope.

Claims

1. An instruction buffer for nested loops, used in a processor including an instruction dispatch unit, a control status register, and a processing engine, configured to fetch instructions from the instruction dispatch unit, decode the instructions to obtain one or more loop count indices respectively associated with one or more nested loops in the instructions, obtain one or more loop counts respectively associated with the one or more loop count indices from the control status register, and send the one or more nested loops to the processing engine based on the one or more loop counts respectively associated with the one or more loop count indices.

2. The instruction buffer of claim 1 is further configured to obtain, by decoding the instruction, one or more other nested loops associated with one or more other nested loops in the instruction that are different from the one or more nested loops, and to send the one or more other nested loops to the processing engine based on the one or more other nested loops associated with the one or more other nested loops.

3. The instruction buffer according to claim 1 or 2 is further configured to send a buffer empty state indication to the instruction distribution unit when the unoccupied buffer space in the instruction buffer is greater than a buffer empty state threshold, so that the instruction distribution unit sends the instruction to the instruction buffer in response to the buffer empty state indication.

4. The instruction buffer according to claim 1 or 2 is further configured to receive from the processing engine an engine full status indication indicating that the unoccupied buffer space in the processing engine is less than an engine full status threshold, and to stop sending the instruction to the processing engine in response to the engine full status indication.

5. The instruction buffer according to claim 1 or 2, further configured to, for any nested loop in the instructions, count the number of reads experienced by the nested loop and exit the nested loop when the number of reads experienced by the nested loop reaches the total number of loops associated with the nested loop.

6. The instruction buffer according to claim 1 or 2, wherein, Any nested loop in the instructions begins with a loop start instruction or a loop start with an immediate instruction and ends with a loop end instruction, wherein the loop start instruction and the loop end instruction contain a loop identifier associated with the nested loop, and the loop start with an immediate instruction contains a loop identifier associated with the nested loop and a total number of loops.

7. The instruction buffer of claim 6 is further configured to cache the instructions in the form of a stack, and to increment the write pointer by 1 each time an entry is written to the stack.

8. The instruction buffer of claim 7 is further configured to, in the absence of a loop start instruction or a loop start and immediate value instruction of the outermost nested loop in the instructions, increment the read pointer by 1 whenever an entry is read from the stack, and calculate the number of entries in the stack based on the read pointer and the write pointer.

9. The instruction buffer of claim 8 is further configured to, after reading the loop start instruction or loop start with immediate instruction of the outermost nested loop, calculate the number of entries in the stack based on the read pointer and the pointer value corresponding to the loop start instruction or loop start with immediate instruction of the outermost nested loop.

10. The instruction buffer of claim 7 is further configured such that, for any nested loop in the instructions, if the total number of loops associated with the nested loop is greater than 1, when the loop end instruction of the nested loop is read for the first time, the read pointer jumps back to the loop start instruction of the nested loop or the pointer value corresponding to the loop start and immediate instruction is incremented by 1.

11. The instruction buffer of claim 10, further configured to, if the number of reads experienced by the nested loop has not yet reached the total number of loops associated with the nested loop, when the next read entry corresponding to the loop end instruction of the nested loop is predicted based on the current pointer value of the read pointer and the pointer value corresponding to the loop end instruction of the nested loop, cause the read pointer to jump back to the pointer value corresponding to the loop start instruction of the nested loop or the pointer value corresponding to the loop start and immediate instruction plus 1.

12. The instruction buffer of claim 11, further configured to increment the read pointer by 2 when the number of reads experienced by the nested loop reaches the total number of loops associated with the nested loop, and the next read entry corresponding to the loop end instruction of the nested loop is predicted based on the current pointer value of the read pointer and the pointer value corresponding to the loop end instruction of the nested loop.

13. The instruction buffer of claim 7 is further configured such that, for any nested loop in the instructions, when the total number of loops associated with the nested loop is equal to 1, the read pointer is incremented by 1 when the loop end instruction of the nested loop is read.

14. The instruction buffer according to claim 7, wherein, The instruction also includes an operation end instruction, and the instruction buffer is further configured to cause the read pointer to jump to the next aligned address when the operation end instruction is read.

15. A processor comprising an instruction dispatch unit, a control status register, a processing engine, and an instruction buffer according to any one of claims 1 to 14.

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