Encoding method, decoding method, communication node and storage medium

Abstract

An encoding method, comprising: on the basis of the number of rows of a parity check matrix (PCM), the number of columns of the PCM, a lifting value, the number of punctures in systematic columns of the PCM, and a code rate, determining a shortening sequence; on the basis of the length of the shortening sequence, the number of rows of the PCM, the number of columns of the PCM, and the lifting value, determining a bit sequence to be encoded; and on the basis of the shortening sequence, the PCM and the lifting value, encoding the bit sequence to be encoded, so as to obtain an encoded bit sequence.

Description

Encoding methods, decoding methods, communication nodes, and storage media Technical Field

[0001] This application relates to the field of wireless communication technology, such as an encoding method, a decoding method, a communication node, and a storage medium. Background Technology

[0002] With the rapid development of technologies such as big data, cloud computing, and latency-sensitive networks, the number of user devices in wireless communication networks is exploding. These networks will carry diverse applications and massive amounts of data, placing high demands on data transmission rates, throughput, reliability, and latency. Currently, with the development of virtual reality / augmented reality, intelligent transportation, intelligent industrial control, and intelligent logistics, the demand for ultra-high data rates, ultra-low latency, and ultra-high reliability is becoming increasingly stringent. In future mobile communication air interface standard protocols, the peak rate requirement will increase by one or two orders of magnitude compared to related 5G mobile communication systems. How to design encoding and decoding methods to improve data error correction performance, increase the robustness of data communication, and meet the requirements of higher peak rates has become an urgent problem to be solved. Summary of the Invention

[0003] This application provides an encoding method, a decoding method, a communication node, and a storage medium.

[0004] This application provides an encoding method applied to a first communication node, including:

[0005] The shortened sequence is determined based on the number of rows in the Parity Check Matrix (PCM), the number of columns in the PCM, the boost value, the number of punctures in the systematic column of the PCM, and the bit rate.

[0006] The bit sequence to be encoded is determined based on the length of the shortened sequence, the number of rows of the PCM, the number of columns of the PCM, and the boost value.

[0007] The bit sequence to be encoded is encoded according to the shortened sequence, the PCM, and the boost value to obtain the encoded bit sequence.

[0008] Wherein, the boost value and the length of the bit sequence to be encoded are both positive integers; the code rate is a real number greater than 0 and less than 1; the number of punctures in the system column of the PCM is a non-negative integer less than the size of the system column of the PCM, the size of the system column is the difference between the number of columns and the number of rows of the PCM, the number of rows and the number of columns of the PCM are both integers greater than 0, and the number of columns of the PCM is greater than the number of rows of the PCM; the length of the encoded bit sequence is an integer greater than the length of the bit sequence to be encoded; the elements in the shortening sequence are used to indicate the position where the system column of the PCM is shortened, and the number of elements in the shortening sequence is an integer less than the size of the system column of the PCM and greater than or equal to 0.

[0009] This application also provides a decoding method applied to a second communication node, including:

[0010] Receive a data sequence to be decoded, the data sequence to be decoded including all or part of the data of the encoded bit sequence;

[0011] The shortened sequence is determined based on the number of rows in the parity check matrix (PCM), the number of columns in the PCM, the boost value, the number of punctures in the systematic column of the PCM, and the bit rate.

[0012] Based on the shortened sequence, the PCM, the boost value, and the data sequence to be decoded, the data sequence to be decoded is decoded to obtain the decoded bit sequence;

[0013] Wherein, the boost value is a positive integer; the code rate is a real number greater than 0 and less than 1; the number of punctures in the system column of the PCM is a non-negative integer less than the size of the system column of the PCM, the size of the system column is the difference between the number of columns and the number of rows of the PCM, both the number of rows and the number of columns of the PCM are positive integers, and the number of columns of the PCM is greater than the number of rows of the PCM; the length of the encoded bit sequence is an integer greater than the length of the bit sequence to be encoded; the elements in the shortening sequence are used to indicate the position where the system column of the PCM is shortened, and the number of elements in the shortening sequence is an integer less than the size of the system column of the PCM and greater than or equal to 0.

[0014] This application also provides a communication node, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the above-described encoding or decoding method.

[0015] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described encoding or decoding method. Attached Figure Description

[0016] Figure 1 is a schematic diagram of an application scenario of an encoding / decoding method provided in an embodiment of this application;

[0017] Figure 2 is a flowchart of an encoding method provided in an embodiment of this application;

[0018] Figure 3 is a flowchart of a decoding method provided in an embodiment of this application;

[0019] Figure 4 is a schematic diagram of a first shortened sequence provided in an embodiment of this application;

[0020] Figure 5 is a schematic diagram of the performance curve of a second shortening sequence provided in an embodiment of this application;

[0021] Figure 6 is a schematic diagram of the performance curve of another second shortened sequence provided in an embodiment of this application;

[0022] Figure 7 is a schematic diagram of the performance curve of another second shortening sequence provided in an embodiment of this application;

[0023] Figure 8 is a schematic diagram of the performance curve of another second shortening sequence provided in an embodiment of this application;

[0024] Figure 9 is a schematic diagram of an encoding device provided in an embodiment of this application;

[0025] Figure 10 is a schematic diagram of a decoding device provided in an embodiment of this application;

[0026] Figure 11 is a schematic diagram of the hardware structure of a communication node provided in an embodiment of this application. Detailed Implementation

[0027] In wireless communication systems, the transmitting end performs channel coding on the data to be transmitted to obtain a coded bit subsequence, and then maps the coded bit subsequence into constellation modulation symbols before sending it to the receiving end. In the data transmission channel, errors can occur due to factors such as multipath propagation, noise, and interference. The transmitting end adds redundant information to the data to be transmitted through channel coding, allowing the receiving end to recover the original data from this redundancy, thus eliminating the distortion introduced during transmission. The receiving end needs to perform channel decoding on the received constellation modulation symbols to recover the transmitted data.

[0028] Currently, commonly used channel coding methods include Low Density Parity Check (LDPC), polar coding, turbo coding, and convolutional coding. LDPC is defined by a sparse (or low-density) PCM, and its decoding performance can be improved through iterative decoding, such as using belief-transfer decoding.

[0029] LDPC codes are a type of forward error correction coding. In the 5G New Radio (NR) standard, the physical layer uses LDPC codes as the primary coding scheme for the data channel. 5G LDPC codes employ a quasi-cyclic (QC) structure, which, in addition to maintaining excellent performance, allows for higher decoding parallelism. QC-LDPC codes have two base graphs (BGs). The LDPC code can be defined by the PCM and boost value of the BG. In this application, the PCM of the BG is collectively referred to as PCM, which is the unexpanded matrix in the QC-LDPC code. The expanded matrix is ​​called the extended PCM. In BG2, the size Kb of the system column is determined according to the input information bit length B, as shown in Table 1.

[0030] Table 1. Flowchart for determining the system column size based on the input information bit length.

[0031] The above determination process can be understood as follows: For BG2, Kb is determined based on the input information bit length B, thereby determining the amount of shortening. The shortening position starts from the last systematic column of BG. That is, within the range of the input information bit length corresponding to the same Kb value, regardless of the change in the magnitude of the boost value Z, there is only one shortening position sequence. For example, if the dimension of BG2 is 42*52 and the total number of systematic columns is the first 10 columns, when Kb=9, the 10th systematic column is shortened; when Kb=8, the 9th and 10th systematic columns are shortened; and when Kb=6, the 7th, 8th, 9th, and 10th systematic columns are shortened.

[0032] The shortening operation involves selecting certain positions within the codeword and deciding not to send information at these positions. The shortening positions are known at both the transmitting and receiving ends, and are typically set to null or 0 at these positions. For example, the shortening position might be the last L columns of the system column in a PCM. Before shortening, the system column matrix has kb columns; after shortening, the system column matrix has Kb columns. The structure of a shortened PCM can be represented as follows: Among them, Hb s For the system column matrix, Hb pFor the check column matrix, the number of columns in the system column matrix is ​​Kb, and the number of columns in the check column matrix is ​​mb. If the shortened position is the last L columns of the system column in the PCM, then the (kb-L)*Z+1 to kb*Z bits in the codeword are known at both the transmitting and receiving ends. It can be understood that the aforementioned (kb-L)*Z+1 to kb*Z bits are known at both the transmitting and receiving ends, such as being all equal to null or 0.

[0033] According to the 5G NR protocol, within the range of input information bit length corresponding to the same Kb value, multiple boost values ​​have the same shortening position sequence. However, the shortening position sequence may not be optimal for every boost value. In this embodiment, the shortening sequence is determined based on the number of rows and columns of the parity check matrix (PCM), the boost value, the number of punctures in the PCM system column, and the code rate. This ensures higher reliability, higher data error correction performance, and increased robustness of data communication under any selectable boost value or code rate.

[0034] Figure 1 is a schematic diagram of an application scenario of an encoding / decoding method provided in an embodiment of this application. As shown in Figure 1, the first communication node 100 can transmit the encoded bits to the second communication node 200, and the second communication node 200 can decode the received bits. In one example, the first communication node 100 and the second communication node 120 may include, but are not limited to, the following electronic devices: base station (BS), access point (AP), node B, g node B (generalized node B), radio network controller (RNC), evolved node B (eNB), base station controller (BSC), base transceiver station (BTS), transceiver function (TF), radio router, radio transceiver, basic service set (BSS), extended service set (ESS), or radio base station (RBS). The first and second communication nodes can also be access terminals, user equipment (UE), user units, user stations, mobile stations, mobile stations, remote stations, remote terminals, mobile devices, user terminals, wireless communication equipment, user agents, or user devices. For example, the second processing node can be a cellular phone, cordless phone, Session Initiation Protocol (SIP) phone, Wireless Local Loop (WLL) station, Personal Digital Assistant (PDA), handheld device with wireless communication capabilities, computing device, or other processing device connected to a wireless modem, in-vehicle device, wearable device, 5G network, or terminal device in future 5G or higher networks, etc., without specific limitations.

[0035] In light of the above application scenarios, the LDPC code encoding method in this embodiment is generally executed by an electronic device with a certain computing power. In some possible implementations, the LDPC encoding method can be implemented by the processor calling computer-readable instructions stored in the memory.

[0036] It is understood that the execution subject of the LDPC code encoding method provided in this embodiment may be, but is not limited to, the first communication node in the scenario diagram shown in Figure 1. Alternatively, those skilled in the art can choose to set the corresponding execution subject according to the actual application scenario, and this embodiment does not impose any restrictions. Here, in order to more conveniently describe the application scenario and principle of this application, the first communication node is often used as the execution subject of the LDPC code encoding method in the relevant parts of the following related embodiments, but this should not be construed as a limitation on the embodiments of this application.

[0037] Figure 2 is a flowchart of an encoding method provided in an embodiment of this application. This method can be applied to a first communication node, which can be an encoding end. As shown in Figure 2, the method provided in this embodiment includes:

[0038] 110. The shortened sequence is determined based on the number of rows of the parity check matrix PCM, the number of columns of the PCM, the boost value, the number of punctures in the system column of the PCM, and the bit rate.

[0039] 120. The bit sequence to be encoded is determined based on the length of the shortened sequence, the number of rows of the PCM, the number of columns of the PCM, and the boost value.

[0040] 130. The bit sequence to be encoded is encoded according to the shortened sequence, the PCM, and the boost value to obtain the encoded bit sequence.

[0041] Wherein, the boost value (Z) and the length (B) of the bit sequence to be encoded are both positive integers; the code rate (R) is a real number greater than 0 and less than 1; the number of punctures in the PCM system column is a non-negative integer less than the size of the PCM system column (kb), the size of the system column (kb) is the difference between the number of PCM columns (nb) and the number of PCM rows (mb), the number of PCM rows (mb) and the number of PCM columns (nb) are both integers greater than 0, and the number of PCM columns (nb) is greater than the number of PCM rows (mb); the length (N) of the encoded bit sequence is an integer greater than the length (B) of the bit sequence to be encoded; the elements in the shortening sequence are used to indicate the position where the PCM system column is shortened, and the number of elements in the shortening sequence is an integer less than the size of the PCM system column (kb) and greater than or equal to 0.

[0042] The encoding method in this embodiment determines the optimal shortened sequence based on the number of PCM rows, the number of PCM columns, the boost value, the number of punctures in the PCM system column, and the code rate. It then determines the bit sequence to be encoded based on the length of the shortened sequence, the number of PCM rows, the number of PCM columns, and the boost value. Encoding is performed on this basis, which can ensure higher reliability under any selectable boost value, thereby improving the error correction performance of the data, increasing the robustness of data communication, and meeting the requirements of higher peak rates.

[0043] In one embodiment, determining the shortened sequence based on the number of rows of the PCM, the number of columns of the PCM, the boost value, the number of punctures in the system columns of the PCM, and the bit rate includes:

[0044] The first shortened sequence is obtained based on the lift value;

[0045] Determine the second shortened sequence based on the first shortened sequence;

[0046] Wherein, the second shortening sequence is a subset of the first shortening sequence, and the elements in both the first and second shortening sequences are used to indicate the position where the system column of the PCM is shortened. The number of elements (L1) in the first shortening sequence is an integer greater than 0 that is less than the size (kb) of the system column of the PCM. The number of elements (L2) in the second shortening sequence is less than or equal to the number of elements in the first shortening sequence and is an integer greater than or equal to 0. The second shortening sequence is the determined shortening sequence.

[0047] In one embodiment, the method further includes:

[0048] Send all or part of the encoded bit sequence to the second communication node.

[0049] In one embodiment, obtaining the first shortened sequence based on the boost value includes:

[0050] The first shortening sequence is obtained based on the preset range or preset value of the increase value;

[0051] Each preset range or preset value corresponds to a first shortening sequence.

[0052] In one embodiment, determining the second shortened sequence based on the first shortened sequence includes one of the following:

[0053] The first L2 elements of the first shortened sequence constitute the second shortened sequence;

[0054] The last L2 elements of the first shortened sequence constitute the second shortened sequence; or

[0055] The L2 elements at preset positions of the first shortened sequence constitute the second shortened sequence.

[0056] In one embodiment, the number of elements (which may be L2) in the shortened sequence (which may be a second shortened sequence) is determined according to at least one of the following: a preset value; the number of rows of the PCM; the number of columns of the PCM; the number of punctures in the system columns of the PCM; and the bit rate.

[0057] In one embodiment, L2 is obtained by rounding up or down the quotient of the first value and the second value;

[0058] Wherein, the first value is equal to the difference between the third value and the fourth value; the third value is equal to the difference between the number of columns of the PCM and the number of rows of the PCM; the fourth value is equal to the product of the bitrate and the fifth value; the fifth value is equal to the difference between the number of columns of the PCM and the number of punches in the system columns of the PCM; and the second value is equal to the difference between 1 and the bitrate.

[0059] In one embodiment, the method further includes:

[0060] The boost value is determined based on at least one of the following: signaling indication, preset value, or parallelism requirement.

[0061] In one embodiment, obtaining a first shortening sequence based on a preset range or preset value of the increase value includes:

[0062] The first shortening sequence is determined according to a preset table or preset procedure, wherein the preset table or preset procedure is used to indicate the shortening sequence corresponding to each increase value interval.

[0063] In one embodiment, determining the bit sequence to be encoded based on the length of the shortened sequence, the number of rows of the PCM, the number of columns of the PCM, and the boost value includes:

[0064] The length of the bit sequence to be encoded is determined based on the length of the shortened sequence, the number of PCM rows, the number of PCM columns, and the boost value;

[0065] Based on the length of the bit sequence to be encoded, obtain a bit sequence of the corresponding length.

[0066] In one embodiment, the bit sequence to be encoded is encoded according to the shortened sequence, the PCM, and the boost value to obtain the encoded bit sequence, including:

[0067] The zero-padded bit sequence to be encoded is determined based on the shortened sequence, PCM, and boost value; wherein the length of the zero-padded bit sequence to be encoded is the product of the size of the system column and the boost value;

[0068] The zero-padded bit sequence to be encoded is encoded according to the PCM and the boost value to obtain an encoded bit sequence of length N.

[0069] In one embodiment, the zero-padded bit sequence to be encoded is encoded according to the PCM and the boost value to obtain an encoded bit sequence of length N, including:

[0070] The PCM is matrix-expanded according to the boost value to obtain the extended PCM corresponding to the zero-padded bit sequence to be encoded.

[0071] The zero-padded bit sequence to be encoded is encoded according to the extended PCM to obtain an encoded bit sequence of length N.

[0072] In one embodiment, the bit sequence to be encoded is encoded according to the shortened sequence, the PCM, and the boost value to obtain the encoded bit sequence, including:

[0073] The shortened PCM is obtained based on the shortened sequence and the PCM;

[0074] The shortened PCM and the boost value are used to encode the bit sequence to be encoded, resulting in an encoded bit sequence of length N.

[0075] In one embodiment, the bit sequence to be encoded is encoded according to the shortened PCM and the boost value to obtain an encoded bit sequence of length N, including:

[0076] Based on the boost value, the shortened PCM is matrix-expanded to obtain the extended PCM corresponding to the bit sequence to be encoded.

[0077] The bit sequence to be encoded is encoded according to the extended PCM to obtain an encoded bit sequence of length N.

[0078] Figure 3 is a flowchart of a decoding method provided in an embodiment of this application. This method can be applied to a second communication node, which can be a decoding end. It should be noted that technical details not described in detail in this embodiment can be found in any of the above embodiments. As shown in Figure 3, the method provided in this embodiment includes:

[0079] 210, Receive the data sequence to be decoded, the data sequence to be decoded includes all or part of the data of the encoded bit sequence.

[0080] 220. The shortened sequence is determined based on the number of rows, columns, boost value, number of punctures in the systematic column of the PCM, and bit rate of the parity check matrix PCM.

[0081] 230. Based on the shortened sequence, the PCM, the boost value, and the data sequence to be decoded, the data sequence to be decoded is decoded to obtain the decoded bit sequence.

[0082] Wherein, the boost value is a positive integer; the code rate is a real number greater than 0 and less than 1; the number of punctures in the system column of the PCM is a non-negative integer less than the size of the system column of the PCM, the size of the system column is the difference between the number of columns and the number of rows of the PCM, both the number of rows and the number of columns of the PCM are positive integers, and the number of columns of the PCM is greater than the number of rows of the PCM; the length of the encoded bit sequence is an integer greater than the length of the bit sequence to be encoded; the elements in the shortening sequence are used to indicate the position where the system column of the PCM is shortened, and the number of elements in the shortening sequence is an integer less than the size of the system column of the PCM and greater than or equal to 0.

[0083] In one embodiment, determining the shortened sequence based on the number of rows of the PCM, the number of columns of the PCM, the boost value, the number of punctures in the system columns of the PCM, and the bit rate includes:

[0084] The first shortened sequence is obtained based on the lift value;

[0085] The second shortening sequence is determined based on the number of rows of the PCM, the number of columns of the PCM, the first shortening sequence, the number of punches in the system columns of the PCM, and the bit rate;

[0086] Wherein, the second shortening sequence is a subset of the first shortening sequence, and the elements in both the first and second shortening sequences are used to indicate the position where the PCM system column is shortened. The number of elements (L1) in the first shortening sequence is an integer greater than 0 that is less than the size (kb) of the PCM system column. The number of elements (L2) in the second shortening sequence is less than or equal to the number of elements in the first shortening sequence and is an integer greater than or equal to 0. The second shortening sequence is the determined shortening sequence.

[0087] The encoding and decoding methods of this application are illustrated by way of some embodiments below.

[0088] Example 1

[0089] The LDPC code encoding method provided in this embodiment mainly includes the following operations:

[0090] S1: Obtain the first shortened sequence based on the lift value;

[0091] S2: Determine the second shortened sequence based on at least the following parameters: number of PCM rows, number of PCM columns, first shortened sequence, number of punctures in PCM system columns, and bitrate;

[0092] S3: Determine the bit sequence to be encoded based on at least the following parameters: second shortened sequence length, number of PCM rows, number of PCM columns, and boost value;

[0093] S4: Obtain the encoded bit sequence based on at least the following parameters: second shortened sequence, PCM, boost value, and bit sequence to be encoded.

[0094] Optionally, it also includes S5: sending all the bits of the encoded bit sequence to the second communication node, or sending a portion of the bits of the encoded bit sequence.

[0095] The first shortening sequence is an ordered set of index values, and the second shortening sequence is a subset of the first shortening sequence. Elements in both sequences indicate the position where the corresponding PCM system column should be shortened. The number of elements in the first shortening sequence, L1, is an integer less than the number of PCM columns, kb, and greater than 0. The number of elements in the second shortening sequence, L2, is an integer less than or equal to L1 and greater than or equal to 0. The PCM is a matrix of size mb*nb, and the system column size, kb, is the difference between nb and mb. Both mb and nb are integers greater than 0, and nb is greater than mb. The boost value, Z, is an integer greater than 0. The length of the bit sequence to be encoded, B, is an integer greater than 0. The code rate, R, is a real number greater than 0 and less than 1. The length of the encoded bit sequence, N, is an integer greater than B.

[0096] The encoded bit sequence is obtained by encoding the PCM, the shortened sequence, the shortened systematic column size, and the boost value into the bit sequence to be encoded. The shortened sequence is a list of position indices that indicate the shortening of the PCM systematic column according to the shortening position of the LDPC code. The number of elements in the shortened sequence is less than the number of columns in the PCM and greater than 0.

[0097] PCM is a matrix of size mb*nb. The system column size kb is the difference between nb and mb. mb and nb are integers greater than 0, and nb is greater than mb. The boost value Z is an integer greater than 0. The length B of the bit sequence to be encoded is an integer greater than 0. The PCM system punch column PunN is a non-negative integer less than kb.

[0098] In one embodiment, S1 and S2 can be combined into a single operation, namely, determining the shortened sequence based on at least the following parameters: the number of rows in the PCM, the number of columns in the PCM, the boost value, the number of punctures in the PCM system columns, and the bitrate. Here, the shortened sequence can be understood as a second shortened sequence.

[0099] In one embodiment, within the range of input information bit length corresponding to the same Kb value, all boost values ​​are divided into multiple intervals, each interval being called a preset range. Obtaining a first shortening sequence based on the boost value includes: obtaining the first shortening sequence based on the preset range or preset value where the boost value is located. The preset range or preset value where the boost value is located has a one-to-one or many-to-one mapping relationship with the first shortening sequence. The one-to-one mapping relationship means that each preset boost value range or each preset value corresponds to a unique first shortening sequence; the many-to-one mapping relationship means that at least two preset boost value ranges or at least two preset values ​​correspond to one first shortening sequence. The first shortening sequence is an ordered set of index values, and the elements in the first shortening sequence indicate the position where the corresponding PCM system column should be shortened. The length L1 of the first shortening sequence is an integer greater than 0 that is less than the size kb of the PCM system column. Beneficial effects: Different boost values ​​may have different optimal first shortening sequences. Constructing the optimal first shortening sequence corresponding to each preset boost value or preset boost value range into a dynamically selectable configuration item, selecting the optimal shortening sequence based on the boost value before encoding can improve the reliability of data transmission. It should be noted that the terms "preset range" and "preset boost value range" have the same meaning and can be used interchangeably. The terms "preset value" and "preset boost value" have the same meaning and can be used interchangeably.

[0100] In S1, the boost value is a known value. The boost value can be obtained from at least one of the following: signaling indication, preset value, or parallelism requirement.

[0101] In one example, the boost value is obtained based on the signaling and preset boost values. t bits indicate at most 2t preset boost values, where t is an integer greater than 0. In one example, t = 2, two bits b1b0 indicate the selected boost value. There are 4 preset boost values. When b1b0 = 00, the boost value is Z0, as shown in Table 2.

[0102] Table 2 shows the boost values ​​corresponding to two bits.

[0103] In another example, the boost value can be obtained based on the parallelism requirement. Because in QC-LDPC codes, the decoder can decode with parallelism equal to the boost value, a high parallelism decoder can increase decoding speed but also increases decoder complexity and cost. Therefore, the boost value can be determined based on the parallelism requirement, for example, the boost value equal to the parallelism requirement.

[0104] In one embodiment, the representation of obtaining the first shortened sequence based on the preset range or preset value of the boost value may include, but is not limited to, a preset table or a preset process.

[0105] In this embodiment of the application, the representation of the obtained shortened sequence can be at least one of the following:

[0106] Method 1: The first shortening sequence is obtained based on a preset table. The preset table indicates the shortening sequence corresponding to each boost value. The shortening sequence indicates the position where the PCM system column is shortened. In this method, the preset table is shown in Table 3.

[0107] Table 3 shows the first shortening sequence corresponding to the increase value range.

[0108] In another form, the increment range of the above preset table can be not only a range, but also an equality judgment, as shown in Table 4.

[0109] Table 4 shows the first shortening sequence corresponding to the increase value range.

[0110] Method 2: The first shortening sequence is obtained according to a preset process. The preset process is used to indicate the first shortening sequence corresponding to each preset increase value interval. The first shortening sequence is used to indicate the position where the PCM system column is shortened. In this method, the preset process is shown in Table 5.

[0111] Table 5. A flowchart for obtaining the first shortened sequence.

[0112] In another form, the increment range of the above-mentioned preset process can be not only a range, but also an equality judgment, as shown in Table 6.

[0113] Table 6. Another flowchart for obtaining the first shortened sequence.

[0114] In this embodiment, in the above-mentioned preset table or preset process, the number of elements in the first shortened sequence is equal, all equal to L1, where L1 is an integer greater than 0 and less than the system column kb.

[0115] In this embodiment, in the aforementioned preset table or preset process, the elements in the first shortening sequence are used to indicate the positions where the PCM system columns are shortened. In one example, the column index value is used to indicate the position to be shortened, where the column index value is an integer greater than or equal to 0 and less than kb. In another example, the column index value is an integer greater than 0 and less than or equal to kb.

[0116] In this embodiment, the first shortened sequence S0, S1, ..., S in the aforementioned preset table or preset process M-1There must be at least two distinct shortened sequences, meaning that at least one element at a common position differs between the two shortened sequences. Therefore, it can be understood that the first shortened sequence is ordered; even if the sets of element values ​​in two first shortened sequences are equal, but the order in which the elements appear is different, they are still considered two shortened sequences. In one example, shortened sequence S0 = [3,4,5,6] is different from shortened sequence S1 = [3,4,6,5] because the values ​​at the third and fourth positions are not equal. In another example, shortened sequence S0 = [3,4,5,6] is the same as shortened sequence S1 = [3,4,5,6].

[0117] In one example, the shortening sequence is obtained according to a preset table, which indicates the shortening sequence corresponding to each lift value. The shortening sequence indicates the position where the PCM system column is shortened. The PCM in this example is shown in Table 7. The PCM dimension size is 4*20 columns, mb=4, nb=20, kb=nb-mb=16, the length of the first shortening sequence L=8, the optimal first shortening sequence when the lift value Z=64 is [3,14,10,12,13,9,7,2], and the optimal first shortening sequence when the lift value Z=128 is [10,3,2,14,13,12,11,7]. The size of the elements in the first shortening sequence is an integer greater than or equal to 0 and less than kb. In one example, assuming only one column of the PCM is shortened, and the first element of the first shortening sequence is selected, then when the boost value Z = 64, the codeword bits corresponding to the 3+1=4th column of the PCM are shortened; when the boost value Z = 128, the codeword bits corresponding to the 10+1=11th column of the PCM are shortened. Here, "3" and "10" are the first elements of the first shortening sequence when Z = 64.

[0118] Table 7 PCM

[0119] In the above example, the shortening of the codeword bits corresponding to the PCM based on the element values ​​in the first shortening sequence is further explained. In one example, the boost value is Z, the number of rows in the PCM is mb, the number of columns is nb, the codeword length is nb*Z, and the number of system bits is kb*Z, where kb = nb - mb. Therefore, each column of the PCM corresponds to Z consecutive bits in the codeword. In this example, as shown in Figure 4, "0" in 1106 indicates the system column index of the PCM, which has a total of kb different index values. "kb" in 1108 indicates the check column index of the PCM, which has a total of mb different index values. 1102 represents the Z codeword bits corresponding to the PCM system column index "0", and 1104 represents the Z codeword bits corresponding to the PCM check column index "kb". Assuming that the element value in the first shortened sequence is "0", then the Z system bits 1102 corresponding to the PCM system column index "0" are set to 0 bits. Since both the transmitting and receiving ends know that the positions are all 0 bits, no data information to be encoded is placed at the positions of the Z system bits 1102.

[0120] In another example, if the element value in the first shortened sequence is "0", then the Z system bits 1102 corresponding to the PCM system column index "0" are set to NULL, where NULL represents empty. Therefore, the column with PCM index "0" does not participate in encoding, which can be understood as the actual encoded PCM system column size being kb-1. Since both the transmitting and receiving ends know that these positions are NULL, no data to be encoded is placed at the Z system bits 1102 positions.

[0121] In one embodiment, the second shortening sequence is determined based on at least the following parameters: the number of rows in the PCM, the number of columns in the PCM, the first shortening sequence, the number of punctures in the system columns of the PCM, and the bitrate. In this embodiment, the length L2 of the second shortening sequence is an integer greater than 0 and less than or equal to L1, including: the length of the second shortening sequence is determined according to a preset value, or based on the number of rows mb in the PCM, the number of columns nb in the PCM, the number of punctures in the system columns of the PCM, and the bitrate. According to this embodiment, a feasible second shortening sequence length is determined according to the following expression:

[0122] Here, `floor()` represents taking the largest integer less than or equal to the target value. In one example, the number of rows in the PCM is mb = 4, the number of columns is nb = 20, the code rate is R = 0.85, the number of punctured columns in the PCM system is PunN = 2, and the length of the second shortening sequence is L2 = 4. A PCM system punctured column refers to the PCM system column corresponding to the bits in the encoded codeword that are not transmitted. At the receiving end, the probability that the codeword bits corresponding to the above system columns are equal to 0 or 1 is equal. In one example, the PCM dimension is 4*14, and the boost value is Z = 256. If there are two system punctured columns, one 0 and one 1, then the first 2*Z = 512 bits of the encoded codeword are not transmitted. At the receiving end, the probability that the first 512 bits of the codeword are equal to 0 or 1 is equal.

[0123] Another feasible way to shorten the sequence length can be determined based on the following expression:

[0124] Here, ceil() represents taking the smallest integer greater than or equal to the target value. In one example, the number of rows in the PCM is mb = 4, the number of columns in the PCM is nb = 20, the bitrate is R = 0.85, the number of punctured columns in the PCM system is PunN = 2, and the length of the second shortened sequence is L2 = 5.

[0125] Another feasible way to shorten the sequence length can be determined based on the following expression:

[0126] Here, `round()` represents taking the integer with the smallest difference from the target value. In one example, the number of rows in the PCM is mb = 4, the number of columns in the PCM is nb = 20, the bitrate is R = 0.85, the number of punctured columns in the PCM system is PunN = 2, and the length of the second shortened sequence is L2 = 5.

[0127] In one embodiment, the second shortened sequence is composed of L2 elements of the first shortened sequence. The second shortened sequence is obtained according to, but not limited to, one of the following: the first L2 elements of the first shortened sequence constitute the second shortened sequence, the last L2 elements of the first shortened sequence constitute the second shortened sequence, or the L2 elements at a preset position of the first shortened sequence constitute the second shortened sequence.

[0128] In one example, the first L2 elements of the first shortened sequence constitute the second shortened sequence. The first shortened sequence is represented as S1 = [s0, s1, ..., s2]. L1-1 The second shortened sequence is the sequence S2 = [s0, s1, ..., s2], which is composed of the first L2 elements of the first shortened sequence. L2-1 ].

[0129] In one example, the last L2 elements of the first shortened sequence constitute the second shortened sequence, and the first shortened sequence is represented as S1 = [s0, s1, ..., s2]. L1-1 The second shortened sequence is the sequence S2 = [s], which is composed of the last L2 elements of the first shortened sequence. L1-L2 ,s1,...,s L1-1 ].

[0130] In one example, the L2 elements at preset positions of the first shortened sequence constitute the second shortened sequence. The preset positions are formed by first selecting the elements at odd positions of the first shortened sequence and then selecting the elements at even positions of the first shortened sequence.

[0131] In one embodiment, the bit sequence to be encoded is determined based on at least the following parameters: the length of the second shortened sequence, the number of PCM rows, the number of PCM columns, and the boost value. This includes: the length of the bit sequence to be encoded is determined based on the second shortened sequence length L2, the number of PCM rows mb, the number of PCM columns nb, and the boost value Z. One feasible implementation is that the length B of the bit sequence to be encoded is equal to (nb - mb - L2) * Z. Wherein, the second shortened sequence length L2 is an integer greater than 0 and less than (nb - mb), mb and nb are integers greater than 0, and nb is greater than mb; the boost value Z is an integer greater than 0.

[0132] In this embodiment, the bit sequence to be encoded is obtained from the transport block. The number of bits in the transport block is greater than or equal to the number of bits in the bit sequence to be encoded. Since the length of the bit sequence to be encoded is related to the length of the second shortened sequence L2, the number of rows mb of the PCM, the number of columns nb of the PCM, and the boost value Z, the bit sequence to be encoded is obtained from the transport block according to the obtained bit sequence length. For example, the transport block is segmented with an interval of size B, and each segment of bit data is the bit sequence to be encoded, where B is the length of the bit sequence to be encoded.

[0133] In this embodiment, after obtaining the length B of the bit sequence to be encoded, the first communication node obtains a bit sequence of length B or a bit sequence of length B that is an integer multiple of B based on the obtained length value B, encodes the bit sequence of length B, or segments the bit sequence of length B that is an integer multiple of B to obtain multiple sub-bit sequences of length B, and encodes the sub-bit sequences of length B.

[0134] In one example, the length of the bit sequence to be encoded is determined based on the length of the second shortened sequence L2, the number of PCM rows mb, the number of PCM columns nb, and the boost value Z. The length of the bit sequence to be encoded is B = (nb - mb - L2) * Z. When the number of PCM rows mb = 4, the number of PCM columns nb = 20, and the code rate R = 0.7, the length of the second shortened sequence L2 is obtained as 6. When the boost value Z = 128, the length of the bit sequence to be encoded is obtained as B = (20 - 4 - 6) * 128 = 1280; when the boost value Z = 64, the length of the bit sequence to be encoded is obtained as B = (20 - 4 - 6) * 64 = 640.

[0135] In one embodiment, the operation of obtaining the encoded bit sequence based on at least the following parameters—the second shortening sequence, PCM, boosting value, and the bit sequence to be encoded—may include, but is not limited to:

[0136] 1. Obtain the zero-padded bit sequence to be encoded based on the determined second shortened sequence, PCM, and boost value; wherein the length of the zero-padded bit sequence to be encoded is kb*Z;

[0137] Second: Encode the zero-padded bit sequence to be encoded according to PCM and the boost value to obtain an encoded bit sequence of length N.

[0138] In this embodiment, since B = (nb-mb-L2)*Z, the position of the zero-filling bit is the codeword bit position corresponding to the shortened system column in the shortened sequence. The number of zero-filling bits corresponding to L2 elements of the second shortened system column is L2*Z, and L2 is equal to the number of elements in the second shortened sequence.

[0139] In one example, the bit sequence to be encoded is represented as a = {a0, a1, ..., a...} B-1 The elements in the shortened sequence are the last L2 column of the system column. The resulting zero-padded bit sequence is a′={a0,a1,...,a...}. B-1 ,0 B ,0 B+1 ,...,0 kb*Z-1 The positions of the padding zero bits are known at both the transmitting and receiving ends. The kb*ZB padding zero bits may be omitted when the first communication node sends encoded data to the second communication node.

[0140] In operation two of this embodiment, the zero-padded bit sequence to be encoded is encoded according to the PCM and the boost value to obtain an encoded bit sequence of length N. In one feasible manner, the encoded bit sequence b is obtained by encoding according to the following process:

[0141] The PCM is matrix-extended based on the boost value Z to obtain the extended PCM corresponding to the bit sequence to be encoded after zero padding.

[0142] The zero-padded bit sequence to be encoded is encoded using extended PCM to obtain an encoded bit sequence of length N.

[0143] Here, the lift value Z serves as the dimension of the standard permutation matrix, enabling the expansion of the PCM. For example, elements in the PCM indicating all-zero square matrices can be replaced with Z*Z all-zero matrices. Similarly, elements in the PCM indicating cyclic shifts of the identity matrix can be replaced with cyclic shift matrices of the identity matrix. After the replacements are completed, an expanded PCM for each PCM can be obtained.

[0144] To facilitate understanding of the process of expanding a matrix based on the lift value, we will first provide an example of the specific representation of the parity matrix.

[0145] In one example, the extended PCM H of the LDPC code is an mb*Z row and nb*Z column matrix, composed of mb*nb submatrices, each of which is a different power of a Z*Z standard permutation matrix (corresponding to a cyclic shift matrix of the identity matrix) or a Z*Z all-zero square matrix. The extended PCM has the following form:

[0146] if have That is, a Z*Z all-zero square matrix; if If it is an integer greater than or equal to 0, the corresponding submatrix is ​​the standard permutation matrix P. The z×z standard permutation matrix P, which is the z-th power (i.e., the cyclic shift of the identity matrix), is shown below (the standard permutation matrix is ​​formed by cyclically shifting the identity matrix one bit to the right):

[0147] so, This allows each submatrix to be uniquely identified. If a submatrix is ​​a square matrix consisting entirely of zeros, the corresponding... Using -1 (or null values), if a submatrix is ​​obtained by cyclic shift 's' of the identity matrix, then... Equals s, therefore all This can form a PCM. Therefore, a PCM includes two types of elements: elements indicating an all-zero square matrix and elements indicating a cyclic shift of the identity matrix.

[0148] Z is the dimension of the standard permutation matrix (submatrix), and is called the lifting size. The base graph of the LDPC code is obtained by replacing the elements indicating cyclic shifts of the identity matrix in the PCM with "1" and replacing all elements indicating all-zero square matrices with "0". Therefore, the base graph of the LDPC code includes only two types of elements: "0" and "1", where "0" indicates an element at that index position that is an all-zero square matrix, and "1" indicates an element at that index position that is a cyclic shift of the identity matrix. For ease of description, only the elements indicating cyclic shifts of the identity matrix in the PCM and their row and column indices can be described, while the remaining row and column indices are assumed to indicate elements indicating all-zero square matrices. Alternatively, the elements indicating cyclic shifts of the identity matrix can be represented by their cyclic shift values, while the elements indicating all-zero square matrices can be described using -1, null values, or empty values.

[0149] In one example, a single LDPC code PCM (2 rows, 4 columns) is shown below, with a boost value of 4:

[0150] In this example, the extended PCM H is:

[0151] In this example, the corresponding base diagram is as follows:

[0152] Based on the specific manifestations of PCM and extended PCM, the encoding process of the bit sequence to be encoded described in the embodiments of this application will be explained below:

[0153] 1. Obtain the zero-padded bit sequence to be encoded based on the determined second shortened sequence, PCM, and boost value;

[0154] The length of the bit sequence to be encoded after zero padding is kb*Z, and the position of the zero-padded bits is the position of the codeword bit corresponding to the shortened system column in the shortened sequence.

[0155] In one example, the bit sequence to be encoded is represented as a = {a0, a1, ..., a...} B-1}, shorten the sequence to the last L columns of the system column, and you get the zero-padded bit sequence a′={a0,a1,...,a B-1 ,0 B ,0 B+1 ,...,0 kb*Z-1}

[0156] Second: Encode the zero-padded bit sequence to be encoded according to PCM and the boost value to obtain an encoded bit sequence of length N.

[0157] In this operation, the zero-padded bit sequence to be encoded is described as a′={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 kb*Z-1 The output encoded bit sequences are b = {b0, b1, ..., b}. N-1 The length of the encoded bit sequence is N bits.

[0158] For the zero-padded bit sequence a′ to be encoded, the zero-padded bit sequence is encoded according to PCM and the boost value Z to obtain the encoded bit sequence b. The encoded bit sequence b is obtained by encoding according to the following process:

[0159] The PCM is matrix-extended based on the boost value Z to obtain the extended PCM corresponding to the zero-padded bit sequence to be encoded.

[0160] The zero-padded bit sequence to be encoded is encoded using extended PCM to obtain an encoded bit sequence of length N.

[0161] Among them, according to PCM H b And the boost value Z, determine the extended PCM as H, that is, H b Replace the elements of the zero-indexed square matrix with a Z*Z zero-indexed matrix, and then... b The elements of the identity matrix that are cyclically shifted are replaced with a Z*Z cyclic shift matrix of the identity matrix (the shift value is equal to the element value, and can be a rightward or leftward cyclic shift). Similarly, each extended PCM includes a system column matrix H. s And check column matrix H p That is, the extended PCM has the following structure: [H s H p ].

[0162] According to PCM H bs The boost value Z is used to encode the bit sequence of the information to be encoded to obtain the encoded bit sequence. It can be understood that the encoded bit sequence can be calculated by the extended PCM H.

[0163] v = H s ×a′,p=(H p ) -1 ×v,

[0164] Therefore, the encoded bit sequence can be represented as The length of the encoded bit sequence is N.

[0165] In this embodiment, LDPC code shortening is an effective means of adjusting the code rate. It is achieved by selectively omitting some codeword positions while maintaining the excellent performance characteristics of the LDPC code as much as possible. The shortening operation involves selecting certain positions in the codeword and deciding not to send information at these positions. In this way, the shortened positions are known at both the transmitting and receiving ends. Typically, the shortened positions are set to 0, without directly changing the size of the PCM. These shortened positions do not participate in the encoding process.

[0166] For the codeword bit position corresponding to the shortened systematic column in the shortened sequence, if the shortened position is the last L columns of the systematic column in the PCM, then the (kb-L)*Z+1 to kb*Z bits in the codeword are known at both the transmitting and receiving ends, for example, set to 0 at the position. Since one element in the shortened sequence refers to one column of the PCM, one element in the PCM corresponds to a shortening of the boost value Z bits.

[0167] In one example of this embodiment, the number of rows in the PCM is mb = 4, the number of columns in the PCM is nb = 20, and the PCM is shown in Table 7. The first shortened sequence is obtained according to a preset table, and the first shortened sequences when the lift value Z equals 64 and 128 are shown in Table 8.

[0168] Table 8 shows the first shortening sequence corresponding to the increase value range.

[0169] In the first shortened sequence, the elements are integers greater than or equal to 0 and less than Kb. For example, the element "3" represents the index number corresponding to the 4th column of the PCM; the element "0" represents the index number corresponding to the 1st column of the PCM.

[0170] In this example, with a bitrate R = 12 / 14 and a PCM system column punch count PunN = 2, the second shortened sequence length is obtained according to one of the following feasible methods:

[0171] In one example, the first L2 elements of the first shortened sequence are selected to form the second shortened sequence. When Z = 64, the second shortened sequence is [3, 14, 10, 12], and when Z = 128, the second shortened sequence is [10, 3, 2, 14, 13]. The reason for choosing the second shortened sequence [3, 14, 10, 12] instead of [10, 3, 2, 14, 13] for encoding the bit sequence at Z = 64 is that it provides better error correction performance. For example, as shown in Figure 5, the code rate R = 12 / 14, the length of the sequence to be encoded B = 768, and the boost value used in the encoding process is 64. The solid line is the performance curve obtained by using the second shortened sequence [3,14,10,12] corresponding to Z = 64, and the dashed line is the performance curve obtained by using the second shortened sequence [10,3,2,14,13] corresponding to Z = 128. It can be seen that when the boost value is equal to 64, choosing the first and second shortened sequences corresponding to Z = 64 has better performance than choosing the first and second shortened sequences corresponding to Z = 128. In the figure, AWGN represents Additive White Gaussian Noise (AWGN), QPSK represents Quadrature Phase Shift Keying (QPSK), LNMS represents Layered Normalized Min-Sum Algorithm (LNMS) for LDPC decoding, BLER represents Block Error Rate (BLER), and SNRdB represents Signal-to-Noise Ratio in Decibel (SNRdB), all in dB.

[0172] The reason for choosing the second shortened sequence [10,3,2,14,13] instead of the second shortened sequence [3,14,10,12] for encoding the bit sequence with Z=128 is that the second shortened sequence [10,3,2,14,13] has better error correction performance when the boost value Z=128. For example, as shown in Figure 6, with a code rate R=12 / 14, a sequence length B=1536, and a boost value of 128 used in the encoding process, the solid line represents the performance curve obtained using the second shortened sequence [3,14,10,12] corresponding to Z=64, and the dashed line represents the performance curve obtained using the second shortened sequence [10,3,2,14,13] corresponding to Z=128. It can be seen that when the boost value is equal to 128, choosing the first and second shortened sequences corresponding to Z=128 has better performance than choosing the first and second shortened sequences corresponding to Z=64.

[0173] In another example, when the bit rate R = 8 / 10 and the number of punctures in the PCM system column PunN = 2, the second shortened sequence length is obtained according to one of the following feasible methods.

[0174] In one example, the first L2 elements of the first shortened sequence are selected to form the second shortened sequence. When Z = 64, the second shortened sequence is [3,14,10,12,13,9,7,2], and when Z = 128, the second shortened sequence is [10,3,2,14,13,12,11,7]. The reason for choosing the second shortened sequence [3,14,10,12,13,9,7,2] for encoding the bit sequence to be encoded at Z = 64, instead of using the second shortened sequence [10,3,2,14,13,12,11,7], is that choosing the second shortened sequence [3,14,10,12,13,9,7,2] at a boost value of Z = 64 provides better error correction performance. For example, as shown in Figure 7, the code rate R = 8 / 10, the length of the sequence to be encoded B = 512, and the boost value used in the encoding process is 64. The solid line represents the performance curve obtained using the second shortened sequence [3,14,10,12,13,9,7,2] corresponding to Z = 64, and the dashed line represents the performance curve obtained using the second shortened sequence [10,3,2,14,13,12,11,7] corresponding to Z = 128. It can be seen that when the boost value is equal to 64, choosing the first and second shortened sequences corresponding to Z = 64 has better performance than choosing the first and second shortened sequences corresponding to Z = 128. In the figure, AWGN represents the additive white Gaussian noise channel, QPSK represents the quadrature phase shift keying modulation scheme, LNMS represents the hierarchical normalized minimum sum algorithm used in LDPC decoding, BLER represents the block error rate, and SNRdB represents the simulated channel ratio in dB.

[0175] The reason for choosing the second shortened sequence [10,3,2,14,13,12,11,7] to encode the bit sequence to be encoded at Z=128 instead of using the second shortened sequence [3,14,10,12,13,9,7,2] is that the second shortened sequence [10,3,2,14,13,12,11,7] has better error correction performance when the boost value Z=128. For example, as shown in Figure 8, the code rate R = 8 / 10, the length of the sequence to be encoded B = 1024, and the boost value used in the encoding process is 128. The solid line is the performance curve obtained by using the second shortened sequence [3,14,10,12,13,9,7,2] corresponding to Z = 64, and the dashed line is the performance curve obtained by using the second shortened sequence [10,3,2,14,13,12,11,7] corresponding to Z = 128. It can be seen that when the boost value is equal to 128, in the high signal-to-noise ratio region, choosing the first and second shortened sequences corresponding to Z = 128 has better performance than choosing the first and second shortened sequences corresponding to Z = 64.

[0176] Example 2

[0177] In this embodiment, the process of LDPC code PCM selection and encoding method further includes:

[0178] S5: Send all bits of the encoded bit sequence to the second communication node, or send a portion of the encoded bit sequence.

[0179] The length of the encoded bit sequence is N, and the number of bits sent is E, where E is an integer less than or equal to N.

[0180] In one embodiment, a second encoded bit sequence of length E is obtained by bit selection of the encoded bit sequence according to at least one of the following: punctured bit position, zero-padding shortened bit position, code rate, and length of the bit sequence to be encoded.

[0181] The length of the encoded bit sequence obtained above includes source information bits, zero-padding bits, and parity bits. The length of the encoded bits may not meet the code rate requirements, so it is necessary to select some bits for transmission.

[0182] In this embodiment, the number of parity bits in the second encoded bit sequence is obtained according to at least the following method: (floor(B / R)-B+puncSysBit), and the number of parity bits punctured from the encoded bit sequence is obtained according to at least the following method: mb*Z-(floor(B / R)-B+puncSysBit). Where B is the length of the bit sequence to be encoded, puncSysBit is the number of system bit punctures, puncParBit is the number of parity bit punctures, R is the bit rate, and floor() represents taking the largest integer less than or equal to the target value; besides floor(), ceil() or round() can also be used, representing taking the smallest integer greater than or equal to the target value and taking the integer with the smallest difference from the target value, respectively.

[0183] In this embodiment, the punch bit position is preset and determined; in one example, the system bit punch position is located at the first puncSysBit bits of the encoded bit sequence, and the parity bit punch position is located at the last puncParBit bits of the encoded bit sequence.

[0184] In one example, the second encoded bit sequence is the bit sequence obtained by deleting the first puncSysBit system punch bits, the kb*ZB zero-padding bits, and the last puncParBit check punch bits from the encoded bit sequence.

[0185] Example 3

[0186] In this embodiment, the second shortened sequence is determined based on at least the following parameters: the number of rows in the PCM, the number of columns in the PCM, the first shortened sequence, and the bitrate. The number of punctures in the system columns of the PCM is excluded. In this embodiment, the length L2 of the second shortened sequence is an integer greater than 0 and less than or equal to L1, including: the length of the second shortened sequence is determined according to a preset value, or according to the number of rows mb in the PCM, the number of columns nb in the PCM, and the bitrate. According to this embodiment, a feasible length of the second shortened sequence is determined according to the following expression:

[0187] Here, floor() represents taking the largest integer less than or equal to the target value. In one example, the number of rows in the PCM is mb = 4, the number of columns in the PCM is nb = 20, the bitrate is R = 0.7, and the length of the second shortened sequence is L2 = 6.

[0188] Another feasible way to shorten the sequence length can be determined based on the following expression:

[0189] Here, ceil() represents taking the smallest integer greater than or equal to the target value. In one example, the number of rows in the PCM is mb = 4, the number of columns in the PCM is nb = 20, the bitrate is R = 0.7, and the length of the second shortened sequence is L2 = 7.

[0190] Another feasible way to shorten the sequence length can be determined based on the following expression:

[0191] Here, `round()` represents taking the integer with the smallest difference from the target value. In one example, the number of rows in the PCM is mb = 4, the number of columns in the PCM is nb = 20, the bitrate is R = 0.7, and the length of the second shortened sequence is L2 = 7.

[0192] In one embodiment, the second communication node sends all bits of the encoded bit sequence, or sends a portion of the encoded bit sequence, and performs bit selection on the encoded bit sequence according to at least one of the following to obtain a second encoded bit sequence of length E: punctured bit positions, zero-padding shortened bit positions, code rate, or the length of the bit sequence to be encoded. In this case, the punctured bit positions do not include system column bits, and may only include parity column bits. For example, in obtaining the second encoded bit sequence, it is not necessary to delete the first puncSysBit system bits from the encoded bit sequence.

[0193] Example 4

[0194] In this embodiment, the bit sequence to be encoded is determined based on at least the following parameters: the length of the second shortened sequence, the number of rows in the PCM, the number of columns in the PCM, and the boost value. Specifically, the length of the bit sequence to be encoded is determined based on the length of the second shortened sequence L2, the number of rows in the PCM mb, the number of columns in the PCM nb, and the boost value Z. The length B of the bit sequence to be encoded is an integer less than (nb-mb-L2)*Z and greater than or equal to (nb-mb-L2-1)*Z.

[0195] Wherein, the length of the second shortened sequence L2 is an integer greater than 0 and less than (nb-mb), mb and nb are integers greater than 0, and nb is greater than mb; the boost value Z is an integer greater than 0.

[0196] Since the length B of the bit sequence to be encoded is an integer less than (nb-mb-L2)*Z and greater than or equal to (nb-mb-L2-1)*Z, it is necessary to zero-padded the bits to be encoded to a length of kb*Z.

[0197] The positions for zero-padding bits are the codeword bit positions corresponding to the shortened systematic column in the shortened sequence, plus the additional padding positions. Specifically, the number of zero-padding bits corresponding to the L2 elements of the second shortened systematic column is L2*Z, where L2 equals the number of elements in the second shortened sequence. The additional zero-padding bits are kb*ZB-L2*Z zero bits padded at preset positions when kb*Z>B+L2*Z. In one example, the additional padding positions are at codeword positions with indices B+1 to Kb*Z, and the codeword positions with indices Kb*Z+1 to Kb*Z are the codeword bit positions corresponding to the shortened systematic column. Here, Kb = kb-L2.

[0198] In one example, the bit sequence to be encoded is represented as a = {a0, a1, ..., a...} B-1 The extra padding positions are at codeword positions from index B+1 to Kb*Z, at which point a′={a0,a1,...,a B-1 ,0 B ,0 B+1 ,...,0 Kb*Z-1}; Shorten the sequence so that the elements are the last L2 column of the system column, and you get a″={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 Kb*Z-1 ,…,0 kb*Z-1 The positions of the padding zero bits are known at both the transmitting and receiving ends. The Kb*ZB padding zero bits may be omitted when the first communication node sends encoded data to the second communication node.

[0199] 1. Obtain the zero-padded bit sequence to be encoded based on the determined second shortened sequence, PCM, and boost value;

[0200] The length of the bit sequence to be encoded after zero padding is kb*Z, and the position of the zero-padded bits is the position of the codeword bit corresponding to the shortened system column in the shortened sequence.

[0201] In one example, the bit sequence to be encoded is represented as a = {a0, a1, ..., a...} B-1}, shorten the sequence to the last L columns of the system column, and you get the zero-padded bit sequence a′={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 kb*Z-1}

[0202] Second: Encode the zero-padded bit sequence to be encoded according to PCM and the boost value to obtain an encoded bit sequence of length N.

[0203] In this operation, the zero-padded bit sequence to be encoded is described as a′={a0,a1,…,a B-1 ,0 B ,0 B+1 ,…,0 kb*Z-1 The output encoded bit sequences are b = {b0, b1, ..., b}. N-1 The length of the encoded bit sequence is N bits.

[0204] For the zero-padded bit sequence a′ to be encoded, the zero-padded bit sequence is encoded according to PCM and the boost value Z to obtain the encoded bit sequence b. The encoded bit sequence b is obtained by encoding according to the following process:

[0205] Based on the boost value Z, the shortened PCM is matrix-extended to obtain the extended PCM corresponding to the zero-padded bit sequence to be encoded.

[0206] The zero-padded bit sequence to be encoded is encoded using extended PCM to obtain an encoded bit sequence of length N.

[0207] Wherein, according to the PCM H b And the boost value Z, determine the extended PCM as H, that is, H b Replace the elements of the zero-indexed square matrix with a Z*Z zero-indexed matrix, and then... b The elements of the identity matrix that are cyclically shifted are replaced with a Z*Z cyclic shift matrix of the identity matrix (the shift value is equal to the element value, and can be a rightward or leftward cyclic shift). Similarly, each extended PCM includes a system column matrix H. s And check column matrix H p That is, the extended PCM has the following structure: [H s H p ].

[0208] According to PCM H bs The boost value Z is used to encode the bit sequence of information to be encoded, resulting in the encoded bit sequence. It can be understood that the encoded bit sequence can be calculated using the extended PCM H. v = H s ×a′,p=(H p ) -1 ×v,

[0209] Therefore, the encoded bit sequence can be represented as The length of the encoded bit sequence is N.

[0210] In the process of sending all bits of the encoded bit sequence to the second communication node in S5, or sending a portion of the encoded bit sequence, bit selection is performed on the encoded bit sequence according to at least one of the following to obtain a second encoded bit sequence of length E: punctured bit position, zero-padding shortened bit position, code rate, and length of the bit sequence to be encoded.

[0211] Example 5

[0212] In this embodiment, the operation of obtaining the encoded bit sequence based on the second shortened sequence, PCM, boost value, and the parameters of the bit sequence to be encoded may include, but is not limited to:

[0213] 1. Obtain the shortened PCM based on the determined second shortened sequence and PCM;

[0214] Second: Encode the bit sequence to be encoded based on the shortened PCM and the boost value to obtain an encoded bit sequence of length N.

[0215] The process of encoding the bit sequence to be encoded based on the shortened PCM and the boost value to obtain an encoded bit sequence of length N is as follows: the shortened PCM is matrix-extended based on the boost value Z to obtain the extended PCM corresponding to the bit sequence to be encoded; the bit sequence to be encoded is then encoded based on the extended PCM to obtain an encoded bit sequence of length N.

[0216] 1. Obtain the shortened PCM based on the determined second shortened sequence and PCM.

[0217] The shortened PCM is a matrix formed by excluding the systematic columns indicated by the elements in the shortened sequence; in one example, the PCM is described as H b ,

[0218] The second shortened sequence S can be described as S = [s0, s1, ..., s2] L2-1 ], shortened PCM H bs It can be described as:

[0219] Where, [s0,s1,...,s L2-1 Each element in the symbol is a distinct integer greater than or equal to 0 and less than kb, and "\" represents the exclusion symbol.

[0220] Second: Encode the bit sequence to be encoded based on the shortened PCM and the boost value to obtain an encoded bit sequence of length N.

[0221] In this operation, the input bit sequence to be encoded can be described as a = {a0, a1, ..., a...} B-1In one example, B = Kb * Z, and the product of the shortened PCM system column number Kb and the boost value Z is equal to the length B of the bit sequence to be encoded.

[0222] For the bit sequence a to be encoded, the bit sequence is encoded according to the shortened PCM and the boost value Z to obtain the encoded bit sequence b. The encoded bit sequence b is obtained by encoding according to the following process:

[0223] The shortened PCM is matrix-expanded based on the boost value Z to obtain the extended PCM corresponding to the bit sequence to be encoded.

[0224] The extended PCM is used to encode the bit sequence to be encoded to obtain an encoded bit sequence of length N.

[0225] Among them, according to the shortened PCM H bs And the boost value Z, determine the extended PCM as H, that is, H bs Replace the elements of the zero-indexed square matrix with a Z*Z zero-indexed matrix, and then... bs The elements of the identity matrix that are cyclically shifted are replaced with a Z*Z cyclic shift matrix of the identity matrix (the shift value is equal to the element value, and can be a rightward or leftward cyclic shift). Similarly, each extended PCM includes a system column matrix H. s And check column matrix H p That is, the extended PCM has the following structure: [H s H p ].

[0226] According to the shortened PCM H bs The boost value Z is used to encode the bit sequence of information to be encoded, resulting in the encoded bit sequence. It can be understood that the encoded bit sequence can be calculated using the extended PCM H. v = H s ×a, p=(H p ) -1 ×v,

[0227] Therefore, the encoded bit sequence can be represented as The length of the encoded bit sequence is N.

[0228] In this embodiment, LDPC code shortening is an effective means of adjusting the code rate. It is achieved by selectively omitting some codeword positions while maintaining the excellent performance characteristics of the LDPC code as much as possible. Specifically, the shortening operation involves selecting certain positions in the codeword and deciding not to send information at these positions. Thus, the shortened positions are known at both the transmitting and receiving ends. Typically, the shortened positions are set to 0, and these shortened positions do not participate in the encoding process. If the shortened position is the last L columns of the system column in the PCM, then the (Kb-L)*Z+1 to Kb*Z bits in the codeword are known at both the transmitting and receiving ends. Since an element in the shortened sequence refers to a column in the PCM, an element in the PCM corresponds to a shortening of the boost value Z bits.

[0229] Example 6

[0230] In this embodiment, upon receiving the data sequence to be decoded, the second communication node can perform data processing to obtain the original bit sequence to be encoded. Figure 8 shows a flowchart of a data processing method provided in this application embodiment. The execution entity of this LDPC decoding method can be the aforementioned second communication node, or other electronic devices with certain computing capabilities. These electronic devices may include, for example, terminal devices, servers, or other processing devices. Terminal devices can be cellular phones, cordless phones, Session Initiation Protocol (SIP) phones, Wireless Local Loop (WLL) stations, Personal Digital Assistants (PDAs), handheld devices with wireless communication capabilities, computing devices, or other processing devices connected to a wireless modem, in-vehicle devices, wearable devices, electronic devices in 5G networks, or future 5G or higher networks, etc. Specifically, this is achieved through the following operations:

[0231] S21: Receive all or part of the data sequence to be decoded, corresponding to the encoded bit sequence;

[0232] S22: Obtain the first shortened sequence based on the lift value;

[0233] S23: Determine the second shortened sequence based on at least the following parameters: number of PCM rows, number of PCM columns, first shortened sequence, number of punctures in PCM system columns, and bitrate;

[0234] S24: Based on at least the following parameters: a second shortened sequence, PCM, boost value, and a data sequence to be decoded, decode all or part of the received encoded bit sequence to obtain the decoded bit sequence.

[0235] In one embodiment, S22 and S23 can be combined into one operation, namely, determining the shortened sequence based on at least the following parameters: the number of PCM rows, the number of PCM columns, the boost value, the number of PCM system column punctures, and the bit rate. The shortened sequence here can be understood as a second shortened sequence.

[0236] The first and second shortened sequences are identical to the data of the first processing node. The first shortened sequence is an ordered set of index values, and the second shortened sequence is a subset of the first shortened sequence. Elements in both sequences indicate the position where the corresponding PCM system column should be shortened. The number of elements in the first shortened sequence, L1, is an integer less than the number of PCM columns, kb, and greater than or equal to 0. The number of elements in the second shortened sequence, L2, is an integer less than or equal to L1 and greater than or equal to 0. The PCM is a matrix of size mb*nb. The system column size, kb, is the difference between nb and mb, where mb and nb are both integers greater than 0, and nb is greater than mb. The boost value, Z, is an integer greater than 0. The length of the decoded bit sequence, B, is an integer greater than 0. The bit rate, R, is a real number greater than 0 and less than 1. The PCM system punched column, PunN, is a non-negative integer less than kb.

[0237] Here, for the received data sequence to be decoded, LDPC decoding can be performed on the data sequence to be decoded based on the second shortened sequence, PCM, and boost value to obtain the same decoded sequence as the bit sequence data to be encoded. The process of processing the encoded bit sequence is equivalent to the decoding process based on the LDPC code, which corresponds to the encoding process, and will not be elaborated here.

[0238] This application also provides an encoding device. Figure 9 is a schematic diagram of an encoding device provided in an embodiment of this application. As shown in Figure 9, the encoding device includes:

[0239] The first sequence determination module 310 is configured to determine the shortened sequence based on the number of rows of the parity check matrix PCM, the number of columns of the PCM, the boost value, the number of punctures in the system column of the PCM, and the bit rate.

[0240] The second sequence determination module 320 is configured to determine the bit sequence to be encoded based on the length of the shortened sequence, the number of rows of the PCM, the number of columns of the PCM, and the boost value.

[0241] The encoding module 330 is configured to encode the bit sequence to be encoded according to the shortened sequence, the PCM, and the boost value to obtain the encoded bit sequence;

[0242] Wherein, the boost value and the length of the bit sequence to be encoded are both positive integers; the code rate is a real number greater than 0 and less than 1; the number of punctures in the system column of the PCM is a non-negative integer less than the size of the system column of the PCM, the size of the system column is the difference between the number of columns and the number of rows of the PCM, the number of rows and the number of columns of the PCM are both integers greater than 0, and the number of columns of the PCM is greater than the number of rows of the PCM; the length of the encoded bit sequence is an integer greater than the length of the bit sequence to be encoded; the elements in the shortening sequence are used to indicate the position where the system column of the PCM is shortened, and the number of elements in the shortening sequence is an integer less than the size of the system column of the PCM and greater than or equal to 0.

[0243] In one embodiment, the first sequence determination module 310 is specifically configured as follows:

[0244] The first shortened sequence is obtained based on the lift value;

[0245] Determine the second shortened sequence based on the first shortened sequence;

[0246] Wherein, the second shortening sequence is a subset of the first shortening sequence, and the elements in both the first and second shortening sequences are used to indicate the position where the system column of the PCM is shortened. The number of elements in the first shortening sequence is an integer greater than 0 that is smaller than the size of the system column of the PCM. The number of elements in the second shortening sequence is less than or equal to the number of elements in the first shortening sequence and is an integer greater than or equal to 0. The second shortening sequence is the determined shortening sequence.

[0247] In one embodiment, the apparatus further includes a transmission module configured to transmit all or part of the bits of the encoded bit sequence to a second communication node.

[0248] In one embodiment, obtaining the first shortened sequence based on the boost value includes:

[0249] The first shortening sequence is obtained based on the preset range or preset value of the increase value;

[0250] Each preset range or preset value corresponds to a first shortening sequence.

[0251] In one embodiment, determining the second shortened sequence based on the first shortened sequence includes one of the following:

[0252] The first L2 elements of the first shortened sequence constitute the second shortened sequence;

[0253] The last L2 elements of the first shortened sequence constitute the second shortened sequence; or

[0254] The L2 elements at preset positions of the first shortened sequence constitute the second shortened sequence.

[0255] In one embodiment, the number of elements in the shortened sequence is determined according to at least one of the following:

[0256] Preset value; or

[0257] The number of rows, the number of columns, the number of punches in the system columns of the PCM, and the bitrate.

[0258] In one embodiment, L2 is obtained by rounding up or down the quotient of the first value and the second value;

[0259] Wherein, the first value is equal to the difference between the third value and the fourth value; the third value is equal to the difference between the number of columns of the PCM and the number of rows of the PCM; the fourth value is equal to the product of the bitrate and the fifth value; the fifth value is equal to the difference between the number of columns of the PCM and the number of punches in the system columns of the PCM; and the second value is equal to the difference between 1 and the bitrate.

[0260] In one embodiment, the apparatus further includes a boost value determination module configured to determine a boost value based on at least one of the following: a signaling indication, a preset value, or a parallelism requirement.

[0261] In one embodiment, obtaining a first shortening sequence based on a preset range or preset value of the increase value includes:

[0262] The first shortening sequence is determined according to a preset table or preset procedure, wherein the preset table or preset procedure is used to indicate the shortening sequence corresponding to each increase value interval.

[0263] In one embodiment, the second sequence determination module 320 is specifically configured as follows:

[0264] The length of the bit sequence to be encoded is determined based on the length of the shortened sequence, the number of rows of the PCM, the number of columns of the PCM, and the boost value.

[0265] Based on the length of the bit sequence to be encoded, obtain a bit sequence of the corresponding length.

[0266] In one embodiment, the encoding module 330 is specifically configured as follows:

[0267] The zero-padded bit sequence to be encoded is determined based on the shortened sequence, PCM, and boost value; wherein the length of the zero-padded bit sequence to be encoded is the product of the size of the system column and the boost value;

[0268] The zero-padded bit sequence to be encoded is encoded according to the PCM and the boost value to obtain an encoded bit sequence of length N.

[0269] In one embodiment, the encoding module 330 is specifically configured to: perform matrix expansion on the PCM according to the boost value to obtain the extended PCM corresponding to the zero-padded bit sequence to be encoded;

[0270] The zero-padded bit sequence to be encoded is encoded according to the extended PCM to obtain an encoded bit sequence of length N.

[0271] In one embodiment, the encoding module 330 is specifically configured as follows:

[0272] The shortened PCM is obtained based on the shortened sequence and the PCM;

[0273] The shortened PCM and the boost value are used to encode the bit sequence to be encoded, resulting in an encoded bit sequence of length N.

[0274] In one embodiment, the bit sequence to be encoded is encoded according to the shortened PCM and the boost value to obtain an encoded bit sequence of length N, including:

[0275] Based on the boost value, the shortened PCM is matrix-expanded to obtain the extended PCM corresponding to the bit sequence to be encoded.

[0276] The bit sequence to be encoded is encoded according to the extended PCM to obtain an encoded bit sequence of length N.

[0277] The encoding device proposed in this embodiment belongs to the same inventive concept as the encoding method proposed in the above embodiments. Technical details not described in detail in this embodiment can be found in any of the above embodiments. Furthermore, this embodiment has the same beneficial effects as the encoding method.

[0278] This application also provides a decoding device. Figure 10 is a schematic diagram of the structure of a decoding device provided in an embodiment of this application. As shown in Figure 10, the decoding device includes:

[0279] The receiving module 410 is configured to receive a data sequence to be decoded, wherein the data sequence to be decoded includes all or part of the data of the encoded bit sequence;

[0280] The sequence determination module 420 is configured to determine the shortened sequence based on the number of rows, the number of columns, the boost value, the number of punctures in the system column of the PCM, and the bit rate of the parity check matrix PCM.

[0281] The decoding module 430 is configured to decode the data sequence to be decoded based on the shortened sequence, the PCM, the boost value, and the data sequence to be decoded, to obtain a decoded bit sequence;

[0282] Wherein, the boost value is a positive integer; the code rate is a real number greater than 0 and less than 1; the number of punctures in the system column of the PCM is a non-negative integer less than the size of the system column of the PCM, the size of the system column is the difference between the number of columns and the number of rows of the PCM, both the number of rows and the number of columns of the PCM are positive integers, and the number of columns of the PCM is greater than the number of rows of the PCM; the length of the encoded bit sequence is an integer greater than the length of the bit sequence to be encoded; the elements in the shortening sequence are used to indicate the position where the system column of the PCM is shortened, and the number of elements in the shortening sequence is an integer less than the size of the system column of the PCM and greater than or equal to 0.

[0283] In one embodiment, the sequence determination module 420 is specifically configured as follows:

[0284] The first shortened sequence is obtained based on the lift value;

[0285] The second shortening sequence is determined based on the number of rows of the PCM, the number of columns of the PCM, the first shortening sequence, the number of punches in the system columns of the PCM, and the bit rate;

[0286] Wherein, the second shortening sequence is a subset of the first shortening sequence, and the elements in both the first and second shortening sequences are used to indicate the position where the PCM system column is shortened. The number of elements (L1) in the first shortening sequence is an integer greater than 0 that is less than the size (kb) of the PCM system column. The number of elements (L2) in the second shortening sequence is less than or equal to the number of elements in the first shortening sequence and is an integer greater than or equal to 0. The second shortening sequence is the determined shortening sequence.

[0287] The encoding device proposed in this embodiment belongs to the same inventive concept as the decoding method proposed in the above embodiments. Technical details not described in detail in this embodiment can be found in any of the above embodiments. Furthermore, this embodiment has the same beneficial effects as the decoding method.

[0288] This application also provides a communication node. Figure 11 is a schematic diagram of the hardware structure of a communication node provided in an embodiment of this application. As shown in Figure 11, the communication node provided in this application includes a processor 510 and a memory 520. The processor 510 in the communication node can be one or more, and Figure 11 shows one processor 510 as an example. The memory 520 is configured to store one or more programs. The one or more programs are executed by the one or more processors 510, so that the one or more processors 510 implement the encoding method or decoding method as described in the embodiment of this application.

[0289] The communication node also includes: a communication device 530, an input device 540, and an output device 550.

[0290] The processor 510, memory 520, communication device 530, input device 540 and output device 550 in the communication node can be connected by a bus or other means. Figure 11 shows an example of connection by bus.

[0291] Input device 540 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the communication node. Output device 550 may include display devices such as a display screen.

[0292] The communication device 530 may include a receiver and a transmitter. The communication device 530 is configured to perform information transmission and reception communication under the control of the processor 510.

[0293] The memory 520, as a computer-readable storage medium, can be configured to store software programs, computer-executable programs, and modules, such as program instructions / modules (e.g., modules in an encoding device) corresponding to the encoding and decoding methods described in the embodiments of this application. The memory 520 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required for at least one function; the data storage area may store data created based on the use of the communication node, etc. Furthermore, the memory 520 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 520 may further include memory remotely located relative to the processor 510, and these remote memories can be connected to the communication node via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0294] This application also provides a storage medium storing a computer program, which, when executed by a processor, implements any of the encoding or decoding methods described in this application.

[0295] This application also provides a computer program storage product, including a computer program / instruction, which, when executed by a processor, implements any of the encoding or decoding methods described in this application.

[0296] The computer storage medium in this application embodiment can be any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. The computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0297] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit programs for use by or in connection with an instruction execution system, apparatus, or device.

[0298] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, radio frequency (RF), etc., or any suitable combination thereof.

[0299] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0300] This application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the encoding and decoding methods described in any of the above embodiments.

[0301] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0302] Those skilled in the art will understand that the term user terminal encompasses any suitable type of wireless user equipment, such as mobile phones, portable data processing portable web browsers, or vehicle-mounted mobile stations.

[0303] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0304] Embodiments of this application can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0305] Any block diagram of logical flow in the accompanying drawings of this application may represent program operations, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program operations and logic circuits, modules, and functions. Computer programs may be stored in memory. Memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Video Disc (DVD) or Compact Disk (CD), etc.). Computer-readable media may include non-transitory storage media. Data processors may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and processors based on multi-core processor architectures.

Claims

1. An encoding method applied to a first communication node, comprising: The shortened sequence is determined based on the number of rows in the parity check matrix (PCM), the number of columns in the PCM, the boost value, the number of punctures in the systematic column of the PCM, and the bit rate. The bit sequence to be encoded is determined based on the length of the shortened sequence, the number of rows of the PCM, the number of columns of the PCM, and the boost value. The bit sequence to be encoded is encoded according to the shortened sequence, the PCM, and the boost value to obtain the encoded bit sequence. Wherein, both the boost value and the length of the bit sequence to be encoded are positive integers; The bit rate is a real number greater than 0 and less than 1; the number of punctures in the system column of the PCM is a non-negative integer less than the size of the system column of the PCM, the size of the system column is the difference between the number of columns and the number of rows of the PCM, both the number of rows and the number of columns of the PCM are integers greater than 0, and the number of columns of the PCM is greater than the number of rows of the PCM; the length of the encoded bit sequence is an integer greater than the length of the bit sequence to be encoded; the elements in the shortened sequence are used to indicate the position where the system column of the PCM is shortened, and the number of elements in the shortened sequence is an integer less than the size of the system column of the PCM and greater than or equal to 0.

2. The method according to claim 1, wherein, The shortened sequence is determined based on the number of rows of the PCM, the number of columns of the PCM, the boost value, the number of punctures in the systematic columns of the PCM, and the bit rate, including: The first shortened sequence is obtained based on the lift value; Determine the second shortened sequence based on the first shortened sequence; Wherein, the second shortening sequence is a subset of the first shortening sequence, and the elements in both the first and second shortening sequences are used to indicate the position where the system column of the PCM is shortened. The number of elements in the first shortening sequence is an integer greater than 0 that is smaller than the size of the system column of the PCM. The number of elements in the second shortening sequence is less than or equal to the number of elements in the first shortening sequence and is an integer greater than or equal to 0. The second shortening sequence is the determined shortening sequence.

3. The method according to claim 1, further comprising: Send all or part of the encoded bit sequence to the second communication node.

4. The method according to claim 2, wherein, The step of obtaining the first shortened sequence based on the boost value includes: The first shortening sequence is obtained based on the preset range or preset value of the increase value; Each preset range or preset value corresponds to a first shortening sequence.

5. The method according to claim 2, wherein, The step of determining the second shortened sequence based on the first shortened sequence includes one of the following: The first L2 elements of the first shortened sequence constitute the second shortened sequence; The last L2 elements of the first shortened sequence constitute the second shortened sequence; or The L2 elements at preset positions of the first shortened sequence constitute the second shortened sequence.

6. The method according to claim 1 or 5, wherein, The number of elements in the shortened sequence is determined according to at least one of the following: Preset value; or The number of rows, the number of columns, the number of punches in the system columns of the PCM, and the bitrate.

7. The method according to claim 5, wherein, L2 is obtained by rounding up or down the quotient of the first and second values; Wherein, the first value is equal to the difference between the third value and the fourth value; the third value is equal to the difference between the number of columns of the PCM and the number of rows of the PCM; the fourth value is equal to the product of the bitrate and the fifth value; the fifth value is equal to the difference between the number of columns of the PCM and the number of punches in the system columns of the PCM; and the second value is equal to the difference between 1 and the bitrate.

8. The method according to claim 1, further comprising: The boost value is determined based on at least one of the following: signaling indication, preset value, or parallelism requirement.

9. The method according to claim 4, wherein, The first shortening sequence is obtained based on the preset range or preset value of the increase value, including: The first shortening sequence is determined according to a preset table or preset procedure, wherein the preset table or preset procedure is used to indicate the shortening sequence corresponding to each increase value interval.

10. The method according to claim 1, wherein, The bit sequence to be encoded is determined based on the length of the shortened sequence, the number of rows in the PCM, the number of columns in the PCM, and the boost value, including: The length of the bit sequence to be encoded is determined based on the length of the shortened sequence, the number of rows of the PCM, the number of columns of the PCM, and the boost value. Based on the length of the bit sequence to be encoded, obtain a bit sequence of the corresponding length.

11. The method according to claim 1, wherein, The bit sequence to be encoded is encoded according to the shortened sequence, the PCM, and the boost value to obtain the encoded bit sequence, including: The zero-padded bit sequence to be encoded is determined based on the shortened sequence, PCM, and boost value; wherein the length of the zero-padded bit sequence to be encoded is the product of the size of the system column and the boost value; The zero-padded bit sequence to be encoded is encoded according to the PCM and the boost value to obtain an encoded bit sequence of length N.

12. The method according to claim 11, wherein, The zero-padded bit sequence to be encoded is encoded according to the PCM and the boost value to obtain an encoded bit sequence of length N, including: The PCM is matrix-expanded according to the boost value to obtain the extended PCM corresponding to the zero-padded bit sequence to be encoded. The zero-padded bit sequence to be encoded is encoded according to the extended PCM to obtain an encoded bit sequence of length N.

13. The method according to claim 1, wherein, The bit sequence to be encoded is encoded according to the shortened sequence, the PCM, and the boost value to obtain the encoded bit sequence, including: The shortened PCM is obtained based on the shortened sequence and the PCM; The shortened PCM and the boost value are used to encode the bit sequence to be encoded, resulting in an encoded bit sequence of length N.

14. The method according to claim 13, wherein, The shortened PCM and the boost value are used to encode the bit sequence to be encoded, resulting in an encoded bit sequence of length N, including: Based on the boost value, the shortened PCM is matrix-expanded to obtain the extended PCM corresponding to the bit sequence to be encoded. The bit sequence to be encoded is encoded according to the extended PCM to obtain an encoded bit sequence of length N.

15. A decoding method applied to a second communication node, comprising: Receive a data sequence to be decoded, the data sequence to be decoded including all or part of the data of the encoded bit sequence; The shortened sequence is determined based on the number of rows in the parity check matrix (PCM), the number of columns in the PCM, the boost value, the number of punctures in the systematic column of the PCM, and the bit rate. Based on the shortened sequence, the PCM, the boost value, and the data sequence to be decoded, the data sequence to be decoded is decoded to obtain the decoded bit sequence; Wherein, the promotion value is a positive integer; The bit rate is a real number greater than 0 and less than 1; the number of punctures in the system column of the PCM is a non-negative integer less than the size of the system column of the PCM, the size of the system column is the difference between the number of columns and the number of rows of the PCM, both the number of rows and the number of columns of the PCM are integers greater than 0, and the number of columns of the PCM is greater than the number of rows of the PCM; the length of the encoded bit sequence is an integer greater than the length of the bit sequence to be encoded; the elements in the shortened sequence are used to indicate the position where the system column of the PCM is shortened, and the number of elements in the shortened sequence is an integer less than the size of the system column of the PCM and greater than or equal to 0.

16. The method according to claim 15, wherein, The shortened sequence is determined based on the number of rows of the PCM, the number of columns of the PCM, the boost value, the number of punctures in the systematic columns of the PCM, and the bit rate, including: The first shortened sequence is obtained based on the lift value; The second shortening sequence is determined based on the number of rows of the PCM, the number of columns of the PCM, the first shortening sequence, the number of punches in the system columns of the PCM, and the bit rate; Wherein, the second shortening sequence is a subset of the first shortening sequence, and the elements in both the first and second shortening sequences are used to indicate the position where the system column of the PCM is shortened. The number of elements in the first shortening sequence is an integer greater than 0 that is smaller than the size of the system column of the PCM. The number of elements in the second shortening sequence is less than or equal to the number of elements in the first shortening sequence and is an integer greater than or equal to 0. The second shortening sequence is the determined shortening sequence.

17. A communication node, comprising: Memory, and one or more processors; The memory is configured to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the encoding method as described in any one of claims 1-14 or the decoding method as described in any one of claims 15-16.

18. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the encoding method as described in any one of claims 1-14 or the decoding method as described in any one of claims 15-16.

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