High freqeuncy reference signal calibration and distribution

Abstract

A reference signal calibration and distribution system (10) is configured to time calibrate and distribute high frequency reference signals on an electronic circuit A low frequency synchronization (synch) signal is derived from the high frequency reference signal, and edge- synchronized to it. Both the low frequency synch signal and the high frequency reference signal are distributed to a plurality of termination points, the latter through a network (22) of adjustable-delay buffers. The former is distributed using a central buffer (16) and passive distribution network, with series RC terminations (38), where C is high ohmic at the synchronization frequency. The high frequency reference signal is sampled by the low frequency synch signal at a subset of the termination points. Based on the sampled voltages, the delays of buffers in the high frequency reference signal distribution network (22) are adjusted, to make sampled voltages near the target, close to mid-range.

Description

[0001] HIGH FREQEUNCY REFERENCE SIGNAL CALIBRATION AND DISTRIBUTION

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to high speed electronics, and in particular to a system and method of calibrating and distributing high frequency reference signals in an electronic circuit.

[0004] BACKGROUND

[0005] Wireless communication networks, deployed around the world, continue to grow in capacity and sophistication. One clear trend in wireless communication network development is the use of higher frequencies for transmissions across the air interface. The Third Generation Partnership Project (3GPP), which develops and promulgates the industry standards governing the structure and interoperability of wireless communication networks, has defined two frequency ranges: FR1 spans 410 - 7125 MHz and FR2 spans 24.25-52.6 GHz. In ongoing research and development, sub-THz bands ( / .e., hundreds of GHz) are of interest. By increasing the carrier frequencies, very wide frequency bands become available, with the potential for reaching extremely high data rates. Also, RADAR and imaging applications benefit from high frequencies and bandwidths, with the potential for very high resolution measurements.

[0006] At these high frequencies, wavelengths are small. Correspondingly, antenna elements are small, and each captures less energy. For example, at 150 GHz an antenna of half a wavelength is 1 mm, and at 300 GHz it is just 0.5 mm. Accordingly, more antenna elements are required to cover the same area with the same link performance and the same inter-site distance.

[0007] Advanced Antenna System (AAS) implementations contemplate hundreds, or even thousands, of antenna elements. Because each antenna element (or subarray of antenna elements) requires a dedicated power amplifier (PA) and receiver chain, the proliferation of antenna elements increases the number of data streams to be processed, increasing the system computational load. Another problem with Radio Frequency (RF) carriers at these high frequencies is that they suffer higher path loss, and hence have limited range, compared to conventional wireless telecom operating frequencies. Beamforming is one technique featured in 5G and 6G, to improve both coverage and capacity.

[0008] Beamforming refers to the use of antennas having increased and controllable directionality, whereby an RF transmission (or reception sensitivity) is narrowly focused, and is “aimed” in a specific direction. This is enabled by transmitting or receiving signals with controlled relative phase and gain in the antenna elements (or subarrays of antenna elements). The relative phases of, e.g., transmit signals sent to each antenna element are controlled to create constructive or destructive interference, thus amplifying the signal in some directions, and attenuating it in others, and hence controlling the direction in which the beam is transmitted. Similar phase manipulation of signals from antenna elements (or subarrays) in a receive antenna can also result in beamforming the antenna array for receiving signals. FIG. 1 shows how a successively larger phase shift at each of adjacent antenna elements results in a directionally steered RF beam.

[0009] Because beamforming combines the outputs of multiple antenna elements (or subarrays), it increases antenna gain, concentrating greater RF signal energy towards a receiver. This mitigates the inherent path loss of higher frequency carrier signals and restores the rated equivalent isotropic radiated power (EIRP) rating of base stations operating at sub- THz frequencies to usable levels.

[0010] With modern integrated circuit (IC) technology, the electronics for a sub-THz antenna array can be integrated, with many antenna channels in each IC. For example, at 300 GHz, an 8x8 mm IC can drive an antenna array of the same size having 16x16 antenna elements. The IC should then have 256 receivers or transmitters (or even 512, if dual polarization is supported).

[0011] To achieve the correct beam shape and direction, it is important that the signal phases of all the channels are properly aligned. At sub-THz frequencies, this presents a formidable challenge. In the example above, signals at 300 GHz are needed, at 256 different places distributed over an 8x8 mm chip, and they must be well phase-aligned to maintain performance. For example, a static phase misalignment of + / - 20 degrees may be allowed for each channel; to maintain the array gain and beam direction in reasonable bounds, this corresponds to no more than + / - 185 fs time error.

[0012] One of the key sources for static time misalignment is local oscillator (LO) reference signal distribution over the IC. Other sources are mismatches in the LO signal generation based on a reference signal, using frequency multipliers or phase locked loops (PLL), and mismatches between signal paths of a receiver or transmitter. The larger the chip and the higher the operating frequency, the more difficult it is to obtain sufficient synchronization accuracy of all of these parts. In this case, more calibration is required, causing overhead in usage of resources, increased complexity of the system, and increased power consumption.

[0013] Distributing a very high frequency reference signal (e.g., clock) to a large plurality of points on an IC, while maintaining phase coherence and mitigating clock skew, stands as a major challenge in Radio Frequency Integrated Circuit (RFIC) design.

[0014] The Background section of this document is provided to place aspects of the present disclosure in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section. SUMMARY

[0015] The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key / critical elements of aspects of the disclosure or to delineate the scope of the disclosure. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[0016] According to aspects of the present disclosure described and claimed herein, a reference signal calibration and distribution system is configured to time calibrate and distribute high frequency reference signals on an electronic circuit. A low frequency synchronization (synch) signal is derived from a high frequency reference signal, and edge-synchronized to it. Both the low frequency synch signal and the high frequency reference signal are distributed to a plurality of termination points, the latter through a network of adjustable-delay buffers. The former is distributed using a central buffer and passive distribution network, with series RC terminations at the end points, where C is high ohmic at the synch fundamental frequency. The high frequency reference signal is sampled by the low frequency synch signal at a subset of the termination points. Based on the sampled voltages, the delays of buffers in the high frequency reference signal distribution network are adjusted, to make sampled voltages near a target, close to mid-range. The central buffer is based on a CMOS inverter or chain of inverters. The transistor sizes of the final buffer stage are chosen so that one transistor, typically the NMOS, has higher drive strength than the other, typically the PMOS, to speed up the signal transition in the signal edge used for sampling.

[0017] One aspect relates to a method of time calibrating and distributing high frequency reference signals in an electronic circuit. A high frequency reference signal is received. A preliminary low frequency synchronization signal is derived by dividing the high frequency reference signal by a predetermined factor. The derived preliminary low frequency synchronization signal is sampled using the high frequency reference signal, to generate a low frequency synch signal, the edges of which are synchronized to the high frequency reference signal. The high frequency reference signal is distributed to a plurality of termination points on the integrated circuit through a network of buffers, at least some of which have adjustable delays. The low frequency synch signal is distributed to a subset of the plurality of termination points from a centrally placed driver. At the subset of the plurality of termination points, the terminal high frequency reference signals are sampled using the low frequency synch signal. The delays of buffers in the network are adjusted such that voltages sampled from the terminal high frequency reference signals during signal transition edges are within a predetermined range.

[0018] Another aspect relates to a reference signal calibration and distribution system configured to time calibrate and distribute high frequency reference signals on an electronic circuit. The system includes: frequency division circuitry configured to receive a high frequency reference signal and output a preliminary low frequency synchronization signal by dividing the high frequency reference signal by a predetermined factor; sampling circuitry configured to sample the derived preliminary low frequency synchronization signal using the high frequency reference signal to generate a low frequency synch signal, the edges of which are synchronized to the high frequency reference signal; a network of buffers, at least some of which have adjustable delays and configured to distribute the high frequency reference signal to a plurality of termination points on the electronic circuit; a centrally placed driver circuit configured to distribute the low frequency synch signal to a subset of the plurality of termination points; sample and hold circuitry at the subset of the plurality of termination points configured to sample the terminal high frequency reference signals, using the low frequency synch signal; and control circuitry configured to adjust the delays of buffers in the network such that voltages sampled from the terminal high frequency reference signals during signal transition edges are within a predetermined range.

[0019] BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of the disclosure are shown. However, this disclosure should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

[0021] FIG. 1 is a diagram demonstrating the relationship between signal phase differences and antenna beam radiation / reception direction.

[0022] FIG. 2 is a block diagram of a reference signal calibration and distribution system on a Radio Frequency Integrated Circuit.

[0023] FIG. 3A is a block diagram of a simulation environment.

[0024] FIG. 3B is a graph of the rising edges of signals at the source and termination of the transmission line of FIG. 3A.

[0025] FIG. 3C is a graph of attenuation of the simulated signal in the transmission line of FIG. 3A vs. frequency.

[0026] FIG. 4A is a graph of the attenuation of the simulated signal in a shorter transmission line than FIG. 3A, vs. frequency.

[0027] FIG. 4B is a graph of the falling edges of signals at the source and termination of the shorter transmission line graphed in FIG. 4A.

[0028] FIG. 5A is a graph of the rise time of signal edges vs. variation in temperature of an entire transmission line.

[0029] FIG. 5B is a graph of variation in edge-crossing instant, with respect to a nominal temperature, vs. variation temperature of an entire transmission line. FIG. 6 is a block diagram of the transmission line of FIG. 2A, broken into segments with different temperature variations.

[0030] FIG. 7 is a graph showing sampling edge variation with a + / - 20% mismatch in transmission line load.

[0031] FIG. 8 is a block diagram of calibration circuitry configured to calibrate the resistance in the RC termination circuits in the system of FIG. 1.

[0032] FIG. 9 is a diagram showing one option for a passive low frequency synch signal distribution network.

[0033] FIG. 10 is a flow diagram of a method of time calibrating and distributing high frequency reference signals in an electronic circuit.

[0034] FIG. 11A is a diagram of wireless communication in a wireless communication network.

[0035] FIG. 11B is a hardware block diagram of a User Equipment operative in a wireless communication network.

[0036] FIG. 110 is a hardware block diagram of a base station operative in a wireless communication network.

[0037] DETAILED DESCRIPTION

[0038] For simplicity and illustrative purposes, the present disclosure is described by referring mainly to an exemplary aspect thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0039] FIG. 2 shows a simplified schematic of a reference signal calibration and distribution system 10 on a RFIC 8. Not shown in FIG. 2 to avoid obscuring aspects of the present disclosure, the RFIC 8 may additionally include Power Amplifiers (PA) in a transmitter chain, Low Noise Amplifiers (LNA) in a receive chain, frequency conversion mixers in both, an antenna switch, and other circuitry, as known in the art. The reference signal calibration and distribution system 10 is configured to time calibrate and distribute high frequency reference signals in any electronic circuit, and is not limited to use on an RFIC 8. However, a particularly useful application of the system 10 is in distributing a very high frequency clock signal (e.g., LO) to a large number of frequency conversion mixers on an RFIC 8.

[0040] A high frequency reference signal (ref) is input to frequency division circuitry 12 that is configured to divide the high frequency reference signal by a predetermined factor, and output a preliminary low frequency synchronization signal. The preliminary low frequency synchronization signal is input to sampling circuitry 14 that is configured to sample the preliminary low frequency synchronization signal, using the high frequency reference signal, to generate a low frequency synch signal. Due to this sampling, the edges of the low frequency synch signal are now synchronized to the high frequency reference signal.

[0041] The high frequency reference signal is distributed to a plurality of termination points on the electronic circuit by a network 22 of buffers, at least some of which have an adjustable delay. Preferably, all buffers in the network 22 have adjustable delays, so the distribution paths in the network 22 are symmetric. The buffer adjustable time delays may be provided through programmable bias and / or load capacitance.

[0042] A centrally placed driver circuit 16 is configured to distribute the low frequency synch signal to a subset of the plurality of termination points that receive the high frequency reference signal. As described further herein, in some aspects, a low frequency synch signal at one termination point may be shared with calibration circuits of nearby termination points, so not all termination points need to receive the low frequency synch signal, easing constraints on its distribution. In other aspects, all of the plurality of termination points also receive the low frequency synch signal for independent calibration ( / .e., the subset of the plurality of termination points also receiving the low frequency synch signal is an improper subset).

[0043] Sample and hold circuitry 18 at the subset of the plurality of termination points is configured to sample the terminal high frequency reference signals - that is, the high frequency reference signals at the “leaves” of the tree-structured distribution network 22 - using the rising or falling edge of the low frequency synch signal as a sample clock. A controller 20 monitors the sampled voltages, and controls the delays in the network 22 of buffers, such that voltages sampled from the terminal high frequency reference signals during signal transition edges are within a predetermined range of a target voltage - which is preferably at or near mid-way. The controller 20 contains Analog to Digital Converters (ADCs). Due to the low frequency of the low frequency synch signal, the sample rate is limited, and most low power ADC types are suitable. For instance, a Successive Approximation Register (SAR) ADC can be used. In one aspect, one ADC is used per sample and hold output; in another aspect, a single ADC is used, with a multiplexer to select the input from among the sample and hold outputs.

[0044] The centrally placed driver circuit 16 is implemented, in one aspect, as a large inverter or chain of inverters, and it drives a passive synch signal distribution network. Since this network is passive, it is not affected by mismatch between active buffers like the high frequency reference signal distribution network 22. The passive synch signal distribution network is terminated by series shunt RC components 24, 26 with high impedance at the synch signal frequency due to the capacitor C 24 being high ohmic at that frequency. For instance, the capacitor 24 may have an impedance with a magnitude of at least 5 times the resistance of the termination resistor R 26 at the synch signal frequency. The termination resistor R 26 has a suitable termination resistance to minimize signal reflections of high frequency harmonics. Although only two branches of the synch signal distribution network are depicted in FIG. 2, in general it has as many branches as the subset of terminal points to which the synch signal is distributed. Several different strategies may be deployed for executing the calibration process. According to one aspect, at start-up all buffers in the high frequency reference signal distribution network 22 start with the same control settings. A common-mode control loop then executes, which increases or decreases the settings of all buffers jointly, depending on the average of the sampled voltages. According to another aspect, differential control loops operate on different levels, for instance one loop that controls the two middle level inverters in FIG 2 in opposite directions, depending on the averages of the sampled outputs of the terminal points they influence. The combination of a common-mode loop and differential loops for the different levels is one example of a control strategy, suitable for a tree-based distribution network. Those of skill in the art may readily devise other calibration and control strategies, given the teachings of the present disclosure.

[0045] The sampling of signals is known to provide a high time resolution, as the time derivatives of the voltage transitions can be very high. For example, this technique is utilized in so-called sampling PLLs. According to aspects of the present invention, it is instead used to achieve high-accuracy time calibration with limited-resolution ADCs. For instance, if a linear transition from low to high state of the high frequency reference signal takes 10 ps, and this corresponds to full scale of a 10-bit ADC, then a Least Significant Bit (LSB) will correspond to 10 ps / 2A10 = 10 fs, which is sufficient resolution for the 300 GHz example discussed above. The accuracy is limited by the slope of the low frequency sync signal, combined with the process spread between the sample and hold circuits 18. Assuming a 10 ps transition from 100 to 700 mV, and a spread in control signal trigger level of + / -10 mV between different sample and hold circuits 18, that corresponds to + / -10 ps*10 mV 1600 mV = + / -167fs, which with small margin is sufficient even for 300 GHz operation.

[0046] The transition time of the low frequency sync signal is thus important, and simulations have been performed to investigate the step response of its distribution. FIG. 3A shows a simulation environment 30 comprising a passive low frequency synch signal distribution network on an IC. The environment 30 includes a signal generator 32, and the centrally placed driver circuit 16 implemented as a chain of inverters, in 22 nm CMOS technology. An 8 mm co-planar waveguide 36, a form of transmission line, simulates the passive distribution network for the low frequency synch signal, corresponding to an RFIC size of about 16x16 mm. Such a large RFIC would be able to drive 256 antennas in a 150 GHz array (as discussed below, a 300GHz RFIC would require half the line length, i.e., 4mm, for 256 antennas). The transmission line 36 is terminated in a representative termination load 38, comprising a 60 Q resistor 24 and a 1.6 pF capacitor 26 connected to signal ground. FIG. 3B graphs the rising edge transitions at the source and load ends of the transmission line 36. As this graph shows, the signal rise time at the driver 16 is 5 ps, and at the load 38 it is 20 ps. This is suitable for distribution of the low frequency sync signal, with the purpose of high frequency reference signal edge alignment. This transition time is sufficient for 150 GHz operation, and the 8 mm line length allows for the synchronization of high frequency reference signals on a very large RFIC driving 256 antennas. FIG. 30 graphs the signal attenuation for the 8 mm coplanar waveguide vs. frequency.

[0047] If the line length is reduced, the transition speed is increased, as the high-frequency attenuation is reduced. FIG. 4A graphs the signal attenuation for a 4 mm coplanar waveguide vs. frequency. By reducing the length of the line by half, the attenuation in dB is nominally halved. For example, FIG. 4A shows that the attenuation at 100 GHz is 6.5 dB, which is less than the attenuation of 8 dB at 50 GHz for the 8mm line, as shown in FIG. 3C. Accordingly, the low frequency synch signal edge transition time is reduced to less than half. This has been verified through simulation of the environment 30 of FIG. 3A, but using a 4 mm line in lieu of the 8 mm line 36. As the graph of FIG. 4B shows, by optimizing the drive strength of the transistors in the driver 16 and operating at the falling edges, the transition time of the low frequency synch signal at the driver 16 is reduced from the 5 ps shown in FIG. 3B, to 2.3 ps, and at the load 38 from 20 ps to 8.7 ps. These transition times support operation at 300 GHz.

[0048] FIGs. 5A and 5B show the effect of temperature variation on the low frequency sync signal distribution. A 4 mm transmission line was simulated with an ideal voltage source 32 and ideal RC load 38. For a large temperature variation of 50° C along the entire line, the rise time varies by 700 fs (FIG. 5A), and the edge-crossing instant - that is, the delay with respect to the signal edge crossing at a nominal temperature of 30° C - varies by 300 fs (FIG. 5B). However, in an RFIC driving a large antenna array, the temperature variation will not be such that some entire transmission lines will have a high temperature and some entire lines a low temperature, which is the only case in which the results from this simulation could be directly applied to find the mismatch. Instead, the temperature will vary periodically over the RFIC as power is consumed by an array of transceivers, each generating similar amounts of heat. This is especially true in a sub-THz RFIC, which will only support one beam at a time, so all transmitters will have the same nominal output amplitude.

[0049] As FIG. 6 shows, the transmission line was split into shorter segments, each with different temperatures, to investigate non-uniform temperature variation. However, in each simulation run, the average temperature across the line was 55° C. The results are listed in Table 1 below, with the temperatures in °C, and wherein the Relative Delay (in fs) is the delay with respect to the delay at a nominal temperature of 30° C. As these data show, the delay is largely insensitive to the temperature profiles, having a variation on the order of 20 fs, but mainly is dependent on the average temperature of 55° C.

[0050] Table 1 : Edge-crossing instant variation for segmented temperature profile

[0051] FIG. 7 shows the impact of + / - 20% variation in the resistor value in the RC load 38 at the terminal points of the low freguency synch signal distribution, where the signal’s edge crossing instant varies on the order of 360 fs. A resistor value mismatch in the load 38 of + / - 20% would cause a timing uncertainty egual to the entire budget at 300 GHz. Accordingly, some calibration of the load resistors 24 may be reguired, although variations as large as + / - 20% are not expected between different resistors 24.

[0052] FIG. 8 shows one example of calibration circuitry 40 configured to calibrate the resistance 24 in an RC termination circuit 38 to be within a predetermined range of values. To facilitate calibration, the RC loads 38 are arranged with the resistor 24 connected to signal ground, and the capacitor 26 connected to the transmission line 36 output. DC current is injected into the resistor 24 in the node between the capacitor 26 and resistor 24, and the voltage is measured. According to Ohm’s Law, the ratio of DC voltage to DC current is a measure of the DC resistance. According to one aspect, to ensure that all resistors 24 are measured egually, they are connected to the same central current source 42, through routing 44 over the electronic circuit. In one aspect, the current source 42 comprises an active cascode topology, created to have a high DC output resistance.

[0053] At each resistor 24, a switch 46 connects the resistor 24, mutually exclusively to resistors 24 at the other terminal points, to the current source 42 through the routing 44. At each resistor 24 there is also a connection 48 routed back to a central location, to a comparator 50 comparing the voltage to a reference level Vref. By using a central comparator 50, the problem of mismatch in offset voltage between local comparators due to variations in processes, voltage, and temperature (PVT) is avoided. Each resistor 24 is programmable, by selectively enabling resistances from a bank 24prOg of parallel instances of series shunt resistors and switches. This allows the resistance (24, 24prOg) to be programmed digitally by a controller 52 based on the comparator 50 output. After calibration, each resistor (24, 24prOg) drops close to the reference voltage when the predetermined DC current is injected, i.e., they have nearly the same DC resistance. In one aspect, the calibrated resistors (24, 24prOg) are within 5%. In another aspect, the calibrated resistors (24, 24prOg) are within 1 %.

[0054] In one aspect, dummy branches (not shown in FIG. 8), with resistors having much higher values, are switched on when an active branch is switched off, and vice versa. This ensures the same number of switches in the respective on and off states, thereby minimizing any variation of the load 38 capacitance when the resistance (24, 24prOg) requires adjustment.

[0055] In one aspect of the present disclosure, where the reference signal calibration and distribution system 10 is implemented on an RFIC driving antenna elements in beamforming operations, the effects of static errors between load resistors 24 are calibrated for in measurements when calibrating the beams of the system. The resulting beam weights take the static phase mismatch of the low frequency synch signals into account. In one aspect, this is then complemented by temperature sensors close to the load resistors 24, based on which the resistances (24, 24prOg) are adjusted to increase temperature stability. This form of calibration is not as accurate as the calibration circuitry 40 of FIG. 8, but it may simplify system design by avoiding the need for the cross-chip routing to transport the DC current and voltage for the matched resistance measurement.

[0056] When the low frequency synch signal is distributed across the electronic circuit, some coupling to the high frequency reference signal may occur, causing spurs in the latter. However, the frequency of the low frequency synch signal is many orders of magnitude lower than the high frequency reference signal. For example, the high frequency reference signal may be in the GHz range, while the low frequency synch signal may be a few kHz. When only one high frequency reference signal edge in a thousand, or one in a million, is disturbed, the spur power is very low. Still, in one aspect, to suppress such spurs, when a digital PLL is used, the Time to Digital Converter (TDC) comparison for the particular high frequency reference signal edge coinciding with the low frequency synch signal is simply discarded in the digital domain, by setting the digital phase error input to the loop filter by the TDC to zero for that clock cycle.

[0057] According to one aspect of the present disclosure, the low frequency synch signal is distributed across the electronic circuit via an H-tree network to a subset of the terminal points at which the high frequency reference signal is sampled. FIG. 9 depicts one representative example of such an H-tree network. The transmission line is branched into two at each T- shaped intersection. As a result of branching, the characteristic impedance of the following branched lines is doubled to ensure matching. In the distributing network, each T-shape should have the same length of its three arms, and then connect to next level T-branches with same shape but half the length, etc. The terminal points are thus evenly distributed over the area, and all lengths are equal from the centrally located driver circuit 16. The impedance ratio scales up by 16x for the transmission line distribution from the centrally located driver circuit 16 to the sixteen endpoints. This wide range of characteristic impedance for transmission lines can be realized by configuring the signal track width, thickness, and distance to the ground plane (the latter two by choice of metal layers). In one aspect, to accommodate the bottleneck created by the requirement of wide impedance ratio, the low frequency synch signal distribution is restricted to a proper subset of the plurality of terminal points of the high frequency reference signal, where the synchronization edge information is shared by a number of closely-spaced S / H circuits 18.

[0058] FIG. 10 is a flow diagram showing the steps in a method 100 of time calibrating and distributing high frequency reference signals in an electronic circuit. A high frequency reference signal is received (block 102), such as one derived from a crystal oscillator or the like. A preliminary low frequency synchronization signal is derived by dividing the high frequency reference signal by a predetermined factor (block 104). The derived preliminary low frequency synchronization signal is sampled using the high frequency reference signal, to generate a low frequency synch signal, the edges of which are synchronized to the high frequency reference signal (block 106). The high frequency reference signal is distributed to a plurality of termination points on the integrated circuit through a network of buffers, at least some of which have adjustable delays (block 108). The low frequency synch signal is distributed to a subset of the plurality of termination points from a centrally placed driver (block 110). At the subset of the plurality of termination points, the terminal high frequency reference signals are sampled, using the low frequency synch signal (block 112). The delays of buffers in the network are adjusted such that voltages sampled from the terminal high frequency reference signals during signal transition edges are within a predetermined range (block 114).

[0059] Those of skill in the art will recognize that the method 100 may be executed as required or desired, to calibrate the high frequency reference signal distribution network 22. For example, the method 100 may be performed as part of a power-on initialization, in response to detected temperature changes, periodically, at random, or the like.

[0060] In general, apparatuses described herein may perform the method 100 and any other processing by implementing any functional means, modules, units, or circuitry. In one aspect, for example, the apparatuses comprise respective circuits or circuitry configured to perform the steps shown in FIG. 10. The circuits or circuitry in this regard may comprise circuits dedicated to performing certain functional processing and / or one or more microprocessors in conjunction with memory. For instance, the circuitry may include one or more microprocessor or microcontrollers, as well as other digital hardware, which may include digital signal processors (DSPs), special-purpose digital logic, and the like. The processing circuitry may be configured to execute program code stored in memory, which may include one or several types of memory such as read-only memory (ROM), random-access memory, cache memory, flash memory devices, optical storage devices, etc. Program code stored in memory may include program instructions for executing one or more telecommunications and / or data communications protocols as well as instructions for carrying out one or more of the techniques described herein, in several embodiments. In embodiments that employ memory, the memory stores program code that, when executed by the one or more processors, carries out the techniques described herein. Figure 11 A is a diagram of transmissions over the air interface of a Radio Access Network (RAN) of a wireless communication network 60, such as a 3GPP 4G (Long Term Evolution, or LTE) or 5G (New Radio, or NR), or 6G network. A User Equipment (UE) 70, such as a smartphone, receives and transmits modulated RF signals, over one or more antennas, from and to a base station 80, such as an LTE eNB, an NR gNB or any RAN node serving as (part of) a base station or access point, for example an AAS installation.

[0061] One or both of the UE 70 and base station 80 includes a transceiver 72, 82 that employes a reference signal calibration and distribution system 10, configured to time calibrate and distribute high frequency reference signals on an RFIC, according to aspects of the present disclosure.

[0062] Figure 11 B is a block diagram of the UE 70 of Figure 11 A. As used herein, the term UE may refer to a user-operated telephony terminal, a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a pair of Augmented Reality (AR) or Virtual Reality (VR) glasses or headset, etc. A UE 70 may also be referred to as a radio device, a radio communication device, a wireless communication device, a wireless terminal, or simply a terminal - unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices or devices capable of machine- to-machine communication, sensors equipped with a radio network device, wireless-enabled table computers, mobile terminals, smartphones, laptop-embedded equipped (LEE), laptopmounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), and the like.

[0063] The UE 70 transmits and receives RF signals on at least one antenna 74, which may be internal or external, as indicated by dashed lines. In general, the antenna(s) 74 may implement beamforming, requiring tight control of relative phase between high frequency reference signals distributed to RF front end circuits. A transceiver 72, which includes an RFIC 8 employing a reference signal calibration and distribution system 10 according to aspects of the present disclosure (see FIG. 2), is operatively connected to the antenna(s) 74, and transmits and receives modulated RF carrier signals to and from network nodes. The transceiver 72, as well as other components of the UE 70, are controlled by processing circuitry 76. Memory 78 operatively connected to the processing circuitry 76 stores software in the form of computer instructions operative to cause the processing circuitry 76 to control the transceiver 72, including the RFIC 8. A user interface 79 may include output devices such as a display and speakers (and / or a wired or wireless connection to audio devices such as ear buds), and / or input devices such as buttons, a keypad, a touchscreen, and the like. As indicated by the dashed lines, the user interface 79 may not be present in all UEs 70; for example, UEs 70 designed for MTC, such as loT devices, may perform dedicated functions such as sensing / measuring, monitoring, meter reading, and the like, and may not have any user interface 79 features. Figure 11C is a block diagram of the base station 80 of Figure 11 A. A base station 80 - known in various network implementations as a Radio Base Station (RBS), Base Transceiver Station (BTS), Node B (NB), enhanced Node B (eNB), Next Generation Node B (gNB), or the like - is a node of a wireless communication network that implements a RAN in a defined geographic area called a cell, by providing radio transceivers to communicate wirelessly with a plurality of UEs 70. As used herein, the base station 80 may additionally or alternatively comprise an access point for a microcell, picocell, femtocell, and / or Wireless Local Area Network (WLAN) such as Wi-Fi, WiMAX, or the like.

[0064] The base station 80 transmits and receives RF signals on a plurality of antennas 84. In particular, the antennas 84 may comprise an AAS that performs beamforming. As indicated by the broken line, the antennas 84 may be located remotely from the base station 80, such as on a tower or building. A transceiver 82, which includes an RFIC 8 employing the reference signal calibration and distribution system 10 according to aspects of the present disclosure (FIG. 2), is operatively connected to the antennas 84, and transmits and receives modulated RF carrier signals to and from a plurality of UEs 70. The transceiver 82, as well as other components of the base station 80, are controlled by processing circuitry 86. Memory 88 operatively connected to the processing circuitry 86 stores instructions operative to cause the processing circuitry 86 to control the transceiver 82, including the RFIC 8. Although the memory 88 is depicted as being separate from the processing circuitry 86, those of skill in the art understand that the processing circuitry 86 includes internal memory, such as a cache memory or register file. Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry 86 to actually be executed by other hardware, perhaps remotely located (e.g., in the so-called “cloud”). Communication circuitry 89 provides one or more communication links to one or more other network nodes, propagating communications to and from UEs 70, from and to other network nodes or other networks, such as telephony networks or the Internet.

[0065] In all aspects, the processing circuitry 76, 76 may comprise any sequential state machine operative to execute machine instructions stored as machine-readable computer programs in memory 78, 88, such as one or more hardware-implemented state machines (e.g., in discrete logic, FPGA, ASIC, etc.), programmable logic together with appropriate firmware; one or more stored-program, general-purpose processors, such as a microprocessor or Digital Signal Processor (DSP), together with appropriate software; or any combination of the above.

[0066] In all aspects, the memory 78, 88 may comprise any non-transitory machine- readable media known in the art or that may be developed, including but not limited to magnetic media (e.g., floppy disc, hard disc drive, etc.), optical media (e.g., CD-ROM, DVD-ROM, etc.), solid state media (e.g., SRAM, DRAM, DDRAM, ROM, PROM, EPROM, Flash memory, solid state disc, etc.), or the like. In all aspects, the transceiver 72, 82 is operative to communicate with one or more other transceivers via a Radio Access Network (RAN) according to one or more communication protocols known in the art or that may be developed, such as IEEE 802. xx, LTE, NR, LITRAN, WiMax, or the like. The transceiver 72, 82 implements transmitter and receiver functionality appropriate to the RAN links (e.g., frequency allocations and the like).

[0067] In all aspects, the communication circuitry 89 may comprise a receiver and transmitter interface used to communicate with one or more other nodes over a communication network according to one or more communication protocols known in the art or that may be developed, such as Ethernet, TCP / IP, SONET, ATM, IMS, SIP, or the like. The communication circuitry 89 implements receiver and transmitter functionality appropriate to the communication network links (e.g., optical, electrical, and the like). The transmitter and receiver functions may share circuit components and / or software, or alternatively may be implemented separately.

[0068] Aspects of the present disclosure provide numerous advantages over the prior art, and may also provide one or more of the following technical advantage(s). The reference signal calibration and distribution system 10 described and claimed herein reduces static time errors in the high frequency reference signals - such as LO signals used in an RFIC for frequency conversion and beamforming - allowing for less calibration, larger chips, and higher carrier frequencies. The system 10 requires no additional input signals to the electronic circuit, as the synchronization signal is derived locally from the existing reference signal input. The system 10 imposes very low power consumption overhead, using a CMOS inverter-based buffer with low frequency signal and high-ohmic low-frequency load. After time calibration has been performed, the reference signal calibration and distribution system 10 can be disabled and used intermittently, triggered by, e.g., elapsed time or a change in sensed operating temperature. The system also relaxes time matching requirements on the high frequency reference signal distribution network 22, on both active and passive parts. The calibration procedure can absorb errors.

[0069] FIGs. 11B-C depict an RFIC including the reference signal calibration and distribution system 10 according to aspects of the present disclosure. Additionally, aspects of the disclosure are described herein with reference to an RFIC 8 driving antennas. This particular application is used herein to provide an enabling disclosure and full explanation of aspects of the disclosure to those of skill in the art, but it is not limiting. In general, the reference signal calibration and distribution system 10 according to aspects of the present disclosure, and / or the method 100, may be implemented in an RFIC 8 in a transceiver 72, 82; an IC other than an RFIC 8; or an electronic circuit other than an IC, such as an electronic circuit implemented on a Printed Circuit Board (PCB).

[0070] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. All references to a / an / the element, apparatus, component, means, step, etc., are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step. Any feature of any of the aspects disclosed herein may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any other aspects, and vice versa. Other objectives, features and advantages of the enclosed aspects will be apparent from the description.

[0071] The term “unit” may have conventional meaning in the field of electronics, electrical devices and / or electronic devices and may include, for example, electrical and / or electronic circuitry, devices, modules, processors, memories, logic solid state and / or discrete devices, computer programs or instructions for carrying out respective tasks, procedures, computations, outputs, and / or displaying functions, and so on, as such as those that are described herein.

[0072] As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to,” or with respect to processing circuitry, “programmed to.”

[0073] Some of the aspects contemplated herein are described more fully with reference to the accompanying drawings. Other aspects, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the aspects set forth herein; rather, these aspects are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0074] The present disclosure may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the disclosure. The present aspects are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended aspects are intended to be embraced therein.

Claims

CLAIMSWhat is claimed is:

1. A method (100) of time calibrating and distributing high frequency reference signals in an electronic circuit, characterized by: receiving (102) a high frequency reference signal; deriving (104) a preliminary low frequency synchronization signal by dividing the high frequency reference signal by a predetermined factor; sampling (106) the derived preliminary low frequency synchronization signal using the high frequency reference signal to generate a low frequency synch signal, the edges of which are synchronized to the high frequency reference signal; distributing (108) the high frequency reference signal to a plurality of termination points on the electronic circuit through a network (22) of buffers, at least some of which have adjustable delays, yielding terminal high frequency reference signals at the termination points; distributing (110) the low frequency synch signal to a subset of the plurality of termination points from a centrally placed driver (16); at the subset of the plurality of termination points, sampling (112) the terminal high frequency reference signals, using the low frequency synch signal; and adjusting (114) the delays of buffers in the network (22) such that voltages sampled from the terminal high frequency reference signals during signal transition edges are within a predetermined range.

2. The method (100) of claim 1 wherein the subset of the plurality of termination points is an improper subset of the plurality of termination points.

3. The method (100) of any preceding claim wherein distributing (110) the low frequency synch signal comprises driving the low frequency synch signal from the centrally placed driver (16) into a passive distribution network.

4. The method (100) of any preceding claim wherein the centrally placed driver (16) comprises one or a chain of CMOS inverters.

5. The method (100) of claim 4 wherein transistor sizes in a final CMOS inverter are selected such that a first transistor has a higher drive strength than a second transistor.

6. The method (100) of any preceding claim wherein distributing (110) the low frequency synch signal comprises terminating the low frequency synch signal at the subset of the plurality of termination points with series Resistance-Capacitance (RC) termination circuits (38).

7. The method (100) of claim 6 wherein the R and C component values are selected such that the capacitance is high-ohmic at the frequency of the synch signal.

8. The method (100) of claim 6 or 7 further comprising calibrating the resistances (24) at the subset of the plurality of termination points to each be within a predetermined range of values.

9. The method (100) of claim 8 wherein the predetermined range of values varies by no more than 5%.

10. The method (100) of claim 8 wherein the predetermined range of values varies by no more than 1%.11 . The method (100) of any of claims 8-10 wherein the RC termination circuits (38) are each configured with a variable resistance circuit (24, 24prOg) connected to ground, and wherein calibrating the resistances (24) comprises, sequentially for each termination point, iteratively: injecting a predetermined DC current into a node between the capacitance (26) and the variable resistance circuit (24, 24prOg); measuring a DC voltage drop between the variable resistance circuit (24, 24prOg) and ground; and adjusting a resistance value of the variable resistance circuit (24, 24prOg).

12. The method (100) of any preceding claim wherein all of the buffers in the high frequency reference signal distribution network (22) have adjustable delays.

13. A reference signal calibration and distribution system (10) on an electronic circuit, characterized by: frequency division circuitry (12) configured to receive (102) a high frequency reference signal and output a preliminary low frequency synchronization signal; sampling circuitry (14) configured to sample (104) the preliminary low frequency synchronization signal using the high frequency reference signal, to generate a low frequency synch signal; a network (22) of buffers at least some of which have adjustable delays and are configured to distribute (106) the high frequency reference signal to a plurality of termination points on the electronic circuit, yielding terminal high frequency reference signals at the termination points;a centrally placed driver circuit (16) configured to distribute (110) the low frequency synch signal to a subset of the plurality of termination points; sample and hold circuitry (18) at the subset of the plurality of termination points configured to sample (112) the terminal high frequency reference signals, using the low frequency synch signal; and control circuitry (20) configured to adjust (114) the delays of buffers in the network (22)14. The system (10) of claim 13 wherein the subset of the plurality of termination points is an improper subset of the plurality of termination points.

15. The system (10) of any of claims 13-14 further comprising a passive distribution network configured to receive the low frequency synch signal from the centrally placed driver circuit (16) and distribute it to the subset of the plurality of termination points.

16. The system (10) of claim 15 wherein the passive distribution network has an “H-tree” network topology.

17. The system (10) of any of claims 13-16 wherein the centrally placed driver circuit (16) comprises one or a chain of CMOS inverters.

18. The system (10) of claim 17 wherein transistor sizes in a final CMOS inverter are selected such that one has a higher drive strength than the other.

19. The system (10) of any of claims 13-18 further comprising series Resistance- Capacitance (RC) termination circuits (38) at the subset of the plurality of termination points.

20. The system (10) of claim 19 wherein component values of the RC termination circuits (38) are selected such that the capacitance (26) is high-ohmic at the frequency of the low frequency synch signal.

21. The system (10) of any of claims 19-20 further comprising calibration circuitry (40) configured to calibrate the resistance (24, 24prOg) in the RC termination circuits (38)20.

22. The system (10) of any of claims 19-21 wherein the RC termination circuits (38) are configured with a variable resistance circuit (24, 24prOg) connected to ground;23. A Radio Frequency Integrated Circuit, RFIC (8), comprising the reference signal calibration and distribution system (10) of any of claims 13-22.1824. A User Equipment (70) operative in a wireless communication network (60), comprising the RFIC (8) of claim 23.

25. A base station (80) operative in a wireless communication network (60), comprising a the RFIC (8) of claim 23.

26. A computer program product comprising machine readable instructions configured to, when executed on control circuitry, cause the reference signal calibration and distribution system (10) of any of claims 13-23 to execute the method (100) of any of claims 1-12.

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