Testing core die through a scribe lane with mechanical stress-free access from a seal ring

The use of a seal ring with bridge interconnect structures for core die testing addresses the challenge of restricted test pad placement, enabling stress-free and effective circuit testing in fine-pitch stacking structures.

WO2026128073A1 Publication Date: 2026-06-18QUALCOMM INC
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Patent Information

Application Number
PCT/US2025/050372
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-12-13
Filing Date
2025-10-09
Publication Date
2026-06-18

AI Technical Summary

Technical Problem

Fine-pitch stacking structures in core dies restrict test pad placement for wafer-level testing, and conventional methods like hybrid bonding and fusion bonding hinder effective circuit testing due to topographical changes and narrow scribe lanes, leading to parasitic loading and area losses.

Method used

A die with a seal ring and bridge interconnect structures across it allows mechanical, stress-free access for testing, using BEOL metal interconnects to route signals from test pads outside the seal ring to core circuits, ensuring moisture-blocking and damage resistance during singulation.

Benefits of technology

Enables effective circuit testing of core dies at the wafer-level without mechanical stress, maintaining seal ring integrity and preventing damage during singulation, while allowing for fine-pitch stacking structures.

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Abstract

A die is described. The die includes a first seal ring on a periphery of the die, which encloses a core of the die. The die also includes one or more bridge interconnect structures across the first seal ring to route a signal from a test pad outside of the first seal ring to a circuit in the core.
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