Electrode for chip packaging and chip packaging structure using the electrode

Abstract

An electrode for chip packaging is provided, the electrode comprising: a first base material, the thermal expansion coefficient of the first base material is in the range of 0-12×10 ‑6 / ℃; and a second base material, the second base material is a conductive material and the thermal conductivity of the second base material is in the range of 60-600W / m﹒ k; wherein the first base material and the second base material are mixed to form a composite material, or one of the first base material and the second base material is embedded in one or more parts of the other. A chip packaging structure is also provided, comprising: a chip; and one or more electrodes as described above connected to the chip, wherein the first base material and the second base material are connected to the chip through a welding layer or a conductive connection.

Description

Technical Field

[0001] The invention relates to a packaging electrode, in particular to an electrode used for chip packaging and a chip packaging structure using the electrode. Background Art

[0002] When power chips are used, good heat dissipation is required on the one hand. On the other hand, during thermal fatigue tests such as temperature rise and fall cycles or impact, the chip will be damaged and fail because the thermal expansion coefficient of the heat dissipation electrode does not match that of the chip.

[0003] Traditional chip packaging has two copper electrodes welded on both sides of the chip, and the whole is made of ceramic or plastic. Since copper has good heat dissipation and conductivity, but its thermal expansion coefficient is high, it is easy to pull and damage the chip during thermal fatigue tests such as temperature cycling (-40℃-85℃) or temperature shock. Using copper as an electrode is not compatible with thermal fatigue performance such as temperature cycling or temperature shock. Therefore, it is necessary to develop a chip packaging electrode to prevent the chip from being damaged and failing during the temperature cycling process. Summary of the invention

[0004] The purpose of the present invention is to provide an electrode for chip packaging to solve the problem that the chip is damaged by being pulled by the electrode during thermal fatigue such as temperature cycling or temperature shock.

[0005] To achieve the above objectives, the present invention provides an electrode for chip packaging, the electrode comprising:

[0006] The first base material has a thermal expansion coefficient in the range of 0-12×10 -6 / ℃; and

[0007] A second base material, wherein the second base material is a conductive material and has a thermal conductivity in the range of 60-600 W / m﹒ k;

[0008] The first matrix material and the second matrix material are mixed to form a composite material, or one of the first matrix material and the second matrix material is embedded in one or more locations of the other to form an electrode.

[0009] Furthermore, the first surface of the electrode exposes the first base material and the second base material.

[0010] Furthermore, at least a portion of the first matrix material has a porous interconnected structure, and the second matrix material is filled in the pores of the porous interconnected structure; or at least a portion of the second matrix material has a porous interconnected structure, and the first matrix material is filled in the pores of the porous interconnected structure.

[0011] Further, the first base material is provided with at least one pit or through hole, and the second base material is provided in the pit or through hole.

[0012] Further, the second base material is provided with at least one pit or through hole, and the first base material is provided in the pit or through hole.

[0013] Furthermore, the first base material is a metal material or a non-metal material

[0014] Preferably, the metal material is one of molybdenum, tungsten, and iron-nickel alloy, or a mixture of two or more thereof.

[0015] Preferably, the non-metallic material is one of graphite, aluminum oxide ceramics, aluminum nitride, beryllium oxide, silicon carbide, or a mixture of two or more thereof.

[0016] Furthermore, it is characterized in that the second matrix material is one of copper, aluminum, silver, and gold, or a mixture of two or more thereof, or a composite material including one of copper, aluminum, silver, and gold or two or more thereof.

[0017] Furthermore, the electrode further comprises a metal layer, and the metal layer covers at least a portion of the outer surface of the first base material.

[0018] Preferably, the material of the metal layer is copper, silver, gold, aluminum or nickel.

[0019] The present invention also provides a chip packaging structure, comprising:

[0020] Chips; and

[0021] One or more electrodes as described above are connected to the chip, wherein the first base material and the second base material are connected to the chip via a solder layer or a conductive connection.

[0022] The electrode for chip packaging of the present invention adopts a thermal expansion coefficient in the range of 0-12×10 -6 / ℃ and a second base material with a thermal conductivity range of 60-600W / m﹒k are mixed to form a composite material, or one of the first base material and the second base material is embedded in one or more positions of the other. Through the above arrangement, the electrode formed by the first base material and the second base material has a thermal expansion coefficient that is close to the thermal expansion coefficient of the chip as a whole, and has good electrical and thermal conductivity, can be used as an electrode material, and at the same time will not pull the chip to cause damage to the chip during thermal fatigue processes such as temperature cycling or temperature shock. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a microscopic image of electrodes according to certain embodiments of the present invention.

[0024] Figure 2A is a top view of an electrode according to some embodiments of the present invention.

[0025] Figure 2B -D is a longitudinal cross-section of the porous interconnected pore structure of certain embodiments of the present invention.

[0026] Figure 3 is a cross-sectional view of an electrode according to another embodiment of the present invention.

[0027] Figure 4 is a cross-sectional view of an electrode according to another embodiment of the present invention.

[0028] Figure 5 is a cross-sectional view of an electrode according to another embodiment of the present invention.

[0029] Figure 6 is a cross-sectional view of an electrode according to another embodiment of the present invention.

[0030] Figure 7 is a cross-sectional view of an electrode according to another embodiment of the present invention.

[0031] Figure 8 is a cross-sectional view of a chip packaging structure according to some embodiments of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] In an embodiment of the present invention, the electrode for chip packaging includes a thermal expansion coefficient ranging from 0 to 12×10 -6 / ℃ first base material and the thermal conductivity range of 60-600W / m﹒k second base material, the first base material and the second base material can be mixed to form a composite material to make an electrode. Similarly, one of the first base material and the second base material can be embedded in one or more parts of the other to make an electrode.

[0034] The electrode for chip packaging of the present invention adopts a thermal expansion coefficient in the range of 0-12×10 -6 / ℃ and a second base material with a thermal conductivity range of 60-600W / m﹒k are mixed to form a composite material, or one of the first base material and the second base material is embedded in one or more parts of the other. Through the above arrangement, the electrode formed by the first base material and the second base material has a thermal expansion coefficient that is close to the thermal expansion coefficient of the chip as a whole, and has good electrical and thermal conductivity, can be used as an electrode material, and will not pull the chip and cause chip damage during the temperature cycle.

[0035] Specifically, see Figure 1 , Figure 1 It is a microstructure diagram of an electrode of some embodiments of the present invention. The electrode used for chip packaging includes a first base material 102 and a second base material 104. The first base material 102 and the second base material 104 are mixed to form a composite material to form the electrode.

[0036] Likewise, in some embodiments, one of the first base material and the second base material may be embedded in one or more locations of the other to form an electrode. FIGS. 2-7 show some embodiments of the electrode for chip packaging of the present invention.

[0037] Referring to FIG. 2 , in a certain embodiment, at least a portion of the first base material 102 has a porous interconnected structure, and the second base material 104 is filled in the holes of the porous interconnected structure. Conversely, in certain embodiments, at least a portion of the second base material has a porous interconnected structure, and the first base material is filled in the holes of the porous interconnected structure. By setting a porous interconnected structure for the first base material or the second base material, and then filling the holes in the porous interconnected structure with the second base material or the first material, the thermal expansion coefficient of the entire electrode can be adjusted so that the overall thermal expansion coefficient of the electrode matches the chip, which can prevent the electrode from generating tension on the chip during the temperature cycle and causing damage and failure of the chip.

[0038] The porous interconnected structure herein refers to a structure having multiple holes, at least some of which are vertically connected, and the holes can be interconnected or separated from each other. Figure 2B -D, Figure 2B -D is a longitudinal section of a porous interconnected pore structure of certain embodiments of the present invention. Figure 2BAs shown, in some embodiments, the pores 22 in the porous structure 20 penetrate from the top surface of the material to the bottom surface of the material. In other words, when the first base material has a porous structure, the pores 22 penetrate from the top surface of the first base material to the bottom surface of the first base material, so that the second base material filled in the pores 22 also penetrates from the top surface of the first base material to the bottom surface of the first base material; conversely, when the first base material has a porous structure, it is also the same. Those skilled in the art should be able to understand and will not be repeated here. Figure 2B In the embodiment, each hole 22 is not connected. However, in some embodiments, two holes 22 in the plurality of holes 22 may be connected, such as Figure 2C shown. Figure 2B and Figure 2C The direction of the holes in the porous structure 20 is generally vertical, but in some embodiments, the shape of the holes in the porous structure 20 can be irregular, and the holes can extend randomly in the material as long as they can extend from the top surface of the material to the bottom surface, such as Figure 2D shown.

[0039] See also Figure 3 In some embodiments, the first base material 102 is provided with a through hole 110, and the second base material 104 is provided in the through hole 110. The number of through holes 110 is not limited to one, and the number of through holes 110 can be more than one according to actual needs. The first base material 102 is also not limited to being provided with through holes, and the first base material 102 can be provided with one or more pits, and the second base material 104 is provided in the pits. The first base material 102 can also be provided with through holes and pits at the same time. Different numbers of through holes and pits can be provided according to actual conditions, so as to adjust the overall expansion characteristics of the electrode and reduce the stress generated by the electrode on the chip.

[0040] Conversely, see Figure 4 In some embodiments, the second base material 104 is provided with a pit 112, and the first base material 102 is provided in the pit 112. The number of the pit 112 is not limited to one, and the number of the pit 112 can be more than one according to actual needs. Similarly, the second base material 104 is not limited to having a through hole, and the second base material 104 can be provided with one or more through holes, and the first base material 102 is provided in the through hole. The second base material 104 can also be provided with through holes and pits at the same time. Different numbers of through holes and pits can be provided according to actual conditions, so as to adjust the overall expansion characteristics of the electrode and reduce the stress generated by the electrode on the chip.

[0041] In some embodiments, the first matrix material is a metal material or a non-metal material. The metal material can be one of molybdenum, tungsten, and iron-nickel alloy, or a mixture of two or more thereof. The non-metal material can be one of graphite, aluminum oxide ceramics, aluminum nitride, beryllium oxide, and silicon carbide, or a mixture of two or more thereof.

[0042] In some embodiments, the second matrix material is one of copper, aluminum, silver, and gold, or a mixture of two or more thereof, or a composite material including one of copper, aluminum, silver, and gold, or two or more thereof.

[0043] See also Figure 5-7 In some embodiments, the electrode may further include a metal layer, which covers at least a portion of the outer surface of the first substrate material. By covering the outer surface of the substrate with a metal layer, the thermal conductivity of the electrode can be further improved, and the stress generated by the electrode on the chip during the temperature cycle can be reduced.

[0044] See also Figure 5 In some embodiments, the metal layer 106 covers the outer sidewall of the first base material 102. Figure 6 In some embodiments, the metal layer 106 covers the entire outer surface of the first base material 102. Figure 7 In some embodiments, the metal layer 106 covers the first base material 102 and the second base material 104. In the above embodiments, the material of the metal layer can be copper, silver, gold, aluminum or nickel.

[0045] In some embodiments, the first surface of the electrode exposes the first base material and the second base material, and the first surface is used to connect to the chip through a solder layer or a conductive connection. When the electrode also includes a metal layer or other material, and the first surface of the electrode exposes the metal layer or other material, the electrode is connected to the chip through the metal layer or other material through a solder layer or a conductive connection.

[0046] Various embodiments of the electrode of the present invention are described above. These embodiments can be implemented separately, or different embodiments can be combined. For example, the material mentioned in one embodiment can be used in another embodiment, and the structure in one embodiment can also be combined with the structure of other embodiments. The embodiments in this article are only used for examples and should not be regarded as limitations of the present invention.

[0047] The present invention also provides a chip packaging structure, comprising: a chip; and one or more electrodes connected to the chip as described above, wherein the first base material and the second base material are connected to the chip via a welding layer or a conductive connection. Figure 8In some embodiments, the chip packaging structure includes two electrodes according to the embodiments of the present invention and a chip 202 disposed between the two electrodes, wherein each electrode includes a first base material 102 and a second base material 104 disposed in a through hole 110 of the first base material 102, wherein the first base material 102 and the second base material are connected to the chip 202 via a solder layer 204. In other embodiments, the base and the conductive pillar may also be connected to the chip via a conductive connector.

[0048] It should be understood that when the first surface of the electrode exposes the first base material and the second base material, the first surface is connected to the chip through a solder layer or a conductive connection, and the first base material and the second base material are directly connected to the chip. When the electrode also includes a metal layer or other material, and the first surface of the electrode exposes the metal layer or other material, the electrode is connected to the chip through the metal layer or other material through a solder layer or a conductive connection, and the first base material and the second base material are indirectly connected to the chip.

[0049] The above lists only chip packaging structures using some of the electrodes mentioned above, but the packaging structure can use any of the electrode structures mentioned above, which will not be described in detail here.

[0050] In some embodiments, the chip packaging structure is a TSS (Thyristor Surge Suppressor) chip packaging structure, and the TSS chip packaging structure includes a TSS chip and two electrodes, one of which is connected to the upper surface of the TSS chip, and the other is connected to the lower surface of the TSS chip. The two electrodes are connected to the TSS chip through solder layers, respectively. Similarly, it should be understood that the chip packaging structure of the present invention is not limited to the TSS chip packaging structure. The above is only an example. The chip packaging structure of the present invention can also be a packaging structure of any semiconductor chip. The chip in the chip packaging structure can be a semiconductor chip made of basic chip materials such as silicon, germanium, and gallium arsenide.

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An electrode for chip packaging, the electrode comprising: The first base material has a thermal expansion coefficient in the range of 0-12×10 -6 / ℃; as well as A second base material, wherein the second base material is a conductive material and has a thermal conductivity in the range of 60-600 W / (m·K); The first matrix material and the second matrix material are mixed to form a composite material, or one of the first matrix material and the second matrix material is embedded in one or more parts of the other; The first surface of the electrode exposes the first base material and the second base material; At least a portion of the first matrix material has a porous interconnected pore structure, and the second matrix material is filled in the pores of the porous interconnected pore structure; The porous interconnected hole structure has a plurality of holes, at least a portion of which are vertically connected, and the holes are interconnected; The electrode further includes a metal layer covering at least a portion of an outer surface of the first base material.

2. The electrode according to claim 1, characterized in that The first base material is provided with at least one recess or through hole, and the second base material is provided in the recess or through hole.

3. The electrode according to claim 1, characterized in that: The second base material is provided with at least one pit or through hole, and the first base material is arranged in the pit or through hole; or at least a part of the second base material has a porous interconnected pore structure, and the first base material is filled in the pores of the porous interconnected pore structure.

4. The electrode according to claim 1, characterized in that The first base material is a metal material or a non-metal material.

5. The electrode according to claim 4, characterized in that The metal material is one of molybdenum, tungsten, and iron-nickel alloy, or a mixture of two or more thereof.

6. The electrode according to claim 4, characterized in that The non-metallic material is one of graphite, aluminum oxide ceramics, aluminum nitride, beryllium oxide, and silicon carbide, or a mixture of two or more thereof.

7. The electrode according to claim 1, characterized in that The second matrix material is one of copper, aluminum, silver and gold, or a mixture of two or more thereof, or a composite material including one of copper, aluminum, silver and gold or more thereof.

8. The electrode according to claim 1, characterized in that The material of the metal layer is copper, silver, gold, aluminum or nickel.

9. A chip packaging structure, comprising: chip; as well as One or more electrodes as claimed in any one of claims 1 to 8 connected to the chip, wherein the first matrix material and the second matrix material are connected to the chip via a conductive connection.

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