Rough z buffer utilizing a position only shading (posh) geometry data processing pipeline

Abstract

This application discloses position only shading (POSH) geometry data processing with coarse Z buffer. Systems, apparatuses, and methods can provide a way to adaptively process and actively cull geometry data. Systems, apparatuses, and methods can provide processing of geometry data including surface triangles for a digital representation of a scene by a position only shading (POSH) pipeline. More specifically, systems, apparatuses, and methods can provide a way to identify surface triangles in one or more exclusion regions and non-exclusion regions and cull surface triangles in one or more exclusion regions.

Description

TECHNICAL FIELD

[0001] Embodiments relate generally to data processing, and more particularly to data processing via a graphics processing unit. BACKGROUND

[0002] Currently, graphics processing systems cull geometry data that will not be rendered in a rendering pipeline. Conventional graphics processing systems can perform binning based on processing geometry in a multi-GPU environment. These solutions can limit performance, such as the amount of parallel processing that can be possible or adaptively processed and / or active culling of geometry data. BRIEF DESCRIPTION OF DRAWINGS

[0003] Various advantages of embodiments will be apparent from reading the following description and by reference to the drawings, in which:

[0004] Figure 1 is a block diagram showing a computer system configured to implement one or more aspects of the embodiments described herein;

[0005] Figures 2A-2D illustrates a parallel processor component according to an embodiment;

[0006] Figures 3A-3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0007] Figures 4A-4F illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0008] Figure 5 illustrates a graphics processing pipeline according to an embodiment;

[0009] Figure 6 is a conceptual diagram of an example of a positional only shading pipeline (POSH) configured with a coarse Z buffer according to an embodiment;

[0010] Figure 7A is a conceptual diagram of an example of a view frustum exclusion region according to an embodiment;

[0011] Figure 7B is a flow diagram of an example of a method of managing a positional only shading pipeline (POSH) according to an embodiment;

[0012] Figure 8A is a conceptual diagram of an example of a vertex shader in a POSH according to an embodiment;

[0013] Figure 8Bis a conceptual diagram of an example of a view near plane and a view far plane according to an embodiment;

[0014] Figure 8C is a flow diagram of an example of a method of exposing outflow data to a vertex shader in a position only shading pipeline (POSH) according to an embodiment;

[0015] Figure 9A is a conceptual diagram of an example of surface triangles in a scene representation with exclusion regions according to an embodiment;

[0016] Figure 9B is a conceptual diagram of an example of resolution fragments of various sizes according to an embodiment;

[0017] Figure 9C is a flow diagram of an example of a method of managing coarse-grained rasterization with a coarse Z buffer according to an embodiment;

[0018] Figure 10A is a conceptual diagram of an example of multiple graphics processing units (GPUs) in communication with a position only shading pipeline (POSH) according to an embodiment;

[0019] Figure 10B is a conceptual diagram of an example of distribution and density attribute storage implementation according to an embodiment;

[0020] Figure 10C is a flow diagram of an example of a method of rendering a primitive with a position only shading pipeline (POSH) using multiple GPUs according to an embodiment;

[0021] Figure 11 is a diagram of an example of a head mounted display (HMD) system according to an embodiment;

[0022] Figure 12 is a block diagram of an example of functional components included in an HMD system according to an embodiment; Figure 11

[0023] Figure 13 is a block diagram of an example of a general processing cluster included in a parallel processing unit according to an embodiment;

[0024] Figure 14 is a conceptual diagram of an example of a graphics processing pipeline that can be implemented within a parallel processing unit according to an embodiment;

[0025] Figure 15 is a block diagram of an example of a stream multi-processor according to an embodiment;

[0026] Figures 16-18 is a block diagram of an example of an overview of a data processing system according to an embodiment;

[0027] Figure 19 ​is a block diagram of an example of a graphics processing engine according to an embodiment;

[0028] Figures 20-22 is a block diagram of an example of an execution unit according to an embodiment;

[0029] Figure 23 is a block diagram of an example of a graphics pipeline according to an embodiment;

[0030] Figures 24A-24B is a block diagram of an example of a graphics pipeline according to an embodiment;

[0031] Figure 25 is a block diagram of an example of a graphics software architecture according to an embodiment;

[0032] Figure 26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0033] Figure 27 is a block diagram of an example of a system on a chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0034] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of skill in the art upon

[0035] System Overview

[0036] Figure 1 is a block diagram showing a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processor(s) 102 and a system memory 104 communicating via an interconnection path 105 that can include a memory hub 105. The memory hub 105 can be a separate component coupled with one or more processors 102 via the interconnection path 105, or can be integrated within one or more processors 102. The memory hub 105 communicates with an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that can enable the computing system 100 to receive input from one or more input devices 108 and to provide output to one or more output devices 110A. Additionally, the I / O hub 107 can enable a display controller to provide graphics, send commands, and receive status

[0037] In one embodiment, processing subsystem 101 includes one or more parallel processor(s) 112 coupled to memory hub 105 via a bus or other communication link 113. Communication link 113 can be one of any number of standards-based communication links, such as, but not limited to, a PCI Express bus, or can be a vendor specific communications interface or communications structure. In one embodiment, one or more parallel processor(s) 112 form a computationally-focused, parallel, or vector processing system that includes a large number of processing cores and / or processing clusters (such as a many integrated core (MIC) processor). In one embodiment, one or more parallel processor(s) 112 form a graphics processing subsystem that can output pixels to one or more display device(s) 110A coupled via I / O hub 107. One or more parallel processor(s) 112 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 110B.

[0038] Within I / O subsystem 111, system storage 114 can be connected to the I / O hub 107 to provide storage mechanisms to compute system 100. An I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components, such as a network adapter 118 and / or wireless network adapter 119 that can be integrated into the platform, and various other devices that can be added via one or more add-in device(s) 120. Network adapter 118 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 119 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network adapter that includes one or more wireless radios.

[0039] Compute system 100 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which can also be connected to I / O hub 107. The communication paths for which various components in Figure 1 The communication paths interconnecting the various components in FIG. 1 can use any suitable protocols and technologies including, but not limited to, PCI (Peripheral Component Interconnect) based protocols and technologies, such as PCI Express, or any other bus or point-to-point communication interfaces and / or protocols, such as NV-Link high-speed interconnect, or interconnect protocols known in the art.

[0040] In one embodiment, the one or more parallel processors 112 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 include circuitry optimized for general use, while maintaining the underlying computational architecture described herein. In yet another embodiment, components of computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 can be integrated into a

[0041] It will be recognized that the computing system 100 shown in FIG. 1 is a simplified diagram of an embodiment of a system that is illustrative of the present disclosure. Numerous variants and modifications are possible. The connection topology can be modified as desired, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the processor(s) 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and memory hub 105 are integrated into a single chip. Some embodiments can include two or more groups of processors 102 attached via multiple sockets, which can couple with two or more instances of the parallel processor(s) 112.

[0042] Some of the particular components shown herein are optional and can not be included in all implementations of the computing system 100. For example, any number of add-in cards or peripherals can be supported, or some components can be eliminated. Additionally, some architectures can use different terminology for components similar to those shown in FIG. 1. For example, in some architectures the memory hub 105 can be called a northbridge and the I / O hub 107 can be called a southbridge. Figure 1 Different terminology can be used for components similar to those shown in FIG. 1 in some architectures. For example, in some architectures the memory hub 105 can be called a northbridge and the I / O hub 107 can be called a southbridge.

[0043] Figure 2AA parallel processor 200 according to an embodiment is shown. Various components of the parallel processor 200 can be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). According to an embodiment, the illustrated parallel processor 200 is a variant of one or more parallel processors 112 shown in FIG. 1. Figure 1

[0044] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 can be directly connected to the other devices. In one embodiment, the I / O unit 204 communicates with other devices via the use of a hub or switch interface, such as memory hub 105. The connections between the memory hub 105 and the I / O unit 204 form communication links 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, where the host interface 206 receives commands required to carry out processing tasks and the memory crossbar 216 facilitates communication between the memory crossbar 216 and the memory device(s) 212.

[0045] When the host interface 206 receives a command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210 that is configured to distribute the commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in an active state before tasks are distributed to processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executing on a microcontroller. The microcontroller implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations with coarse and fine grain granularity to enable fast preemption and context switching for threads executing on the processing array 212. In one embodiment, host software can demonstrate a work load via one of a number of image processing doorbells for scheduling on the processing array 212. The work load can then be automatically distributed by the scheduler 210 logic within the scheduler microcontroller across the processing array 212.

[0046] ​The processing cluster array 212 can include up to "N" processing clusters (e.g., cluster 214A, 214B, through 214N). Each cluster 214A-214N of the processing cluster array 212 can execute a plurality of concurrent threads. The scheduler 210 can allocate work to the clusters 214A-214N of the processing cluster array 212 using various scheduling and / or work distribution algorithms. The scheduling can be dynamic, taking into account the workloads of the individual clusters 214A-214N, or can be assisted by compiler logic during compilation of program logic configured for execution by the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 can be allocated for processing different types of programs or for performing different types of computations.

[0047] The processing cluster array 212 can be configured to perform a wide variety of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel compute operations. For example, the processing cluster array 212 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0048] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In an embodiment in which the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 can include additional logic to support such graphics processing tasks as texture mapping

[0049] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into approximately equal sized tasks to better enable distribution of the graphics processing operations to the multiple clusters 214A-214N in processing cluster array 212. In some embodiments, multiple portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform surface

[0050] During operation, processing cluster array 212 can receive processing tasks to be executed via scheduler 210, which receives commands defining the processing tasks from front end 208. For graphics processing operations, the processing tasks can comprise indices of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data) and state parameters and commands defining how the data is to be processed (e.g., what programs are to be executed). Scheduler 210 can be configured to fetch the indices corresponding to the tasks, or can receive these indices from front end 208. Front end 208 can be configured to ensure that processing cluster array 212 is configured in an effective state prior to initiating the workload specified by an incoming command buffer (e.g., a batched buffer, a push buffer, etc.).

[0051] Each of one or more instances of parallel processing unit 202 may be coupled to parallel processor memory 222. Parallel processor memory 222 may be accessed via memory crossbar switch 216, which receives memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 may access parallel processor memory 222 via memory interface 218. Memory interface 218 may include multiple partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), each partition unit being coupled to a portion (e.g., memory cell) of parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0052] In various embodiments, memory cells 224A to 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (e.g., synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, memory cells 224A to 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of memory cells 224A to 224N can vary and may be selected from a variety of conventional designs. Render targets (e.g., frame buffers or texture maps) may be stored across memory cells 224A to 224N, thereby allowing partitioning cells 220A to 220N to write in parallel to multiple portions of each render target to efficiently utilize the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be excluded to facilitate a unified memory design that utilizes system memory by incorporating local cache memory.

[0053] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written into any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to pass the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N where additional processing operations can be performed on the output. Each cluster 214A-214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I / O unit 204 and a connection to a local instance of the parallel processor memory 222 to enable the processing core(s) within the different processing clusters 214A-214N to communicate with system memory or other memories not local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 can use virtual channels to separate traffic streams between the clusters 214A-214N and the partition units 220A-220N.

[0054] While a single instance of the parallel processor 200 is shown in the parallel processor 200, any number of instances of the parallel processor 200 can be included. For example, a plurality of instances of the parallel processor 200 can be provided on a single add-in card, or multiple add-in cards can be interconnected. The different instances of the parallel processor 200 can be configured to interoperate, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences.

[0055] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is a Figure 2AThe partition unit 220 includes, by way of example, an L2 cache 221, a frame buffer interface 225 and a ROP (raster operations unit) 226. The L2 cache 221 is a read / write cache that is configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent write requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory 222 (e.g., within the parallel processor memory 222 of FIG. 2).

[0056] In graphics applications, the ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, and so forth. The ROP 226 then outputs processed graphics data that is stored in graphics memory. In some embodiments, the ROP 226 includes compression logic to compress depth or color data that is written to memory, and decompress depth or color data that is read from memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by the ROP 226 can vary based on the statistical properties of the data to be compressed. For example, in one embodiment, delta color compression performs per-tile on depth and color data.

[0057] In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2) rather than in the partition unit 220. In such embodiments, read and write requests for pixel data are transmitted via the memory crossbar 216 rather than pixel fragment data. Processed graphics data can be displayed on one or more display devices 110, routed to a Figure 1 further processing by the processor(s) 102, or routed to further processing by one of the processing entities within the parallel processor 200. Figure 2A

[0058] Figure 2C ​is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of FIG. 2. A processing cluster 214 can be configured to execute a large number of threads in parallel, where the term“thread” refers to an instance of a particular program executing on a particular set of input data. In some embodiments, single-instruction-multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads. In other embodiments, single-instruction-multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronous threads, using a common instruction unit configured to issue instructions to each of the processing clusters within the processing cluster. Unlike SIMD execution, where all processing clusters typically execute identical instructions, SIMT execution allows different threads to follow divergent execution paths, as dictated by the given thread program. One of ordinary skill in the art will understand that a SIMD processing regime represents a functional subset of a SIMT processing regime.

[0059] Operation of a processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors having different architectures can be included within a processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within a processing cluster 214. The graphics multiprocessor 234 can process data and a data crossbar 240 can be used to distribute the processed data to one of a number of possible destinations, including other shader units. The pipeline manager 232 can facilitate distribution by specifying destinations for processed data to be distributed via the data crossbar 240.

[0060] Each graphics multiprocessor 234 within a processing cluster 214 can include a complete set of execution logic (e.g., arithmetic logic units, load-store units, etc.). The execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. The execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting operations, and compute operations. In one embodiment, different operations can be performed by the same functional unit hardware, but under different usage scenarios in the pipeline. For example, a single arithmetic logic unit can be used for both integer and floating point arithmetic on different usage scenarios.

[0061] The instructions transmitted to processing cluster 214 constitute a thread. A set of threads that execute across a set of parallel processing engines is a thread group. A thread group performs the same program on different input data. Each thread in a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than there are processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than there are processing engines, one or more of the processing engines can be idle during the period that the thread group is being processed. A thread group can also include more threads than there are processing engines within graphics multiprocessor 234. When a thread group includes more threads than there are processing engines, processing can be performed on a subset of the threads on a particular processing engine during a clock cycle. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234, each thread group being assigned to a different processing engine.

[0062] In one embodiment, graphics multiprocessor 234 includes an internal cache memory to perform load and store operations. In one embodiment, graphics multiprocessor 234 can bypass the internal cache and use the cache memory within processing cluster 214 (e.g., Ll cache 308). Each graphics multiprocessor 234 also has access to L2 cache within a partition unit (e.g., partition units 220A-220N of FIG. 2) that is shared among all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 also has access to off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processor 202 can be used as global memory. Multiple embodiments, in which processing clusters 214 include multiple instances of graphics multiprocessor 234, can share common instructions and data, which can be stored in Ll cache 308.

[0063] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to translate virtual addresses into physical addresses, in other embodiments, one or more instances of MMU 245 can reside in memory interface 218 of FIG. 2. MMU 245 includes a set of page table entries (PTEs) used to translate a virtual address into a physical address by mapping it to a frame of physical memory, and optionally an address margin. MMU 245 can include an address translation lookaside buffer (TLB) or cache for receiving and storing translations of virtual addresses to physical addresses. The physical address is processed to distribute surface data access locality, allowing efficient request interleaving between multiple threads. The address margin, if used, can be used to access set of frame buffers shared between multiple processing clusters 214.

[0064] In graphics and compute applications, processing cluster 214 can be configured such that each graphics processing unit 234 is coupled to a texture unit 236 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. Texture data is read from either an internal texture LI cache (not shown) or, in some embodiments, an LI cache within graphics processing unit 234 as needed, and fetched from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics processing unit 234 outputs processed tasks to data crossbar 240 to provide processed tasks to another processing cluster 214 for further processing or to store processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 216. PreROP 242 (e.g., pre-raster operations unit) is configured to receive data from graphics processing units 234, direct data to ROP units, which can be grouped together with a partition unit (e.g., partition units 220A-220N of FIG. 2) as described herein. PreROP 242 unit can perform optimizations for color blending, organize pixel color data, and perform address translations.

[0065] It will be recognized that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units, e.g., graphics processing units 234, texture units 236, preROP 242, etc., can be included in a processing cluster 214. In addition, while a single processing cluster 214 is shown, any number of processing clusters 214 can be included in a parallel processing unit as described herein. In one embodiment, each processing cluster 214 can be configured to operate using a separate and distinct processing unit, LI cache, etc. independent of other processing clusters 214.

[0066] Figure 2D A graphics processing unit 234 according to one embodiment is shown. In such an embodiment, graphics processing unit 234 is coupled with a pipeline manager 232 of a processing cluster 214. Graphics processing unit 234 has an execution pipeline that includes, without limitation, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. GPGPU cores 262 and load / store units 266 are coupled with cache memory 272 and shared memory 270 via a memory and cache interconnect 268.

[0067] In one embodiment, instruction cache 252 receives a stream of instructions to be executed from pipeline manager 232. These instructions are cached in instruction cache 252 and, once fetched, are dispatched for execution via instruction unit 254. Instruction unit 254 can dispatch instructions to threads groups being handled by thread dispatcher 255 in a round robin or some other functional manner. In one embodiment, instruction unit 254 dispatches instructions associated with a thread in a thread group based on a number of instructions associated with a thread group in which the thread is included. For example, if a thread group includes four threads, and the thread associated with a particular instruction is the first listed in the thread group, then instruction unit 254 can dispatch four instructions associated with the thread group to the thread. In another example, if a thread group includes four threads, and the thread associated with a particular instruction is the second listed in the thread group, then instruction unit 254 can dispatch three instructions associated with the thread group to the thread. In this manner, the number of instructions dispatched by instruction unit 254 can vary based on the position of a thread associated with an instruction in a thread group.

[0068] Register file 258 provides a set of registers for functional units of graphics multiprocessor 324. Register file 258 can provide temporary storage for operands processed by functional units of graphics multiprocessor 324. In one embodiment, register file 258 is divided into registered file segments that are allocated to different threads or warps based on availability.

[0069] GPGPU cores 262 can each include floating point, integer, and / or single instruction multiple data (SIMD) execution units supporting multiple execution lanes. For example, each GPGPU core 262 can include floating point units supporting double precision, single precision, and / or half precision floating point arithmetic operations. In one embodiment, GPGPU cores 262 include a number of integer ALUs supporting integer arithmetic operations, bitwise shift operations, and / or bitwise comparison operations. In one embodiment, GPGPU cores 262 include single instruction multiple data (SIMD) execution lanes, which provide for simultaneous execution of instructions on multiple lanes of execution for threaded Zonal SIMD code instances. In one embodiment, GPGPU cores 262 support floating point, integer, and / or boolean operations on single precision (e.g., 32-bit), double precision (e.g., 64-bit), and / or half precision (e.g., 16-bit) data values.

[0070] In one embodiment, the GPGPU cores 262 include SIMD execution logic capable of

[0071] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows load / store units 266 to communicate with the shared memory 270 and the register file 258 to facilitate load and store operations between the shared memory 270 and the register file 258. The register file 258 is operable with the same frequency as the GPGPU cores 262, such that data transfers between the GPGPU cores 262 and the register file 258 are at a very low latency. The shared memory 270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 234. The cache memory 272 can be used to cache data, such as texture data, as referenced by threads executing on the functional units and texture units 236. The shared memory 270 can also be used to store program metadata, executed threads, and so forth. Threads executing on the GPGPU cores 262 can also store data, other than automatically cached data, in the shared memory.

[0072] Figures 3A-3B Additional graphics multiprocessors according to embodiments are shown. The shown graphics multiprocessors 325, 350 are variants of the graphics multiprocessor 234 of Figure 2C FIG. 2. The shown graphics multiprocessors 325, 350 can be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads concurrently.

[0073] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 is similar to the graphics multiprocessor 234 of Figure 2DThe graphics multiprocessor 234 of FIG. 3B includes a number of additional instances of execution resource units. For example, graphics multiprocessor 325 can include multiple instances of the instruction unit 332A-332B, register file 334A-334B, and texture unit 344A-344B. Graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B), and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0074] The various components can communicate via an interconnect 327. In one embodiment, the interconnect 327 includes one or more crossbars to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect 327 is a separate high-speed network structure layer on which each of the components of the graphics multiprocessor 325 are stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect 327. For example, the GPGPU cores 336A-336B, 337A-337B, and 338A-338B can each communicate with the shared memory 346 via the interconnect 327. The interconnect 327 can arbitrate communications between the components within the graphics multiprocessor 325 to ensure fair bandwidth allocation.

[0075] Figure 3B A graphics multiprocessor 350 is shown according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A-356D, where each set of execution resources includes multiple instruction units, register file, GPGPU cores, and load store units, as shown in Figure 2D and Figure 3A The execution resources 356A-356D can work in unison to perform texture operations in coordination with the texture units 360A-360D, while sharing the instruction cache 354 and shared memory 362. In one embodiment, the execution resources 356A-356D can share the instruction cache 354 and shared memory 362, as well as multiple instances of the texture and / or data cache memory 358A-358B. The various components can communicate via an interconnect 352 that is similar to the interconnect 327 of Figure 3A FIG. 3A.

[0076] Those of skill in the art will appreciate that Figure 1 , Figures 2A-2D and Figures 3A-3BThe architecture described in the middle is descriptive and non-limiting in the scope of the present embodiments. Thus, the technology described herein can be implemented on any properly configured processing unit including, but not limited to, one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) including multi-core CPUs, one or more parallel processing units such as the parallel processing unit 202 of FIG. 2, and one or more graphics processors or specialized processing units without departing from the scope of the embodiments described herein.

[0077] In some embodiments, parallel processors or GPGPUs as described herein are communicatively coupled to host / processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / cores over a bus or other interconnect (e.g., a high-speed

[0078] Techniques for GPU-to-host processor interconnect

[0079] Figure 4A An exemplary architecture is shown in which a plurality of GPUs 410-413 are communicatively coupled to a plurality of multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 440-443 support communication at a throughput level of 4GB / s, 30GB / s, 80GB / s or higher depending on the implementation. Various interconnect protocols can be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the application are not limited to any particular communication protocol or throughput level.

[0080] Further, in one embodiment two or more of GPUs 410-413 are interconnected over high-speed links 444-445, which can be implemented using the same or different protocol / links than used for high-speed links 440-443. Similarly, two or more of multi-core processors 405-406 can be connected over a high-speed link 433, which can be a Symmetric Multi-Processor (SMP) bus operating at 20GB / s, 30GB / s, 120GB / s or higher. Alternatively, Figure 4AAll communication between the various system components shown in FIG. 4 can be implemented using the same protocol / link (e.g., via a common interconnect fabric). However, as noted, the underlying principles of the application are not limited to any particular type of interconnect technology.

[0081] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memories 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memories 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 can utilize the same or different memory access technologies. By way of example and without limitation, processor memories 401-402 and GPU memories 420-423 can be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories such as 3D XPoint or nanorandom access memory. In one embodiment, some portion of the memory can be volatile memory and another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0082] As described below, while various processors 405-406 and GPUs 410-413 can be physically coupled to particular memories 401-402, 420-423, respectively, a unified memory architecture can be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the individual physical memories. For example, processor memories 401-402 can each include 64 GB of system memory address space, and GPU memories 420-423 can each include 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0083] Figure 4B Additional details are shown for an interconnect between multi-core processor 407 and graphics acceleration module 446, according to one embodiment. Graphics acceleration module 446 can include one or more GPU chips integrated on a line card that is coupled to processor 407 via high-speed link 440. Alternatively, graphics acceleration module 446 can be integrated on the same package or chip as processor 407.

[0084] The illustrated processor 407 includes multiple cores 460A-D, each with a translation lookaside buffer 461A-D and one or more caches 462A-D. The cores can include various other components for executing instructions and processing data, which are not illustrated to avoid obscuring the principles of the application (e.g., instruction fetch unit, branch prediction unit, decoders, execution units, reorder buffer, etc.). The caches 462A-D can include level one (Ll) and level two (L2) caches. Additionally, one or more shared caches 426 can be included in the cache hierarchy and shared by the multiple sets of cores 460A-D. For example, one embodiment of the processor 407 includes 24 cores, each with its own Ll cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches are shared by two adjacent cores. The processor 407 and graphics accelerator integrated module 446 are connected with system memory 441, which can include processor memories 401-402.

[0085] Consistency of data and instructions stored in the various caches 462A-D, 456 and system memory 441 is maintained via inter-core communication over the coherence bus 464. For example, each cache can have cache coherency logic / circuitry associated therewith to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snoop protocol is implemented via the coherence bus 464 to snoop cache accesses. Cache snoop / coherency techniques are well understood by those skilled in the art, and will not be described in detail here to avoid obscuring the principles of the application.

[0086] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer to the cores. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0087] In one implementation, the accelerator integration circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N can each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N can comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In other words, the graphics acceleration module can be a GPU with a plurality of graphics processing engines 431-432, N or the graphics processing engines 431-432, N can be individual GPUs integrated on a common package, line card, or chip.

[0088] In one embodiment, the accelerator integration circuit 436 includes a memory management unit (MMU) 439 to provide translation of virtual addresses into physical addresses, supply memory protection, and provide storage for process registration values. In one embodiment, at least a portion of the memory management unit 439 is implemented in software. The memory management unit 439 can also include a data cache 439 and an instruction cache 439 to provide quick access to frequently accessed data and instructions. In one embodiment, at least one of the data cache 439 and instruction cache 439 is a hardware component; however, in other embodiments, at least one of the data cache 439 and instruction cache 439 is a software component.

[0089] A set of registers 445 store context data for threads executed by the graphics processing engines 431, 432, N, and a context management circuit 448 manages thread contexts. For example, the context management circuit 448 can perform save and restore operations to save and restore the context of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engines). For example, upon a context switch, the context management circuit 448 can store current register values to a designated area in memory (e.g., identified by a context pointer). It can then restore these register values upon a return to the context. In one embodiment, an interrupt management circuit 447 receives and processes interrupts from the system.

[0090] In one implementation, virtual / effective addresses from the graphics processing engines 431 are translated to real / physical addresses in system memory 411 by the MMU 439. One embodiment of the accelerator integration circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator modules 446 can be dedicated to a single application executing on the processor 407 or can be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which multiple applications or virtual machines (VMs) share the resources of the graphics processing engines 431-432, N. These resources can be subdivided into“slices” that are allocated to the VMs and / or applications based on processing requirements and priorities associated with the different VMs and / or applications.

[0091] Thus, the accelerator integration circuit functions as a bridge to the system of graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integration circuit 436 can provide virtualization facilities for the host processor to manage virtualization of graphics processing engines, interrupts, and memory management.

[0092] Since the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can use effective address values to directly address these resources. In one embodiment, one function of the accelerator integration circuit 436 is to physically separate the graphics processing engines 431-432, N so that they appear to the system as independent units.

[0093] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M can be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory such as 3D XPoint or Nano-Ram.

[0094] In one embodiment, to reduce data traffic on the high-speed link 440, biasing techniques are used to ensure that data stored in graphics memory 433-434, M is data that will be used most frequently by the graphics processing engines 431-432, N and preferably not used by the cores 460A-D (at least not frequently). Similarly, the biasing mechanism attempts to keep data required by the cores (and preferably not by the graphics processing engines 431-432, N) within the caches 462A-D, 456 and system memory 411 of those cores.

[0095] Figure 4C Another embodiment is shown in which the accelerator integration circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly over the high-speed link 440 to the accelerator integration circuit 436 via the interface 437 and the interface 435 (again, these interfaces can utilize any form of bus or interface protocol). The accelerator integration circuit 436 can perform same operations as those described with respect to the Figure 4B

[0096] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter can include a programming model controlled by the accelerator integration circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0097] In one embodiment of the dedicated process model, the graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. The single application can funnel other application requests to the graphics engines 431-432, N, providing virtualization within the VM / partition.

[0098] In the dedicated process programming model, the graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize the graphics processing engines 431-432, N to allow access by each operating system. For a hypervisor-less, single-partition system, the graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432, N to provide access to each process or application.

[0099] ​For the shared programming model, graphics acceleration module 446 or individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in system memory 41 1 and can be addressed using the effective-to-real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when it registers its context with the graphics processing engines 431-432, N (that is, calls system software to add the process element to a process element linked list). The lower 16 bits of the process handle can be an offset into the process element linked list of the process element.

[0100] Figure 4D An exemplary accelerator integration slice 490 is shown. As used herein, a "slice" includes a specified portion of the processing resources of accelerator integration circuit 436. An application effective address space 482 within system memory 41 1 stores process elements 483. In one embodiment, process elements 483 are stored in response to GPU invocations 481 from an application 480 executing on processor 407. Process elements 483 contain process state for the corresponding application 480. A work descriptor (WD) 484 contained in process element 483 can be a single job requested by the application, or can contain a pointer to a queue of jobs. In the latter case, WD 484 is a pointer to a job request queue in the address space 482 of the application.

[0101] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N can be shared by all or a subset of processes in a system. Embodiments of the invention include an infrastructure for setting up process state and sending WDs 484 to graphics acceleration module 446 to start jobs in a virtualized environment.

[0102] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns graphics acceleration module 446 or individual graphics processing engines 431. Since graphics acceleration module 446 is owned by a single process, the hypervisor initializes accelerator integration circuit 436 for the owning partition and the operating system initializes accelerator integration circuit 436 for the owning process when graphics acceleration module 446 is assigned.

[0103] In operation, a WD fetch unit 491 in accelerator integration slice 490 fetches a next WD 484 that includes an indication of work to be done by one of the graphics processing engines of graphics acceleration module 446. Data from WD 484 can be stored in registers 445 and used by MMU 439, interrupt management circuit 447, and / or context management circuit 446 as shown. For example, one embodiment of MMU 439 includes segment / page walk circuitry to access segment / page tables 486 within OS virtual address space 485. Interrupt management circuit 447 can handle interrupt events 492 received from graphics acceleration module 446. When performing graphics operations, effective addresses 493 generated by graphics processing engines 431-432, N are translated to real addresses by MMU 439.

[0104] In one embodiment, a set of identical registers 445 are replicated for each graphics processing engine 431-432, N and / or graphics acceleration module 446 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in accelerator integration slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0105] Table 1 - Hypervisor Initialized Registers

[0106] 1 Slice Control Register 2 Real Address (RA) Scheduling Process Region Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Descriptor Register

[0107] Exemplary registers that can be initialized by an operating system are shown in Table 2.

[0108] Table 2 - Operating System Initialized Registers

[0109] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work Descriptor

[0110] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engines 431-432, N. It contains all information needed for the graphics processing engines 431-432, N to do its work, or it can be a pointer to a memory location where an application has set up a command queue of work to be done.

[0111] Figure 4E Additional details of one embodiment of a shared model are shown. This embodiment includes a hypervisor real address space 498 in which a list of process elements 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes graphics acceleration module engines for an operating system 495.

[0112] The shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced sharing and graphics directed sharing.

[0113] In this model, the system hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization by the system hypervisor 496, the graphics acceleration module 446 can follow the following requirements: 1) Application job requests must be autonomous (i.e., state does not need to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees completion of an application's job request (including any translation faults) within a specified amount of time, or the graphics acceleration module 446 provides the ability to preempt processing of a job. 3) The graphics acceleration module 446 must guarantee fairness between processes when operating in the directed shared programming model.

[0114] In one embodiment, for the shared model, the application 480 is required to utilize a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP) for operating system 495 system calls. The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, a valid address pointer to a user defined structure, a valid address pointer to a command queue, or any other data structure used to describe work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to an application setting the AMR. If the accelerator integration circuit 436 and graphics acceleration module 446 implementation does not support a user authority mask override register (UAMOR), then the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Alternatively, the hypervisor 496 can apply the current authority mask override register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the valid address of an area in the application's address space 482 to be used by the graphics acceleration module 446 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area can be pinned system memory.

[0115] Upon receiving the system call, operating system 495 can verify that application 480 is registered and has been given permission to use graphics acceleration module 446. Operating system 495 then invokes hypervisor 496 with the information shown in Table 3.

[0116] Table 3 - OS to hypervisor invocation parameters

[0117] 1 Work Descriptor (WD) 2 Authority Mask Register (AMR) Value (Potentially Masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0118] Upon receiving the hypervisor call, hypervisor 496 verifies that operating system 495 is registered and has been given permission to use graphics acceleration module 446. Hypervisor 496 then places process element 483 into a corresponding process element linked list for the type of graphics acceleration module 446. The process element can include the information shown in Table 4.

[0119] Table 4 - process element information

[0120] 1 Work Descriptor (WD) 2 Authority Mask Register (AMR) Value (Potentially Masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table Derived from Hypervisor Invocation Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0121] In one embodiment, the hypervisor initializes a number of accelerator integration slice 490 registers 445.

[0122] As Figure 4F One embodiment of the present application, as shown in FIG. 4, employs a unified memory that is addressable via a common virtual memory address space for accessing physical processor memory 401-402 and GPU memory 420-423. In such an implementation, operations performed on GPU 410-413 access processor memory 401-402 and vice versa with the same virtual / effective memory address space, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated GPU memory 420, etc. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of processor memory 401-402 and GPU memory 420-423, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0123] In one embodiment, bias / coherence management circuit 494A-494E within one or more of MMU 439A-439E ensures cache coherence between host processors (e.g., 405) and the caches of GPU 410-413, and implements bias techniques that indicate the physical memory in which certain types of data should be stored. WhileFigure 4F Multiple instances of bias / coherency management circuitry 494A-494E are shown in the middle, but the bias / coherency circuitry can be implemented within the MMU(s) of the host processor(s) 405 and / or within the accelerator integration circuit 436.

[0124] One embodiment allows GPU additional memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) techniques, but without the typical performance penalties associated with full system cache coherency. This ability to access GPU additional memory 420-423 as system memory without the heavy cache coherency overhead provides a beneficial operating environment for GPU offload. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU additional memory 420-423 without cache coherency overhead can be critical to the execution time of offloaded computations. In cases with substantial streaming write memory traffic, for example, the cache coherency overhead can significantly reduce the effective write bandwidth seen by the GPU 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offload.

[0125] In one implementation, selection between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table can be used, for example, which can be a page-granularity structure (i.e., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU additional memory page. The bias table can be implemented using a stolen memory range of one or more GPU additional memories 420-423, with or without a bias cache (e.g., to cache frequently used / recently used entries of the bias table) in the GPU 410-413. Alternatively, the entire bias table can be kept within the GPU.

[0126] In one implementation, the bias table entries associated with each access to GPU additional memory 420-423 are accessed prior to the actual access to the GPU memory, resulting in the following operations. First, local requests from the GPUs 410-413 that look for their pages in the GPU bias (these local requests find their pages in the GPU bias) are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPUs that look for their pages in the host bias (these local requests find their pages in the host bias) are forwarded to the processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, requests from the processor 405 that look for requested pages in the host processor bias complete like a normal memory read request. Alternatively, requests for GPU bias pages can be forwarded to the GPUs 410-413. Then, if the GPU is not currently using the page, it can transition the page to the host processor bias.

[0127] The bias state of a page can be changed by a software-based mechanism, a hardware- assisted software-based mechanism, or a purely hardware-based mechanism for a limited set of cases.

[0128] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn invokes a device driver of the GPU, which in turn sends a message (or queues a command descriptor) to the GPU, instructing it to change the bias state and, for some transitions, perform a cache flushing operation in the host. The cache flushing operation is needed for a transition from the host processor 405 bias to the GPU bias, but is not needed for the reverse transition.

[0129] In one embodiment, cache coherency is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 405. To access these pages, the processor 405 can request access from the GPU 410, which can or can not grant access immediately depending on the implementation. Thus, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are those pages that are needed by the GPU but not needed by the host processor 405 (and vice versa).

[0130] Graphics Processing Pipeline

[0131] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor can implement the graphics processing pipeline 500 shown. The graphics processor can be included within a parallel processing subsystem as described herein, such as the parallel processor 200 of FIG. 2, which in one embodiment is a GPU.Figure 1 Variations of the parallel processor 112 of FIG. 4A are also capable of performing the functions of the graphics processing pipeline 500. For example, the shader

[0132] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to shade and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data, stored in caches, local or system memory, to use when processing vertex data and can be programmed to transform the vertex data from an object-based coordinate representation to the world space coordinate space or the normalized device coordinate space.

[0133] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads stored vertex attributes as needed, and constructs graphics primitives for processing by the tessellation control processing unit 508. The graphics primitives include triangles, lines, points, patches, and the like, as supported by various graphics processing application programming interfaces (APIs).

[0134] The tessellation control processing unit 508 treats the input vertices as control points for the geometry patch. The control points are converted from the input representation (e.g., the base of the patch) from the patch to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate tessellation factors for the edges of the geometry patch. The tessellation factors are applied to individual edges and quantify the view-dependent level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parametric coordinates of the tessellated patch to generate surface representations and vertex attributes for each vertex associated with the geometric primitives.

[0135] A second instance of the primitive assembler 514 receives the vertex attributes from the tessellation evaluation processing unit 512, reads the stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphics primitives into one or more new graphics primitives and compute parameters for rasterization of the new graphics primitives.

[0136] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry stream. The geometry processing unit 516 outputs the parameters and vertices that specify the new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scale, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use while processing the geometry data. The viewport scale, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0137] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion of new graphics primitives to generate fragments, and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit that is configured to perform fragment shader programs or pixel shader programs. The fragment / pixel processing unit 524 transforms fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader programs. For example, the fragment / pixel processing unit 524 can be programmed to perform operations such as, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction that produce an output of shaded fragments or pixels to the raster operations unit 526. The fragment / pixel processing unit 524 can read data stored in the parallel processor memory or system memory for use while processing fragment data. The fragment or pixel shader programs can be configured to shade with samples, pixels, tiles, or other granularity depending on the sampling rate configured for the processing unit.

[0138] The raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stencil operations, z-test operations, blending operations, and the like. The raster operations unit 526 outputs pixel data as processed graphics data, which is stored in graphics memory (e.g., parallel processor memory 222 and / or system memory 104 in FIG. 2) for display on one or more display devices 110, for further processing by one or more processors 102 or parallel processor(ies) 112, or for some combination thereof. In some embodiments, the raster operations unit 526 is configured to compress z or color data that is written to memory and decompress z or color data that is read from memory. Figure 1

[0139] Position Only Shading Pipeline (POSH) with Coarse Z Buffer

[0140] Figure 6 is a conceptual diagram 600 of an example of a position only shading pipeline (POSH) configured with a coarse Z buffer system according to embodiments. The POSH configured with a Z buffer system can include a POSH system 602 including a power supply 604 to supply power to the POSH system 602. The POSH system 602 can include a graphics pipeline device 606. The graphics pipeline device 606 can include a position only shading pipeline (POSH) 608, a coarse Z buffer 610, and a rendering pipeline 612. In some embodiments, the graphics pipeline can be as described in FIG. 6A. Figure 5 ​As described at the POSH 608 at the graphics processing pipeline 500. The POSH 608 can perform at least one of positioning geometry data, performing screen space transforms, and culling surface triangles. The geometry data can include surface triangles for a digital representation of a scene. A coarse Z buffer 612 can be used by the POSH 608 to perform coarse rasterization of one or more of the surface triangles identified in one or more of the non-exclusion regions. A rendering pipeline 612 can render the surface triangles remaining after the culling.

[0141] The POSH system 602 can further include a memory 614 coupled to a processor (not shown). The memory 614 can include geometry data 616, lens parameters 618, coarse Z values 620, application parameters 622, performance parameters 624, and / or distribution and density attributes 626. The POSH system 602 can include a display subsystem 628 for displaying rendered geometry data.

[0142] Figure 7A is a conceptual diagram 700 of an example of a field of view exclusion region according to an embodiment. As in Figure 6 The POSH, as described at the POSH 608 in the POSH system 602, can identify one or more exclusion regions 702-740 and non-exclusion regions 742, 744 in a field of view of a user (e.g., a user's view through a see-through view of a headset). The exclusion regions 702-740 and non-exclusion regions 742, 744 can be based on lens parameters and / or foveal parameters for varying image resolution or amount of detail across an image, e.g., according to one or more "fixation points," such as a first fixation point identified by coordinates 746, 748 or a second fixation point identified by coordinates 750, 748. The fixation points can indicate one or more priority resolution areas (e.g., highest) of an image, such as the non-exclusion regions 742, 744, and can correspond to a center of a retina of a user's eye, i.e., a point of regard. One or more surface triangles can be identified by the POSH as exclusion triangles to be culled that are located in one or more exclusion regions, and one or more of the surface triangles can be identified by the POSH as non-exclusion triangles to be rendered that are located in one or more non-exclusion regions. The surface triangles identified as exclusion triangles can include surface triangles at least a portion of which are in one or more of the exclusion regions 702-740, and wherein the surface triangles identified as non-exclusion triangles can include surface triangles that are in one or more of the non-exclusion regions 742, 744.

[0143] Figure 7Bis a flowchart of an example of a method 760 of managing a position only shading pipeline (POSH) according to embodiments. The method 760 can be implemented as a module or related component in a set of logic instructions stored in a non-transitory machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed- function hardware logic using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technologies, or any combination thereof. For example, a computer program code that is used to perform operations shown in method 760 can be written in any combination of one or more programming languages, including an object oriented programming language such as JAVA, SMALLTALK, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages.

[0144] The illustrated processing block 762 provides for computing positions of the geometry data by the POSH. The processing block 764 provides for performing screen space transforms by the POSH. The illustrated processing block 766 provides for identifying surface triangles in one or more of the exclusion regions by the POSH. The processing block 768 provides for culling the one or more surface triangles identified in the exclusion regions by the POSH. The size of the exclusion and non-exclusion regions can be set based on culling parameters. In one implementation, at least a portion of surface triangles located in an exclusion region can be identified as exclusion triangles. The processing block 770 provides for rendering surface triangles identified as located in one or more non-exclusion regions.

[0145] Figure 8Ais a conceptual diagram 800 of an example of a vertex shader 802 in a POSH 804 according to embodiments. A graphics pipeline device 806 can expose surface triangles to the vertex shader 802 and include a render pipeline 808. The render pipeline 808 can stream out data including vertices for tessellation of a patch. The graphics pipeline device 806 can include a clipper 810 and / or settings 812. The clipper 810 and / or settings 812 can be implemented with programmable logic and / or fixed function hardware logic. The graphics pipeline device 806 can adjust a granularity setting, an exclusion region, a non-exclusion region, a clipper parameter, or a settings parameter of stream out data based on a location of one or more of the surface triangles, an application parameter, a lens parameter, or a property of the stream out data. The property of the stream out data can include one or more of a granularity of the stream out data, a motion or a direction of one or more objects, or a gaze of a user. The graphics pipeline device 806 can expose the stream out data to a vertex shader in the POSH 804 based on the adjustment of the granularity setting, the exclusion region, the non-exclusion region, the clipper parameter, or the settings parameter of the stream out data, and wherein the POSH 804 can cull the stream out data.

[0146] Figure 8B is a conceptual diagram 830 of an example of a field of view including a near plane 832 and a far plane 834 according to embodiments. The clipper 810 and / or settings 812 can be dynamically configured based on a depth of a field 836, which can be based on one or more of an application parameter, a lens parameter, or a property of stream out data.

[0147] Turning now to Figure 8C , an example of a method 850 of exposing stream out data to a vertex shader in a POSH according to embodiments is shown. The method 850 can be implemented as a module or related component in a set of logic instructions stored in a non-transitory machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as PLA, FPGA, CPLD, in fixed-functionality hardware logic using circuit technology such as ASIC, CMOS, or TTL or any combination thereof.

[0148] The shown processing box 852 provides for performing geometric culling in POSH. Processing box 854 provides for generating outflow data in the rendering pipeline. The shown processing box 856 provides for dynamically adapting the clipper and / or settings based on the outflow data, the excluded regions, the non-excluded regions, the clipper parameters, or the setting parameters. Box 856 also provides for exposing the outflow data to vertex shaders in POSH so that POSH can further culle the outflow data based on adjustments to the granularity settings of the outflow data, the excluded regions, the non-excluded regions, the clipper parameters, or the setting parameters. The granularity settings can also be based on the position of one or more surface triangles, lens parameters, or attributes of the outflow data. Attributes of the outflow data can include the granularity of the outflow data, the motion or orientation of one or more objects, or one or more of the user's gaze.

[0149] Figure 9A This is a conceptual diagram of example 900 of a surface triangle in a scene representation having exclusion regions 902, 904, 906, and 908 according to an embodiment. A Position-Only Shading Pipeline (POSH) can create a coarse Z-buffer associated with the POSH while processing geometric data. The POSH can perform coarse rasterization based on the coarse Z-value, or one or more performance parameters. The coarse Z-value(s) can indicate the granularity level of detail in the scene. The POSH can store one or more surface triangles as coarse Z-buffer triangles in coarse Z-order. The coarse Z-order can be from Z... 最大 Value to Z 最小 The values ​​are sorted by depth, where Z 最小 Value and the Z 最大 The values ​​can identify and / or correspond to the near and far planes in the scene (e.g., such as...). Figure 8B (As shown at 832, 834). Surface triangles stored as Z-buffer triangles may include non-excluded triangles 910, 912 located within one or more non-excluded regions, and a non-excluded triangle 914 identified as being occluded by at least one other non-excluded triangle identified as opaque. A coarse Z-value can determine the size of exclusion regions 902, 904, 906, 908, and determine whether one or more surface triangles 916 are identified as exclusion triangles, wherein at least a portion of surface triangle 916 is located within one or more exclusion regions. POSH can set the size of the coarse Z-buffer based on the coarse Z-value. The size of the coarse Z-buffer can be proportional to the coarse Z-value. POSH can feed the coarse Z-buffer forward to the rendering pipeline, and the rendering pipeline can render the Z-buffer triangles.

[0150] Figure 9Bis a conceptual diagram 930 of examples of resolution segments 932, 934, 936 having various sizes according to embodiments. The resolution segments can be based on one or more coarse Z values 938, 940, 942 that can indicate a level of granularity of detail in a scene that is to be used by a Position Only Shading Pipeline (POSH) to process geometry data for the scene.

[0151] Figure 9C is a flowchart 950 of an example of a method of managing coarse-granularity rasterization with a coarse Z buffer according to embodiments. The method 950 can be implemented as a module or related components in a set of logical instructions stored in a non-transitory machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as for example a PLA, FPGA, CPLD, in fixed- function hardware logic using circuit technology such as for example ASIC, CMOS, or TTL technology, or any combination thereof.

[0152] The illustrated process block 952 provides for creating a coarse Z buffer by a POSH in processing geometry data. The illustrated process block 954 provides for performing coarse rasterization based on coarse Z values. The process block 954 can further provide for storing one or more of the surface triangles in a Z buffer triangle in a coarse Z order. The coarse Z order can be a depth-ordered order from Z 最大 values to Z 最小 values. The Z 最小 values and the Z 最大 values can correspond to and / or identify a near plane and a far plane in a scene. The illustrated process block 956 provides for sizing the coarse Z buffer based on the coarse Z values, where the size of the coarse Z buffer is proportional to the coarse Z values. The illustrated process block 958 provides for feeding forward the coarse Z buffer to a rendering pipeline, and the rendering pipeline can render the coarse Z buffer triangle. In one implementation, the coarse Z buffer triangle processing by the rendering pipeline can be further processed by the POSH to refine culling of the surface triangles.

[0153] Figure 10Ais a conceptual diagram 1000 of multiple graphics processing units (GPUs) 1002, 1004 in communication with a position only shading pipeline (POSH) 1006, according to an embodiment. The POSH 1006 can process and sort (e.g., in coarse Z order) primitives from geometry data. The graphics processing pipeline and / or the POSH 1006 can determine a number and size of resolution fragments used to process the primitives. The graphics processing pipeline and / or the POSH 1006 can determine one or more GPUs 1002, 1004 in communication with the POSH 1006. The POSH 1006 can generate a geometry stream for the multiple GPUs 1002, 1004 based on determining the one or more GPUs 1002, 1004 in communication with the POSH 1006.

[0154] Figure 10B is a conceptual diagram 1030 of an example of a distribution and density attribute storage implementation, according to an embodiment. The POSH 1032 can record and / or store distribution and density attributes of primitives in a distribution and density attribute storage 1034, and a rendering pipeline 1036 can determine how many and how large resolution fragments to use to render the primitives based on one or more of the distribution and density attributes.

[0155] Figure 10C is a flowchart 1050 of an example of a method of rendering primitives using a position only shading pipeline (POSH) with multiple GPUs, according to an embodiment. The method 1050 can be implemented as modules or related components of a logical instruction set stored in non-transitory, machine- or computer-readable storage medium, such as a RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as a PLA, FPGA, CPLD, in fixed-functionality hardware logic using circuit technology such as ASIC, CMOS, or TTL technology, or any combination thereof.

[0156] The illustrated process block 1052 provides for processing and sorting the primitives of the geometry data. The illustrated process block 1054 provides for recording and / or storing the distribution and density attributes. The illustrated process block 1056 provides for determining a number and size of resolution fragments used to render the geometry data. The illustrated process block 1058 provides for determining whether multiple GPUs are in communication with a position only shading pipeline (POSH). The illustrated process block 1060 provides for generating, by the POSH, a geometry stream for the multiple GPUs. The illustrated process block 1062 provides for rendering the primitives based on the resolution fragments.

[0157] Head-Mounted Display System Overview

[0158] Figure 11A head-mounted display (HMD) system 1100 worn by a user while experiencing an immersive environment, such as, for example, a virtual reality (VR) environment, an augmented reality (AR) environment, a multiplayer three-dimensional (3D) game, etc., is shown. In the illustrated example, one or more straps 1120 hold a frame 1102 of the HMD system 1100 in front of the user's eyes. Accordingly, a left eye display 1104 is positioned to be viewed by the user's left eye and a right eye display 1106 is positioned to be viewed by the user's right eye. In certain examples, such as, for example, a smartphone worn by the user, the left eye display 1104 and the right eye display 1106 can alternatively be integrated into a single display. In the case of AR, the displays 1104, 1106 can be see-through displays that allow the user to view a physical environment with other rendered content (e.g., virtual characters, informational annotations, heads-up displays / HUDs) presented over a live feed of the physical environment.

[0159] In one example, the frame 1102 includes a left downward looking camera 1108 to capture images from an area generally in front of the user and below the left eye (e.g., left hand gestures). In addition, a right downward looking camera 1110 can capture images from an area generally in front of the user and below the right eye (e.g., right hand gestures). The illustrated frame 1102 also includes a left forward looking camera 1112 and a right forward looking camera 1114 to capture images in front of the user's left and right eyes, respectively. The frame 1102 can also include a left side looking camera 1116 to capture images from an area to the left of the user and a right side looking camera 1118 to capture images from an area to the right of the user.

[0160] Images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118, which can have overlapping fields of view, can be used to detect gestures made by the user as well as analyze the external environment and / or render the external environment on the displays 1104, 1106. In one example, the detected gestures are used by a (e.g., internal and / or external) graphics processing architecture to render and / or control a virtual representation of the user in a 3D game. Indeed, the overlapping fields of view can enable the capture of gestures made by other individuals (e.g., in a multiplayer game), where the gestures of the other individuals can also be used to render / control the immersive experience. The overlapping fields of view can also enable the HMD system 1100 to automatically detect obstructions or other hazards in the vicinity of the user. Such an approach is particularly advantageous in advanced driver assistance system (ADAS) applications.

[0161] In one example, the left and right down looking cameras 1108, 1110, which provide overlapping fields of view, provide stereoscopic views with increased resolution. The increased resolution can in turn enable very similar user movements to be distinguished from one another (e.g., with sub-millimeter accuracy). The result can be enhanced performance of the HMD system 1100 with respect to reliability. In fact, the solution presented is useful in a wide variety of applications, such as, for example, colorizing information in AR settings, exchanging virtual tools / devices between multiple users in a multi-user environment, rendering virtual items (e.g., weapons, swords, personnel), etc. The pose of other objects, limbs, and / or body parts can also be detected and used to render / control the virtual environment. For example, spinal cord signals, electroencephalograph signals, eye tracking, breathing or panting, hand motions, etc. can be tracked in real-time, either from the wearer or from other individuals in the shared environment. Images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118 can also be used as contextual inputs. For example, it can be determined that the user is indicating a particular word to be edited in a word processing application or a particular key to be pressed, a particular weapon or direction of travel to be deployed in a game, etc.

[0162] Further, images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118 can be used to implement shared communication or networked interaction in device operation, medical training, and / or tele / remote operation guidance applications. Task-specific pose libraries or neural network machine learning can enable tool identification and feedback to the task. For example, virtual tools can be enabled that translate into remote, real-world actions. In yet another example, the HMD system 1100 translates manipulation of a virtual drill within a virtual scene into remote operation of a drill on a robotic device deployed to search a collapsed building. Moreover, the HMD system 1100 can be programmable to the extent of protocols that include, for example, enable users to add new poses to a list of identifiable poses associated with user actions.

[0163] Additionally, the various cameras in the HMD 1100 can be configurable to detect frequencies of the spectrum outside of the visible wavelengths of the spectrum. The multispectral imaging capability of the input cameras allows for tracking of the position of the user and / or objects by eliminating unnecessary image features (e.g., background noise). For example, in an augmented reality (AR) application such as surgery, instruments and devices are tracked by their infrared reflectivity without the need for additional tracking aid devices. Moreover, the HMD 1100 can be employed in low visibility situations, where "live feeds" from the various cameras can be analyzed by a computer to be augmented or enhanced and displayed to the user as visual or audio cues.

[0164] The HMD system 1100 can also forego performing any type of data communication with remote computing systems or requiring a power cord (e.g., stand-alone mode of operation). In this regard, the HMD system 1100 can be a "cordless" device having a power unit that enables the HMD system 1100 to operate independent of an external power system. Accordingly, a user can play a full-featured game without being tethered to another device (e.g., game console) or power source. In the word processing example, the HMD system 1100 presents a virtual keyboard and / or virtual mouse on the displays 1104 and 1106 to provide a virtual desktop or word processing scenario. Thus, pose identification data captured by one or more of the cameras represents user typing activity on the virtual keyboard or movement of the virtual mouse. Advantages include, but are not limited to, portability and privacy of a virtual desktop from individuals nearby. The underlying graphics processing architecture can support compression and / or decompression of video and audio signals. Also, providing separate images to the user's left and right eyes can assist in rendering, generating, and / or perceiving 3D scenes. The relative positions of the left eye display 1104 and the right eye display 1106 can also be adjustable to match variations in interocular separation between different users.

[0165] Figure 11 The number of cameras shown in the middle is merely to aid in the discussion. In fact, the HMD system 1100 can include fewer than six or more than six cameras depending on the environment.

[0166] Functional Components of an HMD System

[0167] Figure 12 The HMD system is shown in more detail. In the example shown, the frame 1102 includes a power unit 1200 (e.g., battery power, adapter) that provides power to the HMD system. The frame 1102 also includes a motion tracking module 1220 (e.g., accelerometer, gyroscope) that provides motion tracking data, orientation data, and / or position data to a processor system 1204. The processor system 1204 can include a network adapter 1224 coupled to an I / O bridge 1206. The I / O bridge 1206 can enable communication between the network adapter 1224 and various components such as, for example, an audio input module 1210, an audio output module 1208, a display device 1207, an input camera 1202, and so on.

[0168] In the example shown, the audio input module 1210 includes a right audio input 1218 and a left audio input 1216 that detect sound that can be processed to identify voice commands of the user and individuals nearby. Voice commands identified in the captured audio signals can enhance pose identification during modal switching and other applications. Also, the captured audio signals can provide 3D information to enhance an immersive experience.

[0169] The audio output module 1208 can include a right audio output 1214 and a left audio output 1212. The audio output module 1208 can deliver sound to the ears of a user and / or other nearby individuals. The audio output module 1208 can be in the form of earbuds, on-ear speakers, over-ear speakers, loudspeakers, etc., or any combination thereof, the audio output module 1208 can deliver stereo and / or 3D audio content to the user (e.g., spatially localized). The illustrated frame 1102 also includes a wireless module 1222 that facilitates communication between the HMD system and various other systems (e.g., computers, wearable devices, game consoles). In one example, the wireless module 1222 communicates with the processor system 1204 via a network adapter 1224.

[0170] The illustrated display device 1207 includes a left eye display 1104 and a right eye display 1106, where virtual content rendered on the displays 1104, 1106 can be obtained from the processor system 1204 via an I / O bridge 1206. The input cameras 1202 can include the left side look camera 1116, the right side look camera 1118, the lower left look camera 1108, the front left look camera 1112, the front right look camera 1114, and the lower right look camera 1110, which have already been discussed.

[0171] Turning now to Figure 13 , a general processing cluster (GPC) 1300 is shown. The illustrated GPC 1300 can be incorporated into a processing system such as, for example, the processor system 1204 (already discussed) Figure 12 ) already discussed. The GPC 1300 can include a pipeline manager 1302 that communicates with a scheduler 1306. In one example, the pipeline manager 1302 receives tasks from the scheduler 1306 and assigns them to one or more of the streaming multi-processors (SMs) 1304. Each of the SMs 1304 can be configured to process a different set of

[0172] Thus, as each SM 1304 sends a processed task to the work distribution crossbar 1308, the processed task can be provided to another GPC 1300 for further processing. The output of SM 1304 can also be sent to a pre-raster operations (pre-ROP) unit 1314 that is configured to perform operations such as address translations, organize picture color data, perform alpha test, blend color, and the like. The SM 1304 can include an internal first level (LI) cache (not shown) that can store data stored in the memory 1312. The SM 1304 can also have access to a second level (L2) cache (not shown) via the memory management unit (MMU) 1310, and a first level one and a half (LI.5) cache 1306. The MMU 1310 can be configured to translate virtual addresses into physical addresses, and can include a set or range of page table entries (PTE) use to map a virtual address into a physical address of a location of a memory. The illustrated GPU 1300 includes a texture unit 1312.

[0173] Graphics Pipeline Architecture

[0174] Turning now to Figure 14 , a graphics processing pipeline 1400 is shown. In the illustrated example, a world space pipeline 1420 includes a primitive distributor (PD) 1402. The PD 1402 can collect vertex data associated with high order services, graphics primitives, triangles, and the like, and send the vertex data to a vertex attribute fetch unit (VAF) 1404. The VAF 1404 can fetch vertex attributes associated with each incoming vertex from shared memory and store the vertex data and associated vertex attributes to shared memory.

[0175] The illustrated world space pipeline 1420 also includes a vertex, tessellation, geometry processing unit (VTG) 1406. The VTG 1406 can include, for example, a vertex processing unit, a tessellation initialization processing unit, a task distributor, a task generation unit, a topology generation unit, a geometry processing unit, a tessellation processing unit, and the like, or any combination thereof. In one example, the VTG 1406 is a programmable execution unit configured to execute geometry programs, tessellation programs, and vertex shader programs. The programs executed by the VTG 1406 can process vertex data and vertex attributes received from the VAF 1404. Also, the programs executed by the VTG 1406 can generate graphics primitives, color values, surface normal factors, and transparency values at each vertex of a graphics primitive for further processing within the graphics processing pipeline 1400.

[0176] The vertex processing units of the VTG 1406 can be programmable execution units that execute vertex shader programs that light and transform vertex data as specified by the vertex shader programs. For example, the vertex processing units can be programmed to transform vertex data from an object-based coordinate representation (e.g., object space) to an alternative coordinate system such as world space or normalized device coordinates (NDC) space. In addition, the vertex processing units can read vertex data and vertex attributes stored in shared memory by the VAF 1404 and process the vertex data and vertex attributes. In one example, the vertex processing units store the processed vertices in shared memory.

[0177] The tessellation initialization processing units (e.g., hull shader, tessellation control shader) can execute tessellation initialization shader programs. In one example, the tessellation initialization processing units process vertices generated by the vertex processing units and generate graphics primitives sometimes referred to as "patches." The tessellation initialization processing units can also generate various patch attributes, where the patch data and patch attributes are stored in shared memory. The task generation unit of the VTG 1406 can fetch the data and attributes of the vertices and patches from shared memory. In one example, the task generation unit generates tasks for processing the vertices and patches for processing by later stages in the graphics processing pipeline 1400.

[0178] The tasks generated by the task generation unit can be redistributed by the task distributor of the VTG 1406. For example, the tasks generated by various instances of the vertex shader programs and the tessellation initialization programs can be significantly different between one graphics processing pipeline 1400 and another. Accordingly, the task distributor can redistribute the tasks so that each graphics processing pipeline 1400 has nearly the same workload at later pipeline stages.

[0179] As already discussed, the VTG 1406 can also include a topology generation unit. In one example, the topology generation unit fetches the tasks distributed by the task distributor, indexes the vertices including the vertices associated with the patches, and computes tessellation vertices and coordinates (UVs) of indices to connect the tessellation vertices to form graphics primitives. The indexed vertices can be stored in shared memory by the topology generation unit. The tessellation processing units of the VTG 1406 can be configured to execute tessellation shader programs (e.g., domain shader, tessellation evaluation shader). The tessellation processing units can read input data from shared memory and write output data to shared memory. The output data can be passed from shared memory to the geometry processing units (e.g., next shader stage) as input data.

[0180] The geometry processing unit of the VTG 1406 can execute a geometry shader program to transform graphics primitives (e.g., triangles, lines, points, etc.). In one example, vertices are grouped to construct a graphics primitive, where the geometry processing unit subdivides the graphics primitive into one or more new graphics primitives. The geometry processing unit can also compute parameters such as, for example, plane equation coefficients that can be used to rasterize the new graphics primitives.

[0181] The illustrated world space pipeline 1420 also includes a viewport scaling, culling, and clipping unit (VPC) 1408 that obtains parameters and vertices that define new graphics primitives from the VTG 1406. In one example, the VPC 1408 performs clipping, flipping, perspective correction, and viewport transformation to identify graphics primitives that can potentially be viewed in a final rendered image. The VPC 1408 can also identify graphics primitives that can not be viewable.

[0182] The graphics processing pipeline 1400 can also include a tiling unit 1410 coupled to the world space pipeline 1420. The tiling unit 1410 can be a graphics primitive ordering engine, where graphics primitives are processed in the world space pipeline 1420 and then sent to the tiling unit 1410. In this regard, the graphics processing pipeline 1400 can also include a screen space pipeline 1422, where screen space can be divided into cache tiles. Each cache tile can thus be associated with a portion of screen space. For each graphics primitive, the tiling unit 1410 can identify a set of cache tiles that intersect (e.g., tile) the graphics primitive. After tiling a number of graphics primitives, the tiling unit 1410 can process the graphics primitives on a cache tile by cache tile basis. In one example, graphics primitives associated with a particular cache tile are sent to a setup unit 1412 in the screen space pipeline 1422 one tile at a time. A graphics primitive that intersects multiple cache tiles can be processed in the world space pipeline 1420 once, but sent to the screen space pipeline 1422 multiple times.

[0183] In one example, the setup unit 1412 receives vertex data from the VPC 1408 via the tiling unit 1410 and computes parameters associated with the graphics primitives. The parameters can include, for example, edge equations, bias plane equations, and depth plane equations. The screen space pipeline 1422 can also include a rasterizer 1414 coupled to the setup unit 1412. The rasterizer can scan convert the new graphics primitives and send fragment and coverage data to a pixel shading unit (PS) 1416. The rasterizer 1414 can also perform Z culling and other Z-based optimizations.

[0184] The PS 1416, which has access to shared memory, can execute a fragment shader program that transforms the fragments received from the rasterizer 1414. More specifically, the fragment shader program can shade the fragments at a pixel level granularity (e.g., work as a pixel shader program). In another example, the fragment shader program shades the fragments at a sample level granularity, where each pixel includes multiple samples, and each sample represents a portion of the pixel. Also, depending on the environment (e.g., sampling rate), the fragment shader program can shade the fragments at any other granularity. The PS 1416 can perform blending, shading, perspective correction, texture mapping, etc. to generate shaded fragments.

[0185] The illustrated screen space pipeline 1422 also includes a raster operations unit (ROP) 1418 that can perform operations such as stencil, Z test, blending, and so forth. The ROP 1418 can then output the pixel data as processed graphics data to one or more rendered targets (e.g., a graphics memory). The ROP 1418 can be configured to compress Z or color data that is written to memory and decompress Z or color data that is read from memory. The location of the ROP 1418 can vary depending on the environment.

[0186] The graphics processing pipeline 1400 can be implemented by one or more processing elements. For example, the VTG 1406 and / or the PS 1416 can be implemented in one or more SMs, the PD 1402, the VAF 1408, the binning unit 1410, the setup unit 1412, the rasterizer 1414, and / or the ROP 1418 can be implemented in the processing elements of the particular GPCs in conjunction with the corresponding partition units. The graphics processing pipeline 1400 can also be implemented in fixed function hardware logic. Indeed, the graphics processing pipeline 1400 can be implemented in a PPU.

[0187] Thus, the illustrated world space pipeline 1420 processes graphics objects in 3D space, where the position of each graphics object is known relative to other graphics objects and to a 3D coordinate system. In contrast, the screen space pipeline 1422 can process graphics objects that have been projected from the 3D coordinate system to a 2D planar surface representing the surface of a display device. Moreover, the world space pipeline 1420 can be divided into an alpha stage pipeline and a beta stage pipeline, where the alpha stage pipeline includes the pipeline stages from the PD 1402 up to the task generation unit. The beta stage pipeline includes the pipeline stages from the topology generation unit up to the VPC 1408. In such a case, the graphics processing pipeline 1400 can perform a first set of operations (e.g., single thread, thread group, multiple thread groups acting in concert) in the alpha stage pipeline and a second set of operations (e.g., single thread, thread group, multiple thread groups acting in concert) in the beta stage pipeline.

[0188] If multiple graphics pipelines 1400 are in use, the vertex data and vertex attributes associated with a set of graphics objects can be divided so that each graphics processing pipeline 1400 has a similar workload throughout the alpha stage. Accordingly, the alpha stage processing can substantially scale the number of vertex data and vertex attributes, such that the number of vertex data and vertex attributes generated by the task generation unit is significantly greater than the number of vertex data and vertex attributes processed by the PD 1402 and VAF 1404. Moreover, the task generation units associated with different graphics processing pipelines 1400 can generate vertex data and vertex attributes having different quality levels, i.e., start the alpha stage with the same number of attributes. In such a case, the task distributor can redistribute the attributes generated by the alpha stage pipeline, such that each graphics processing pipeline 1400 has approximately the same workload at the beginning of the beta stage pipeline.

[0189] Turning now to Figure 15 A streaming multiprocessor (SM) 1500 is shown. The illustrated SM 1500 includes a K scheduler unit 1504 coupled to an instruction cache 1502, where each scheduler unit 1504 receives a thread block array from a thread block scheduler (not shown) and manages scheduling of instructions for one or more thread blocks in each active thread block array. The scheduler unit 1504 can schedule threads for execution in parallel thread groups, where each group can be referred to as a "warp." Accordingly, each thread of a warp can execute identical instructions. In addition, the scheduler unit 1504 can manage a plurality of different thread blocks, allocating thread blocks to warps for execution. The scheduler unit can then schedule instructions from multiple different warps on various functional units during each clock cycle. Each scheduler unit 1504 can include one or more instruction dispatch units 1522, where each dispatch unit 1522 sends instructions to one or more of the functional units. The number of dispatch units 1522 can vary depending on the environment. In the illustrated example, the scheduler unit 1504 includes two dispatch units 1522 that cause two different instructions from the same thread block to be dispatched during each clock cycle.

[0190] The SM 1500 can also include a register file 1506. The register file 1506 includes a set of registers that are allocat ed to and used by the functional units of the SM 1500. The register file 1506 is divided into an instruction register set 1522 and a data register set 1524. In one example, the instruction register set 1522 is used to store instructions and instruction related data that are used by the functional units of the SM 1500. The data register set 1524 is used to store data

[0191] The illustrated SM 1500 also includes M double precision units (DPUs) 1510, N special function units (SFUs) 1512, and P load / store units (LSUs) 1514. Each DPU 1510 can implement double-precision floating point arithmetic and each SFU 1512 can perform special functions such as, for example, a fast fourier transform (FFT). Additionally, each LSU 1514 can perform load and store operations between the shared memory 1518 and the register file 1506. In one example, the load and store operations are performed on a cache line granular level. In one example, the cache line granularity is 128 bytes. The load store units 1514 couple with the shared memory 1518 and the register file 1506, in one example, via a crossbar.

[0192] The SM 1500 can be implemented in a graphics processor (e.g., a graphics processing unit / GPU), where the texture units / L1 caches 1520 access texture mapping from memory and sample the texture mappings to generate sampled texture values for the shader programs. The texture operations performed by the texture units / L1 caches 1520 include, but are not limited to, trilinear interpolation and anisotropic filtering. In one example, the graphics processor includes multiple banks of the shared memory 1518 for efficient memory

[0193] Additional System Overview Examples

[0194] Figure 16is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and can be a single processor desktop system, a multiprocessor workstation system, or a server system having many processors 1602 or processor cores 1607. In one embodiment, system 1600 is a processing platform incorporated within a system-on-a-chip (SoC) for use in mobile, handheld, or embedded devices.

[0195] Embodiments of system 1600 can include or be included in a server-based gaming platform, a game console (including game and media consoles), a mobile gaming console, a handheld game console, or an online game console. In some embodiments, system 1600 is a mobile phone, a smart phone, a tablet, or a mobile internet device. Data processing system 1600 can also include, be coupled to, or be integrated within a wearable device, such as a smart watch wearable device, smart glasses device, augmented reality device, or virtual display device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface produced by one or more graphics processors 1608.

[0196] In some embodiments, one or more processors 1602 each include one or more processor cores 1607 to process instructions which, when executed, implement the operations of system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, instruction set 1609 can facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). Multiple processor cores 1607 can each process a different instruction set 1609, which can include instructions to facilitate the emulation of other instruction sets. Processor core 1607 can also include other processing devices, such as a digital signal processor (DSP).

[0197] In some embodiments, the processor 1602 includes cache memory 1604. Depending upon the architecture, the processor 1602 can have a single -level cache or a multi -level cache. In some embodiments, the cache memory is shared among the various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or last level cache (LLC) (not shown) that can be shared between the processor cores 1607 using known cache coherency techniques. A register file 1606 is also included in the processor 1602, which can include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). Some of the registers can be general registers, while others can be specific to the design of the processor 1602.

[0198] In some embodiments, the processor 1602 is coupled to a processor bus 1610 for communicating data signals between the processor 1602 and other components in the system 1600, such as address, data, or control signals. In one embodiment, the system 1600 uses an exemplary 'hub' system architecture, including a memory controller hub 1616 and an input / output (I / O) controller hub 1630. The memory controller hub 1616 facilitates communication between the memory device and other components in the system 1600, while the I / O controller hub 1630, provides connections between the

[0199] The memory device 1620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase- change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment, the memory device 1620 can operate as system memory for the system 1600, to store data 1622 and instructions 1621 for use when executing applications or processes by one or more processors 1602. The memory controller hub 1616 also couples with an optional external graphics processor 1612, which can couple with the graphics processor 1608 in the processor 1602, for performing graphics and media operations.

[0200] In some embodiments, ICH 1630 enables peripheral devices to be connected to memory devices 1620 and processor 1602 via a high-speed I / O bus. I / O peripherals include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., hard disk drive, flash memory, etc.), and a legacy I / O controller 1640 for coupling to legacy (e.g., Personal Systems 2 (PS / 2)) devices. One or more Universal Serial Bus (USB) controllers 1642 connect input devices such as keyboard and mouse 1644 combinations. A network controller 1634 can also be coupled to ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1610. It will be appreciated that the system 1600 shown is exemplary and not limiting, as other types of data processing systems that are differently configured can also be used. For example, the I / O controller hub 1630 can be integrated within the one or more processors 1602, or the memory controller hub 1616 and the I / O controller hub 1630 can be integrated within a separate external graphics processor, such as external graphics processor 1612.

[0201] Figure 17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A-1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Figure 17 Those elements of the system 1700 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. The processor 1700 can include additional cores up to and including the additional core 1702N represented by the dashed line box. Each of the processor cores 1702A-1702N includes one or more internal cache units 1704A-1704N. In some embodiments, each processor core is also able to access one or more shared cache units 1706.

[0202] The internal cache units 1704A-1704N and shared cache units 1706 represent a cache memory hierarchy within the processor 1700. The cache memory hierarchy can include at least one level of instruction and data caches within each processor core and one or more levels of shared mid-level caches, such as a level two (L2), level three (L3), level four (L4), or other level cache, with the highest level cache in front of the external memory being classified as an LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 1706 and 1704A-1704N.

[0203] In some embodiments, the processor 1700 also includes a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express buses). The system agent core 1710 provides management functionality for the various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 that manage access to various external memory devices (not shown).

[0204] In some embodiments, one or more of the processor cores 1702A-1702N include support for simultaneous multi-threading. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A-1702N during multi-threaded processing. The system agent core 1710 can additionally include a power control unit (PCU) including logic and components to regulate the power state of the processor cores 1702A-1702N and the graphics processor 1708.

[0205] In some embodiments, the processor 1700 additionally includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, the graphics processor 1708 couples with a set of shared cache units 1706 and the system agent core 1710 includes one or more integrated memory controllers 1714. In some embodiments, a display controller 1711 couples with the graphics processor 1708 to drive graphics processor output to one or more coupled displays. In some embodiments, the display controller 1711 can be separate from the graphics processor 1708, or can be integrated within the graphics processor 1708 or system agent core 1710, coupled with the graphics processor 1708 via at least one interconnect.

[0206] In some embodiments, ring-based interconnect units 1712 are used to couple the internal components of the processor 1700. However, alternative interconnect units can be used, such as point-to-point interconnect, switched interconnect, or other technology. In some embodiments, the graphics processor 1708 couples with the ring interconnect 1712 via an I / O link 1713.

[0207] The exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including an on package I / O interconnect that facilitates communication between various processor components and a high performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702-1702N and the graphics processor 1708 use the embedded memory module 1718 as a shared last level cache.

[0208] In some embodiments, the processor cores 1702A-1702N are homogeneous cores executing the same instruction set architecture. In another embodiment, the processor cores 1702A-1702N are heterogeneous with respect to instruction set architecture (ISA) in that one or more of the processor cores 1702A-1702N execute a first instruction set and at least one of the other cores executes a second instruction set, which can be a subset of the first instruction set or a different instruction set altogether. In one embodiment, the processor cores 1702A-1702N are heterogeneous with respect to microarchitecture in that one or more of the cores has a relatively higher power consumption and one or more of the cores has a relatively lower power consumption. Additionally, the processor 1700 can be implemented on one or more chips or as a SoC integrated circuit having the illustrated components in addition to other components not shown.

[0209] Figure 18 is a block diagram of a graphics processor 1800 that can be a discrete graphics processing unit, or can be graphics processor integrated with one or more processing cores. In some embodiments, the graphics processor communicates with the processor(s) across a bus to register map I / O interface and utilizes commands placed into the processor memory that are fetched and executed by the graphics processor. In some embodiments, the graphics processor 1800 includes a memory interface 1814 to access a memory. The memory interface 1814 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0210] In some embodiments, the graphics processor 1800 also includes a display controller 1802 to drive display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlay planes for compositing and for compositing layers of a video or user-generated interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 to encode, decode, or transcode media into a format native for one or more media

[0211] In some embodiments, graphics processor 1800 includes a block image transfer (BLIT) engine 1804 to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 1810. In some embodiments, graphics processing engine 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0212] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional graphics shapes and scenes using processing functions that act upon 3D primitive shapes (for example, rectangle, triangle, etc.). The 3D pipeline 1812 includes programmable and fixed function elements that perform various tasks to generate output to a display. While the 3D pipeline 1812 can be used to perform media operations, an embodiment of GPE 1810 also includes a media pipeline 1816 that is specifically used to perform media operations, such as video post-processing and image enhancements.

[0213] In some embodiments, media pipeline 1816 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video convert.

[0214] In some embodiments, 3D / media subsystem 1815 includes logic to perform a threadwalk for 3D and media threads generated by 3D pipeline 1812 and media pipeline 1816. In one embodiment, the pipeline sends threadwalk requests to 3D / media subsystem 1815 that includes thread dispatch logic to arbitrate the requests and dispatch the various requests to available thread execution resources. Execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D / media subsystem 1815 includes one or more internal caches to cache it instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and to store output data.

[0215] 3D / Media Processing

[0216] Figure 19 is a block diagram of a graphics processing engine 1910 of a graphics processor, according to some embodiments. In one embodiment, the GPE 1910 is a version of the GPE 1810 shown in FIG. 18. Figure 18 Figure 19 Elements in the figures have the same reference designators (or names) in some embodiments have the same or similar functionality as in any other figures herein, but are not limited to that identified in the text.

[0217] In some embodiments, the GPE 1910 is coupled with a command streamer 1903 that provides a command stream to the 3D pipeline 1912 and the media pipeline 1916 of the GPE. In some embodiments, the command streamer 1903 is coupled to memory, which can be system memory, or can be one or more of internal cache memory and shared cache memory. In some embodiments, the command streamer 1903 receives commands from the memory and sends the commands to the 3D pipeline 1912 and / or media pipeline 1916. The commands are instructions for the 3D pipeline 1912 and media pipeline 1916. In one embodiment, the commands form a workload made up of batches of

[0218] In some embodiments, a sample engine 1930 is coupled with memory (e.g., cache memory or system memory) and the execution unit array 1914. In some embodiments, the sample engine 1930 provides a memory access mechanism for the execution unit array 1914 that allows the execution array 1914 to read graphics and media data from memory. In some embodiments, the sample engine 1930 includes logic to perform specialized image sampling operations for media.

[0219] ​In some embodiments, specialized media sampling logic in the sampling engine 1930 includes a de-noise / de-interlace module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the de-noise / de-interlace module 1932 includes logic to perform one or more of de-noise or de-interlace algorithms on decoded video data. De-interleave logic combines alternating fields of interlaced video content into a single frame of video. De-noise logic reduces or removes data noise from video and image data. In some embodiments, the de-noise and de-interleave logic is motion adaptive and uses spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the de-noise / de-interlace module 1932 includes specialized motion detection logic (e.g., within the motion estimation engine 1934).

[0220] In some embodiments, the motion estimation engine 1934 provides hardware acceleration of video operations by performing video acceleration functions, such as motion vector estimation and prediction, on video data. The motion estimation engine determines motion vectors that describe the transformation of image data between successive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on macroblock-level video for which it would otherwise be too computationally intensive to perform using a general purpose processor. In some embodiments, the motion estimation engine 1934 is generally available to graphics processor components in order to assist video decode and processing functions that are sensitive or adaptive to the direction or magnitude of motion within video data.

[0221] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to improve the visual quality of produced images and video. In some embodiments, the scaling and filtering module 1936 processes image and video data during sampling operations before providing the data to the execution unit array 1914.

[0222] In some embodiments, GPE 1910 includes a data port 1944 that provides an additional mechanism by which the graphics subsystem accesses memory. In some embodiments, data port 1944 facilitates memory accesses for operations, including render target writes, constant buffer reads, temporal memory space reads / writes, and media surface accesses. In some embodiments, data port 1944 includes cache memory space to cache accesses to memory. The cache memory can be a single data cache, or separated into multiple caches for multiple subsystems accessing memory via the data port (e.g., a render buffer cache, a constant buffer cache, etc.). In some embodiments, threads executing on execution units in execution unit array 1914 communicate with the data port by exchanging messages through a data distribution interconnect coupled with each of the subsystems of GPE 1910.

[0223] Execution Unit

[0224] Figure 20 is a block diagram of another embodiment of a graphics processor 2000. Figure 20 Elements in the figures having the same or similar reference numbers (or names) as elements in another figure indicate like or similar elements.

[0225] In some embodiments, graphics processor 2000 includes a ring interconnect 2002, a front-end 2004, a media engine 2037, and graphics cores 2080A-2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of a plurality of processors integrated on a multi-core processing system.

[0226] In some embodiments, graphics processor 2000 receives batches of commands via ring interconnect 2002. The incoming commands are translated to one or more command streams in command streamer 2003 in pipeline front-end 2004. In some embodiments, graphics processor 2000 includes scalable execution logic to perform 3D geometry processing and media processing via the graphics core(s) 2080A-2080N. For 3D geometry processing commands, command streamer 2003 supplies commands to geometry pipeline 2036. For at least some media processing commands, command streamer 2003 supplies commands to video front end 2034, which couples with a media engine 2037. In some embodiments, media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing, and a multi-format encode / decode (MFX) 2033 engine to

[0227] In some embodiments, graphics processor 2000 includes scalable thread execution resources featuring modular cores 2080A-2080N (sometimes called core slices), each having multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes called core sub-slices). In some embodiments, graphics processor 2000 can have any number of graphics cores 2080A-2080N. In some embodiments, graphics processor 2000 includes graphics core 2080A having at least first sub-core 2050A and second sub-core 2060A. In other embodiments, graphics processor is a low power processor with a single sub-core (e.g., 2050A). In some embodiments, graphics processor 2000 includes multiple graphics cores 2080A-2080N each including a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. Each sub-core in the set of first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media / texture samplers 2054A-2054N. Each sub-core in the set of second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In some embodiments, each sub-core 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In some embodiments, these shared resources include shared cache memory and pixel operation logic. Other shared resources can also be included in the graphics processor.

[0228] Figure 21Thread execution logic 2100 is shown, including an array of processing elements employed in some embodiments of GPEs. Figure 21 Those elements of the figures having the same reference numerals (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0229] In some embodiments, thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array including a number of execution units 2108A-2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, these included components are interconnected via an interconnect structure, which links to each of these components. In some embodiments, thread execution logic 2100 includes one or more connections to memory, such as system memory or cache memory, through one of instruction cache 2106, data port 2114, sampler 2110, and execution unit array 2108A-2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, execution unit array 2108A-2108N includes any number of individual execution units.

[0230] In some embodiments, execution unit array 2108A-2108N is primarily used for executing “shader” programs. In some embodiments, execution units in array 2108A-2108N execute an instruction set that includes native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution unit supports vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general compute processing (e.g., compute and media shaders).

[0231] Each of execution units in execution unit array 2108A-2108N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical execution unit used for data element access, masking, and flow control within instructions. The number of channels can be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units 2108A-2108N support integer and floating-point data types.

[0232] The instruction set of the execution unit includes single instruction multiple data (SIMD) with each element being 8-bits, 16-bits, 32-bits, 64-bits, or 128-bits. In one embodiment, the execution unit supports a moving- vector with instructions to support SIMD with a size up to 64 bits (e.g., SIMD64) and a moving- vector with instructions to support SIMD with a size of 128 bits (e.g., SIMD128). However, the underlying architecture can support single instruction multiple data (SIMD) with a size of 8-bits, 16-bits, 32-bits, 64-bits or 128-bits, and the execution unit can be configured to support a different size SIMD with the same architecture by setting the size as an implementation parameter.

[0233] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for execution units. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during a sampling process before providing the sampled data to the execution units.

[0234] During execution, the graphics pipeline and media pipeline send thread initiation requests to the thread execution logic 2100 via thread generation and dispatch logic. In some embodiments, the thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics and media pipelines and instantiates requested threads on one or more execution units 2108A to 2108N. For example, a geometry pipeline (e.g., 2036) of a graphics processing cluster 2030 dispatches vertex processing, tessellation or geometry processing threads to the thread execution logic 2100 Figure 20 ). In some embodiments, the thread dispatcher 2104 can also handle run-time thread generation requests from execution of shader programs. Figure 21

[0235] ​Once a set of geometry objects has been processed and rasterized into pixel data, a pixel shader 2102 is invoked to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, the pixel shader 2102 computes values for vertex attributes that are interpolated across a rasterized object. In some embodiments, the pixel shader 2102 then executes an application programming interface (API) supplied pixel shader program. To execute the pixel shader program, the pixel shader 2102 dispatches threads to execution units (e.g., 2108A) via a thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses texture sampling logic in a sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and input geometry compute pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0236] In some embodiments, a data port 2114 provides a memory access mechanism for the thread execution logic 2100 to output processed data to memory for processing on a graphics processor output pipeline. In some embodiments, the data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data for memory access via the data port.

[0237] Figure 22 FIG. 22 is a block diagram illustrating a graphics processor instruction format according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set that includes a variety of different instructions. The solid lined boxes illustrate the components that are generally included in an execution unit or instruction pipeline, while the dashed lines include components that are optional or that are

[0238] In some embodiments, a graphics processor execution unit natively supports instructions in a 128-bit format 2210. A 64-bit compact instruction format 2230 can be used for some instructions based on a selected instruction, instruction option, and number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted to the 64-bit format 2230. Native instructions available in the 64-bit format 2230 vary based on the implementation. In some embodiments, a set of index values in the instruction is used to partially compact instructions. The execution unit hardware references a set of compression tables based on the index values and uses the compression table output in reconstructing the native instruction in the 128-bit format 2210.

[0239] For each format, the instruction opcode 2212 defines the operation that the execution unit is to perform. The execution unit executes each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. In some embodiments, the instruction control field 2214 enables control over certain execution options, such as swizzle and data channel order (e.g., interleave). For 128-bit instructions 2210 an exec-size field 2216 limits the number of data channels that will be executed in parallel. In some embodiments, the exec-size field 2216 is not available for use in the 64-bit compact instruction format 2230.

[0240] Some execution units instructions have up to three operands, including two source operands src02220, src1 2222 and one destination 2218. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of an instruction can be an immediate (e.g., hard-coded) value passed with the instruction.

[0241] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode information 2226 that specifies, for example, whether a direct register addressing mode or an indirect register addressing mode is used. When using direct register addressing mode, the register address for one or more operands is provided directly by bits in the instruction 2210.

[0242] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode defines the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1 -byte aligned access mode, where the byte alignment of the access mode determines the access alignment for the instruction operands. For example, the instruction 2210 can use byte-aligned addressing for source and destination operands when in a first mode, and 16-byte aligned addressing for all source and destination operands when in a second mode.

[0243] In one embodiment, the address mode portion of access / address mode field 2226 determines whether the instruction will use direct addressing or indirect addressing. When using direct register addressing mode, the bits in instruction 2210 directly provide the register address of the operand(s). When using indirect register addressing mode, the register address of the operand(s) can be calculated based on an address register value and an address immediate field in the instruction.

[0244] In some embodiments, instructions are grouped based on the opcode 2212 bit fields to simplify opcode decoding 2240. For 8-bit opcodes, bits 4, 5, and 6 allow the execution units to determine the type of opcode. The exact opcode grouping shown is exemplary only. In some embodiments, move and logic opcode group 2242 includes data move and logical instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group 2242 shares five most-significant bits (MSBs), with move (mov) instructions taking the form 0000xxxxb and logical instructions taking the form 0001xxxxb. Flow control instruction group 2244 (e.g., call, jmp) includes instructions that take the form 0010xxxxb (e.g., Ox20). Hybrid instruction group 2246 includes a mix of instructions including synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., Ox30). Parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, mul) that take the form 0100xxxxb (e.g., Ox40). Parallel math group 2248 performs arithmetic operations across data lanes in parallel. Vector math group 2250 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., Ox50). Vector math group performs arithmetic such as dot product calculations on vector operands.

[0245] Graphics Pipeline

[0246] Figure 23 is a block diagram of another embodiment of a graphics processor 2300. Figure 23 Elements in the figures having the same or similar reference numbers (or names) as elements in another figure indicate similar or equivalent elements. However, individual elements can not be discussed in each figure if these elements have been discussed before or are clear from the context.

[0247] In some embodiments, graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a render output pipeline 2370. In some embodiments, graphics processor 2300 is a graphics processor included in a multi-core processor that includes one or more general-purpose processing cores. Graphics processor 2300 is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 2300 via a ring interconnect 2302. In some embodiments, ring interconnect 2302 couples graphics processor 2300 to other processing components such as other graphics processors or general-purpose processors. Commands from ring interconnect 2302 are translated to micro-operations by a command streamer 2303, which supplies micro-operations to individual components of graphics pipeline 2320 or media pipeline 2330.

[0248] In some embodiments, command streamer 2303 directs the operation of a vertex fetcher 2305 that reads vertex data from memory and executes vertex processing commands provided by command streamer 2303. In some embodiments, vertex fetcher 2305 provides vertex data to a vertex shader 2307 that performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 2305 and vertex shader 2307 execute vertex processing instructions by dispatching execution threads to thread execution units 2352A, 2352B via thread dispatcher 2331.

[0249] In some embodiments, thread execution units 2352A, 2352B are arrays of vector processors having a set of instruction templates for performing graphics and media operations. In some embodiments, thread execution units 2352A, 2352B have an additional Ll cache 2351 that is specific to each array or shared among arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned into separate regions for data and instructions.

[0250] In some embodiments, graphics pipeline 2320 includes tessellation components for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures tessellation operations. A programmable domain shader 2317 provides post-processing evaluation of tessellation output. A tessellator 2313 operates in the direction of hull shader 2311 and includes specialized logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to graphics pipeline 2320. In some embodiments, tessellation components 2311, 2313, 2317 can be bypassed if tessellation is not used.

[0251] In some embodiments, a complete geometric object can be processed by the geometry shader 2319 via one or more threads dispatched to execution units 2352A, 2352B, or can proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on an entire geometric object (rather than a vertex or patch of vertices as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0252] Prior to rasterization, the clipper 2329 processes the vertex data. The clipper 2329 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer 2373 (e.g., a depth test component) in the render output pipeline 2370 dispatches pixel shaders to convert geometric objects to their per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, an application can bypass the rasterizer 2373 and access un-rasterized vertex data via the egress unit 2323.

[0253] The graphics processor 2300 has an interconnect bus, interconnect fabric or some other interconnect mechanism to allow data and messages to be passed between components of the processor. In some embodiments, execution units 2352A, 2352B and associated caches 2351, texture and media sampler 2354, and the texture / sampler caches 2358 are interconnected via a data port 2356 to perform memory accesses and communicate with other components of the processor. In some embodiments, sampler 2354, caches 2351, 2358, and execution units 2352A, 2352B each have separate memory access ports to the data port 2356.

[0254] In some embodiments, the render output pipeline 2370 includes a rasterizer 2373 that converts a vertex-based representation of objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed function triangle and line rasterization. An associated render cache 2378 and depth cache 2379 are also available in some embodiments. Pixel operation components 2377 perform pixel-based operations, although in some examples pixel operations associated with 2D operations (e.g., bit block image transfers and blends) are performed by 2D engine 2341, or replaced by display controller 2343 using an overlay display plane at display time. In some embodiments, a shared L3 cache 2375 is available for all graphics components, allowing sharing of data without use of main system memory.

[0255] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front-end 2334. In some embodiments, the video front-end 2334 receives pipeline commands from the command streamer 2303. In some embodiments, the media pipeline 2330 includes a separate command streamer. In some embodiments, the video front-end 2334 processes media commands before sending the commands to the media engine 2337. In some embodiments, the media engine 2337 includes thread spawning functionality to process media

[0256] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and coupled to the graphics processor via the ring interconnect 2302, or some other interconnect bus or fabric. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 contains special purpose logic that is, in some embodiments, capable of operating independently of the 3D pipeline. In some embodiments, display controller 2343 is coupled to the

[0257] In some embodiments, graphics pipeline 2320 and media pipeline 2330 can be configured to perform operations based on a number of graphics and media programming interfaces and not specific to any one application programming interface (API). In some embodiments, driver software for a graphics processor translates a particular API's calls made to the graphics processor into commands that the graphics processor performs. In some embodiments, support is available for the Open Graphics Library (OpenGL) and the Open Computing Language (OpenCL) from the Khronos Group, which can make use of the graphics processor's processing units to perform graphics and compute processing. The Direct3D library from the Microsoft Corporation can also be supported in some embodiments. Future APIs from other parties also can be supported as long as mappings exist from the API's calls to the pipeline commands of the graphics processor.

[0258] Graphics Pipeline Programming

[0259] Figure 24A FIG. 24 is a block diagram illustrating a graphics processor command format 2400 according to some embodiments. Figure 24B FIG. 25 is a block diagram illustrating a graphics processor command sequence 2410 according to some embodiments. Figure 24A The solid lined boxes in FIG. 25 illustrate the components of a graphics processor according to an embodiment of the present disclosure. The graphics processor is a parallel processor that processes data to be rendered on the screen. The graphics processor contains one or more shader processors coupled with memory and cache units to process the vertex and element shader programs. The graphics processor also includes one or more graphics processing units (GPUs) for processing graphics primitives. The graphics processor also includes fixed function and programmable logic for manipulating textures and performing other graphical operations. The graphics processor also includes one or more memory controllers that Figure 24A The exemplary graphics processor command format 2400 includes a data field to identify a target client unit for the command 2402, a command operation code (opcode) 2404 and related data for the command 2406. A sub-opcode 2405 and a command size 2408 are also included in some commands.

[0260] In some embodiments, the client 2402 specifies a client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to direct further processing of the command and to route the command data to the appropriate client unit. In some embodiments, graphics processor client units include memory interface units, render units, 2D units, 3D units, and media units. Each client unit has a corresponding processing pipeline that processes the commands. Once a command has been received by a client unit, the client unit reads the opcode 2404 and, if present, the sub-opcode 2405 to determine the operation to perform. The client unit uses information in the data field 2406 to perform the command. For some commands an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser determines the size of at least some of the commands based on the command opcode. In some embodiments, commands are aligned via multiples of a doubleword.

[0261] Figure 24B The flowchart in FIG. 23 illustrates an exemplary graphics processor command sequence 2300. In some embodiments, software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example, as embodiments are not limited to these specific commands or to this command sequence. Moreover, the described commands can be issued in alternative orders, or in parallel, or be omitted, depending on the implementation. The described sample commands sequence is also not indicative of a graphics processor's command sequence's full functionality, but is merely an example.

[0262] In some embodiments, the graphics processor command sequence 2300 can begin with a pipeline flush command 2302 to cause any active graphics pipelines to complete any currently pending commands in those pipelines. For pipeline synchronization, the graphics processor is caused to pause command processing, until all active graphics pipelines complete their current set of commands. In some embodiments, a pipeline flush is implemented by stalling the graphics processor's command parser after a send flush command has been received. In some embodiments, the pipeline flush is implemented by using a send flush command to trigger a context switch in the graphics processor. In some embodiments, the send flush command is used to complete processing of one context before starting processing of another context. In some embodiments, the send flush command is used to complete processing of a set of commands before starting processing of another set of commands.

[0263] In some embodiments, a pipeline select command 2304 is used when the command sequence requires the graphics processor to switch between pipelines. In some embodiments, the pipeline select command 2304 is only needed once for each context switch, unless the context switch is due to a cache miss and a pipeline flush command 2302 was not issued for the missing data. In some embodiments, the pipeline select command 2304 is used to select the pipeline for processing the following commands.

[0264] In some embodiments, pipeline control commands 2306 configure a graphics pipeline for operation. In some embodiments, pipeline control commands 2306 configure the pipeline state for the active pipeline. In some embodiments, pipeline control commands 2306 are used to set pipeline state for the pipeline being used for processing. In some embodiments, pipeline control commands 2306 are used to set pipeline state for one or more other pipelines.

[0265] In some embodiments, return buffer state commands 2416 are used to configure a set of return buffers for a respective pipeline to write data into. Some pipeline operations require allocation, selection, or configuration of one or more return buffers into which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 2416 includes selecting the size and number of return buffers for a set of pipeline operations.

[0266] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on a pipeline determination 2420, the command sequence is tailored for a 3D pipeline 2422 that begins with 3D pipeline state 2430 and a media pipeline 2424 that begins at media pipeline state 2440.

[0267] The commands for 3D pipeline state 2430 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured prior to processing 3D primitive commands. The values for these commands are determined based at least in part on the particular 3D API in use. In some embodiments, the 3D pipeline state 2430 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0268] In some embodiments, 3D primitives 2432 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via 3D primitives 2432 are forwarded to a vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitives 2432 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitives 2432 commands are used to perform vertex operations on 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches shader execution threads to the graphics processor execution units.

[0269] In some embodiments, the 3D pipeline 2422 is triggered via execution of a 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in the command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operations are complete, the resulting geometry is rasterized and the pixel engine shades the resulting pixels. Additional commands to control pixel shading and pixel back end operations can also be included for those operations.

[0270] In some embodiments, the graphics processor command sequence 2410 follows the media pipeline 2424 path when performing media operations. Generally, the specific use and programming of the media pipeline 2424 depends on the media or compute operations to be performed. Video decode operations can be offloaded to the media pipeline during media decode. In some embodiments, the media pipeline can be bypassed and media decode can be performed entirely or partially in software using the resources provided by one or more of the general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to execute SIMD vector operations using computational shader programs that are not specifically related to the rendering of graphics primitives.

[0271] In some embodiments, the media pipeline 2424 is configured in a similar manner as the 3D pipeline 2422. A set of media pipeline state commands 2440 are dispatched or placed into the command queue prior to the media object commands 2442. In some embodiments, the media pipeline state commands 2440 include data to configure the media pipeline elements used to process the media object. This includes data to configure video decode and video encode logic within the media pipeline (such as encode or decode modes). In some embodiments, the media pipeline state commands 2440 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0272] In some embodiments, media object command 2442 supplies pointers to media objects to be processed by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 2442. Once the pipeline states are configured and media object command 2442 is queued, media pipeline 2424 is triggered via execution command 2444 or an equivalent execution event (e.g., register write). The output from media pipeline 2424 can then be post-processed by operations provided by 3D pipeline 2422 or media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0273] Graphics Software Architecture

[0274] Figure 25 An exemplary graphics software architecture of a data processing system 2500 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, the processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. The graphics application 2510 and the operating system 2520 each execute in the system memory 2550 of the data processing system.

[0275] In some embodiments, the 3D graphics application 2510 includes one or more shader programs, which include shader instructions 2512. The shader language instructions may be in the form of a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 2514 in machine language suitable for execution by a general-purpose processor core 2534. The application also includes geometric objects 2516 defined by vertex data.

[0276] In some embodiments, the operating system 2520 is from Microsoft Corporation. The operating system 2520 is a proprietary Unix-like operating system using a variant of the Linux kernel or an open-source Unix-like operating system. When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 rendered in HLSL into a low-level shader language. This compilation can be just-in-time (JIT) compilation, or pre-compilation of the application-executable shaders. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 2510.

[0277] In some embodiments, the user-mode graphics driver 2526 includes a back-end shader compiler 2527 that is used to translate shader instructions 2512 into hardware-specific instructions. When OpenGL API is in use, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functions 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates to a graphics processor 2532 in order to dispatch commands and instructions.

[0278] IP core implementation

[0279] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium which represents and / or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium can include instructions which represent various logic within the processor. When read by a machine, the instructions can cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as "IP cores," are reusable units of logic for the implementation of an integrated circuit. The IP cores can be stored on a tangible, machine-readable medium including: a hard disk; CD-ROM; optical storage; flash storage; nonvolatile memory; or similar storage. The IP cores can be supplied to the manufacturing facility used to fabricate the integrated circuit either from the design facility, the customer, or from a third-party distributor. The IP cores are configured to fabricate discrete circuits in the integrated circuit, and the integrated circuit is configured to perform the operations described for any of the embodiments herein when the integrated circuit is in operation.

[0280] Figure 26 is a block diagram showing an IP core development system 2600 according to an embodiment, which can be used to fabricate integrated circuits to perform operations. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facility 2630 can employ a high-level programming language (e.g., C / C++) to generate a software simulation 2610 of the IP core design. The software simulation 2610 can be used to design, test, and verify the behavior of the IP core. A register transfer level (RTL) design can then be created or synthesized from the simulation model 2600. The RTL design 2615 is an abstraction of the behavior of the integrated circuit (including the associated logic that executes in the modeled digital signals) that models the flow of digital signals between hardware registers, including the associated logic executed to implement the modeled digital signals. In addition to an RTL design 2615, a logic level or transistor level design can also be created, designed, or synthesized. As such, specific details of the embodiments can vary from one embodiment to another implementation depending on the specific requirements of the design and the problems to be solved.

[0281] The RTL design 2615 or equivalent can be further synthesized, by the design facility, into a hardware model 2620, which can be in a hardware description language (HDL) or some other representation of a physical design. The HDL can be further simulated or tested to validate the IP core design. The IP core design can be stored for delivery to a 3rdparty fabrication facility 2665 using non-volatile memory 2640 (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design can be transmitted (e.g., via the Internet) by way of a wired connection 2650 or wireless connection 2660. The fabrication facility 2665 can then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0282] Figure 27 is a block diagram showing an exemplary system on a chip integrated circuit 2700, which can be manufactured using one or more IP cores. The exemplary integrated circuit includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and can additionally include an image processor 2715 and / or a video processor 2720, any of which can be a modular IP core from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic including USB controllers 2725, UART controllers 2730, SPI / SDIO controllers 2735, I2S / I2C controllers 2740. In addition, the integrated circuit can include a display controller 2755 that is coupled with one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage can be provided by a flash memory subsystem 2760, including a flash memory and a flash memory controller. Memory interfaces can be provided via a memory controller 2765 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770. 2 S / I 2 Ccontrollers 2740. In addition, the integrated circuit can include a display controller 2755 that is coupled with one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage can be provided by a flash memory subsystem 2760, including a flash memory and a flash memory controller. Memory interfaces can be provided via a memory controller 2765 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0283] In addition, other logic and circuits can be included in the processors of the integrated circuit 2700, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0284] The embodiments have been described with respect to specific embodiments. However, a person of ordinary skill in the art will understand that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the preceding claims. The foregoing description and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

[0285] Additional notes and examples

[0286] Example 1 can include a position-only shading pipeline utilizing a coarse Z buffer system, the system comprising: a power supply to supply power to the system; a graphics pipeline device; and a rendering pipeline to render the surface triangles remaining after the culling, the graphics pipeline device comprising a position-only shading pipeline to: locate geometry data, the geometry data comprising surface triangles for a digital representation of a scene; perform a screen space transform; and cull at least one of the surface triangles.

[0287] Example 2 can include the system of example 1, wherein the position-only shading pipeline identifies the at least one of the surface triangles culled as excluded triangles, and identifies surface triangles remaining after the culling as non-excluded triangles, wherein the surface triangles identified as excluded triangles comprise at least a portion of surface triangles in one or more excluded regions, and wherein the surface triangles identified as non-excluded triangles comprise surface triangles in one or more non-excluded regions.

[0288] Example 3 can include the system of example 2, wherein the size of the excluded regions and the non-excluded regions are set based on culling parameters, and wherein the culling parameters comprise one or more of: lens parameters for depth perception for near and far planes; performance parameters; head-mounted display parameters; or other device parameters.

[0289] Example 4 can include the system of example 3, wherein the graphics pipeline device exposes the surface triangles to a vertex shader, wherein the rendering pipeline generates egress data, wherein the egress data comprises vertices for tessellation of a patch, wherein the graphics pipeline device adjusts a granularity setting of the egress data, the excluded regions, the non-excluded regions, clipper parameters, or setting parameters based on a position of one or more of the surface triangles, the lens parameters, or attributes of the egress data, wherein the attributes of the egress data comprise one or more of a granularity of the egress data, a motion or direction of one or more objects, or a gaze of a user; and exposes the egress data to the vertex shader in the position-only shading pipeline based on the adjustment of the granularity setting of the egress data, the excluded regions, the non-excluded regions, the clipper parameters, or the setting parameters, and wherein the position-only shading pipeline culls the egress data.

[0290] Example 5 can include the system of example 1, wherein the position-only shading pipeline creates a coarse Z buffer associated with the position-only shading pipeline, wherein the coarse Z buffer is created while processing the geometry data, and wherein the position-only shading pipeline stores one or more of the surface triangles as coarse Z buffer triangles in a coarse Z order, wherein the coarse Z order is an order from a Z 最大 value to a Z 最小 value, wherein the Z 最小 value and the Z 最大 value identify a near plane and a far plane in the scene.

[0291] Example 6 can include the system of example 5, wherein the position-only shading pipeline performs coarse rasterization based on a coarse Z value, wherein the coarse Z value indicates a level of granularity of detail in the scene, wherein a surface triangle stored as the Z buffer triangle includes a non-excluded triangle identified as occluded by at least another non-excluded triangle of the non-excluded triangles identified as opaque, wherein the position-only shading pipeline adjusts a size of the coarse Z buffer based on the coarse Z value, wherein the size of the coarse Z buffer is proportional to the coarse Z value, wherein the position-only shading pipeline feeds forward the coarse Z buffer to the rendering pipeline, wherein the rendering pipeline renders the Z buffer triangle.

[0292] Example 7 can include the system of any of examples 1-6, wherein the geometry data includes primitives, wherein the position-only shading pipeline: processes and classifies the primitives; records distribution and density properties of the primitives; determines a number and size of resolution tiles used to process the primitives; determines at least two graphics processing units (GPUs) to communicate with the position-only shading pipeline; generates a geometry stream for the at least two GPUs; and wherein the at least two GPUs render the primitives based on one or more of the resolution tiles or the distribution and density properties.

[0293] Example 8 can include a position-only shading pipeline with a coarse Z buffer device, the device comprising: a position-only shading pipeline to: locate geometry data, the geometry data including surface triangles for a digital representation of a scene; perform a screen space transform; and cull at least one of the surface triangles; and a rendering pipeline to render the surface triangles remaining after the culling.

[0294] Example 9 can include the device of example 8, wherein the position-only shading pipeline is to identify the at least one of the surface triangles that is culled as an excluded triangle, and to identify surface triangles that remain after the culling as non-excluded triangles, wherein the surface triangles identified as excluded triangles include at least a portion of the surface triangles that are in one or more excluded regions, and wherein the surface triangles identified as non-excluded triangles include the surface triangles that are in one or more non-excluded regions, wherein sizes of the excluded regions and the non-excluded regions are set based on culling parameters, and wherein the culling parameters include one or more of: lens parameters for depth perception for near and far planes; performance parameters; head-mounted display parameters; or other device parameters.

[0295] Example 10 can include the device of example 9, further comprising a vertex shader, wherein the graphics pipeline device is to expose the surface triangles to the vertex shader, wherein the rendering pipeline is to generate egress data, wherein the egress data includes vertices for tessellation of a patch, wherein the device is to: adjust a granularity setting of the egress data, the excluded regions, the non-excluded regions, clipper parameters, or setting parameters based on a position of one or more of the surface triangles, the lens parameters, or properties of the egress data, wherein the properties of the egress data include one or more of a granularity of the egress data, a motion or direction of one or more objects, or a gaze of a user; and expose the egress data to a vertex shader in the position-only shading pipeline based on the adjustment to the granularity setting of the egress data, the excluded regions, the non-excluded regions, the clipper parameters, or the setting parameters, and wherein the position-only shading pipeline is to cull the egress data.

[0296] Example 11 can include the device of example 8, wherein the position-only shading pipeline is to create a coarse Z buffer associated with the position-only shading pipeline, wherein the coarse Z buffer is created while processing the geometry data, and wherein the position-only shading pipeline is to store one or more of the surface triangles as coarse Z buffer triangles in a coarse Z order, wherein the coarse Z order is a depth ordered sequence from a Z 最大 value to a Z 最小 value, wherein the Z 最小 value and the Z 最大 value identify near and far planes in the scene.

[0297] Example 12 can include the device of example 11, wherein the position-only shading pipeline is to perform coarse rasterization based on a coarse Z value, wherein the coarse Z value is indicative of a level of granularity of detail in the scene, wherein a surface triangle stored as the Z buffer triangle includes a non-excluded triangle identified as occluded by at least another non-excluded triangle in the non-excluded triangles identified as opaque, wherein the position-only shading pipeline is to set a size of the coarse Z buffer based on the coarse Z value, wherein the size of the coarse Z buffer is proportional to the coarse Z value, wherein the position-only shading pipeline is to feed forward the coarse Z buffer to the rendering pipeline, wherein the rendering pipeline is to render the Z buffer triangle.

[0298] Example 13 can include the device of any of examples 8 to 12, wherein the geometry data includes primitives, wherein the position-only shading pipeline is to: process and sort the primitives; record distribution and density properties of the primitives; determine a number and size of resolution fragments used to process the primitives; determine at least two graphics processing units (GPUs) to communicate with the position-only shading pipeline; generate a geometry stream for the at least two GPUs; and wherein the at least two GPUs are to render the primitives based on one or more of the resolution fragments or the distribution and density properties.

[0299] Example 14 can include at least one non-transitory computer-readable storage medium comprising a set of instructions, which when executed by a computing device, cause the computing device to: locate, by a position-only shading pipeline, geometry data, the geometry data including surface triangles for a digital representation of a scene; perform, by the position-only shading pipeline, a screen space transform; cull, by the position-only shading pipeline, at least one of the surface triangles; and render, by a rendering pipeline, the surface triangles remaining after the culling.

[0300] Example 15 can include the at least one non-transitory computer-readable storage medium of example 14, wherein the instructions, when executed, cause the computing device to: identify, by the position-only shading pipeline, the at least one of the surface triangles that is culled as an excluded triangle, and identify surface triangles that remain after the culling as non-excluded triangles, wherein the surface triangles identified as excluded triangles include at least a portion of surface triangles that are in one or more excluded regions, and wherein the surface triangles identified as non-excluded triangles include surface triangles that are in one or more non-excluded regions, wherein sizes of the excluded regions and the non-excluded regions are set based on culling parameters, and wherein the culling parameters include one or more of: lens parameters for depth perception of near and far planes; performance parameters; head-mounted display parameters; or other device parameters.

[0301] Example 16 can include the at least one non-transitory computer-readable storage medium of example 15, wherein the instructions, when executed, cause the computing device to: expose the surface triangles to a vertex shader; generate, by the rendering pipeline, egress data, wherein the egress data includes vertices for tessellation of a patch; adjust a granularity setting of the egress data, the excluded regions, the non-excluded regions, clipper parameters, or setting parameters based on a position of one or more of the surface triangles, the lens parameters, or properties of the egress data, wherein the properties of the egress data include one or more of a granularity of the egress data, a motion or direction of one or more objects, or a gaze of a user; and expose the egress data to the vertex shader in the position-only shading pipeline based on the adjustment to the granularity setting of the egress data, the excluded regions, the non-excluded regions, the clipper parameters, or the setting parameters; and cull, by the position-only shading pipeline, the egress data.

[0302] Example 17 can include the at least one non-transitory computer-readable storage medium of example 14, wherein the instructions, when executed, cause the computing device to: create, by the position-only shading pipeline, a coarse Z buffer associated with the position-only shading pipeline, wherein the coarse Z buffer is created while processing the geometry data; and store, by the position-only shading pipeline, one or more of the surface triangles as coarse Z buffer triangles in a coarse Z order, wherein the coarse Z order is a depth-ordered order from Z 最大 values to Z 最小 values, wherein the Z 最小 values and the Z 最大 values identify near and far planes in the scene.

[0303] Example 18 can include the at least one non-transitory computer-readable storage medium of example 17, wherein the instructions, when executed, cause a computing device to: perform coarse rasterization by the position-only shading pipeline based on a coarse Z value, wherein the coarse Z value indicates a level of granularity of detail in the scene, wherein surface triangles stored as the Z buffer triangles include non-excluded triangles identified as occluded by at least another non-excluded triangle in the non-excluded triangles identified as opaque; adjust a size of the coarse Z buffer by the position-only shading pipeline based on the coarse Z value, wherein the size of the coarse Z buffer is proportional to the coarse Z value, wherein the position-only shading pipeline feeds forward the coarse Z buffer to the rendering pipeline; and render the Z buffer triangles by the rendering pipeline.

[0304] Example 19 can include the at least one non-transitory computer-readable storage medium of any of examples 14 to 18, wherein the instructions, when executed, cause a computing device to: process and classify the primitives; record distribution and density properties of the primitives; determine a number and size of resolution fragments used to process the primitives; determine at least two graphics processing units (GPUs) to communicate with the position-only shading pipeline; generate a geometry stream for the at least two GPUs; and wherein the at least two GPUs render the primitives based on one or more of the resolution fragments or the distribution and density properties.

[0305] Example 20 can include a method of managing a position-only shading pipeline with a coarse Z buffer, further comprising: processing, by a position-only shading pipeline, geometry data, the geometry data including surface triangles for a digital representation of a scene; and rendering, by a rendering pipeline, surface triangles remaining after the culling, the processing step including the steps of: locating geometry data, the geometry data including surface triangles for the scene; performing a screen space transform; and culling at least one of the surface triangles.

[0306] Example 21 can include the method of example 20, further comprising: identifying the at least one of the surface triangles culled as an excluded triangle, and identifying surface triangles remaining after the culling as non-excluded triangles, wherein surface triangles identified as excluded triangles include at least a portion of the surface triangles in one or more exclusion regions, and wherein surface triangles identified as non-excluded triangles include surface triangles in one or more non-exclusion regions.

[0307] Example 22 can include the method of example 21, wherein a size of the exclusion region and the non-exclusion region is set based on a culling parameter, and wherein the culling parameter includes one or more of: lens parameters for depth perception for near and far planes; performance parameters; head-mounted display parameters; or other device parameters.

[0308] Example 23 can include the method of example 22, further comprising: exposing the surface triangles to a vertex shader; generating stream-out data by the rendering pipeline, the stream-out data including vertices for tessellation of a patch; adjusting a granularity setting of the stream-out data, the exclusion region, the non-exclusion region, a clipper parameter, or a setting parameter based on a position of one or more of the surface triangles, the lens parameters, or a property of the stream-out data, wherein the property of the stream-out data includes one or more of a granularity of the stream-out data, a motion or a direction of one or more objects, or a gaze of a user; and exposing the stream-out data to the vertex shader in the position-only shading pipeline based on the adjustment to the granularity setting of the stream-out data, the exclusion region, the non-exclusion region, the clipper parameter, or the setting parameter, and culling the stream-out data by the position-only shading pipeline.

[0309] Example 24 can include the method of example 20, wherein the processing by the position-only shading pipeline further comprises: creating a coarse Z buffer associated with the position-only shading pipeline, wherein the coarse Z buffer is created while processing the geometry data; storing one or more of the surface triangles as Z buffer triangles in a coarse Z order, wherein the coarse Z order is a depth ordered sequence from a Z 最大 value to a Z 最小 value, wherein the Z 最小 value and the Z 最大 value identify a near plane and a far plane in the scene; performing coarse rasterization based on a coarse Z value, wherein the coarse Z value indicates a level of granularity of detail in the scene, wherein the surface triangles stored as the Z buffer triangles include the non-exclusion triangles identified as occluded by at least one of the other ones of the non-exclusion triangles identified as opaque; setting a size of the coarse Z buffer based on the coarse Z value, wherein the size of the coarse Z buffer is proportional to the coarse Z value; and feeding forward the coarse Z buffer to the rendering pipeline, the method further comprising rendering the coarse Z buffer triangles by the rendering pipeline.

[0310] Example 25 can include the method of any of examples 20-24, wherein the geometry data comprises primitives, the method further comprising: processing and classifying the primitives by the position-only shading pipeline; recording distribution and density properties of the primitives; determining a number and size of resolution tiles used to process the primitives; determining that at least two graphics processing units (GPUs) are in communication with the position-only shading pipeline; generating a geometry stream for the at least two GPUs; and rendering the primitives by the at least two GPUs based on one or more of the resolution tiles or the distribution and density properties.

[0311] Example 26 can include a position-only shading pipeline with a coarse Z buffer system, the system comprising means for performing any of examples 20-24, wherein the geometry data comprises primitives, the system further comprising means for: processing and classifying the primitives; recording distribution and density properties of the primitives; determining a number and size of resolution tiles used to process the primitives; determining that at least two graphics processing units (GPUs) are in communication with the position-only shading pipeline; generating a geometry stream for the at least two GPUs; and rendering the primitives by the at least two GPUs based on one or more of the resolution tiles or the distribution and density properties.

[0312] Embodiments are applicable for use with all manner of semiconductor integrated circuit ("IC") chips. Examples of these chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on a chip (SoCs), SSD / NAND controller ASICs, and the like. In some of the drawings, signal conductor lines are represented with lines. Some can be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and / or have arrows at one or more ends, to indicate a primary information flow direction. This, however, should not be taken to mean that the that only these numbered and arrowed lines are involved in the information flow between nodes represented by the drawing. Weaving and other signal interactions involving unnumbered, unarrowed, and / or other lines can be present in some embodiments.

[0313] Example sizes / models / values / ranges may have been given, although the embodiments are not limited thereto. As manufacturing technologies (e.g., photolithography) mature over time, it is expected that smaller devices can be manufactured. Furthermore, to simplify the illustrations and discussion and to avoid obscuring certain aspects of the embodiments, well-known power / ground connections to the IC chip and other components may or may not be shown in the figures. Additionally, arrangements may be shown in block diagram form to avoid obscuring the embodiments, also given that details regarding the implementation of such block diagram arrangements are highly dependent on the computational system in which the embodiments are implemented; i.e., such details should be entirely within the view of those skilled in the art. In the context of setting forth specific details (e.g., circuitry) to describe exemplary embodiments, it should be apparent to those skilled in the art that embodiments can be practiced with or without variations in these specific details. The description is therefore to be considered illustrative rather than restrictive.

[0314] The term "coupling" may be used herein to refer to any type of direct or indirect relationship between the components under discussion, and may be applied to electronic, mechanical, fluid, optical, electromagnetic, electrical, or other connections. Furthermore, the terms "first," "second," etc., may be used herein merely to facilitate discussion and do not carry any specific, temporary, or temporal significance, unless otherwise specified. Moreover, the indefinite article "a" or "an" should be understood to mean "one or more" or "at least one."

[0315] As used in this application and claims, a list of items described by the term "one or more" may refer to any combination of the listed items. For example, the phrase "one or more of A, B, and C" may mean A, B, and C; A and B; A and C; B and C; or A, B, and C.

[0316] Various embodiments have been described above with reference to specific examples. However, those skilled in the art will understand that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the foregoing description and drawings are considered illustrative rather than restrictive.

Claims

1. A system comprising: Power supply, used to supply power to the system; Graphics pipeline equipment, the graphics pipeline equipment comprising: Position-only coloring pipeline, used for: Positioning geometric data, the geometric data including surface triangles for a digital representation of the scene; Perform screen space transformations; and Remove at least one of the surface triangles; and A rendering pipeline is used to render the surface triangles remaining after the culling. The sizes of the excluded and non-excluded regions are set based on rejection parameters, which include lens parameters for depth sensing in the near and far planes. The graphics pipeline device exposes the surface triangles to the vertex shader, the rendering pipeline generates outgoing data, and the outgoing data includes vertices for surface tessellation for piecewise subdivision. The graphics pipeline device: The granularity setting of the outflow data, the exclusion region, the non-exclusion region, the clipper parameter, or the setting parameter are adjusted based on the position of one or more of the surface triangles, the lens parameter, or the attribute of the outflow data, wherein the attribute of the outflow data includes one or more of the following: the granularity of the outflow data, the movement or orientation of one or more objects, or the user's gaze.

2. The system as claimed in claim 1, wherein, The position-only coloring pipeline identifies at least one of the surface triangles that has been rejected as excluded triangles and identifies the remaining surface triangles after the rejection as non-excluded triangles, wherein the surface triangles identified as excluded triangles include at least a portion of the surface triangles located in one or more excluded regions, and wherein the surface triangles identified as non-excluded triangles include the surface triangles located in one or more non-excluded regions.

3. The system as described in claim 2, wherein, The rejection parameters further include one or more of the following: performance parameters; head-mounted display parameters; or other device parameters.

4. The system as described in claim 3, wherein, The graphics pipeline equipment further includes: Based on the granularity setting of the outflow data, the exclusion region, the non-exclusion region, the clipper parameters, or the adjustment of the setting parameters: The outflowing data is exposed to the vertex shader in the position-only shading pipeline, wherein the position-only shading pipeline discards the outflowing data.

5. The system as described in claim 2, wherein, The position-only shading pipeline creates a coarse Z-buffer associated with the pipeline, wherein the coarse Z-buffer is created when processing the geometry data, and wherein the position-only shading pipeline stores one or more of the surface triangles as coarse Z-buffer triangles in a coarse Z-order, wherein the coarse Z-order is from Z 最大 Value to Z 最小 The values ​​are sorted by depth, where Z 最小 Value and the Z 最大 The value identifies the near plane and far plane in the scene.

6. The system of claim 5, wherein, The position-only shading pipeline performs coarse rasterization based on a coarse Z-value, wherein the coarse Z-value indicates the granularity level of detail in the scene, wherein the surface triangles stored as Z-buffer triangles include non-excluded triangles identified as being occluded by at least one other non-excluded triangle identified as opaque, wherein the position-only shading pipeline adjusts the size of the coarse Z-buffer based on the coarse Z-value, wherein the size of the coarse Z-buffer is proportional to the coarse Z-value, wherein the position-only shading pipeline feeds the coarse Z-buffer forward to the rendering pipeline, wherein the rendering pipeline renders the Z-buffer triangles.

7. The system as claimed in any one of claims 1 to 6, wherein, The geometric data includes primitives, wherein the location-only coloring pipeline: The graphic elements are processed and classified; Record the distribution and density attributes of the primitives; Determine the number and size of the resolution segments used to process the primitives; At least two graphics processing units (GPUs) are identified to communicate with the location-only shading pipeline; Generate geometry flows for the at least two GPUs; and The at least two GPUs render the primitives based on the resolution fragment or one or more of the distribution and density attributes.

8. An apparatus comprising: Position-only coloring pipeline, used for: Positioning geometric data, the geometric data including surface triangles for a digital representation of the scene; Perform screen space transformation; as well as At least one of the surface triangles must be removed; as well as The rendering pipeline is used to render the surface triangles remaining after the culling. The sizes of the excluded and non-excluded regions are set based on rejection parameters, which include lens parameters for depth sensing in the near and far planes. A vertex shader, wherein the position-only shading pipeline is used to expose the surface triangles to the vertex shader, wherein the rendering pipeline is used to generate outgoing data, wherein the outgoing data includes vertices for tessellation of the surface for piecewise subdivision, wherein the device is used for: The granularity setting of the outflow data, the exclusion region, the non-exclusion region, the clipper parameter, or the setting parameter are adjusted based on the position of one or more of the surface triangles, the lens parameter, or the attribute of the outflow data, wherein the attribute of the outflow data includes one or more of the following: the granularity of the outflow data, the movement or orientation of one or more objects, or the user's gaze.

9. The device as claimed in claim 8, wherein, The position-only coloring pipeline is used to identify at least one of the surface triangles that has been rejected as excluded triangles, and to identify the remaining surface triangles after the rejection as non-excluded triangles, wherein the surface triangles identified as excluded triangles include at least a portion of the surface triangles located in one or more exclusion regions, and wherein the surface triangles identified as non-excluded triangles include surface triangles located in one or more non-excluded regions, and wherein the rejection parameters further include one or more of the following: performance parameters; head-mounted display parameters; or other device parameters.

10. The device as claimed in claim 9, wherein, The device is further used for: Based on the granularity setting of the outflow data, the exclusion region, the non-exclusion region, the clipper parameters, or the adjustment of the setting parameters: The outflowing data is exposed to the vertex shader in the position-only shading pipeline, wherein the position-only shading pipeline is used to discard the outflowing data.

11. The device as claimed in claim 9, wherein, The position-only shading pipeline is used to create a coarse Z-buffer associated with the position-only shading pipeline, wherein the coarse Z-buffer is created when processing the geometry data, and wherein the position-only shading pipeline is used to store one or more of the surface triangles as coarse Z-buffer triangles in a coarse Z-order, wherein the coarse Z-order is from Z 最大 Value to Z 最小 The values ​​are sorted by depth, where Z 最小 Value and the Z 最大 The value identifies the near plane and far plane in the scene.

12. The device as claimed in claim 11, wherein, The position-only shading pipeline is used to perform coarse rasterization based on a coarse Z-value, wherein the coarse Z-value indicates the granularity level of detail in the scene, wherein the surface triangles to be stored as the Z-buffer triangles include non-excluded triangles identified as being occluded by at least one other non-excluded triangle identified as opaque, wherein the position-only shading pipeline is used to set the size of the coarse Z-buffer based on the coarse Z-value, wherein the size of the coarse Z-buffer is proportional to the coarse Z-value, wherein the position-only shading pipeline is used to feed the coarse Z-buffer forward to the rendering pipeline, wherein the rendering pipeline is used to render the Z-buffer triangles.

13. The device as claimed in any one of claims 8 to 12, wherein, The geometric data includes primitives, wherein the location-only coloring pipeline is used for: The graphic elements are processed and classified; Record the distribution and density attributes of the primitives; Determine the number and size of the resolution segments used to process the primitives; At least two graphics processing units (GPUs) are identified to communicate with the location-only shading pipeline; Generate geometry flows for the at least two GPUs; and The at least two GPUs are used to render the primitives based on the resolution fragment or one or more of the distribution and density attributes.

14. A method comprising: The geometric data, including surface triangles representing a digital representation of a scene, is processed by a location-only coloring pipeline. The processing steps include the following: Positioning geometric data, the geometric data including surface triangles for the scene; Perform screen space transformations; and Remove at least one of the surface triangles; and The rendering pipeline renders the remaining surface triangles after the culling. The size of the exclusion and non-exclusion regions is set based on the exclusion parameters. The culling parameters include lens parameters for depth perception of the near and far planes, and the method further includes: Expose the surface triangles to the vertex shader; The rendering pipeline generates outgoing data, which includes vertices for surface tessellation for tiling; The granularity setting of the outflow data, the exclusion region, the non-exclusion region, the clipper parameter, or the setting parameter are adjusted based on the position of one or more of the surface triangles, the lens parameter, or the attribute of the outflow data, wherein the attribute of the outflow data includes one or more of the following: the granularity of the outflow data, the movement or orientation of one or more objects, or the user's gaze.

15. The method of claim 14, further comprising: The at least one of the surface triangles that is removed is identified as an excluded triangle, and the remaining surface triangles after the removal are identified as non-excluded triangles, wherein the surface triangles identified as excluded triangles include at least a portion of the surface triangles located in one or more excluded regions, and wherein the surface triangles identified as non-excluded triangles include surface triangles located in one or more non-excluded regions.

16. The method of claim 15, wherein, The rejection parameters further include one or more of the following: performance parameters; head-mounted display parameters; or other device parameters, and the method further includes: Based on the granularity setting of the outflow data, the exclusion region, the non-exclusion region, the clipper parameters, or the adjustment of the setting parameters: Expose the outflowing data to the vertex shader in the position-only shading pipeline; and The outgoing data is removed by the location-only coloring pipeline.

17. The method of claim 15, in, The processing performed by the location-only coloring pipeline further includes: Create a coarse Z-buffer associated with the position-only shading pipeline, wherein the coarse Z-buffer is created when processing the geometry data. One or more of the surface triangles are stored as Z-buffer triangles in a coarse Z-order, wherein the coarse Z-order is from Z 最大 Value to Z 最小 The values ​​are sorted by depth, where Z 最小 Value and the Z 最大 The value identifies the near plane and far plane in the scene. Coarse rasterization is performed based on a coarse Z-value, wherein the coarse Z-value indicates the granularity level of detail in the scene, and wherein the surface triangles stored as Z-buffer triangles include non-excluded triangles identified as being occluded by at least one other non-excluded triangle identified as opaque. The size of the rough Z-buffer is set based on the rough Z-value, wherein the size of the rough Z-buffer is proportional to the rough Z-value. The method further includes feeding the coarse Z-buffer forward to the rendering pipeline and rendering the coarse Z-buffer triangle by the rendering pipeline.

18. The method according to any one of claims 14 to 17, wherein, The geometric data includes primitives, and the method further includes: The graphic elements are processed and classified; Record the distribution and density attributes of the primitives; Determine the number and size of the resolution segments used to process the primitives; At least two graphics processing units (GPUs) are identified to communicate with the location-only shading pipeline; Generate geometry flow for the at least two GPUs; and The primitives are rendered by the at least two GPUs based on the resolution fragment or one or more of the distribution and density attributes.

19. A system for a position-only coloring pipeline utilizing a coarse Z-buffer, the system comprising means for performing any one of claims 14 to 17, wherein, The geometric data includes primitives, and the system further includes means for performing the following: The graphic elements are processed and classified; Record the distribution and density attributes of the primitives; Determine the number and size of the resolution segments used to process the primitives; At least two graphics processing units (GPUs) are identified to communicate with the location-only shading pipeline; Generate geometry flow for the at least two GPUs; as well as The primitives are rendered by the at least two GPUs based on the resolution fragment or one or more of the distribution and density attributes.

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