Coarse grain consistency

Abstract

The present application relates to coarse-grained consistency. One embodiment provides a general-purpose graphics processing device, including a general-purpose graphics processing computing block that processes a workload including graphics or computing operations, a first cache memory, and a consistency module, so that the first cache memory can consistently cache data for the workload, the data being stored in a memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor includes a second cache memory that is consistent with the first cache memory.

Description

Technical Field

[0001] Embodiments relate generally to data processing, and more particularly to data processing via a general purpose graphics processing unit. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and tile data.

[0003] To further increase performance, graphics processors typically implement processing techniques such as pipelining, which attempts to process as much graphics data as possible in parallel across different parts of the graphics pipeline. Parallel graphics processors with a single instruction, multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to increase processing efficiency. A general overview of software and hardware for a SIMT architecture can be found in Shane Cook, CUDA Programming , Chapter 3, pages 37-51 (2013) and / or Nicholas Wilt, CUDA Manual, A Comprehensive Guide to GPU Programming , sections 2.6.2 to 3.1.2 (June 2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In order that the above-described features of the present embodiment can be understood in detail, a more specific description of the embodiments briefly summarized above can be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it is to be noted that the drawings illustrate only typical embodiments and are not to be considered as limiting the scope thereof.

[0005] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] Figures 2A-2D illustrates a parallel processor assembly according to an embodiment;

[0007] Figure 3A-3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0008] Figures 4A-4FAn exemplary architecture is illustrated in which a plurality of GPUs are communicatively coupled to a plurality of multi-core processors;

[0009] Figure 5 is a conceptual diagram of a graphics processing pipeline according to an embodiment;

[0010] Figure 6 illustrates a heterogeneous processing system with heterogeneous hardware coherence according to an embodiment;

[0011] Figure 7 illustrates a logical structure for coarse-grained consistency according to an embodiment;

[0012] Figure 8 is a flow chart of logic enabling coarse-grained consistency in a heterogeneous processing system;

[0013] Fig. 9 is a block diagram of a data processing system according to an embodiment;

[0014] Fig.10 is a block diagram of a processing system according to an embodiment;

[0015] Fig.11 is a block diagram of a processor according to an embodiment;

[0016] Fig.12 is a block diagram of a graphics processor according to an embodiment;

[0017] Fig.13 is a block diagram of a graphics processing engine of a graphics processor in accordance with some embodiments;

[0018] Fig.14 is a block diagram of a graphics processor provided by an additional embodiment;

[0019] Fig.15 illustrates thread execution logic including an array of processing elements employed in some embodiments;

[0020] Fig.16 is a block diagram illustrating a graphics processor instruction format according to some embodiments;

[0021] Fig.17 is a block diagram of a graphics processor according to another embodiment;

[0022] Figures 18A-18B illustrates a graphics processor command format and command sequence according to some embodiments;

[0023] Fig.19 illustrates an exemplary graphics software architecture for a data processing system according to some embodiments;

[0024] Fig. 20is a block diagram illustrating an IP core development system according to an embodiment;

[0025] Fig.21 is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment;

[0026] Fig. 22 is a block diagram illustrating an additional graphics processor according to an embodiment; and

[0027] Fig.23 is a block diagram illustrating an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0028] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect, such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0029] Graphics processors are increasingly being used for general purpose computing tasks. Example uses of general purpose GPU (GPGPU) processing include, but are not limited to, machine learning, video analysis, facial recognition, and autonomous vehicle control. GPGPU processing can be made more efficient via the use of heterogeneous memory systems, where hardware managed consistency is enabled between the host processor (e.g., CPU) and the GPU. Heterogeneous hardware CPU and GPGPU consistency can significantly simplify the programming model used to enable heterogeneous computing.

[0030] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the present embodiment.

[0031] System Overview

[0032] Figure 11 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 that communicate via an interconnect path, which may include a memory hub 105. The memory hub 105 may be a separate component within a chipset assembly, or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. In addition, the I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, which may be included in the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0033] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication organization. In one embodiment, the one or more parallel processors 112 form a parallel or vector processing system focused on computing, which includes a large number of processing cores and / or processing clusters, such as many integrated core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and display interface (not shown) to enable a direct connection to one or more display devices 110B.

[0034] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connectivity between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that may be integrated into the platform, as well as various other devices that may be added via one or more plug-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radio devices.

[0035] Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 107. Figure 1 The communication paths for the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol(s), such as the NV Link high-speed interconnect, or interconnect protocols known in the art.

[0036] In one embodiment, the one or more parallel processors 112 incorporate circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuits optimized for general-purpose processing while retaining the underlying computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, the memory hub 105, (multiple) processors 102, and the I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0037] It will be appreciated that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of (multiple) processors 102, and the number of (multiple) parallel processors 112, can be modified as desired. For example, in some embodiments, the system memory 104 is directly connected to the (multiple) processors 102 rather than through a bridge, and other devices communicate with the system memory 104 via the memory hub 105 and the (multiple) processors 102. In other alternative topologies, the (multiple) parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Large embodiments may include two or more sets of processors 102 attached via multiple sockets, which may be coupled to two or more instances of the (multiple) parallel processors 112. Some of the specific components shown herein are optional, and may not be included in all implementations of computing system 100. For example, any number of add-in cards or peripherals may be supported, or some components may be excluded.

[0038] Figure 2A A parallel processor 200 is illustrated according to an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the illustrated parallel processor 200 is Figure 1 A variation of the one or more parallel processors 112 shown in .

[0039] In one embodiment, parallel processor 200 includes parallel processing unit 202. Parallel processing unit includes I / O unit 204, which enables communication with other devices, including other instances of parallel processing unit 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface (such as memory hub 105). The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory cross bar 216, wherein host interface 206 receives commands related to performing processing operations and memory cross bar 216 receives commands related to performing memory operations.

[0040] When host interface 206 receives command buffers via I / O unit 204, host interface 206 may direct work operations to execute those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state before distributing tasks to processing clusters of processing cluster array 212.

[0041] Processing cluster array 212 may include up to "N" processing clusters (eg, cluster 214A, cluster 214B, through cluster 214N). Each cluster 214A-214N of processing cluster array 212 is capable of executing a large number (eg, thousands) of concurrent threads, where each thread is an instance of a program.

[0042] In one embodiment, different clusters 214A-214N may be assigned for processing different types of programs, or for performing different types of computations. Scheduler 210 may use a variety of scheduling and / or work distribution algorithms (which may vary depending on the workload caused by each type of program or computation) to allocate work to clusters 214A-214N of processing cluster array 212. Scheduling may be handled dynamically by scheduler 210, or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing cluster array 212.

[0043] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic to perform processing tasks including, but not limited to, linear and nonlinear data transformations, filtering of video and / or audio data, and / or modeling operations (e.g., applying laws of physics to determine position, velocity, and other properties of an object).

[0044] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may deliver data from system memory via I / O unit 204 for processing. During processing, the delivered data may be stored to on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0045] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A-214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0046] During operation, the processing cluster array 212 may receive processing tasks to be performed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program to perform). The scheduler 210 may be configured to extract the index corresponding to the task, or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an upcoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0047] Each of the one or more instances of parallel processing unit 202 may be coupled to parallel processor memory 222. Parallel processor memory 222 may be accessed via memory crossbar 216, which may receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar 216 may access parallel processor memory 222 via memory interface 218. Memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B to partition unit 220N), each of which is directly coupled to a portion (e.g., memory cells) of parallel processor memory 222. The number of partition units 220A-220N is generally equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding memory cell 224B, and an Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0048] In various embodiments, the memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A to 224N may vary and may be selected from one of various conventional designs. Rendering targets such as frame buffers or texture maps may be stored across the memory units 224A to 224N, thereby allowing the partition units 220A to 220N to write portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, in order to facilitate the use of a unified memory design of system memory combined with local cache memory, local instances of the parallel processor memory 222 may be excluded.

[0049] In one embodiment, any one of the clusters 214A to 214N of the processing cluster array 212 can process data to be written to any one of the memory units 224A to 224N within the parallel processor memory 222. The memory crossbar 216 can be configured to route the output of each cluster 214A to 214N to the input of any partition unit 220A to 220N or another cluster 214A to 214N for further processing. Each cluster 214A to 214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I / O unit 204, and a connection to the local instance of the parallel processor memory 222, so that the processing units within different processing clusters 214A to 214N can communicate with the system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 may use virtual channels to separate traffic flows between the clusters 214A to 214N and the partition units 220A to 220N.

[0050] Although a single instance of parallel processing unit 202 is illustrated in parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example and in one embodiment, some instances of parallel processing unit 202 may include floating point units with higher precision relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in various configurations and form factors, including but not limited to desktops, laptops, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0051] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A2 is an example of one of the partition units 220A to 220N. As illustrated, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent writeback requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Dirty updates can also be sent to the frame buffer via the frame buffer interface 225 for opportunistic processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as the memory units 224A to 224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0052] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. and outputs pixel data as processed graphics data for storage in graphics memory. In some embodiments, ROP 226 can be configured to compress z or color data written to memory and decompress z or color data read from memory. In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A to 214N of FIG. 2) rather than within partition unit 220. In such embodiments, read and write requests for pixel data are transmitted through memory crossbar 216 rather than pixel tile data.

[0053] The processed graphics data can be displayed on a display device (such as Figure 1 100 ), routed for routing by the processor(s) 102 , or routed for routing by the processor(s) 102 . Figure 2A The processing is further processed by one of the processing entities within parallel processor 200.

[0054] Figure 2C2 is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A to 214N of FIG. 2. The processing cluster 214 can be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, a single instruction multiple data (SIMD) instruction issuance technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, by using a common instruction unit configured to issue instructions to a processing engine set within each of the processing clusters, a single instruction multiple thread (SIMT) technique is used to support the parallel execution of a large number of substantially synchronized threads. Unlike the SIMD execution regime in which all processing engines typically execute the same instruction, the SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. It will be appreciated by those skilled in the art that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0055] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of Figure 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data cross bar 240 can be used to distribute the processed data to one of multiple possible destinations including other shader units. The pipeline manager 232 can promote the distribution of processed data by specifying a destination for the processed data to be distributed via the data cross bar 240.

[0056] Each graphics multiprocessor 234 within a processing cluster 214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.), which may be pipelined to allow new instructions to be issued before previous instructions are completed. Any combination of function execution logic may be provided. In one embodiment, the function logic supports a variety of operations, including integer and floating point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (AND, OR, XOR), shifts, and calculations of various algebraic functions (e.g., planar interpolation, trigonometry, exponential and logarithmic functions, etc.); and different operations may be performed using the same function unit hardware.

[0057] The series of instructions transmitted to the processing cluster 214 constitute threads, as defined previously herein, and a collection of a certain number of concurrently executed threads across parallel processing engines (not shown) within the graphics multiprocessor 234 is referred to herein as a thread group. As used herein, a thread group refers to a thread group that concurrently executes the same program on different input data, wherein a thread of the group is assigned to a different processing engine within the graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 234, in which case some processing engines will be idle during a cycle when the thread group is being processed. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor 234, in which case processing will occur within consecutive clock cycles. Each graphics multiprocessor 234 can support up to G thread groups concurrently. In addition, within a graphics multiprocessor 234, multiple related thread groups may be active at the same time (in different stages of execution).

[0058] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory that performs load and store operations. In one embodiment, the graphics multiprocessor 234 can abandon the internal cache and use cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 is also able to access the L2 cache within the partition unit (e.g., partition units 220A to 220N of Figure 2) shared among all processing clusters 214, and can be used to transfer data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory external to the parallel processing unit 202 can be used as global memory. In which the processing cluster 214 includes multiple instances of the graphics multiprocessor 234, embodiments can share common instructions and data that can be stored in the L1 cache 308.

[0059] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more on tileization) and optionally cache line indexes. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to allow efficient request interleaving among partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0060] In graphics and computing applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234, and the texture data is fetched from an L2 cache, a local parallel processor memory, or a system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, a local parallel processor memory, or a system memory via a memory crossbar 216. A preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to a ROP unit, which can be located using a partition unit (e.g., partition units 220A to 220N of FIG. 2 ) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0061] It will be appreciated that the core architecture described herein is illustrative, and variations and modifications are possible. For example, any number of processing units, such as graphics multiprocessors 234, texture units 236, preROPs 242, etc., may be included within a processing cluster 214. Additionally, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of a processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0062] Figure 2DA graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0063] In one embodiment, the instruction cache 252 receives the instruction stream to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch the instructions as thread groups (e.g., wraps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. The instruction can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to translate addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0064] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 324. Register file 258 provides temporary storage for operands for data paths of functional units (e.g., GPGPU core 262, load / store unit 266) connected to graphics multiprocessor 324. In one embodiment, register file 258 is divided between each of the functional units so that each functional unit is assigned a dedicated portion of register file 258. In one embodiment, register file 258 is divided between different wire harnesses being executed by graphics multiprocessor 324.

[0065] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. Depending on the embodiment, the GPGPU cores 262 may be similar in architecture, or may be different in architecture. For example and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In addition, the graphics multiprocessor 324 may include one or more fixed-function or special-function units that perform specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0066] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. In one embodiment, the shared memory 270 can be used to enable communication between threads executing on the functional units. For example, the cache memory 272 can be used as a data cache to cache texture data transferred between the functional units and the texture unit 236.

[0067] FIG. 3A to FIG. 3B Additional graphics multiprocessors are illustrated according to an embodiment. The illustrated graphics multiprocessors 325, 350 are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0068] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes Figure 2DThe graphics multiprocessor 325 may include multiple additional instances of the execution resource unit of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and (multiple) texture units 344A-344B. The graphics multiprocessor 325 also includes multiple sets of graphics or computing execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource unit has a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346. The various components can communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325.

[0069] Figure 3B A graphics multiprocessor 350 is shown according to an additional embodiment. Figure 2D and Figure 3A As shown in , the graphics processor includes multiple sets of execution resources 356A-356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load-store units. The execution resources 356A-356D can work in cooperation with (multiple) texture units 360A-360D for texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A-356D can share multiple instances of the instruction cache 354 and the shared memory 362 as well as texture and / or data cache memories 358A-358B. The various components can be connected via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0070] Those skilled in the art will understand that Figure 1 , 2A The architectures described in FIG. 2A-2D and FIG. 3A-3B are illustrative and are not limiting with respect to the scope of the present embodiments. Thus, the techniques described herein may be implemented on any appropriately configured processing unit, including without limitation, one or more mobile application processors, one or more desktop or server central processing units (CPUs), including multi-core CPUs, one or more parallel processing units, such as parallel processing unit 202 of FIG. 2 , and one or more graphics processors or special purpose processing units, without departing from the scope of the embodiments described herein.

[0071] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0072] Technology for interconnecting the GPU to the host processor

[0073] Figure 4A An exemplary architecture is illustrated in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440-443 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughputs depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0074] Furthermore, in one embodiment, two or more of GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in can be implemented using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0075] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0076] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of the system memory address space, and the GPU memories 420-423 may each include 32GB of the system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0077] Figure 4B Additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment are illustrated. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0078] The illustrated processor 407 includes a plurality of cores 460A-460D, each having a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, reorder buffer, etc.) for executing instructions and processing data, which are not illustrated to avoid obscuring the underlying principles of the present invention. Caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by a collection of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441, which may include the processor memories 401-402.

[0079] Coherence is maintained for data and instructions stored in the various caches 462A-462D, 456, and the system memory 441 via inter-core communications over the coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the present invention.

[0080] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. In particular, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0081] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a block transfer engine. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, 43N may be separate GPUs integrated on a common package, line card, or chip.

[0082] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual to physical memory translation (also known as effective to real memory translation) and memory access protocols for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in the cache 438 and the graphics memory 433-434, N is kept consistent with the core caches 462A-462D, 456 and the system memory 411. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, N (e.g., sending updates to cache 438 involving modifications / accesses of cache lines on processor caches 462A-462D, 456 and receiving updates from cache 438).

[0083] The set of registers 445 stores context data for threads executed by the graphics processing engines 431-432, N, and the context management circuit 448 manages the thread contexts. For example, the context management circuit 448 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, the context management circuit 448 can store the current register values ​​to a designated area in memory (e.g., identified by a context pointer). It can then restore the register values ​​when returning to that context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0084] In one implementation, the virtual / effective addresses from the graphics processing engine 431 are translated by the MMU 439 into actual / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executed on the processor 407, or may be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). Resources may be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0085] Thus, the accelerator integrated circuit acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0086] Since the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear to the system as independent units.

[0087] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3DXPoint or Nano-Ram.

[0088] In one embodiment, to reduce the amount of data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memory 433-434, M is the data that will be used most frequently by graphics processing engines 431-432, N, and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 431-432, N) within caches 462A-462D, 456 of the core and system memory 411.

[0089] Figure 4C Another embodiment is illustrated in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via interface 437 and interface 435 over a high-speed link 440 (which again can utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to Figure 4B The same operations as those described, but performed with potentially higher throughput given their close proximity to the coherency bus 462 and caches 462A-462D, 426.

[0090] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0091] In one embodiment of a dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0092] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0093] For the shared programming model, the graphics acceleration module 446 or the separate graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 411 and can be addressed using the effective address to actual address translation technology described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (that is, calling the system software to add a process element to the process element link table). The lower 16 bits of the process handle can be the offset of the process element within the process element link table.

[0094] Figure 4D An exemplary accelerator integrated slice 490 is illustrated. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit 436. An application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, process elements 483 are stored in response to a GPU call 481 from an application 480 executed on a processor 407. Process elements 483 contain process states for corresponding applications 480. The work descriptor (WD) 484 contained in process element 483 may be a single job requested by an application, or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the address space 482 of the application.

[0095] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting up process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0096] In one implementation, a dedicated process programming model is implementation specific. In this model, a single process owns a graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 to get the owned partition, and the operating system initializes the accelerator integrated circuit 436 to get the owned process when assigning the graphics acceleration module 446.

[0097] In operation, the WD extraction unit 491 in the accelerator integrated slice 490 extracts the next WD 484, which includes an indication of the work to be completed by one of the graphics processing engines of the graphics acceleration module 446. As illustrated, the data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447 and / or the context management circuit 446. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can handle the interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431-432, N is translated into an actual address by the MMU 439.

[0098] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431-432, N and / or graphics acceleration module 446 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0099] Table 1 – Registers initialized by the hypervisor

[0100] 1 Slice Control Register 2 Process area pointer dispatched by real address (RA) 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt Vector Table Entry Limits 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0101] Example registers that may be initialized by the operating system are shown in Table 2.

[0102] Table 2 – Registers initialized by the operating system

[0103] 1 Process and thread identification 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual Address (VA) Segment Table Pointer 5 Permission masking 6 Job Descriptor

[0104] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information required by the graphics processing engine 431-432, N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for work to be done.

[0105] Figure 4E Additional details for one embodiment of a sharing model are illustrated. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine to an operating system 495.

[0106] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-directed sharing.

[0107] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization through the hypervisor 496, the graphics acceleration module 446 may be subject to the following requirements: 1) The application's job request must be autonomous (that is, no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The application's job request is guaranteed to be completed within a specified amount of time by the graphics acceleration module 446, including any translation errors, or the graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a directed sharing programming model, the graphics acceleration module 446 must be guaranteed to be fair between processes.

[0108] In one embodiment, for the shared model, the application 480 is necessary to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the targeted acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 446, and the WD can be in the following form: a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application of setting the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current privilege mask override register (AMOR) value before placing the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application's address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state is not required to be saved between jobs or when a job is preempted. The context save / restore area may be pinned system memory.

[0109] Upon receiving the system call, the operating system 495 can verify that the application 480 has been registered and given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

[0110] Table 3 - OS call parameters to the hypervisor

[0111] 1 Job Descriptor (WD) 2 Authority Mask Register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0112] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and been given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a process element link table for the corresponding type of graphics acceleration module 446. The process element may contain the information shown in Table 4.

[0113] Table 4 – Process Element Information

[0114] 1 Job Descriptor (WD) 2 Authority Mask Register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from the hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilizes Record Pointers 12 Storage Descriptor Register (SDR)

[0115] In one embodiment, the hypervisor initializes multiple accelerator integrated slices 490 of registers 445 .

[0116] like Figure 4F As illustrated in , one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memory 401-402 and GPU memory 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memory 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 401-402 and GPU memory 420-423, thereby allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0117] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between the caches of the host processor (e.g., 405) and GPUs 410-413, and also implement biasing techniques that indicate where certain types of data should be stored. Figure 4F4. Multiple instances of bias / consistency management circuits 494A-494E are illustrated in , but the bias / consistency circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436.

[0118] One embodiment allows the GPU-attached memory 420-423 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the typical performance drawbacks associated with full system cache coherence. The ability to access the GPU-attached memory 420-423 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows the host processor 405 software to set up operands and access calculation results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memory 420-423 without cache coherence overhead can be critical to the execution time of the offloaded calculation. For example, in the case of a large number of streaming write memory services, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offloading.

[0119] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granular structure that includes 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented in the stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., to cache entries of the bias table that are frequently / recently used). Alternatively, the entire bias table may be maintained within the GPU.

[0120] In one implementation, the bias table entry associated with each access to the GPU-attached memory 420-423 is accessed before the GPU memory is actually accessed, resulting in the following operations. First, local requests from GPUs 410-413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from GPUs whose pages are found in the host bias are forwarded to processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, requests from processor 405 to find the requested page in the host processor bias complete the request as a normal memory read. Alternatively, requests for GPU bias pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, the GPU can then convert the page to the host processor bias.

[0121] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of circumstances, a purely hardware-based mechanism.

[0122] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message to the GPU (or queues a command descriptor) directing the GPU to change the bias state, and for some transitions, performs a cache flush operation in the host. The cache flush operation is necessary for a transition from host processor 405 bias to GPU bias, but not for the reverse transition.

[0123] In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is beneficial to ensure that GPU-biased pages are those that are required by the GPU but not by the host processor 405, and vice versa.

[0124] Graphics processing pipeline

[0125] Figure 5 2 is a conceptual diagram of a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as parallel processor 200 of FIG. 2 , which in one embodiment is Figure 12 . As described herein, various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a tile / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A-220N of FIG. 2 ). Alternatively, the graphics processing pipeline 500 may be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., such as parallel processor memory 222 in FIG. 2 ) via a memory interface 528, which may be an example of the memory interface 218 of FIG. 2 .

[0126] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for high-order surfaces and primitives, etc. and outputs the vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that is configured to execute a vertex shader program, thereby lighting and transforming vertex data as specified by the vertex shader program. For example, the vertex processing unit 504 can be programmed to transform vertex data from an object-oriented coordinate representation (object space) to a coordinate system that is alternatively based on a space such as a world space or a normalized device coordinate (NDC) space. The vertex processing unit 504 can read data stored in a cache, local or system memory for use in processing vertex data.

[0127] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504, reads stored vertex attributes as needed, and constructs graphics primitives for processing by tessellation control processing unit 508, where graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0128] The tessellation control processing unit 508 treats the input vertices as control points for a geometric patch and transforms these control points from an input representation of the patch (often referred to as a basis for the patch) into a representation suitable for efficient surface estimation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 also computes tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as line, triangle or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate vertex attributes and a surface representation for each vertex associated with the geometric primitive.

[0129] The second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads the stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that is configured to execute a geometry shader program, transforming the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. For example, the geometry processing unit 516 may be programmed to subdivide a graphics primitive into one or more new graphics primitives and calculate parameters, such as plane equation coefficients, for rasterizing the new graphics primitives.

[0130] In some embodiments, the geometry processing unit 516 may also add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518, which receives the parameters and vertices from the geometry processing unit 516, reads the stored vertex attributes as needed, and constructs the graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 may read data stored in the parallel processor memory or the system memory for use in processing the geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0131] The rasterizer 522 scan converts the new graphics primitives and outputs tile and coverage data to the tile / pixel processing unit 524. In addition, the rasterizer 522 may be configured to perform z-culling and other z-based optimizations.

[0132] The tile / pixel processing unit 524 is a programmable execution unit configured to execute a tile shader program or a pixel shader program. The tile / pixel processing unit 524 transforms tiles or pixels received from the rasterizer 522 as specified by the tile or pixel shader program. For example, the tile / pixel processing unit 524 can be programmed to perform operations such as perspective correction, texture mapping, shading, blending, etc. to generate shaded tiles or pixels output to the raster operation unit 526. The tile / pixel processing unit 524 can read data stored in a parallel processor memory or a system memory for use in processing tile data. The tile or pixel shader program can be configured to shade with samples, pixels, tiles, or other granularities depending on the programmed sampling rate.

[0133] The raster operation unit 526 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory. The processed graphics data may be stored in graphics memory (e.g., parallel processor memory 222 in FIG. 2 ) and / or as Figure 1 104 in the system memory 104 for display on one of the one or more display devices 110 or for further processing by the one or more processors 102 or one of the parallel processor(s) 112. In some embodiments, the raster operation unit 526 is configured to compress z or color data written to memory and decompress z or color data read from memory.

[0134] Coarse grain consistency

[0135] The embodiments described herein can significantly reduce the system snoop bandwidth required for hardware-consistent GPGPU / CPU memory accesses, thereby improving performance and reducing power for heterogeneous processing applications. In one embodiment, memory consistency is supported at a large granularity in the range of 1 kilobyte to 4 kilobytes. The large granularity consistency as described herein is different from the cache line consistency (e.g., 64 bytes) used in existing implementations. In one embodiment, a combination of snoop-based and directory-based consistency is used to enable hardware-based CPU and GPGPU cache consistency. The GPGPU and CPU can each implement an "ownership table" to track ownership of access permissions to a given memory area. The agent (CPU or GPU) obtains ownership of the area by sending a zone snoop to the system that defines the area in the memory for which the agent is requesting ownership. Once the ownership of the area is acquired by the agent and recorded in the ownership table associated with the agent, subsequent access to the memory area can be performed without any snoop request.

[0136] Figure 6A heterogeneous processing system 600 with heterogeneous hardware consistency according to an embodiment is illustrated. In one embodiment, the heterogeneous processing system 600 includes a plurality of processors (CPUs 602A-602D) and a GPGPU 620. Each CPU 602A-602D and GPGPU 620 is capable of accessing a shared virtual memory (SVM). In one embodiment, any CPU 602A-602D can allocate a surface in system memory 640. The surface can then be made accessible to GPGPU 620 by mapping the address of the surface into the virtual memory space of GPGPU 620. In one embodiment, the CPUs 602A-602D and GPGPU 620 can access the same physical memory via different virtual memory addresses. In one embodiment, the CPUs 602A-602D and GPGPU 620 have a unified virtual memory space, wherein at least a portion of the memory 640 can be accessed by the CPUs 602A-602D and GPGPU 620 using the same virtual address. Using unified virtual memory, a process on CPU 602A-602D may pass pointers to surfaces to GPGPU 620.

[0137] Each CPU 602A-602D may include a level 1 cache (L1 cache 604), a level 2 (L2 cache 606). The L1 cache 604 may include separate portions for instructions and data. In one embodiment, each CPU includes multiple cores. In such an embodiment, each core has a separate instance of the L1 cache 604, while the L2 cache 606 is shared between the cores. A last level cache (LLC 610) is shared between all CPUs 602A-602D. Multiple CPUs 602A-602D may share data between themselves and with the GPGPU 620 via the LLC 610.

[0138] GPGPU 620 includes L1 cache 621, L2 cache 622, and L3 cache (L3 cache 622). L1 cache 621 may include separate parts for instructions and data, or may be a unified cache. L2 cache 622 may include multiple caches, including a rendering cache or a depth cache. In one embodiment, GPGPU 620 also includes local memory 630. Local memory 630 may be on-board DRAM memory, for example, where GPGPU 620 is a plug-in card or a multi-chip module. In one embodiment, local memory 630 is SRAM memory on the die of GPGPU 620. Local memory 630 may also be embedded DRAM memory on the package with GPGPU 620.

[0139] Each cache memory in the CPU 602A-602D and GPGPU 620 is managed on a cache line basis. The number of cache lines within a cache depends on the size of each cache line and the size of the cache. The size of the cache line may vary across embodiments, and the various caches may not use cache lines of the same size. In one embodiment, each cache line of the CPU 602A-602D is 64 bytes, although not all embodiments are limited to 64 byte cache lines. In such an embodiment, the GPGPU 620 also includes a 64 byte cache line.

[0140] Enabling hardware managed cache coherence between the CPUs 602A-602D and the GPGPU 620 will significantly simplify programming of heterogeneous workloads on heterogeneous processing systems. However, the snooping overhead introduced by each cache line coherence can introduce significant overhead into the system. The embodiments described herein enable hardware coherence between the CPUs 602A-602D and the GPGPU 620 via coarse-grained coherence, where memory coherence is supported at a kilobyte granularity. Coarse-grained coherence between the GPGPU 620 and multiple CPUs 602A-602D can be enabled via the use of ultra-high-speed cache lines (e.g., hyperlines). A hyperline is a coarse-grained coherence unit that includes multiple cache lines. The size of a hyperline can vary across embodiments. In one embodiment, a hyperline is a 1 kilobyte region. In one embodiment, a hyperline is a 4 kilobyte region. In one embodiment, the size of a hyperline can be configured to be a fraction of the size of a cache line. N For example, in the case of a 64-byte cache line size, you can set N =16 to configure a 1 kilobyte hyperline.

[0141] Coherence at the hyperwire level may be enabled via multiple data structures and dedicated cache memories. In one embodiment, coherence is enabled via the use of a hyperwire ownership table (SLOT 632), a hyperwire directory table (SDT 642), and a hyperwire directory table cache (SDTC 612). SLOT 632 may be stored in a local memory 630 of a GPGPU 620. SDT 642 may be stored in a system memory 640 accessible by CPUs 602A-602D and GPGPU 620. SDTC 612 is a cache memory that may store hyperwire directory table entries. In one embodiment, SDTC 612 is an on-die cache memory of CPUs 602A-602D.

[0142] In one embodiment, SLOT 632 is used to indicate superline ownership for GPGPU 620. For cache activity within a superline owned by the GPU, no consistency flow is necessary, and no broadcast snoop data is required by GPGPU 620. In one embodiment, SLOT 632 can track whether any cache line within a superline is cached in L3 cache 624. Although cache coherence can be tracked at the superline level, L3 cache 624 can continue to operate at cache line granularity. In one embodiment, one or more internal caches within CPU 602A-602D and GPGPU 620 are not cache coherent. For example, global heterogeneous coarse-grained system coherence may be limited to data stored in L3 cache 623 of GPGPU 620 and last level cache 610 shared between CPU 602A-602D and GPGPU 620. In such an embodiment, the region of memory 640 may be a declared shared virtual memory that will be globally coherent and the data within the shared virtual memory may be cached only in cache memories participating in the globally heterogeneous coarse-grained coherent system, thereby bypassing lower level cache memories in the GPGPU 620 and / or CPUs 602A-602D.

[0143] SDT 642 is a table indicating the ownership of hyperwires stored in DRAM. In one embodiment, SDT 642 is stored in "stolen" memory, which is accessible by GPGPU 620 and CPU 602A-602D, but is inaccessible to the operating system executed on the CPU. In such an embodiment, SDT 642 is limited to listing the ownership of hyperwires outside of stolen memory. The size of SDT 642 can vary based on the size of the hyperwire and the size of memory 640. For example and in one embodiment, in the case of a 2 kilobyte hyperwire, an SDT 642 of approximately 2 megabytes can cover 8 gigabytes of memory. Entries within SDT 642 can be cached in SDTC 612. SDTC 612 can function in a manner similar to a TLB, which is shared between GPGPU 620 and CPU 602A-602D, where entries for SDT 642 are cached in SDTC 612 in a manner similar to that of page table entries from a page table stored in the TLB.

[0144] In order for an agent (one of the CPUs 602A-602D or the GPGPU 620) on the heterogeneous processing system 600 to take ownership of a hyperline, the agent may send a region snoop to the system. Once ownership of the region (e.g., one or more hyperlines) is acquired and recorded in the corresponding ownership table (e.g., SDT 642, SLOT 632), subsequent accesses to the memory region may be made without requiring or triggering a snoop request. In one embodiment, a region snoop may be performed via a request for ownership operation. The request for ownership operation may be used when an agent (e.g., the GPGPU 620) is about to attempt to perform a cache line write to a hyperline for which the agent does not have current ownership.

[0145] Figure 7 FIG. 7 illustrates a logical structure for coarse-grained consistency according to an embodiment. In the embodiments described herein, the coarse-grained consistency can be implemented in a heterogeneous processing system (e.g., Figure 6 A hyperline is a region of memory that is multiple cache lines in size (e.g., cache line AN). Agents (CPUs, GPUs, etc.) within the system can send region snoops for address ranges. Based on the size of the address range and the degree of associativity of the cache memories within the system, caches in various processor caches can be N Each cache line is mapped to the address range specified by the hyperline. In one embodiment, all cache memories having cache lines within a hyperline will have those cache lines mapped to a single coherence state.

[0146] can be obtained through a super line ownership table (e.g. Figure 6632) to track signal lines owned by the GPGPU. An exemplary SLOT entry 720 includes a superline tag (SL tag 722), a set of coherence protocol state bits (e.g., MESI 724), a set of per-cache line valid bits 726, and a least recently used (LRU) state bit 728. The SL tag 722 is used to identify the superline 710 to which the SLOT entry 720 is associated. The cache coherence protocol state bits track the state associated with the cache coherence protocol in use through a coarse-grained coherence system. MESI 724 (modified, exclusive, shared, invalid) is used by the illustrated embodiment, however, other embodiments may use other coherence protocols, wherein the coherence behavior of the embodiment is adapted accordingly. For example, a modified, exclusive, shared, invalid, forwarding (MESIF) protocol may be used to enable cache-to-cache forwarding of shared cache lines. Each cache line valid bit 726 indicates a valid or invalid state for each cache line within the superline 710. The LRU field 728 bits keep track of the least recently used status for any cache storing the SLOT entry 720. For example and in one embodiment, the SLOT entry 720 for a hyperline may be cached in a coherent cache within a GPGPU.

[0147] SDT entries 730 may be stored in a hyperlink directory table (e.g. Figure 6 In one embodiment, SDT entry 730 is a three-bit entry stored for each hyperline in memory. For each hyperline, a shared / exclusive bit (S / E 732) is used to indicate whether the hyperline is in a shared state or an exclusive state. CPU bit 734 and GPU bit 736 indicate whether ownership resides in the CPU or GPU.

[0148] The SDTC entry 740 may be stored in a hyperline directory table cache (SDTC 612), which is a cache memory stored within the processor die of the CPU. The SDTC entry 740 includes a hyperline tag (SL tag 742) identifying the hyperline, cached data from the SDT entry 730 (e.g., S / E 732, CPU bit 734, GPU bit 736), and an LRU field 748. In one embodiment, the SL tag 742 is generated based on the address of the hyperline. In one embodiment, the SDT entry 730 is indexed based on the hyperline tag, and the SL tag 742 stored in the SDTC entry 740 is the hyperline tag that indexes the SDT entry 730 for which the cached data is located. The LRU field 748 for the SDTC entry 740 is used to determine which entry is evicted from the SDTC when a cache entry is replaced, wherein the least recently used entry is evicted from the SDTC.

[0149] In an embodiment where a MESI or MESI-compatible consistency protocol is enabled for global heterogeneous consistency, a hyperline may only be written if it is in a modified or exclusive state. If the hyperline is in a shared state, all cache lines associated with the hyperline are invalidated before the agent performs a write with global consistency. A cache holding a cache line from a hyperline in a modified state listens to attempted reads from other globally consistent caches in the system for the corresponding main memory location and inserts the data held in the cache. In one embodiment, this operation may be performed by backing off the listened read, updating the data stored in the memory, and then changing the hyperline state to a shared state. In one embodiment, some agents are not allowed to maintain a hyperline in a modified state. For example and in one embodiment, GPGPU 620 may maintain a hyperline in a modified state while CPUs 602A-602D are limited to a shared or exclusive state. A cache holding a cache line associated with a hyperline in a shared state may listen to invalidation or request ownership broadcasts from other globally consistent caches and discard the cache line if the associated hyperline is invalidated. In one embodiment, when ownership of a hyperline is taken by an agent, all cache lines associated with the hyperline are transitioned to an exclusive state.

[0150] Figure 8 800 is a flow chart of logic 800 that enables coarse-grained consistency in a heterogeneous processing system. Logic 800 may be implemented across heterogeneous processing systems (e.g. Figure 6 The cache management system of the heterogeneous processing system 600 is distributed, including an L3 cache within the GPGPU, a last-level cache shared between the CPU and the GPGPU, and one or more memory controllers within the system.

[0151] In one embodiment, the logic 800 may request access to a virtual memory address from a process executing on an agent of a heterogeneous processing system, as shown at block 802. In response, the logic 800 may determine whether the agent has ownership of a hyperline associated with the virtual address, as shown at block 804. At least one of the plurality of cache lines in the hyperline is associated with the requested virtual memory address. The logic 800 may then determine whether the agent owns the hyperline at block 805. The logic 800 may determine ownership of the hyperline by checking an ownership directory associated with the agent. Figure 6 In the case where the agent is a GPGPU, the agent may check a locally stored hyperwire ownership table (e.g., SLOT 632). In the case where the agent is a CPU, if an access to the hyperwire directory table cache is missed, the agent may check the hyperwire directory table cache (e.g., SDTC 612) or the hyperwire directory table (e.g., SDT 642).

[0152] Back to Figure 8 , if the agent owns the hyperline, the logic 800 may allow the agent to access the virtual memory address, as shown at block 810. When the address is within the range of the owned hyperline, the access to the virtual memory address can be performed without causing or requiring a global snoop request. In this scenario, any other agent with cache lines associated with addresses within the hyperline range will have invalidated those cache lines when ownership is transferred to the agent. If the agent does not own the cache line, as determined at block 805, the logic 800 may send a zone snoop to obtain ownership of the memory zone including the virtual memory address, as shown at block 806. The zone snoop may indicate that the agent intends to take ownership of any cache lines associated with the hyperlines within the snooped zone. In one embodiment, a zone snoop may cause multiple hyperlines to change ownership.

[0153] Changing the hyperline ownership may invalidate any cache lines held by other agents within the global heterogeneous coarse-grained consistency system. Any dirty data within those caches may be evicted and written back to memory, and in some embodiments, forwarded to other cache memories. Once ownership is acquired, the logic 800 may then set the hyperline to an owned state within a directory or ownership table within the agent, as shown at block 808. The specific owned state may vary across embodiments. In one embodiment, the owned state is an exclusive state that may be set within a SLOT, SDT, or SDTC entry, such as Figure 7 As shown in . Setting the hyperline to the owned state may allow the agent to access the virtual memory address at block 810 .

[0154] Fig. 9900 is a block diagram of a data processing system 900 according to an embodiment. The data processing system 900 is a heterogeneous processing system having a processor 902, a unified memory 910, and a GPGPU 920. The processor 902 may be any of the general-purpose processors or central processing units (CPUs) described herein. The GPGPU 920 may be any of the GPGPUs or parallel processors described herein. In one embodiment, the processor 902 and the GPGPU 920 are integrated within a system-on-chip integrated circuit. In one embodiment, the processor 902 and the GPGPU 920 are attached to a separate system board. The processor 902 may be connected or soldered to a motherboard socket. The GPGPU 920 may reside on a board of a plug-in graphics card device and may be connected to the system via a system bus such as a PCIe bus.

[0155] In one embodiment, processor 902 includes cache memory 904 and coherence module 905. Cache memory 904 can coherently cache data stored in a coherent shared virtual memory. Coherence operations for processor 902 can be performed by coherence module 905. Coherence module 905 can perform any of the CPU-side coherence operations described herein.

[0156] The processor 902 may execute instructions for a compiler 915 stored in the system memory 912. The compiler 915 is executed on the processor 902 to compile the source code 914A into a finely compiled code 914B. The compiled code 914B may include code that may be executed by the processor 902 and / or code that may be executed by the GPGPU 920. During compilation, the compiler 915 may perform operations to insert metadata relating to various characteristics and metrics of the source code 914A and the compiled source code 914B. The compiler 915 may include the information necessary to perform such operations, or the operations may be performed with the help of a runtime library 916. The runtime library 916 may also facilitate the compiler 915 in the compilation of the source code 914A, and may also include instructions that are linked to the compiled code 914B at runtime to facilitate execution on the GPGPU 920.

[0157] Unified memory 910 represents a unified address space that can be accessed by processor 902 and GPGPU 920. Unified memory includes system memory 912 and GPGPU memory 918. GPGPU memory 918 includes GPGPU local memory 928 within GPGPU 920, and may also include some or all of system memory 912. For example, compiled code 914B stored in system memory 912 may also be mapped into GPGPU memory 918 for access by GPGPU 920.

[0158] GPGPU 920 includes a plurality of computing blocks 921A-921N, which include a plurality of computing clusters such as Figure 2C The computing cluster 214 of the GPGPU 920. The GPGPU 920 also includes a set of registers 924, a cache memory 926, and a consistency module 925 that can be shared among the computing blocks 921A-921N. The consistency module 925 can be configured to manage consistency operations on the GPGPU 920 to enable global heterogeneous coarse-grained consistency for shared virtual memory. The GPGPU 920 can additionally include a GPGPU local memory 928, which is a physical memory of a graphics card or a multi-chip module shared with the GPGPU 920.

[0159] In one embodiment, each of the computational blocks 921A-921N includes a TLB 922A-922N and at least one cache 923A-923N shared among the computational cluster within the computational blocks 921A-921N. Common resources shared among the computational elements of the computational blocks can be efficiently utilized by attempting to schedule threads that will access common data to the same computational blocks. In one embodiment, a global heterogeneous coarse-grained consistency system can be enabled at the GPGPU 920 via a consistency module 925, which can perform any of the GPU-side coarse-grained consistency operations described herein. Global cache coherence can be maintained between one or more cache memories (e.g., caches 923A-923N and / or shared cache 926) within the GPGPU 920 and the cache memory 904 within the processor 902.

[0160] Additional Exemplary Graphics Processing Systems

[0161] Details of the embodiments described above may be incorporated into the graphics processing systems and devices described below. Figures 10 to 23 The graphics processing systems and devices of illustrative embodiments illustrate alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0162] Additional Exemplary Graphics Processing System Overview

[0163] Fig.101 is a block diagram of a processing system 1000 according to an embodiment. In various embodiments, the system 1000 includes one or more processors 1002 and one or more graphics processors 1008, and may be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1002 or processor cores 1007. In one embodiment, the system 1000 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0164] Embodiments of the system 1000 may include or be incorporated into a server-based gaming platform, a gaming console (including gaming and media consoles, mobile gaming consoles, handheld gaming consoles, or online gaming consoles). In some embodiments, the system 1000 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. The data processing system 1000 may also include a wearable device such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device, coupled to the wearable device, or integrated into the wearable device. In some embodiments, the data processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0165] In some embodiments, each of the one or more processors 1002 includes one or more processor cores 1007 that process instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 1007 is configured to process a specific instruction set 1009. In some embodiments, the instruction set 1009 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1007 may each process a different instruction set 1009, which may include instructions that facilitate the emulation of other instruction sets. The processor core 1007 may also include other processing devices, such as a digital signal processor (DSP).

[0166] In some embodiments, the processor 1002 includes a cache memory 1004. Depending on the architecture, the processor 1002 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 1002. In some embodiments, the processor 1002 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor core 1007 using known cache coherence techniques. In addition, a register file 1006 is included in the processor 1002, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1002.

[0167] In some embodiments, the processor 1002 is coupled to a processor bus 1010 to transmit communication signals such as addresses, data, or control signals between the processor 1002 and other components in the system 1000. In one embodiment, the system 1000 uses an exemplary 'hub' system architecture, including a memory controller hub 1016 and an input-output (I / O) controller hub 1030. The memory controller hub 1016 facilitates communication between memory devices and other components of the system 1000, while the I / O controller hub (ICH) 1030 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1016 is integrated within the processor.

[0168] The memory device 1020 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable properties to act as process memory. In one embodiment, the memory device 1020 may operate as system memory for the system 1000 to store data 1022 and instructions 1021 for use when the one or more processors 1002 execute applications or processes. The memory controller hub 1016 is also coupled to an optional external graphics processor 1012, which may communicate with the one or more graphics processors 1008 in the processor 1002 to perform graphics and media operations.

[0169] In some embodiments, the ICH 1030 enables peripherals to be connected to the memory device 1020 and the processor 1002 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 1046, a firmware interface 1028, a wireless transceiver 1026 (e.g., Wi-Fi, Bluetooth), a data storage device 1024 (e.g., a hard drive, flash memory, etc.), and a traditional I / O controller 1040 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1042 connect input devices, such as a keyboard and mouse 1044 combination. A network controller 1034 may also be coupled to the ICH 1030. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1010. It will be appreciated that the illustrated system 1000 is exemplary and not limiting, as other types of data processing systems with different configurations may also be used. For example, the I / O controller hub 1030 may be integrated within the one or more processors 1002 , or the memory controller hub 1016 and the I / O controller hub 1030 may be integrated into a discrete external graphics processor, such as the external graphics processor 1012 .

[0170] Fig.11 is a block diagram of an embodiment of a processor 1100 having one or more processor cores 1102A- 1102N, an integrated memory controller 1114 , and an integrated graphics processor 1108 . Fig.11 Those elements having the same reference numerals (or names) as those of any other figures herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. The processor 1100 may include additional cores up to and including the additional core 1102N represented by the dashed box. Each of the processor cores 1102A-1102N includes one or more internal cache units 1104A-1104N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 1106.

[0171] Internal cache units 1104A-1104N and shared cache unit 1106 represent a cache memory hierarchy within processor 1100. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1106 and 1104A-1104N.

[0172] In some embodiments, the processor 1100 may also include a set of one or more bus controller units 1116 and a system agent core 1110. The one or more bus controller units 1116 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1110 provides management functions for various processor components. In some embodiments, the system agent core 1110 includes one or more integrated memory controllers 1114 to manage access to various external memory devices (not shown).

[0173] In some embodiments, one or more of the processor cores 1102A-1102N include support for simultaneous multithreading. In such embodiments, the system agent core 1110 includes components for coordinating and operating the cores 1102A-1102N during multithreaded processing. In addition, the system agent core 1110 may include a power control unit (PCU) including logic and components for adjusting the power state of the processor cores 1102A-1102N and the graphics processor 1108.

[0174] In some embodiments, in addition, the processor 1100 includes a graphics processor 1108 that performs graphics processing operations. In some embodiments, the graphics processor 1108 is coupled to a set of shared cache units 1106 and a system agent core 1110, which includes the one or more integrated memory controllers 1114. In some embodiments, a display controller 1111 is coupled to the graphics processor 1108 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1111 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1108 or the system agent core 1110.

[0175] In some embodiments, a ring-based interconnect unit 1112 is used to couple the internal components of the processor 1100. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some embodiments, the graphics processor 1108 is coupled to the ring interconnect 1112 via an I / O link 1113.

[0176] Exemplary I / O links 1113 represent at least one of a plurality of types of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1118, such as an eDRAM module. In some embodiments, each of processor cores 1102A-1102N and graphics processor 1108 use embedded memory module 1118 as a shared last-level cache.

[0177] In some embodiments, the processor cores 1102A-1102N are homogeneous cores that implement the same instruction set architecture. In another embodiment, the processor cores 1102A-1102N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 1102A-1102N implement a first instruction set, while at least one of the other cores implements a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 1102A-1102N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, the processor 1100 can be implemented on one or more chips or as a SoC integrated circuit having the illustrated components in addition to other components.

[0178] Fig.12 1 is a block diagram of a graphics processor 1200, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 1200 includes a memory interface 1214 to access memory. The memory interface 1214 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0179] In some embodiments, the graphics processor 1200 also includes a display controller 1202 to drive display output data to a display device 1220. The display controller 1202 includes hardware for one or more overlay planes for a display and a combination of multiple layers of video or user interface elements. In some embodiments, the graphics processor 1200 includes a video codec engine 1206 that encodes, decodes, or transcodes media to, from, or between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421 M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG, and Motion JPEG (MJPEG) formats).

[0180] In some embodiments, graphics processor 1200 includes a block image transfer (BLIT) engine 1204 that performs two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1210. In some embodiments, GPE 1210 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0181] In some embodiments, GPE 310 includes a 3D pipeline 1212 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1212 includes programmable and fixed functional elements that perform various tasks within execution threads that are spawned to elements and / or 3D / media subsystem 1215. While 3D pipeline 1212 can be used to perform media operations, embodiments of GPE 1210 also include a media pipeline 1216 specifically for performing media operations, such as video post-processing and image enhancement.

[0182] In some embodiments, the media pipeline 1216 includes fixed-function or programmable logic units to replace or represent the video codec engine 1206 to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration. In some embodiments, in addition, the media pipeline 1216 also includes a thread spawning unit to spawn threads for execution on the 3D / media subsystem 1215. The spawned threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 1215.

[0183] In some embodiments, the 3D / media subsystem 1215 includes logic for executing threads spawned by the 3D pipeline 1212 and the media pipeline 1216. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1215, which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. The execution resources include an array of graphics execution units that handle 3D and media threads. In some embodiments, the 3D / media subsystem 1215 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0184] Additional Exemplary Graphics Processing Engines

[0185] Fig.13 is a block diagram of a graphics processing engine 1310 of a graphics processor in accordance with some embodiments. In one embodiment, the graphics processing engine (GPE) 1310 is Fig.12 A version of the GPE 1210 is shown in FIG. Fig.13 Elements having the same reference number (or name) as elements in any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Fig.12 1310. The 3D pipeline 1212 and the media pipeline 1216 of the GPE 1310. The media pipeline 1216 is optional in some embodiments of the GPE 1310 and may not be explicitly included in the GPE 1310. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 1310.

[0186] In some embodiments, the GPE 1310 is coupled to or includes a command streamer 1303 that provides a command stream to the 3D pipeline 1212 and / or the media pipeline 1216. In some embodiments, the command streamer 1303 is coupled to a memory, which may be a system memory or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 1303 receives commands from the memory and sends the commands to the 3D pipeline 1212 and / or the media pipeline 1216. The commands are instructions extracted from a ring buffer storing commands for the 3D pipeline 1212 and the media pipeline 1216. In one embodiment, in addition, the ring buffer includes a batch command buffer storing a plurality of command batches. The commands for the 3D pipeline 1212 may also include references to data stored in the memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 1212 and / or image data and memory objects for the media pipeline 1216. The 3D pipeline 1212 and the media pipeline 1216 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 1314 .

[0187] In various embodiments, the 3D pipeline 1212 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 1314. The graphics core array 1314 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution unit) within the graphics core array 1314 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0188] In some embodiments, graphics core array 1314 also includes execution logic that performs media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit further includes general logic that can be programmed to perform parallel general computing operations. The general logic can be connected to Fig.10 (multiple) processor cores 1007 or Fig.11 The general logic within cores 1102A-1102N in the process performs processing operations in parallel or in combination.

[0189] Output data generated by threads executing on graphics core array 1314 can output data to memory in unified return buffer (URB) 1318. URB 1318 can store data for multiple threads. In some embodiments, URB 1318 can be used to send data between different threads executing on graphics core array 1314. In some embodiments, URB 1318 can also be used for synchronization between threads on the graphics core array and fixed function logic within shared function logic 1320.

[0190] In some embodiments, graphics core array 1314 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 1310. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0191] The graphics core array 1314 is coupled to a shared function logic 1320, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 1320 are hardware logic units that provide dedicated supplementary functions to the graphics core array 1314. In various embodiments, the shared function logic 1320 includes, but is not limited to, a sampler 1321, a math 1322, and an inter-thread communication (ITC) 1323 logic. In addition, some embodiments implement one or more caches 1325 within the shared function logic 1320. The shared functions are implemented in the case where the demand for a given dedicated function is insufficient to be included in the graphics core array 1314. Instead, a single instantiation of the dedicated function is implemented as an independent entity in the shared function logic 1320 and shared among the execution resources within the graphics core array 1314. The precise set of functions shared between the graphics core array 1314 and included within the graphics core array 1314 varies between embodiments.

[0192] Fig.14 is a block diagram of another embodiment of a graphics processor 1400 . Fig.14 Elements having the same reference number (or name) as elements in any other figures herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0193] In some embodiments, graphics processor 1400 includes ring interconnect 1402, pipeline front end 1404, media engine 1437, and graphics cores 1480A-1480N. In some embodiments, ring interconnect 1402 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0194] In some embodiments, the graphics processor 1400 receives batches of commands via a ring interconnect 1402. Incoming commands are interpreted by a command streamer 1403 in a pipeline front end 1404. In some embodiments, the graphics processor 1400 includes scalable execution logic that performs 3D geometry processing and media processing via graphics core(s) 1480A-1480N. For 3D geometry processing commands, the command streamer 1403 supplies the commands to a geometry pipeline 1436. For at least some media processing commands, the command streamer 1403 supplies the commands to a video front end 1434, which is coupled to a media engine 1437. In some embodiments, the media engine 1437 includes a video quality engine (VQE) 1430 for video and image post-processing and a multi-format encoding / decoding (MFX) 1433 engine that provides hardware accelerated encoding and decoding of media data. In some embodiments, geometry pipeline 1436 and media engine 1437 each generate execution threads for use with thread execution resources provided by at least one graphics core 1480A.

[0195] In some embodiments, the graphics processor 1400 includes scalable thread execution resource characterization modular cores 1480A-1480N (sometimes referred to as core slices), each having multiple sub-cores 1450A-550N, 1460A-1460N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 1400 can have any number of graphics cores 1480A to 1480N. In some embodiments, the graphics processor 1400 includes a graphics core 1480A, and the graphics core 1480A has at least a first sub-core 1450A and a second sub-core 1460A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 1450A). In some embodiments, the graphics processor 1400 includes multiple graphics cores 1480A-1480N, each including a set of first sub-cores 1450A-1450N and a set of second sub-cores 1460A-1460N. Each sub-core in the set of first sub-cores 1450A-1450N includes at least a first set of execution units 1452A-1452N and a media / texture sampler 1454A-1454N. Each sub-core in the set of second sub-cores 1460A-1460N includes at least a second set of execution units 1462A-1462N and a sampler 1464A-1464N. In some embodiments, each sub-core 1450A-1450N, 1460A-1460N shares a set of shared resources 1470A-1470N. In some embodiments, the shared resources include a shared cache memory and a pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0196] Additional Exemplary Implementation Units

[0197] Fig.15 Thread execution logic 1500 is illustrated, including an array of processing elements employed in some embodiments of a GPE. Fig.15 Elements having the same reference number (or name) as elements in any other figures herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0198] In some embodiments, thread execution logic 1500 includes a shader processor 1502, a thread dispatcher 1504, an instruction cache 1506, a scalable execution unit array including a plurality of execution units 1508A-1508N, a sampler 1510, a data cache 1512, and a data port 1514. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., execution units 1508A, 1508B, 1508C, 1508D, up to any one of 1508N-1 and 1508N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 1500 includes one or more connections to a memory (such as a system memory or cache memory) through one or more of the instruction cache 1506, the data port 1514, the sampler 1510, and the execution units 1508A-1508N. In some embodiments, each execution unit (e.g., 1508A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 1508A-1508N is scalable to include any number of separate execution units.

[0199] In some embodiments, execution units 1508A-1508N are primarily used to execute shader programs. Shader processor 1502 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 1504. In one embodiment, thread dispatcher includes logic to arbitrate thread initiation requests from graphics and media pipelines and instantiate the requested threads on one or more of execution units 1508A-1508N. For example, the geometry pipeline (e.g., Fig.14 1436) can dispatch vertex, tessellation or geometry shaders to thread execution logic 1500 ( Fig.15) for processing. In some embodiments, thread dispatcher 1504 can also process runtime thread spawning requests from executing shader programs.

[0200] In some embodiments, execution units 1508A-1508N support instruction sets that include native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each of the execution units 1508A-1508N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operations enable efficient execution environments in the face of high-latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and an associated independent thread state. For pipelines capable of integer, single-precision floating-point and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operations, execution is multi-issue per clock. While waiting for data from memory or one of the shared functions, dependency logic within execution units 1508A-1508N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, a fragment shader, or another type of shader program including a different vertex shader.

[0201] Each execution unit in execution units 1508A-1508N operates on an array of data elements. The number of data elements is the "execution size" or number of lanes for an instruction. An execution lane is a logical unit that performs data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, execution units 1508A-1508N support integer and floating point data types.

[0202] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as packed data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on a vector as four separated 64-bit packed data elements (data elements of quadruple word length (QW) size), eight separated 32-bit packed data elements (data elements of double word length (DW) size), sixteen separated 16-bit packed data elements (data elements of word length (W) size) or thirty-two separated 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0203] One or more internal instruction caches (e.g., 1506) are included in the thread execution logic 1500 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 1512) are included to cache thread data during thread execution. In some embodiments, a sampler 1510 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 1510 includes a specialized texture or media sampling function to process the texture or media data during the sampling process before providing the sampled data to the execution unit.

[0204] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 1500 via thread spawning and dispatching logic. Once the group of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 1502 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, template buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values ​​of various vertex attributes, which are interpolated across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 1502 then executes the pixel or fragment shader program supplied by the application programming interface (API). To execute the shader program, the shader processor 1502 dispatches the thread to the execution unit (e.g., 1508A) via the thread dispatcher 1504. In some embodiments, the pixel shader 1502 uses the texture sampling logic in the sampler 1510 to access the texture data in the texture map stored in the memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels from further processing.

[0205] In some embodiments, data port 1514 provides a memory access mechanism for thread execution logic 1500 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 1514 includes or is coupled to one or more cache memories (e.g., data cache 1512) to cache data for memory access via the data port.

[0206] Fig.16 1 is a block diagram illustrating a graphics processor instruction format 1600 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in a variety of formats. Solid line boxes illustrate components that are generally included in execution unit instructions, while dashed lines include optional components or components that are included only in a subset of instructions. In some embodiments, the described and illustrated instruction format 1600 are macroinstructions in that they are instructions supplied to the execution unit, as opposed to micro-operations that result from instruction decoding once execution is processed.

[0207] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 1610. A 64-bit compressed instruction format 1630 may be used for some instructions based on the selected instruction, instruction options, and the number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted to the 64-bit format 1630. The native instructions available in the 64-bit format 1630 vary depending on the embodiment. In some embodiments, the instructions are partially compressed using a set of index values ​​in the index field 1613. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions in the 128-bit instruction format 1610.

[0208] For each format, the instruction opcode 1612 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel, the color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 1614 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel ordering (e.g., swizzling). For instructions in the 128-bit instruction format 1610, the execution size field 1616 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 1616 is not available for use in the 64-bit compressed instruction format 1630.

[0209] Some execution unit instructions have up to three operands, including two source operands (src0 1620, src1 1622) and a destination 1618. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 1624), where the instruction opcode 1612 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0210] In some embodiments, the 128-bit instruction format 1610 includes an access / address mode field 1626, which specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0211] In some embodiments, the 128-bit instruction format 1610 includes an access / address mode field 1626 that specifies an address mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in a first mode, the instruction may use byte aligned addressing for source operands and destination operands, and when in a second mode, the instruction may use 16-byte aligned addressing for all source operands and destination operands.

[0212] In one embodiment, the address mode portion of access / address mode field 1626 determines whether the instruction uses direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0213] In some embodiments, instructions are grouped based on the opcode 1612 bit field to simplify opcode decoding 1640. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is only an example. In some embodiments, the move and logic opcode group 1642 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 1642 shares five most significant bits (MSBs), where the move (mov) instruction is in the form of 0000xxxxb, and the logic instruction is in the form of 0001xxxxb. The flow control instruction group 1644 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 1646 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 1648 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 1648 performs arithmetic operations in parallel across data lanes. The vector math group 1650 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot product calculations.

[0214] Additional Example Graphics Pipeline

[0215] Fig.17 is a block diagram of another embodiment of a graphics processor 1700 . Fig.17 Elements having the same reference number (or name) as elements in any other figures herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0216] In some embodiments, the graphics processor 1700 includes a graphics pipeline 1720, a media pipeline 1730, a display engine 1740, a thread execution logic 1750, and a rendering output pipeline 1770. In some embodiments, the graphics processor 1700 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by writing to registers of one or more control registers (not shown) or via commands issued to the graphics processor 1700 via a ring interconnect 1702. In some embodiments, the ring interconnect 1702 couples the graphics processor 1700 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 1702 are interpreted by a command streamer 1703, which supplies instructions to various components of the graphics pipeline 1720 or the media pipeline 1730.

[0217] In some embodiments, command streamer 1703 directs the operation of vertex fetcher 1705, which reads vertex data from memory and executes vertex processing commands provided by command streamer 1703. In some embodiments, vertex fetcher 1705 provides vertex data to vertex shader 1707, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 1705 and vertex shader 1707 execute vertex processing instructions by dispatching execution threads to execution units 1752A-1752B via thread dispatcher 1731.

[0218] In some embodiments, execution units 1752A-1752B are vector processor arrays with instruction sets for performing graphics and media operations. In some embodiments, execution units 1752A-1752B have an attached L1 cache 1751 that is specific to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0219] In some embodiments, the graphics pipeline 1720 includes a tessellation component that performs hardware accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operation. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellation 1713 operates at the direction of the hull shader 1711 and contains dedicated logic to generate a detailed set of geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 1720. In some embodiments, if tessellation is not used, the tessellation components (e.g., the hull shader 1711, the tessellation 1713, and the domain shader 1717) can be bypassed.

[0220] In some embodiments, the complete geometric object may be processed by the geometry shader 1719 via one or more threads dispatched to execution units 1752A-1752B, or may proceed directly to the clipper 1729. In some embodiments, the geometry shader operates on entire geometric objects rather than vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 1719 receives input from the vertex shader 1707. In some embodiments, the geometry shader 1719 may be programmed by a geometry shader program to perform geometry tessellation if the tessellation unit is disabled.

[0221] Before rasterization, the clipper 1729 processes the vertex data. The clipper 1729 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, the rasterizer and depth test component 1773 in the rendering output pipeline 1770 dispatches a pixel shader to convert the geometric object into its per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 1750. In some embodiments, the application can bypass the rasterizer and depth test component 1773 and access the unrasterized vertex data via the outflow unit 1723.

[0222] The graphics processor 1700 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed among the major components of the processor. In some embodiments, execution units 1752A-1752B and associated cache(s) 1751, texture and media samplers 1754, and texture / sampler cache 1758 are interconnected via data ports 1756 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 1754, caches 1751, 1758, and execution units 1752A-1752B each have separate memory access paths.

[0223] In some embodiments, the rendering output pipeline 1770 includes a rasterizer and a depth test component 1773, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit that performs fixed-function triangle and line rasterization. An associated rendering cache 1778 and depth cache 1779 are also available in some embodiments. A pixel operation component 1777 performs pixel-based operations on data, although in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image delivery) are performed by the 2D engine 1741, or replaced by the display controller 1743 using an overlay display plane at display time. In some embodiments, a shared L3 cache 1775 can be used for all graphics components, allowing data to be shared without using main system memory.

[0224] In some embodiments, the graphics processor media pipeline 1730 includes a media engine 1737 and a video front end 1734. In some embodiments, the video front end 1734 receives pipeline commands from the command streamer 1703. In some embodiments, the media pipeline 1730 includes a separate command streamer. In some embodiments, the video front end 1734 processes the media commands before sending the commands to the media engine 1737. In some embodiments, the media engine 1737 includes a thread spawning function that spawns threads for dispatching to the thread execution logic 1750 via the thread dispatcher 1731.

[0225] In some embodiments, the graphics processor 1700 includes a display engine 1740. In some embodiments, the display engine 1740 is external to the processor 1700 and is coupled to the graphics processor via the ring interconnect 1702 or some other interconnect bus or structure. In some embodiments, the display engine 1740 includes a 2D engine 1741 and a display controller 1743. In some embodiments, the display engine 1740 contains dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 1743 is coupled to a display device (not shown), which can be a system integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0226] In some embodiments, graphics pipeline 1720 and media pipeline 1730 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for graphics processors translates API calls specific to specific graphics or media libraries into commands that can be processed by graphics processors. In some embodiments, support is provided for all open graphics libraries (OpenGL), open computing languages ​​(OpenCL) and / or Vulkan graphics and computing APIs from Khronos Group. In some embodiments, support can also be provided for Direct3D libraries from Microsoft. In some embodiments, combinations of these libraries can be supported. Support can also be provided for open source computer vision libraries (OpenCV). If a mapping from the pipeline of a future API to the pipeline of a graphics processor can be made, future APIs with compatible 3D pipelines will also be supported.

[0227] Graphics pipeline programming

[0228] Fig.18A is a block diagram illustrating a graphics processor command format 1800 according to some embodiments. Fig.18B is a block diagram illustrating a graphics processor command sequence 1810 according to an embodiment. Fig.18A The solid-line boxes in illustrate components that are generally included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig.18A An exemplary graphics processor command format 1800 includes a data field that identifies the target client 1802 of the command, a command operation code (opcode) 1804, and associated data for the command 1806. Some commands also include a sub-opcode 1805 and a command size 1808.

[0229] In some embodiments, client 1802 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser checks the client field of each command to adjust further processing of the command and routes the command data to an appropriate client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads an opcode 1804 and a subopcode 1805 (if present) to determine the operation to be performed. The client unit uses the information in the data field 1806 to execute the command. For some commands, an explicit command size 1808 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, commands are aligned via multiples of a double word length.

[0230] Fig.18B An exemplary graphics processor command sequence 1810 is shown in the flowchart in FIG. 1810. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses the version of the command sequence shown to set up, perform, and terminate a set of graphics operations. The sample command sequence is shown and described for purposes of example only, as embodiments are not limited to these specific commands or to the command sequence. Moreover, commands may be issued as a batch of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially concurrent manner.

[0231] In some embodiments, the graphics processor command sequence 1810 may be started with a pipeline clear command 1812 to cause any active graphics pipeline to complete currently pending commands for the pipeline. In some embodiments, the 3D pipeline 1822 and the media pipeline 1824 do not operate concurrently. The pipeline clear is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline clear, the command parser for the graphics processor will stop command processing until the active drawing engine completes the pending operation and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the rendering cache can be cleared to memory. In some embodiments, the pipeline clear command 1812 can be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0232] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, pipeline select command 1813 is used. In some embodiments, pipeline select command 1813 is required only once in an execution context before issuing pipeline commands, unless the context is to issue commands for both pipelines. In some embodiments, pipeline clear command 1812 is required immediately before a pipeline switch via pipeline select command 1813.

[0233] In some embodiments, pipeline control commands 1814 configure the graphics pipeline for operation and are used to program 3D pipeline 1822 and media pipeline 1824. In some embodiments, pipeline control commands 1814 configure pipeline states for active pipelines. In one embodiment, pipeline control commands 1814 are used for pipeline synchronization and clearing data from one or more cache memories within an active pipeline before processing a batch of commands.

[0234] In some embodiments, return buffer state command 1816 is used to configure a set of return buffers for use in causing a corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 1816 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0235] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline determination 1820 , the command sequence is tailored for either the 3D pipeline 1822 starting at 3D pipeline state 1830 , or the media pipeline 1824 starting at media pipeline state 1840 .

[0236] The commands to configure the 3D pipeline state 1830 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 1830 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0237] In some embodiments, the 3D primitive 1832 command is used to submit a 3D primitive to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 1832 command are forwarded to the vertex extraction function in the graphics pipeline. The vertex extraction function uses the 3D primitive 1832 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 1832 command is used to perform vertex operations on the 3D primitive via a vertex shader. In order to process the vertex shader, the 3D pipeline 1822 dispatches the shader execution thread to the graphics processor execution unit.

[0238] In some embodiments, the 3D pipeline 1822 is triggered via an execute 1834 command or event. In some embodiments, a register write triggers the command execute. In some embodiments, the execute is triggered via a "forward" or "kick" command in a command sequence. In one embodiment, the command execute is triggered using a pipeline synchronization command to clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing on 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized and the pixel engine shades the resulting pixels. For those operations, additional commands that control pixel shading and pixel backend operations may also be included.

[0239] In some embodiments, when performing media operations, the graphics processor command sequence 1810 follows the media pipeline 1824 path. In general, the specific use and manner of programming for the media pipeline 1824 depends on the media or computing operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and the media decoding can be performed in whole or in part using resources provided by one or more general processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0240] In some embodiments, media pipeline 1824 is configured in a similar manner to 3D pipeline 1822. A set of commands to configure media pipeline state 1840 is dispatched or placed into a command queue prior to media object commands 1842. In some embodiments, commands for media pipeline state 1840 include data to configure media pipeline elements that will be used to process media objects. This includes data to configure video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, commands for media pipeline state 1840 also support the use of one or more pointers to "indirect" state elements that contain state setup batches.

[0241] In some embodiments, media object commands 1842 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 1842. Once the pipeline states are configured and media object commands 1842 are queued, media pipeline 1824 is triggered via execution commands 1844 or equivalent execution events (e.g., register writes). The output from media pipeline 1824 can then be post-processed by operations provided by 3D pipeline 1822 or media pipeline 1824. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0242] Graphics software architecture

[0243] Fig.19 An exemplary graphics software architecture for data processing system 1900 according to some embodiments is illustrated. In some embodiments, the software architecture includes a 3D graphics application 1910, an operating system 1920, and at least one processor 1930. In some embodiments, processor 1930 includes a graphics processor 1932 and one or more general purpose processor cores 1934. Graphics application 1910 and operating system 1920 are each executed in system memory 1950 of the data processing system.

[0244] In some embodiments, the 3D graphics application 1910 includes one or more shader programs that include shader instructions 1912. The shader language instructions may be in a high-level shader language, such as High Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 1914 in a machine language suitable for execution by the general purpose processor core 1934. The application also includes graphics objects 1916 defined by vertex data.

[0245] In some embodiments, operating system 1920 is a Microsoft® Windows® operating system from Microsoft Corporation, a dedicated UNIX-style operating system, or an open source UNIX-style operating system using a variant of the Linux kernel. Operating system 1920 may support graphics API 1922, such as Direct3D API, OpenGL API, or Vulkan API. When Direct3D API is being used, operating system 1920 uses a front-end shader compiler 1924 to compile any shader instruction 1912 in HLSL into a lower-level shader language. Compilation may be just-in-time (JIT) compilation, or the application may perform shader precompilation. In some embodiments, during compilation of 3D graphics application 1910, high-level shaders are compiled into low-level shaders. In some embodiments, shader instructions 1912 are provided in an intermediate form, such as a version of a standard portable intermediate representation (SPIR) used by Vulkan API.

[0246] In some embodiments, user mode graphics driver 1926 includes a backend shader compiler 1927 to convert shader instructions 1912 into hardware specific representations. When using the OpenGL API, shader instructions 1912 in the GLSL high level language are passed to user mode graphics driver 1926 for compilation. In some embodiments, user mode graphics driver 1926 uses operating system kernel mode functions 1928 to communicate with kernel mode graphics driver 1929. In some embodiments, kernel mode graphics driver 1929 communicates with graphics processor 1932 to dispatch commands and instructions.

[0247] IP core implementation

[0248] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic such as a processor within an integrated circuit. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to make logic to perform the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit, which may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various consumers or manufacturing organizations that load the hardware model on a manufacturing machine that manufactures the integrated circuit. An integrated circuit may be manufactured so that the circuit performs the operations described in association with any one of the embodiments described herein.

[0249] Fig. 202 is a block diagram illustrating an IP core development system 2000 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 2000 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., a SOC integrated circuit). The design agency 2030 can generate a software simulation 2010 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 2010 can be used to design, test, and verify the behavior of the IP core using a simulation model 2012. The simulation model 2012 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 2015 can then be created or synthesized from the simulation model 2012. The RTL design 2015 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2015, a lower-level design at the logic level or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation can vary.

[0250] The RTL design 2015 or equivalent may be further synthesized by the design agency into a hardware model 2020, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 2040 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for delivery to a third-party fabrication agency 2065. Alternatively, the IP core design may be transmitted (e.g., via the Internet) via a wired connection 2050 or a wireless connection 2060. The fabrication agency 2065 may then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit may be configured to perform operations in accordance with at least one embodiment described herein.

[0251] Exemplary System-on-Chip Integrated Circuit

[0252] Figure 21-23 An exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein are illustrated. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0253] Fig.2121 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2100 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 2100 includes one or more application processors 2105 (e.g., CPUs), at least one graphics processor 2110, and may additionally include an image processor 2115 and / or a video processor 2120, any of which may be modular IP cores from the same or multiple different design organizations. The integrated circuit 2100 includes peripheral or bus logic, including a USB controller 2125, a UART controller 2130, an SPI / SDIO controller 2135, and an I 2 S / I 2 C controller 2140. In addition, the integrated circuit may include a display device 2145 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2150 and a mobile industry processor interface (MIPI) display interface 2155. Storage may be provided by a flash memory subsystem 2160 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2165 for accessing SDRAM or SRAM memory devices. In addition, some integrated circuits include an embedded security engine 2170.

[0254] Fig. 22 2 is a block diagram illustrating an exemplary graphics processor 2210 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 2210 may be Fig.21 A variation of a graphics processor 2110 of the present invention. The graphics processor 2210 includes a vertex processor 2205 and one or more tile processors 2215A-2215N (e.g., 2215A, 2215B, 2215C, 2215D, up to 2215N-1 and 2215N). The graphics processor 2210 can execute different shader programs via separate logic, such that the vertex processor 2205 is optimized to execute operations for vertex shader programs, while the one or more tile processors 2215A-2215N execute tile (e.g., pixel) shading operations for tile or pixel shader programs. The vertex processor 2205 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The (multiple) tile processors 2215A-2215N use the primitives and vertex data generated by the vertex processor 2205 to generate a frame buffer displayed on a display device. In one embodiment, the tile processor(s) 2215A-2215N are optimized to execute tile shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

[0255] In addition, the graphics processor 2210 includes one or more memory management units (MMUs) 2220A-2220B, cache(s) 2225A-2225B, and circuit interconnect(s) 2230A-2230B. The one or more MMUs 2220A-2220B provide virtual to physical address mappings for the integrated circuit 2210, including for the vertex processor 2205 and / or the tile processor(s) 2215A-2215N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 2225A-2225B. In one embodiment, the one or more MMUs 2220A-2220B may communicate with other MMUs within the system, including with Fig.21 The one or more MMUs associated with the one or more application processors 2105, image processor 2115, and / or video processor 2120 are synchronized so that each processor 2105-2120 can participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 2230A-2230B enable the graphics processor 2210 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0256] Fig.23 is a block diagram illustrating an additional exemplary graphics processor 2310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 2310 may be Fig.21 A variation of the graphics processor 2110. The graphics processor 2310 includes Fig. 22 The one or more MMUs 2220A-2220B, caches 2225A-2225B, and circuit interconnects 2230A-2230B of the integrated circuit 2200.

[0257] Graphics processor 2310 includes one or more shader cores 2315A-2315N (e.g., 2315A, 2315B, 2315C, 2315D, 2315E, 2315F, up to 2315N-1 and 2315N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary among embodiments and implementations. In addition, the graphics processor 2310 includes an inter-core task manager 2305, which acts as a thread dispatcher that dispatches execution threads to one or more shader cores 2315A-2315N and a tile unit 2318 that accelerates tile operations for tile-based rendering, where rendering operations for a scene are subdivided in image space, for example to exploit local spatial consistency within a scene or to optimize the use of internal caches.

[0258] The following clauses and / or examples relate to specific embodiments or examples thereof. The details in the examples may be used anywhere in one or more embodiments. The various features of the different embodiments or examples may be combined in various ways with some features included and other features excluded to accommodate various different applications. Examples may include, for example, methods, components for performing the actions of the methods, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of the methods, or the actions of an apparatus or system according to the embodiments and examples described herein. Various components may be components for performing the described operations or functions.

[0259] One embodiment provides a general-purpose graphics processing device, including a general-purpose graphics processing computing block that processes a workload including graphics or computing operations, a first cache memory, and a consistency module, so that the first cache memory can consistently cache data for the workload, the data being stored in a memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor includes a second cache memory that is consistent with the first cache memory. In one embodiment, the computing block includes a plurality of computing clusters, each computing cluster including a plurality of graphics multiprocessors. The first cache memory may be a level 3 cache memory. The consistency module tracks consistency at a hyperline granularity, wherein a hyperline includes a plurality of cache lines. Data storage for the first cache memory may be managed at a cache line granularity, while consistency between the first cache memory and the second cache memory may be managed at a hyperline granularity.

[0260] In one embodiment, before writing data to a cache line in the first cache memory, the coherence module determines an ownership state for a hyperline associated with the cache line. To obtain ownership of the hyperline associated with the cache line, the coherence module may snoop on the broadcast region to obtain ownership of the hyperline associated with the cache line. In one embodiment, the general purpose graphics processing device is a plug-in card connected to a separate general purpose processor via a system bus.

[0261] One embodiment provides a method on a heterogeneous processing system, the method comprising receiving a request to access a virtual memory address from a process executed on an agent of the heterogeneous processing system; determining whether the agent has ownership of a first hyperline associated with the virtual address, the first hyperline being associated with a memory region spanning multiple cache lines; when the agent has ownership of the first hyperline, accessing the virtual memory address from the agent without triggering a snoop request; and when the agent does not have ownership of the hyperline, sending a region snoop request to obtain ownership of the first hyperline. In one embodiment, if the agent has ownership of the first hyperline, including reading an entry for the first hyperline from an on-die hyperline directory table cache. Determining whether the agent has ownership of the first hyperline includes, when the agent is a general purpose processor, reading an entry for the first hyperline from a hyperline directory table in memory. When the agent is a general purpose graphics processing unit, determining whether the agent has ownership of the first hyperline includes reading an entry for the first hyperline from a hyperline ownership table in memory of the general purpose graphics processing unit.

[0262] One embodiment provides a heterogeneous data processing system including a general purpose processor including a first cache memory and a first coherence module, and a general purpose graphics processor including a second cache memory and a second coherence module, wherein the first coherence module and the second coherence module enable heterogeneous coherence between the first cache memory and the second cache memory, enabling heterogeneous coherence at a granularity of multiple cache lines. The heterogeneous data processing system additionally includes a first memory module storing a hyperline directory table, the hyperline directory table tracking ownership for each hyperline owned by the general purpose processor and the general purpose processor, wherein each hyperline is an address region spanning multiple cache lines of the first cache memory and the second cache memory.

[0263] The embodiments described herein relate to specific configurations of hardware such as application specific integrated circuits (ASICs) that are configured to perform certain operations or have predetermined functions. Such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-volatile machine-readable storage media), user input / output devices (e.g., keyboards, touch screens, and / or displays), and network connections. The coupling of the collection of processors and other components is typically through one or more buses and bridges (also referred to as bus controllers). The storage device and the signal carrying the network service represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device typically stores code and / or data for execution on the collection of one or more processors of the electronic device.

[0264] Example

[0265] Example 1: A general-purpose graphics processing device, comprising:

[0266] a general-purpose graphics processing compute block that handles workloads that include graphics or compute operations;

[0267] a first cache memory; and

[0268] A coherence module enables a first cache memory to coherently cache data for a workload, the data being stored in memory within a virtual address space, wherein the virtual address space shared with a separate general purpose processor includes a second cache memory coherent with the first cache memory.

[0269] Example 2: The general-purpose graphics processing device as described in Example 1, wherein the general-purpose graphics processing computing block includes multiple computing clusters, each computing cluster includes multiple graphics multiprocessors.

[0270] Example 3: A general purpose graphics processing device as described in Example 1, wherein the workload is a heterogeneous workload including operations to be performed by the general purpose graphics processing compute block and a separate general purpose processor.

[0271] Example 4: A general purpose graphics processing device as described in Example 1, wherein the first cache memory is a level 3 cache memory.

[0272] Example 5: A general purpose graphics processing device as described in Example 1, wherein the general purpose graphics processing device is a plug-in card connected to a separate general purpose processor via a system bus.

[0273] Example 6: A general purpose graphics processing device as described in Example 1, wherein the coherency module tracks coherency at a hyperline granularity, wherein a hyperline includes a plurality of cache lines.

[0274] Example 7: A general purpose graphics processing device as described in Example 6, wherein data storage for the first cache memory is managed at a cache line granularity, and coherency with the second cache memory is managed at a superline granularity.

[0275] Example 8: The general purpose graphics processing device as described in Example 7, additionally comprising a hyperline ownership table storing a set of hyperlines owned by the general purpose graphics processing device.

[0276] Example 9: The general purpose graphics processing device as described in Example 8, wherein the hyperline ownership table includes an entry for each hyperline in the set of hyperlines owned by the general purpose graphics processing device.

[0277] Example 10: A general purpose graphics processing device as described in Example 9, wherein each entry in the hyperline ownership table includes a hyperline tag and a coherence protocol state for the hyperline.

[0278] Example 11: A general purpose graphics processing device as described in Example 10, wherein the coherence protocol state is one of modified, exclusive, shared, or invalid.

[0279] Example 12: The general purpose graphics processing device of Example 10, wherein each entry in the hyperline ownership table additionally includes a valid bit for each cache line within the hyperline.

[0280] Example 13: A method on an agent of a heterogeneous processing system, the method comprising:

[0281] receiving a request to access a virtual memory address from a process executing on the agent;

[0282] determining whether the agent has ownership of a first hyperline associated with the virtual memory address, the first hyperline being associated with a memory region spanning a plurality of cache lines;

[0283] accessing the virtual memory address from the agent without triggering a snoop request when the agent has ownership of the first hyperline; and

[0284] When the agent does not have ownership of the first hyperline, a zone snoop request is sent to obtain ownership of the first hyperline.

[0285] Example 14: A method as described in Example 13, wherein the agent is a central processing unit.

[0286] Example 15: The method of Example 14, wherein determining whether the agent has ownership of the first hyperline comprises reading an entry for the first hyperline from an on-die hyperline directory table cache.

[0287] Example 16: The method of Example 14, wherein determining whether the agent has ownership of the first hyperline includes reading an entry for the first hyperline from a hyperline directory table in memory.

[0288] Example 17: A method as described in Example 13, wherein the agent is a general purpose graphics processing unit.

[0289] Example 18: The method of Example 17, wherein determining whether the agent has ownership of the first hyperline comprises reading an entry for the first hyperline from a hyperline ownership table within a memory of the general purpose graphics processing unit.

[0290] Example 19: A heterogeneous data processing system comprising:

[0291] a general purpose processor including a first cache memory and a first coherency module; and

[0292] A general purpose graphics processor comprising a second cache memory and a second coherency module, wherein the first coherency module and the second coherency module enable heterogeneous coherency between the first cache memory and the second cache memory, enabling heterogeneous coherency at a multiple cache line granularity.

[0293] Example 20: A heterogeneous data processing system as described in Example 19, additionally including a first memory module storing a hyperline directory table, the hyperline directory table tracking ownership of each hyperline owned by a general-purpose processor and the general-purpose processor, wherein each hyperline is an address region spanning multiple cache lines of a first cache memory and a second cache memory.

[0294] Of course, different combinations of software, firmware and / or hardware can be used to implement one or more parts of the embodiment. Throughout this detailed description, for the purpose of explanation, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that embodiments can be put into practice without some of these specific details. In some instances, known structures and functions are not described in detail to avoid blurring the subject matter of the invention of the embodiment. Accordingly, the scope and spirit of the present invention should be determined according to the appended claims.

Claims

1. A general graphics processing device, comprising: a general-purpose graphics processing compute block that handles workloads that include graphics or compute operations; a first cache memory; as well as a coherence module that enables a first cache memory to coherently cache data for a workload, the data being stored in a memory within a virtual address space, wherein the virtual address space shared with the separate general-purpose processor includes a second cache memory that is coherent with the first cache memory, wherein the coherence module tracks coherence at a hyperline granularity, and a hyperline includes a plurality of cache lines, wherein before writing data to a cache line in the first cache memory, the coherency module determines an ownership status for a hyperline associated with the cache line, and the broadcast region snoops to acquire ownership of the hyperline associated with the cache line when the hyperline is now owned by the general purpose graphics processing device, Wherein, determining the ownership of the hyperline includes reading an entry for the hyperline from a hyperline directory table cache on a die, wherein the hyperline directory table tracks ownership of each hyperline owned by the general-purpose processor and the general-purpose graphics processing device, wherein each hyperline is an address region spanning multiple cache lines of a first cache memory and a second cache memory.

2. The general-purpose graphics processing device as claimed in claim 1, wherein the general-purpose graphics processing computing block includes a plurality of computing clusters, each computing cluster includes a plurality of graphics multiprocessors.

3. The general purpose graphics processing device as claimed in claim 1, wherein the workload is a heterogeneous workload including operations to be performed by the general purpose graphics processing compute block and a separate general purpose processor.

4. The general purpose graphics processing device as claimed in claim 1, wherein the first cache memory is a level 3 cache memory.

5. The general purpose graphics processing device as claimed in claim 1, wherein the general purpose graphics processing device is a plug-in card connected to a separate general purpose processor via a system bus.

6. The general purpose graphics processing device as claimed in claim 1, wherein data storage for the first cache memory is managed at a cache line granularity.

7. The general purpose graphics processing device as claimed in claim 6, additionally comprising a hyperline ownership table storing a set of hyperlines owned by the general purpose graphics processing device.

8. The general purpose graphics processing device of claim 7, wherein the hyperline ownership table includes an entry for each hyperline in a set of hyperlines owned by the general purpose graphics processing device, and each entry in the hyperline ownership table includes a hyperline tag and a coherence protocol state for the hyperline.

9. The general purpose graphics processing device as claimed in claim 8, wherein the coherence protocol state is one of modified, exclusive, shared or invalid.

10. The general purpose graphics processing device of claim 8, each entry in the hyperline ownership table additionally including a valid bit for each cache line within the hyperline.

11. The general purpose graphics processing device of claim 1, wherein the coherency module updates a hyperline ownership table entry for a hyperline associated with the cache line to record ownership of the hyperline.

12. A method on an agent of a heterogeneous processing system, the method comprising: receiving a request to access a virtual memory address from a process executing on the agent; determining whether the agent has ownership of a first hyperline associated with a virtual memory address, the first hyperline being associated with a memory region spanning a plurality of cache lines, wherein determining whether the agent has ownership of the first hyperline comprises reading an entry for the hyperline from an on-die hyperline directory table cache, the hyperline directory table tracking ownership of each hyperline owned by the agent, wherein reading the entry for the hyperline from the on-die hyperline directory table cache comprises reading an ownership bit associated with the agent; accessing the virtual memory address from the agent without triggering a snoop request when the agent has ownership of the first hyperline; as well as When the agent does not have ownership of the first hyperline, a zone snoop request is sent to obtain ownership of the first hyperline.

13. The method of claim 12, wherein the agent is a general purpose graphics processing unit, and determining whether the agent has ownership of the first hyperline comprises reading an entry for the first hyperline from a hyperline ownership table within a memory of the general purpose graphics processing unit.

14. The method of claim 12, wherein the agent is a central processing unit, and determining whether the agent has ownership of the first hyperline comprises reading an entry for the first hyperline from an on-die hyperline directory cache.

15. A heterogeneous data processing apparatus comprising components for executing the method according to any one of claims 12 to 14.

16. A heterogeneous data processing system, comprising: a general purpose processor including a first cache memory and a first coherency module; a general purpose graphics processor including a second cache memory and a second coherence module, wherein the first coherence module and the second coherence module enable heterogeneous coherence between the first cache memory and the second cache memory, heterogeneous coherence is enabled at a plurality of cache line granularities, wherein data storage for the first cache memory is managed at a cache line granularity, coherence of shared virtual memory allocations cached by the first cache memory and the second cache memory is managed at a superline granularity, and the second cache memory is a last level cache shared between the general purpose processor and the general purpose graphics processor; as well as A first memory module stores a hyperline directory table that tracks ownership of each hyperline owned by the general purpose processor and the general purpose graphics processor, wherein each hyperline is a region of addresses spanning a plurality of cache lines of a first cache memory and a second cache memory.

17. A heterogeneous data processing system as described in claim 16, wherein the general-purpose graphics processor also includes a graphics processing computing block for processing workloads including graphics or computing operations, and the general-purpose graphics processing computing block includes multiple computing clusters, each computing cluster includes multiple graphics multiprocessors.

18. The heterogeneous data processing system as claimed in claim 17, additionally comprising a third cache memory for caching entries of the hyperline directory table.

19. The heterogeneous data processing system of claim 18, wherein the general purpose graphics processor comprises a second memory module storing a hyperline ownership table, the hyperline ownership table indicating a set of hyperlines owned by the general purpose graphics processor.

20. The heterogeneous data processing system of claim 16, wherein in order to obtain ownership of the hyperline owned by the general purpose processor, the second consistency module transmits a region snoop for the hyperline to the first consistency module.

21. The heterogeneous data processing system of claim 16, wherein the general purpose processor and the general purpose graphics processor share the same die on a system on chip integrated circuit.

22. The heterogeneous data processing system as claimed in claim 16, wherein the first cache memory and the second cache memory cache data stored in the shared memory.

23. The heterogeneous data processing system of claim 22, wherein the shared memory has a virtual address in a virtual memory address space shared by the general purpose processor and the general purpose graphics processor.

24. The heterogeneous data processing system of claim 16, wherein the first cache memory is accessible to a general purpose graphics processor.

25. A machine-readable medium having instructions stored thereon, which when executed by a machine cause the machine to perform the method according to any one of claims 12-14.

26. A computer program product having instructions which, when executed by a machine, cause the machine to perform the method according to any one of claims 12 to 14.

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