Array substrate and mobile terminal

Abstract

This disclosure relates to an array substrate and a mobile terminal. The array substrate includes: a substrate; a slot; a plurality of pixel units disposed on the substrate to form a display area; pixel units at a first sub-edge constitute a first display area, and pixel units at a second sub-edge constitute a second display area; pixel units in the same row of the first display area share a first gate line; pixel units in the same row of the second display area share a second gate line; a first gate driving circuit located on a first side of the slot is used to drive the pixel units in the first display area through the first gate line; a second gate driving circuit located on a second side of the slot is used to drive the pixel units in the second display area through the second gate line. In the embodiments of this disclosure, the depth of the slot can be reduced to achieve the purpose of narrow bezel design of the mobile terminal.

Description

Technical Field

[0001] This disclosure relates to the field of terminal technology, and in particular to an array substrate and a mobile terminal. Background Technology

[0002] With the widespread adoption of mobile devices such as smartphones, more and more users are opting for mobile devices with large screens and narrow bezels. Because some components on mobile devices, such as the front-facing camera, occupy screen space, parts of the display are unusable. To achieve narrow bezels, related technologies involve notching the array substrate and placing the front-facing camera within this notch, allowing content to be displayed on either side of the camera. This increases the screen area ratio, thus achieving a narrow bezel.

[0003] However, in the process of implementing the technical solution of this invention, the inventors discovered that the grid lines of the pixel units on both sides of the slot need to avoid the slot, occupying part of the display area below the camera and affecting the visual aesthetics. Summary of the Invention

[0004] This disclosure provides an array substrate and a mobile terminal to solve or partially solve the shortcomings of related technologies.

[0005] According to a first aspect of the present disclosure, an array substrate is provided, the array substrate comprising:

[0006] Base;

[0007] A slot is provided at one edge of the substrate;

[0008] Multiple pixel units are arranged on the substrate to form a display area; wherein the pixel units of the first sub-edge constitute the first display area, and the pixel units of the second sub-edge constitute the second display area, wherein the first sub-edge refers to the area where the edge is located on the first side of the slot, and the second sub-edge refers to the area where the edge is located on the second side of the slot;

[0009] Pixel units located in the same row of the first display area share a first gate line;

[0010] Pixel units located in the same row of the second display area share a second gate line;

[0011] A first gate driving circuit located on the first side of the slot is electrically connected to multiple first gate lines and is used to drive pixel units located in the first display area.

[0012] The second gate driving circuit, located on the second side of the slot, is electrically connected to multiple second gate lines and is used to drive the pixel units located in the second display area.

[0013] Optionally, the array substrate further includes: a third display area, which is composed of pixel units below the bottom of the slot; and pixel units in the same row within the third display area share a third gate line;

[0014] The first gate driving circuit is electrically connected to multiple third gate lines and is used to drive pixel units within the third display area.

[0015] Optionally, the first gate driving circuit includes a first driving unit and a second driving unit;

[0016] The first driving unit is electrically connected to multiple first gate lines and is used to drive pixel units located in the first display area;

[0017] The second driving unit is electrically connected to multiple third gate lines and is used to drive pixel units located in the third display area.

[0018] Optionally, a first non-display area is provided on the array substrate, and a first driving unit is provided in the first non-display area;

[0019] The first non-display area is the area between the slot and the first display area.

[0020] Optionally, a second non-display area is provided on the array substrate, and a second gate driving circuit is provided in the second non-display area;

[0021] The second non-display area is the area between the slot and the second display area.

[0022] Optionally, the array substrate further includes at least two clock signal lines; the at least two clock signal lines are disposed on at least one side of the display area.

[0023] Optionally, the at least two clock signal lines extend to the first non-display area; or,

[0024] The at least two clock signal lines extend into the second non-display area; or,

[0025] The at least two clock signal lines extend simultaneously to the first non-display area and the second non-display area.

[0026] Optionally, a third non-display area is provided on the array substrate, and a first driving unit is provided in the third non-display area;

[0027] The third non-display area is the area between the second display area and the substrate.

[0028] Optionally, a fourth non-display area is provided on the array substrate, and a second driving unit is provided in the fourth non-display area;

[0029] The fourth non-display area is the area between the second display area and the substrate.

[0030] According to a second aspect of the present disclosure, a mobile terminal is provided, characterized in that it includes the array substrate described in the first aspect and a preset component, the preset component being disposed within a slot.

[0031] Optionally, the preset component includes at least one of a camera, a receiver, a speaker, and a light sensor.

[0032] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0033] As can be seen from the above embodiments, this disclosure forms a display area by arranging multiple pixel units on a substrate with slots. Pixel units in the same row on the first side of the slot share a first gate line, and pixel units in the same row on the second side of the slot share a second gate line. A first gate driving circuit drives the pixel units on the first side of the slot through multiple first gate lines, and a second gate driving circuit drives the pixel units on the second side of the slot through multiple second gate lines. It is evident that the pixel units on both sides of the slot are driven by different gate driving circuits, and pixel units in the same row do not need to share gate lines. That is, in this embodiment, the gate lines do not need to avoid the slot, which can reduce the depth of the slot and achieve the purpose of narrow bezel design for mobile terminals.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0036] Figure 1 This is a schematic diagram of the structure of an array substrate shown in related technologies;

[0037] Figure 2 This is a schematic diagram of the structure of an array substrate according to an exemplary embodiment;

[0038] Figure 3 This is a schematic diagram of the structure of an array substrate according to another exemplary embodiment;

[0039] Figure 4 This is a schematic diagram of the structure of an array substrate according to yet another exemplary embodiment;

[0040] Figure 5 This is a schematic diagram of the structure of an array substrate according to yet another exemplary embodiment;

[0041] Figure 6 This is a schematic diagram of the structure of an array substrate according to yet another exemplary embodiment;

[0042] Figure 7 This is a schematic diagram of the structure of a mobile terminal according to an exemplary embodiment. Detailed Implementation

[0043] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0044] Figure 1 This is a schematic diagram illustrating the structure of an array substrate according to related technologies. For example... Figure 1 As shown, the array substrate 100 includes a substrate 101. A slot 102 is provided on one edge of the substrate 101, and a number of preset components, such as at least one of a camera, a receiver, a speaker, and a light sensor, can be placed in the slot 102. A plurality of pixel units (not shown) are arranged on the substrate 101. The plurality of pixel units form a display area 103, and the shape of the display area 103 can vary with the shape of the substrate 101 and the slot 102.

[0045] To ensure the display of pixel units on both sides of slot 102, such as Figure 1 As shown, the grid line 106 needs to be designed to avoid it, that is, the first side of the slot 102 ( Figure 1 The grid line 106 (on the left side of the slot 102) extends through the hub area 104 to the second side of the slot 102. Figure 1 (Right side of slot 102). In this way, the gate driver on array (GOA) 105 can pass through gate line 106 ( Figure 1 The text also uses labels G1, ..., Gk, ... Gn to represent the pixel units on both sides of the slot 102 driven by each gate line 106. If the depth of the slot 102 (... Figure 1When the width corresponding to the vertical direction is deep, there will be many rows of pixel units on both sides of the slot 102, and the number of corresponding grid lines 106 will also be large. At this time, the width of the line area 104 is large, which causes the display area below the bottom of the slot 102 to become narrower. In other words, the area between the opening of the slot 102 and the edge 107 of the line area 104 away from the opening is not used for display, which affects the visual aesthetics.

[0046] To address the aforementioned problems, embodiments of this disclosure provide an array substrate, such as... Figure 2 As shown, the array substrate 200 includes:

[0047] 201 substrate;

[0048] A slot 202 is provided on an edge 210 of the base 201;

[0049] Multiple pixel units (not shown in the figure) are arranged on the substrate 201 to form a display area 203; wherein the pixel units of the first sub-edge 211 constitute the first display area, and the pixel units of the second sub-edge 212 constitute the second display area, wherein the first sub-edge 211 refers to the edge 210 located on the first side of the slot 202. Figure 2 The area on the left side of the slot 202; the second sub-edge 212 refers to the area where edge 210 is located on the second side of the slot 202.

[0050] Pixels located in the same row of the first display area share a first gate line 204. Figure 2 Each grid line is further highlighted using the labels G1, ..., Gk, ..., Gn.

[0051] Pixel units in the same row of the second display area share a second gate line 205;

[0052] The first gate driving circuit 207, located on the first side of the slot 202, is electrically connected to multiple first gate lines and is used to drive the pixel units located in the first display area.

[0053] The second gate driving circuit 208, located on the second side of the slot 202, is electrically connected to multiple second gate lines and is used to drive the pixel units located in the second display area.

[0054] Understandably, edge 210 is a region corresponding to a portion of the base on the substrate 201. Since a groove is cut within this edge 210, for ease of understanding, it is assumed that the depth of the groove is the same as the width of edge 210; that is, the groove 202 will divide the edge 210 into two parts. The portion of edge 210 located on the first side of the groove 202 is the first sub-edge 211, and the portion of edge 210 located on the second side of the groove 202 is the second sub-edge 212.

[0055] It should be noted that the above-mentioned pixel units in the same row sharing a first gate line 204 means that pixel units in the same row are controlled by a driving signal from the same first gate line 204, while pixel units in multiple rows are controlled by driving signals from multiple first gate lines 204 respectively. The arrangement of gate lines and pixel units can refer to related technologies, and this disclosure does not limit it.

[0056] The number of pixel units can be set according to actual needs. For ease of understanding, in this embodiment, multiple pixel units are arranged as follows: viewed from the row direction ( Figure 2 (From the left and right direction), the pixel unit is located in one row; from the column direction ( Figure 2 The pixel units are arranged in a row (vertical direction). It is understood that when the arrangement of the pixel units changes, the structure of the array substrate will also be adjusted accordingly, but this will not affect the effectiveness of the embodiments of this disclosure.

[0057] In this embodiment, the pixel units on both sides of the slot 202 are driven by different gate driving circuits. Therefore, pixel units in the same row on both sides of the slot 202 do not need to share gate lines. That is, in this embodiment, the gate lines do not need to avoid the slot 202. Figure 2 As shown, the width of the hub area 104 in the related technology is d1. After adopting the solution of the present disclosure embodiment, the width of this area becomes d2, that is, the width of the hub area 104 is reduced by d3 (i.e. d1-d2). It can be seen that the solution of the present disclosure embodiment can reduce the depth of the slot and achieve the purpose of narrow bezel design of mobile terminal.

[0058] In one embodiment of this disclosure, the array substrate 200 further includes: a third display area, which is composed of pixel units below the bottom of the slot 202; and the pixel units in the same row within the third display area share a third gate line 206;

[0059] The first gate driving circuit 207 is electrically connected to multiple third gate lines 206 and is used to drive pixel units within the third display area.

[0060] To ensure that the first display area and the third display area are in different timing sequences, in one embodiment of this disclosure, the first gate driving circuit 207 further includes a first driving unit 2071 and a second driving unit 2072. The first driving unit 2071 is electrically connected to multiple first gate lines 204 and is used to drive pixel units located in the first display area. The second driving unit 2072 is electrically connected to multiple third gate lines 206 and is used to drive pixel units located in the third display area.

[0061] In one embodiment of this disclosure, such as Figure 2As shown, the first driving unit 2071 is disposed in the area between the substrate 201 and the first display area, and this area does not occupy the display area. Normally, since the second driving unit 2072 is disposed in this area, the placement of the first driving unit 2071 will not increase the width of the aforementioned area. In this embodiment, since the first gate line 204 does not need to avoid the slot 202, the distance d4 between the first side of the slot 202 and the edge of the display area 203 can be reduced. This increases the display area on the first side of the slot 202, which is beneficial for designing a narrow bezel and improving visual aesthetics.

[0062] In yet another embodiment of this disclosure, such as Figure 2 As shown, the second gate driving circuit 208 is disposed in the region between the substrate 201 and the second display area, and this region does not occupy the display area. It is understood that when the aforementioned region is disposed at the edge of the mobile terminal, the width of the second gate driving circuit 208 can be reduced. Figure 2 By increasing its length in the left and right directions, this design further reduces the area of ​​the bezel and increases the area of ​​the display area. In this embodiment, the second grid line 205 does not need to avoid the slot 202, so the distance between the second side of the slot 202 and the second display area can be reduced by d5. This increases the display area on the second side of the slot 202, i.e., the second display area becomes larger, which is beneficial for designing a narrow bezel and improving visual aesthetics.

[0063] In a specific application scenario, in one embodiment of this disclosure, the first driving unit 2071 and the second gate driving circuit 208 can be configured according to... Figure 2 The layout shown can be configured to cancel. Figure 1 The area occupied by the central grid line when avoiding the slot 102, that is, the edge of the display area and the edge of the slot, should be as close as possible, theoretically they can overlap. In practice, a preset... Figure 2 The strip-shaped area shown is for facilitating the welding of pre-designed components and other parts.

[0064] In practical applications, the first driving unit 2071, the second gate driving circuit 208, and the second driving unit 2072 require clock signal lines to control their timing. Depending on the application scenario, this embodiment provides at least two clock signal lines, located on at least one side of the display area. Figure 2 Taking the array substrate shown as an example, it is assumed that the clock signal lines STV1 / STV2 are located between the edge of the display area 203 and the edge of the substrate 201, and on the first and / or second side of the slot 202.

[0065] When the second gate driving circuit 208 is disposed on the array substrate, the clock signal line required by the second gate driving circuit 208 is disposed in the area where the second gate driving circuit 208 is located, that is, in the area between the edge of the display area 203 and the edge of the substrate 201, and on the second side of the slot 202. Of course, the clock signal lines STV1 / STV2 on both sides of the slot 202 need to be provided by the same clock source to ensure that the gate driving circuit drives the pixel units in an orderly manner. Figure 2 The image only shows the case where the array substrate has 2 clock signal lines. It is understood that the clock signal lines can also be set to 3, 4, or even more, and the setting position can be at least one side of the display area.

[0066] Understandably, when the clock signal line is only located on the first (or second) side of the display area, it is necessary to extend the clock signal line to the location of the first and second drive units.

[0067] In one embodiment of this disclosure, such as Figure 3 As shown, a first non-display area 301 is provided on the array substrate 300. The first non-display area 301 is the area between the first side of the slot 202 and the first display area. Accordingly, the aforementioned at least two clock signal lines extend to the first non-display area 301.

[0068] In one embodiment of this disclosure, such as Figure 4 As shown, a second non-display area 402 is provided on the array substrate 400. This second non-display area 402 is the area between the second side of the slot 202 and the second display area. Accordingly, the aforementioned at least two clock signal lines extend to the second non-display area 402.

[0069] In one embodiment, the first non-display area and the second non-display area can be set simultaneously, such as... Figure 4 The first non-display area 401 and the second non-display area 402 are shown. Accordingly, at least two clock signal lines extend to the first non-display area 401 and the second non-display area 402.

[0070] like Figure 4 As shown, taking the clock signal line on the first side of the slot 202 as an example, when the first driving unit 2071 is set in the first non-display area 401, the clock signal line includes a first segment 403, a second segment (not shown in the figure), and a first connecting segment 404.

[0071] The first line segment 403 is located on the first side of the display area 203 and is used for the gate driving circuit (e.g., connected to the pixel unit below the bottom of the slot 202). Figure 2The second driving unit 2072 in the middle provides a clock signal; the first connecting segment 404 is located on the first side of the slot 202 and parallel to the gate line, and is used to connect the first line segment 403 and the second line segment; the second line segment is located in the first non-display area and is used to provide a clock signal to the first driving unit 2071.

[0072] When the second gate driving circuit 208 is disposed in the second non-display area 402, the extension of the clock signal line can be referred to the previous embodiment, and will not be described again here.

[0073] In one embodiment of this disclosure, such as Figure 5 As shown, when at least two clock signal lines are provided on the first side of the display area, the clock signal lines include a first segment 503, a second segment (not shown in the figure), a third segment 506, a first connecting segment 504, and a second connecting segment 505.

[0074] The first line segment 503 is located on the first side of the display area. Figure 5 (Left side of the central display area), for connecting the gate drive circuit (e.g., to the pixel unit below the bottom of the slot 202) Figure 2 The second drive unit 2072 in the middle provides the clock signal;

[0075] The first connecting segment is located on the first side of the slot 202 and is parallel to the grid line, and is used to connect the first line segment 503 and the second line segment.

[0076] The second line segment is located within the first non-display area 501 and is used to provide a clock signal to the first driving unit 2071;

[0077] The second connecting segment 505 is located in the display area below the bottom of the slot and is parallel to the grid line, and is used to connect the first segment 503 and the third segment 506.

[0078] The third segment 506 is located within the second non-display area 502 and is used to provide a clock signal to the second gate drive circuit 208.

[0079] Understandably, the second line segment is used to connect the first connecting segment 504 and the first driving unit 2071 located in the first non-display area 501. Depending on the actual scenario, the second line segment can be parallel to the first gate line or perpendicular to the gate line.

[0080] It is understandable that when the third line segment 506 provides a clock signal to the second gate drive circuit 208, the third connection segment 507 and the fourth line segment can also be set according to the position of the second gate drive circuit 208. The setting of the fourth line segment can refer to the setting method of the second line segment described above, and will not be described in detail here.

[0081] Understandably, due to the width of the array substrate, there is a delay in the transmission of the clock signal line from the first side of the slot to the second side. Therefore, it is necessary to adjust the driving timing of the signals on both sides to achieve the goal of the same signal appearing simultaneously on both sides of the slot. The process of adjusting the clock signal can be performed at the clock source, and the specific adjustment method can be found in related technologies. This disclosure does not limit the specific method.

[0082] In one embodiment of this disclosure, such as Figure 6 As shown, a third non-display area 601 is provided on the array substrate 600, and a first driving unit 2071 is provided in the third non-display area 601. The first driving unit 2071 drives the first display area through the first gate line. Figure 6 The pixel unit is located on the left side of the slot 202. The third non-display area 601 is the area between the first display area and the substrate 201. When the first driving unit 2071 is positioned in the third non-display area 601, it can be cancelled. Figure 1 The central grid line avoids the area occupied by the slot 102, so that the edge of the display area is as close as possible to the edge of the slot, that is, the first display area is larger, which is conducive to designing a narrow bezel and increasing the display area.

[0083] In yet another embodiment of this disclosure, such as Figure 6 As shown, a fourth non-display area 602 is provided on the array substrate 600, and a second gate driving circuit 208 is provided in the fourth non-display area 602. The second gate driving circuit 208 drives the second display area through the second gate line 205. Figure 6 The pixel unit is located on the right side of the slot 202. The fourth non-display area 601 is the area between the second display area and the substrate 201. When the second gate drive circuit 208 is located within the fourth non-display area 602, it can be cancelled. Figure 1 The central grid line avoids the area occupied by the slot, making the edge of the display area as close as possible to the edge of the slot, thus increasing the size of the second display area, which is beneficial for designing narrow bezels and increasing the display area.

[0084] In one embodiment, the array substrate simultaneously comprises a third non-display area 601 and a fourth non-display area 602. This eliminates the need for the gate lines to avoid the slot, allowing the edges of the display area to be as close as possible to the edges of the slot, thus simultaneously increasing the size of both the first and second display areas. This facilitates the design of narrow bezels and increases the display area, enhancing visual appeal and achieving [the desired effect]. Figure 2 The technical effects of the proposed solution are shown.

[0085] Understandably, in order for the first gate driving circuit and the second gate driving circuit to function properly, in one embodiment of this disclosure, the routing position of the clock signal line is adjusted according to the positions of the first gate driving circuit and the second gate driving circuit to extend to the positions of the first gate driving circuit and the second gate driving circuit, thereby providing a clock signal. For specific routing methods, please refer to... Figure 4 and Figure 5 The routing of the clock signal lines will not be described in detail here.

[0086] It should be noted that, for the sake of simplicity in the accompanying drawings and description, the data line is not mentioned in the above embodiments. To implement the scheme of this disclosure embodiment, when the first gate driving circuit and the second gate driving circuit receive the clock signal, they output gate driving signals to each pixel unit. Correspondingly, pixel data is input via the data line. At this time, the pixel unit displays the corresponding pixel value, and after all the pixel units in all rows have been displayed once according to a preset order, one frame of image is displayed. It is understood that dynamic display of the image can be achieved by adjusting the frequency of the clock signal. For the image display principle, please refer to relevant technologies; it will not be detailed here.

[0087] Therefore, in the array substrate provided in this embodiment, the pixel units on both sides of the slot are driven by different gate driving circuits. Thus, pixel units in the same row on both sides of the slot do not need to share gate lines; that is, in this embodiment, the gate lines do not need to avoid the slot. Depending on the arrangement of the gate driving circuit, the width of the busbar area can be reduced in related technologies. For example, the width between the bottom edge of the slot and the display area, the width between the first side of the slot and the display area, and the width between the second side of the slot and the display area, achieving the goal of a narrow bezel design for mobile terminals.

[0088] One embodiment of this disclosure also provides a mobile terminal, which includes the array substrate and preset components provided in the above embodiments. The preset components are disposed within a slot, such as at least one of a camera, a receiver, a speaker, and a light sensor.

[0089] like Figure 7 As shown, the mobile terminal 700 can be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0090] Reference Figure 7 The mobile terminal 700 may include one or more of the following components: a processing component 702, a memory 704, a power supply component 706, a multimedia component 708, an audio component 710, an input / output (I / O) interface 712, a sensor component 714, and a communication component 716.

[0091] Processing component 702 typically controls the overall operation of mobile terminal 700, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 702 may include one or more processors 720 to execute instructions. Furthermore, processing component 702 may include one or more modules to facilitate interaction between processing component 702 and other components. For example, processing component 702 may include a multimedia module to facilitate interaction between multimedia component 708 and processing component 702.

[0092] Memory 704 is configured to store various types of data to support operation on mobile terminal 700. Examples of this data include instructions for any application or method operating on mobile terminal 700, contact data, phonebook data, messages, pictures, videos, etc. Memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0093] The power supply component 706 provides power to various components of the mobile terminal 700. The power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the mobile terminal 700.

[0094] Multimedia component 708 includes a screen that provides an output interface between the mobile terminal 700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 708 includes a front-facing camera and / or a rear-facing camera. When the mobile terminal 700 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0095] Audio component 710 is configured to output and / or input audio signals. For example, audio component 710 includes a microphone (MIC) configured to receive external audio signals when mobile terminal 700 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 704 or transmitted via communication component 716. In some embodiments, audio component 710 also includes a speaker for outputting audio signals.

[0096] I / O interface 712 provides an interface between processing component 702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0097] Sensor assembly 714 includes one or more sensors for providing state assessments of various aspects of mobile terminal 700. For example, sensor assembly 714 can detect the on / off state of mobile terminal 700, the relative positioning of components such as the display and keypad of mobile terminal 700, changes in position of mobile terminal 700 or a component of mobile terminal 700, the presence or absence of user contact with mobile terminal 700, orientation or acceleration / deceleration of mobile terminal 700, and temperature changes of mobile terminal 700. Sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 714 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0098] Communication component 716 is configured to facilitate wired or wireless communication between mobile terminal 700 and other devices. Mobile terminal 700 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 716 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 716 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0099] In an exemplary embodiment, the mobile terminal 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0100] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 704 including instructions, which can be executed by a processor 720 of a mobile terminal 700. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0101] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0102] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate; a slot arranged at one edge of the substrate; a plurality of pixel units arranged on the substrate to form a display area; wherein the pixel units at a first sub-edge form a first display area, the pixel units at a second sub-edge form a second display area, and the pixel units below the bottom of the slot form a third display area; wherein the first sub-edge refers to the area where the edge is located at a first side of the slot, and the second sub-edge refers to the area where the edge is located at a second side of the slot; the pixel units in the same row in the first display area share a first gate line; the pixel units in the same row in the second display area share a second gate line; a first gate drive circuit located at the first side of the slot is electrically connected with a plurality of the first gate lines and used for driving the pixel units in the first display area; the array substrate is provided with a first non-display area, and the first gate drive circuit is arranged in the first non-display area; a second gate drive circuit located at the second side of the slot is electrically connected with a plurality of the second gate lines and used for driving the pixel units in the second display area; the array substrate is provided with a second non-display area, and the second gate drive circuit is arranged in the second non-display area; the second non-display area is located between the second display area and the edge of the substrate above the second display area; the plurality of second gate lines pass through the area between the second display area and the slot; the gate lines of the first gate drive circuit and the second gate drive circuit are not arranged in the area between the third display area and the slot.

2. The array substrate of claim 1, wherein, the pixel units in the same row in the third display area share a third gate line; the first gate drive circuit is electrically connected with a plurality of the third gate lines and used for driving the pixel units in the third display area; the first gate drive circuit comprises a first drive unit and a second drive unit; the first drive unit is electrically connected with a plurality of the first gate lines and used for driving the pixel units in the first display area; the second drive unit is electrically connected with a plurality of the third gate lines and used for driving the pixel units in the third display area.

3. The array substrate of claim 1, wherein, The array substrate further comprises at least two clock signal lines; the at least two clock signal lines are arranged at at least one side of the display area.

4. The array substrate of claim 3, wherein, the at least two clock signal lines at the first side of the display area extend to the first non-display area; and / or, the at least two clock signal lines at the second side of the display area extend to the second non-display area.

5. The array substrate of claim 1, wherein, the first drive unit of the first gate drive circuit is arranged in the first non-display area; the first non-display area is located between the first display area and the edge of the substrate above the first display area.

6. A mobile terminal, characterized by The array substrate comprises the array substrate and a preset component according to any one of claims 1-5, and the preset component is arranged in the slot.

7. The mobile terminal of claim 6, wherein, The preset component comprises at least one of a camera, a microphone, a speaker, and a light sensor.

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