Oscillator and control method

Abstract

The present disclosure relates to an oscillator and a control method. The oscillator includes a voltage-controlled oscillator circuit and a processing circuit. The voltage-controlled oscillator circuit generates an oscillation frequency according to a digital signal. When the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency. The processing circuit determines a second signal value of the digital signal according to the first oscillation frequency and a target oscillation frequency, so as to adjust the oscillation frequency to a second oscillation frequency. The processing circuit further interpolates according to a first frequency difference between the target oscillation frequency and the first oscillation frequency and a second frequency difference between the second oscillation frequency and the first oscillation frequency to determine a target signal value of the digital signal, so as to adjust the oscillation frequency to the target oscillation frequency.

Description

Technical Field

[0001] The embodiments described in this disclosure relate to an oscillator, and more particularly to a voltage-controlled oscillator circuit and a method for controlling its oscillation frequency. Background Technology

[0002] The oscillation frequency of an oscillator is determined by the inductance and capacitance values ​​of the resonant tank. Generally, the oscillation frequency can be adjusted by controlling the capacitance value. However, when environmental conditions (e.g., temperature, voltage) change, it takes considerable time to determine the appropriate control signal to set the capacitance value so that the oscillator operates at the desired oscillation frequency. Summary of the Invention

[0003] One embodiment of this disclosure relates to an oscillator. The oscillator includes a voltage-controlled oscillator circuit and a processing circuit. The voltage-controlled oscillator circuit generates an oscillation frequency based on a digital signal. When the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency. The processing circuit determines a second signal value of the digital signal based on the first oscillation frequency and a target oscillation frequency to adjust the oscillation frequency to a second oscillation frequency. The processing circuit further performs an interpolation operation between a first frequency difference and a second frequency difference to determine a target signal value of the digital signal to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency difference is the difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference is the difference between the second oscillation frequency and the first oscillation frequency.

[0004] One embodiment of this disclosure relates to a control method. The control method includes: generating an oscillation frequency of a voltage-controlled oscillator circuit based on a digital signal, wherein when the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency; determining a second signal value of the digital signal based on the first oscillation frequency and a target oscillation frequency to adjust the oscillation frequency to a second oscillation frequency; and performing an interpolation operation based on a first frequency difference and a second frequency difference to determine a target signal value of the digital signal to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency difference is the difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference is the difference between the second oscillation frequency and the first oscillation frequency.

[0005] In summary, through at least one of the above embodiments, the processing circuit can quickly determine the target signal value in order to control the voltage-controlled oscillator circuit to operate at the target oscillation frequency. Attached Figure Description

[0006] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0007] Figure 1 This is a schematic diagram of an oscillator shown according to some embodiments of the present disclosure;

[0008] Figure 2 As shown in some embodiments of this disclosure Figure 1 A schematic diagram of a voltage-controlled oscillator circuit;

[0009] Figure 3 As shown in some embodiments of this disclosure Figure 2 A schematic diagram of a variable capacitor array;

[0010] Figure 4 This is a schematic diagram illustrating the relationship between a first oscillation frequency, a second oscillation frequency, and a target oscillation frequency according to some embodiments of this disclosure; and

[0011] Figure 5 This is a flowchart illustrating a control method according to some embodiments of the present disclosure.

[0012] Symbol Explanation

[0013] 100: Oscillator

[0014] 102: Voltage-controlled oscillator circuit

[0015] 104: Processing Circuit

[0016] 106: Temporary Register

[0017] 202: Variable Capacitor Array

[0018] 500: Control Methods

[0019] S520, S540, S560, S580: Steps

[0020] LUT: Lookup Table

[0021] C VAR 1. C VAR 2. C1, C2, C3, C4, C5, C6, C7: Capacitors

[0022] N1, N2, N3: Nodes

[0023] M1, M2, M3, SW1, SW2, SW3: Switches

[0024] V SW Digital signals

[0025] S SW 1. S SW 2: Signal value

[0026] S SW 3: Target signal value

[0027] S[1], S[2], S[3]: bits

[0028] V TUNE V B Control voltage

[0029] V DD Supply voltage

[0030] F, F1, F2: Oscillation frequency

[0031] F DES Target oscillation frequency

[0032] ΔF1, ΔF2: Frequency difference

[0033] L1: Inductor Detailed Implementation

[0034] The following is a detailed description of embodiments in conjunction with the accompanying drawings. However, the provided embodiments are not intended to limit the scope of this disclosure, and the description of the structural operation is not intended to limit the order of execution. Any structure resulting from the recombination of elements and producing an apparatus with equivalent technical effects is within the scope of this disclosure. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same or similar elements will be designated with the same symbols in the following description.

[0035] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to the cooperation or interaction of two or more components.

[0036] Figure 1 This is a schematic diagram of an oscillator 100 according to some embodiments of the present disclosure. In some embodiments, the oscillator 100 includes a voltage-controlled oscillator circuit 102, a processing circuit 104, and a register 106. The processing circuit 104 is coupled to the voltage-controlled oscillator circuit 102 and the register 106. The processing circuit 104 can provide a digital signal V. SW The voltage-controlled oscillator circuit 102 is supplied. The voltage-controlled oscillator circuit 102 operates based on the digital signal V. SW The corresponding oscillation frequency F is generated. The processing circuit 104 can detect the voltage-controlled oscillator circuit 102 based on the digital signal V. SW The oscillation frequency F during operation. For example, in some embodiments, the processing circuit 104 includes a counter. This counter is used to count based on a signal with an oscillation frequency F generated by the voltage-controlled oscillator circuit 102 to produce different values. In this way, the processing circuit 104 can detect the oscillation frequency F based on this value.

[0037] Register 106 is used to record digital signal V SWThe correspondence between different signal values ​​and the oscillation frequency F is defined. For example, these correspondences can be implemented in the temporary register 106 using a look-up table (LUT). In some embodiments, when the processing circuit 104 detects the oscillation frequency F, the processing circuit 104 can read the digital signal V corresponding to the oscillation frequency F from the look-up table (LUT). SW The signal value. For example, the processing circuit 104 can read the digital signal V from the corresponding address of the lookup table LUT based on the value generated by the counter. SW The signal value. The above-described configuration of the processing circuit 104 and the temporary register 106 is merely an example, and this disclosure is not limited thereto.

[0038] Figure 2 As shown in some embodiments of this disclosure Figure 1 A schematic diagram of a voltage-controlled oscillator circuit 102. In some embodiments, the voltage-controlled oscillator circuit 102 includes a variable capacitor array 202, an inductor L1, and a capacitor C. VAR 1. Capacitor C VAR 2. Switches M1, M2, and M3. Inductor L1 receives the supplied voltage V. DD The variable capacitor array 202 is coupled to the inductor L1 at nodes N1 and N2. The variable capacitor array 202 receives the digital signal V. SW And based on the digital signal V SW Determine the capacitance value of the variable capacitor array 202. Capacitor C VAR 1 is coupled between node N1 and node N3. Capacitor C VAR 2 is coupled between node N3 and node N2. Node N3 receives the control voltage V. TUNE To determine the capacitor C VAR 1 and capacitor C VAR The capacitance value is 2. For example, in some embodiments, the capacitor C VAR 1 and capacitor C VAR 2 can be implemented by a varactor (varactor diode, variable reactor). In some embodiments, the varactor can be implemented by a transistor. In this example, the gate of the transistor used to implement the varactor receives a control voltage V. TUNE Thus, the control voltage V TUNE Change, capacitor C VAR 1 and capacitor C VAR The capacitance value of capacitor C will change accordingly. (The above refers to capacitor C.) VAR 1 and capacitor C VAR The implementation of 2 is merely an example, and this disclosure is not limited to it.

[0039] Switches M1 and M2 are cross-coupled. That is, the control terminal of switch M1 is coupled to one end of switch M2 at node N2, and the control terminal of switch M2 is coupled to one end of switch M1 at node N1. Switch M3 is coupled between switch M1 and ground, and also coupled between switch M2 and ground. Switch M3 receives the control voltage V. B It is also used as a constant current source. In some embodiments, the variable capacitor array 202, inductor L1, and capacitor C VAR 1. Capacitor C VAR 2 is configured as a resonant circuit. Switches M1 to M2 are configured to generate a negative impedance to cancel out the parasitic resistance of this resonant circuit. In this way, the voltage-controlled oscillator circuit 102 can start generating a signal with an oscillation frequency F.

[0040] In some embodiments, the oscillation frequency F of the voltage-controlled oscillator circuit 102 can be obtained by the following formula (1):

[0041]

[0042] Where C is the variable capacitor array 202, and capacitor C is... VAR 1 and capacitor C VAR The equivalent capacitance of 2, and L is the inductance of inductor L1.

[0043] As previously stated, the capacitance value of the variable capacitor array 202 is based on the digital signal V. SW The value of the variable capacitor array 202 changes, and C in formula (1) changes accordingly, thereby changing the oscillation frequency F of the voltage-controlled oscillator circuit 102. In other words, the oscillation frequency F of the voltage-controlled oscillator circuit 102 can be determined by the digital signal V. SW And thus changed.

[0044] The voltage-controlled oscillator circuit 102 described above is for illustrative purposes only, and other various configurations of the voltage-controlled oscillator circuit 102 are also within the scope of this disclosure.

[0045] Figure 3 As shown in some embodiments of this disclosure Figure 2 A schematic diagram of a variable capacitor array 202. In some embodiments, the variable capacitor array 202 is an N-bit variable capacitor array. N is a positive integer. The nth bit of the variable capacitor array 202 corresponds to 2. (n-1) There are N capacitors. n is a positive integer and is less than or equal to N.

[0046] In some embodiments, the digital signal V SW The signal value consists of multiple bits, each corresponding to an N-bit variable capacitor array. Figure 3 For example, digital signal V SWThe first bit S[1] of the signal value corresponds to capacitor C1. Digital signal V SW The second bit S[2] of the signal value corresponds to capacitors C2 to C3. Digital signal V SW The third bit S[3] of the signal value corresponds to capacitors C4 to C7.

[0047] Specifically, capacitor C1 and switch SW1 are connected in series between nodes N1 and N2, where switch SW1 is controlled by digital signal V. SW The first bit S[1] of the signal value is controlled. Capacitor C2 and capacitor C3 are connected in parallel, and capacitors C2 to C3 are connected in series with switch SW2 between nodes N1 and N2, wherein switch SW2 is controlled by digital signal V SW The second bit S[2] of the signal value is controlled. Capacitors C4 to C7 are connected in parallel, and capacitors C4 to C7 and switch SW3 are connected in series between nodes N1 and N2, wherein switch SW3 is controlled by digital signal V SW The third bit S[3] of the signal value controls the signal. Similarly, the N-bit variable capacitor array and the digital signal V can be deduced. SW The settings between them.

[0048] With the above configuration, the capacitance value of the variable capacitor array 202 can be adjusted by the digital signal V. SW And change. When the capacitance value of the variable capacitor array 202 changes, the variable capacitor array 202 and capacitor C... VAR 1 and capacitor C VAR The equivalent capacitance value of 2 will change accordingly. Based on the above formula (1), when the equivalent capacitance value changes, the oscillation frequency F of the voltage-controlled oscillator circuit 102 will change accordingly. The above variable capacitor array 202 is only an example, and other various configurations of the variable capacitor array 202 are also within the scope of this disclosure.

[0049] Figure 4 The oscillation frequencies F1, F2, and F1, and the target oscillation frequency F2 are shown in some embodiments of this disclosure. DES A diagram illustrating the relationship. Figure 5 This is a flowchart illustrating a control method 500 according to some embodiments of this disclosure. Please refer to the following as well. Figures 1 to 5 .

[0050] In step S520, the processing circuit 104 detects the signal value S of the voltage-controlled oscillator circuit 102 based on the digital signal Vsw. SW 1. The oscillation frequency F1 during operation. In some embodiments, when the oscillator 100 is powered on, the voltage-controlled oscillator circuit 102 determines the oscillation frequency based on the signal value S of the digital signal Vsw. SW1. Generate an initial oscillation frequency (e.g., oscillation frequency F1). In some embodiments, the processing circuit 104 reads the digital signal V corresponding to the oscillation frequency F1 from the lookup table LUT in the temporary register 106. SW signal value S SW 1.

[0051] In step S540, the processing circuit 104 determines the oscillation frequency F1 and the target oscillation frequency F based on the oscillation frequency F1. DES digital signal V SW From signal value S SW 1. Adjust to signal value S SW 2. In some embodiments, the processing circuit 104 includes a frequency detector for comparing the oscillation frequency F1 with the target oscillation frequency FDES. When the oscillation frequency F1 matches the target oscillation frequency F... DES When they are different, the processing circuit 104 will process the signal value S according to a preset value M. SW 1. Adjust to signal value S SW 2.

[0052] For example, when the oscillation frequency F1 is less than the target oscillation frequency F DES At that time, the processing circuit 104 generates a signal value S. SW 2. This reduces the capacitance value of the variable capacitor array 202. In this way, the oscillation frequency F1 can be increased to a higher oscillation frequency. Alternatively, when the oscillation frequency F1 is greater than the target oscillation frequency F... DES At that time, the processing circuit 104 generates a signal value S. SW 2. This increases the capacitance value of the variable capacitor array 202. This reduces the oscillation frequency F1.

[0053] If the switches SW1 to SW3 of the variable capacitor array 202 are implemented using N-type transistors, when the oscillation frequency F1 is less than (greater than) the target oscillation frequency F DES At that time, the processing circuit 104 will process the signal value S SW 1 is subtracted from (or added to) a preset value M to generate a signal value S. SW 2. Assume the signal value S SW 1 is 111 (that is, S[3] = 1, S[2] = 1, S[1] = 1). In this case, switches SW1 to SW3 are all turned on. At this time, capacitors C1 to C7 are connected in series. The capacitance value of the variable capacitor array 202 is actually equal to the sum of the capacitance values ​​of capacitors C1 to C7. If the oscillation frequency F1 is less than the target oscillation frequency F DES (like Figure 4 As shown), the processing circuit 104 processes the digital signal V SW 1 minus a preset value M (e.g., M = 6, corresponding to 110 bits) to generate the signal value S. SW2 is 001. In this case, switch SW1 is turned on, but switches SW2 and SW3 are turned off. At this time, the capacitance value of the variable capacitor array 202 is essentially equal to the capacitance value of capacitor C1. In other words, the capacitance value of the variable capacitor array 202 is reduced to increase the oscillation frequency F1 to the oscillation frequency F2.

[0054] Alternatively, in other examples, if the switches SW1 to SW3 of the variable capacitor array 202 are implemented using P-type transistors, when the oscillation frequency F1 is less than (greater than) the target oscillation frequency F... DES At that time, the processing circuit 104 will process the digital signal V SW 1 is added to (or subtracted from) a preset value M to generate a digital signal V. SW 2. The operation here can be inferred from the corresponding paragraphs above, so it will not be explained again.

[0055] In some embodiments, the capacitance values ​​of capacitors C1 to C7 are the same or partially the same. In some embodiments, the preset value M can be adjusted according to the capacitance values ​​of capacitors C1 to C7. For example, when the capacitance values ​​of capacitors C1 to C7 are the same and the larger the capacitance value, the smaller the preset value M can be set. In some embodiments, the preset value M can also be determined according to the linearity requirements of oscillator 100. By taking into account the linearity requirements of the oscillator, a more accurate oscillation frequency F2 can be obtained, thereby improving the accuracy of the interpolation operation mentioned later.

[0056] In step S560, the processing circuit 104 detects the signal value S of the voltage-controlled oscillator circuit 102 based on the digital signal Vsw. SW 2. The oscillation frequency F2 during operation. In some embodiments, when the digital signal V... SW The signal value is determined by S SW 1 adjusted to S SW After 2, the variable capacitor array 202 is based on the digital signal V SW signal value S SW 2. An oscillation frequency F2 is generated. The counter of the processing circuit 104 can detect the oscillation frequency F2 generated by the variable capacitor array 202.

[0057] In step S580, the processing circuit 104 performs interpolation based on the frequency difference ΔF2 and the frequency difference ΔF1 to determine the frequency F corresponding to the target oscillation frequency. DES A target signal value S SW 3.

[0058] In some embodiments, the processing circuit 104 calculates the difference between the oscillation frequency F2 and the oscillation frequency F1 to determine the frequency difference ΔF1, and calculates the target oscillation frequency F DES The difference between the frequency F1 and the oscillation frequency F1 determines the frequency difference ΔF2. For example... Figure 3 As shown, in some embodiments, the processing circuit 104 can perform interpolation based on the frequency difference ΔF1 and the frequency difference ΔF2 to efficiently determine the target oscillation frequency F. DES The corresponding target signal value S SW 3.

[0059] For example, the processing circuit 104 can calculate the target adjustment value P based on the frequency difference ΔF1, the frequency difference ΔF2, and the aforementioned preset value M. In some embodiments, the target adjustment value P can be obtained by the following formula (2):

[0060]

[0061] Based on the above formula (2), the processing circuit 104 calculates the digital signal V according to the ratio between the frequency difference ΔF2 and the frequency difference ΔF1 and the preset value M. SW The signal value needs to be adjusted by a certain amount (i.e., the target adjustment value P). Next, the processing circuit 104 determines the target adjustment value P and the signal value S. SW 1. Generate target signal value S SW 3. In some embodiments, the target signal value S SW 3 can be obtained from the following formula (3):

[0062] S SW 3 = S SW 1+PΛ (3)

[0063] For example, if the signal value SSW1 is 001 and P is 3 (its corresponding bit is 011), the target signal value S SW 3 is 100. Accordingly, the processing circuit 104 transmits a signal with the target signal value S. SW 3 digital signal V SW The variable capacitor array 202 is configured to determine the states (e.g., on or off) of the switches within it. By determining the states of these switches, the capacitance value of the variable capacitor array 202 can be adjusted. Thus, the variable capacitor array 202 and the capacitor C... VAR 1 and capacitor C VAR The equivalent capacitance value of 2 can be adjusted to be substantially equal to the target capacitance value. Accordingly, this target capacitance value and the inductance value L of inductor L1 can make the oscillation frequency of the voltage-controlled oscillator circuit 102 the target oscillation frequency F. DES .

[0064] In other words, by using the above equations (2) to (3), after obtaining the two oscillation frequencies F1 and F2, the processing circuit 104 can quickly interpolate the target signal value S based on these oscillation frequencies F1 and F2 and their corresponding signal values ​​Ssw1 and Ssw2. SW3. In some related technologies, when environmental conditions (such as operating temperature, voltage, etc.) change, the lookup table needs to be rebuilt. This will consume a lot of time. Compared with the above-mentioned related technologies, the processing circuit 104 can quickly determine the target signal value S. SW 3. In some embodiments, the control method 500 may be repeated multiple times to increase the target signal value S. SW The accuracy of 3.

[0065] The steps of the control method 500 described above are merely examples and are not intended to be performed in the order shown in this example. Without departing from the operational methods and scope of the embodiments of this disclosure, various operations in the control method 500 may be appropriately added, replaced, omitted, or performed in a different order.

[0066] In summary, through at least one of the above embodiments, the processing circuit can quickly determine the target signal value in order to control the voltage-controlled oscillator circuit to operate at the target oscillation frequency.

[0067] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various changes and modifications without departing from the concept and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the claims.

Claims

1. An oscillator comprising: A voltage-controlled oscillator circuit is used to generate an oscillation frequency based on a digital signal, wherein when the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency; and A processing circuit is configured to determine a second signal value of the digital signal based on a first oscillation frequency and a target oscillation frequency, thereby adjusting the oscillation frequency to a second oscillation frequency. When the first oscillation frequency differs from the target oscillation frequency, the processing circuit subtracts a preset value from the first signal value or adds the preset value to the first signal value to generate the second signal value, and adjusts the digital signal from the first signal value to the second signal value. The processing circuit further performs an interpolation operation based on a first frequency difference and a second frequency difference to determine a target signal value for the digital signal, thereby adjusting the oscillation frequency to the target oscillation frequency. The first frequency difference is the difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference is the difference between the second oscillation frequency and the first oscillation frequency.

2. The oscillator of claim 1, wherein the voltage-controlled oscillator circuit includes a variable capacitor array for receiving the digital signal, and a capacitance value of the variable capacitor array is determined according to the digital signal.

3. The oscillator of claim 2, wherein the processing circuit is further configured to compare the first oscillation frequency and the target oscillation frequency to adjust the digital signal.

4. The oscillator of claim 2, wherein when the first oscillation frequency is less than the target oscillation frequency, a capacitance value of the variable capacitor array is reduced according to the second signal value, and when the first oscillation frequency is greater than the target oscillation frequency, the capacitance value of the variable capacitor array is increased according to the second signal value.

5. The oscillator of claim 1, wherein when the first oscillation frequency is less than the target oscillation frequency, the processing circuit subtracts the preset value from the first signal value to generate the second signal value, and when the first oscillation frequency is greater than the target oscillation frequency, the processing circuit adds the preset value to the first signal value to generate the second signal value.

6. The oscillator of claim 1, wherein the processing circuit is further configured to determine a target adjustment value based on a product of a ratio between the first frequency difference and the second frequency difference and the preset value, and to add the first signal value to the target adjustment value to generate the target signal value.

7. The oscillator of claim 1, further comprising: A register is used to store a lookup table, wherein the processing circuit is also used to read the first signal value of the digital signal from the lookup table according to the first oscillation frequency.

8. A control method, comprising: An oscillation frequency of a voltage-controlled oscillator circuit is generated based on a digital signal, wherein when the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency; A second signal value of the digital signal is determined based on the first oscillation frequency and a target oscillation frequency to adjust the oscillation frequency to a second oscillation frequency, wherein determining the second signal value of the digital signal includes: When the first oscillation frequency differs from the target oscillation frequency, a preset value is subtracted from the first signal value or the preset value is added to the first signal value to generate the second signal value; and An interpolation operation is performed based on a first frequency difference and a second frequency difference to determine a target signal value of the digital signal, so as to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency difference is the difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference is the difference between the second oscillation frequency and the first oscillation frequency.

9. The control method of claim 8, wherein adjusting the digital signal comprises: A target adjustment value is determined based on a ratio between the first frequency difference and the second frequency difference, and the preset value; The first signal value is added to the target adjustment value to generate the target signal value; and Adjust the digital signal to the target signal value to adjust the oscillation frequency to the target oscillation frequency.

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