A dual-loop phase-locked loop analog core circuit and phase-locked loop applied to FPGA

Abstract

The present invention relates to a dual-loop phase-locked loop analog core circuit applied to FPGA, characterized in that it includes: a low-pass filter for integrating and filtering a current signal to obtain a voltage signal, wherein the voltage signal includes a fine-tuning voltage signal and a coarse-tuning voltage signal; a voltage-controlled oscillator, wherein the low-pass filter is connected to the voltage-controlled oscillator through a fine-tuning loop and a coarse-tuning loop, and is used to adjust the gain of the voltage-controlled oscillator, and perform frequency modulation processing on the fine-tuning voltage signal and the coarse-tuning voltage signal to obtain a first clock signal. The phase-locked loop analog core circuit of the embodiment of the present invention realizes a dual-loop phase-locked loop structure by nesting low-pass filters without adding additional charge pumps and filters, which not only meets the requirements of locking time and operating frequency range, but also can significantly reduce output clock jitter, while saving power consumption and chip area.

Description

Technical Field

[0001] The present invention relates to the technical field of programmable logic units, and in particular to a dual-loop phase-locked loop analog core circuit and a phase-locked loop applied to FPGA. Background Art

[0002] Field-Programmable Gate Array (FPGA) is a semi-customized circuit chip with abundant on-chip resources for development and flexible and convenient design. It not only solves the problem that customized circuits cannot be upgraded, but also overcomes the disadvantage of the limited number of gate circuits of traditional programmable devices. With the rise of artificial intelligence, higher requirements are placed on the amount of data calculation and the speed of calculation. This has also led to FPGA (Field-Programmable Gate Array) playing an increasingly important role in the field of accelerated computing. Many applications and services can significantly improve computing speed and efficiency with the support provided by FPGA.

[0003] As the integration of FPGAs continues to increase, high-quality on-chip clocks are becoming more and more important. Many FPGAs have built-in PLL (phase-locked loop) units for various clock management functions, such as clock injection removal, clock phase adjustment, clock timing adjustment, and frequency synthesis.

[0004] However, the existing PLL used in FPGA chips needs to meet the various performance indicators of a unified architecture under multiple protocols, which poses a severe challenge to the PLL analog core architecture. It is required to meet the requirements of fast locking, large frequency coverage and low output jitter, while reducing the power consumption and area of ​​the chip. Therefore, it is extremely urgent to design a PLL analog core architecture that meets the FPGA internal clock performance. Summary of the invention

[0005] Therefore, in order to solve the technical defects and shortcomings of the prior art, the present invention proposes a dual-loop phase-locked loop analog core circuit and a phase-locked loop applied to FPGA.

[0006] Specifically, an embodiment of the present invention provides a dual-loop phase-locked loop analog core circuit applied to an FPGA, comprising:

[0007] A low-pass filter is used to integrate and filter the current signal to obtain a voltage signal, wherein the voltage signal includes a fine-tuning voltage signal and a coarse-tuning voltage signal;

[0008] A voltage-controlled oscillator, wherein the low-pass filter is connected to the voltage-controlled oscillator via a fine-tuning loop and a coarse-tuning loop, and is used to adjust the gain of the voltage-controlled oscillator, and to perform frequency modulation processing on the fine-tuning voltage signal and the coarse-tuning voltage signal to obtain a first clock signal.

[0009] In one embodiment of the present invention, the low-pass filter comprises:

[0010] The resistor and capacitor module is used to integrate and filter the current signal to obtain a fine-tuning voltage signal and a feedback voltage signal;

[0011] The transconductance capacitor module is used to receive a reference voltage signal and the feedback voltage signal, and obtain the coarse adjustment voltage signal according to the feedback voltage signal and the reference voltage signal.

[0012] In one embodiment of the present invention, the resistor and capacitor module includes a capacitor C1, a capacitor C2 and a resistor R, wherein one end of the capacitor C1 is connected to the fine-tuning loop, the other end of the capacitor C1 is connected to the ground, and the capacitor C2 and the resistor R are connected in series between the fine-tuning loop and the ground in sequence.

[0013] In one embodiment of the present invention, the transconductance capacitor module includes a transconductance operational amplifier and a capacitor C3, wherein a first input terminal of the transconductance operational amplifier is connected between the resistor R and the capacitor C2, a second input terminal of the transconductance operational amplifier is connected to a reference voltage signal terminal, an output terminal of the transconductance operational amplifier is connected to the coarse adjustment loop, one end of the capacitor C3 is connected to the output terminal of the transconductance operational amplifier, and the other end of the capacitor C3 is connected to the ground terminal.

[0014] In one embodiment of the present invention, it also includes:

[0015] A phase adjustment unit is connected to the voltage-controlled oscillator and is used to perform phase adjustment on the first clock signal to obtain a second clock signal.

[0016] In one embodiment of the present invention, the phase adjustment unit includes a selector connected to the voltage-controlled oscillator, configured to obtain a first phase, and perform phase adjustment on the first clock signal according to the first phase to obtain a second clock signal.

[0017] In one embodiment of the present invention, the phase adjustment unit also includes a phase conversion module, which is connected to the selector, used to obtain a second phase, and transmit the second phase to the selector, so as to phase adjust the first clock signal through the first phase and the second phase to obtain a second clock signal.

[0018] In one embodiment of the present invention, it also includes:

[0019] A charge pump is connected to the low-pass filter and is used to obtain the signal difference and convert the signal difference into a current signal.

[0020] In one embodiment of the present invention, it also includes:

[0021] The phase frequency detector is connected to the charge pump and is used to obtain a reference clock signal and a feedback clock signal and detect a signal difference between the reference clock signal and the feedback clock signal.

[0022] An embodiment of the present invention further provides a phase-locked loop, comprising the dual-loop phase-locked loop analog core circuit described in any one of the above embodiments.

[0023] The embodiments of the present invention have the following beneficial effects:

[0024] The phase-locked loop analog core circuit of the embodiment of the present invention realizes a dual-loop phase-locked loop structure by nesting low-pass filters without adding additional charge pumps and filters. It not only meets the requirements of locking time and operating frequency range, but also can significantly reduce output clock jitter, while saving power consumption and chip area.

[0025] Other aspects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. It should be understood, however, that the drawings are designed for illustrative purposes only and are not intended to limit the scope of the present invention, as reference should be made to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale and are intended merely to conceptually illustrate the structures and processes described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The specific implementation modes of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figure 1 A schematic diagram of the structure of a phase-locked loop analog core circuit provided by an embodiment of the present invention;

[0028] Figure 2 A schematic diagram of the structure of another phase-locked loop analog core circuit provided by an embodiment of the present invention;

[0029] Figure 3 A schematic diagram of the structure of a low-pass filter provided by an embodiment of the present invention;

[0030] Figure 4 A schematic diagram of the structure of a phase adjustment unit provided in an embodiment of the present invention;

[0031] Figure 5 A schematic diagram of the structure of another phase adjustment unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] See also Figure 1 , Figure 1 A schematic diagram of the structure of a phase-locked loop analog core circuit provided by an embodiment of the present invention. An embodiment of the present invention provides a dual-loop phase-locked loop analog core circuit applied to FPGA, the phase-locked loop comprising: a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a phase adjustment unit (Phase Adjust), wherein the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator, and the phase adjustment unit are connected in sequence.

[0034] Specifically, the phase frequency detector is connected to the charge pump, and is used to obtain a reference clock signal and a feedback clock signal, and detect a signal difference between the reference clock signal and the feedback clock signal.

[0035] Furthermore, the reference clock (refclk) and the feedback clock (fbclk) are transmitted to the phase frequency detector through the input end of the phase frequency detector, and the phase frequency detector detects the signal difference between the reference clock and the feedback clock, and transmits the signal difference to the charge pump. The signal difference is the phase difference between the reference clock and the feedback clock. The reference clock serves as a reference signal of the feedback clock, so that the feedback clock is adjusted according to the reference clock so that the phase-locked loop can output the required clock signal.

[0036] Specifically, the charge pump is connected to the phase frequency detector to obtain the signal difference and convert the signal difference into a current signal (Icp_out).

[0037] Furthermore, the phase frequency detector transmits the signal difference to the charge pump, so that the charge pump converts the signal difference into a current signal and transmits the current signal to the low-pass filter.

[0038] Specifically, a low-pass filter is connected to the charge pump and is used to integrate and filter the current signal to obtain a voltage signal, wherein the voltage signal includes a fine-tuning voltage signal (vhf) and a coarse-tuning voltage signal (vlf);

[0039] Furthermore, the low-pass filter is used to integrate and filter the current signal to form a voltage signal through integration and filtering. The voltage signal includes a coarse-adjustment voltage signal and a fine-adjustment voltage signal.

[0040] See also Figure 2The low-pass filter includes a resistor and capacitor module (RC) and a transconductor and capacitor module (GMC), wherein the input end of the resistor and capacitor module is connected to the output end of the charge pump, the output end of the resistor and capacitor module is connected to the voltage-controlled oscillator through a fine-tuning loop, the input end of the transconductor and capacitor module is connected to the resistor and capacitor module and the reference signal end, and the output end of the transconductor and capacitor module is connected to the voltage-controlled oscillator through a coarse-tuning loop, wherein,

[0041] The resistor and capacitor module is used to filter the current signal to obtain a fine-tuning voltage signal and a feedback voltage signal (vcf), wherein the resistor and capacitor module is a passive resistor and capacitor filter;

[0042] The transconductance capacitor module is used to receive a reference voltage signal and a feedback voltage signal, and obtain the coarse adjustment voltage signal according to the feedback voltage signal and the reference voltage signal.

[0043] See also Figure 3 The resistor and capacitor module includes a capacitor C1, a capacitor C2 and a resistor R, wherein one end of the capacitor C1 is connected to the fine adjustment loop, the other end of the capacitor C1 is connected to the ground, and the capacitor C2 and the resistor R are connected in series between the fine adjustment loop and the ground. The transconductance and capacitance module includes a transconductance operational amplifier (GM) and a capacitor C3, wherein a first input end of the transconductance operational amplifier is connected between the resistor R and the capacitor C2, a second input end of the transconductance operational amplifier is connected to the reference voltage signal end, an output end of the transconductance operational amplifier is connected to the coarse adjustment loop, one end of the capacitor C3 is connected to the output end of the transconductance operational amplifier, and the other end of the capacitor C3 is connected to the ground.

[0044] First, the frequency detector compares the reference clock and the feedback clock, and converts the difference between the reference clock and the feedback clock into a current form (Icp_out) that can be recognized by the low-pass filter through the charge pump. The current signal is integrated and filtered by the low-pass filter, and the current signal is converted into a fine-tuning voltage signal and a feedback voltage signal through the resistor and capacitor module of the low-pass filter. The fine-tuning voltage signal is used as the fine-tuning voltage to control the fine-tuning loop; the feedback voltage signal is fed back to the charge pump on the one hand, and on the other hand, the feedback voltage signal is passed through the transconductor capacitor module to generate a coarse-tuning voltage to control the coarse-tuning loop. The fine-tuning voltage signal and the coarse-tuning voltage signal act together on the voltage-controlled oscillator to control the voltage-controlled oscillator to generate the required clock frequency. The coarse-tuning loop passes through PFD, CP, LPF, VCO and divider, where the low-pass filter provides two zero poles and one non-zero pole (the transconductance capacitor module provides a pole very close to the origin, which can be approximated as a zero pole. The transconductance capacitor module also provides some zero poles that are much larger than the bandwidth and can be ignored. So approximately speaking, the low-pass filter corresponding to the coarse-tuning loop provides two zero poles and one non-zero pole), providing a narrow bandwidth. The voltage-controlled oscillator provides high gain through the coarse-tuning loop. The narrow bandwidth provided by the low-pass filter and the voltage-controlled oscillator provide The high gain works together to determine the central frequency of the phase-locked loop (i.e. the frequency of the phase-locked loop), expanding the coverage of the phase-locked loop operating frequency; the fine-tuning loop of the phase-locked loop passes through the RC, VCO and divider in the PFD, CP and LPF, where the resistor and capacitor module in the low-pass filter provides two poles (one zero pole and one non-zero pole), one zero point, and provides a wide bandwidth. The voltage-controlled oscillator provides low gain through the fine-tuning loop. The wide bandwidth provided by the low-pass filter and the low gain provided by the voltage-controlled oscillator work together to speed up the locking time and reduce the output clock jitter. The phase-locked loop analog core circuit module is connected to the divider to form a feedback system, which will not lock the phase-locked loop until the reference clock and the feedback clock are in phase or differ by a fixed value.

[0045] The circuit uses a nested connection of low-pass filters so that the coarse adjustment loop and the fine adjustment loop share a charge pump and a low-pass filter, thereby improving the circuit's reusability. On the one hand, the use of a charge pump reduces power consumption. On the other hand, for passive resistor and capacitor filters, the reuse of low-pass filters greatly reduces the chip area, which is beneficial to system integration. Compared with the traditional low-pass filter, a transconductor capacitor module is added, one input end of the transconductor capacitor module is connected to the feedback voltage signal, and the other input end is connected to the reference voltage signal. The reference voltage signal is generated by Vref_gen (reference voltage generation circuit), and the value of the reference voltage signal is approximately half of the power supply voltage (1 / 2*vdd). At the same time, in order to compensate for the deviation at different temperatures in different processes, the reference voltage signal can be configured to different voltage values ​​according to the control signal of the internal programmable logic unit. The voltage value is plus or minus 20% of 1 / 2*vdd. Taking the power supply voltage of 1V as an example, the reference voltage signal can be configured to 0.4V, 0.45V, 0.5V, 0.55V or 0.6 through the configuration bit. In addition to the dual-loop architecture, in order to further improve the clock performance of the phase-locked loop output, a transconductance operational amplifier is also used to force the feedback voltage signal to approach Vref (1 / 2*vdd). On the one hand, the feedback voltage signal is fed back to the charge pump input, reducing the charging and discharging problem of the parasitic capacitance from the charge pump current source to the substrate, thereby eliminating charge shunting, reducing the charge matching error of the charge pump, and reducing the jitter of the phase-locked loop. On the other hand, due to the feedback effect of the phase-locked loop, the fine-tuning voltage signal will eventually approach the feedback voltage signal, and the feedback voltage signal will approach the reference voltage signal (1 / 2*vdd). This makes the gain of the fine-tuning loop work within a range with good linearity regardless of the frequency at which the phase-locked loop works, further improving the phase-locked loop's ability to suppress jitter. At the same time, the isolation effect of the transconductance capacitor module isolates the coarse-tuning loop and the fine-tuning loop well, so that they do not affect each other under different protocols and working conditions.

[0046] The low-pass filter is connected to the voltage-controlled oscillator through a fine tuning loop and a coarse tuning loop, the fine tuning loop is used to transmit the fine tuning voltage to the voltage-controlled oscillator, and the coarse tuning loop is used to transmit the coarse tuning voltage signal to the voltage-controlled oscillator. The low-pass filter includes two output terminals, namely a first output terminal and a second output terminal, and the voltage-controlled oscillator includes two input terminals, namely a first input terminal and a second input terminal, the first output terminal of the low-pass filter is connected to the first input terminal of the voltage-controlled oscillator through a coarse tuning loop (coarse_tune), the first output terminal of the low-pass filter outputs the coarse tuning voltage signal to the voltage-controlled oscillator through the coarse tuning loop, the second output terminal of the low-pass filter is connected to the second input terminal of the voltage-controlled oscillator through a fine tuning loop (fine_tune), and the second output terminal of the low-pass filter outputs the fine tuning voltage signal to the voltage-controlled oscillator through the fine tuning loop. Among them, the gain of the voltage-controlled oscillator of the coarse adjustment loop is much larger than the gain of the voltage-controlled oscillator of the fine adjustment loop. For example, the gain of the voltage-controlled oscillator of the coarse adjustment loop is 5 times or 10 times the gain of the voltage-controlled oscillator of the fine adjustment loop. The size of the coarse adjustment gain and the fine adjustment gain can be set according to the specific needs of the user, and this embodiment does not impose any specific restrictions on it.

[0047] Specifically, the voltage-controlled oscillator, the low-pass filter is connected to the voltage-controlled oscillator through a fine-tuning loop and a coarse-tuning loop, for adjusting the gain of the voltage-controlled oscillator, and performing frequency modulation processing on the fine-tuning voltage signal and the coarse-tuning voltage signal to obtain a first clock signal.

[0048] Furthermore, the voltage controlled oscillator is used to perform frequency modulation processing on the voltage signal to obtain the first clock signal. The voltage controlled oscillator may include i outputs, where i is an integer greater than or equal to 1, and i is an even number.

[0049] The coarse-tuning voltage signal is transmitted to the voltage-controlled oscillator through the coarse-tuning loop, which can provide a larger gain and a lower bandwidth for the phase-locked loop, and can quickly determine the center frequency of the voltage-controlled oscillator and expand the frequency coverage of the phase-locked loop. The fine-tuning voltage signal is transmitted to the voltage-controlled oscillator through the fine-tuning loop, and can provide a smaller gain and a higher bandwidth for the phase-locked loop. The fine-tuning loop plays a decisive role in the bandwidth of the phase-locked loop device, and can reduce the jitter of the phase-locked loop device and speed up the locking time.

[0050] Specifically, the phase adjustment unit is connected to the voltage-controlled oscillator and is used to perform phase adjustment on the first clock signal to obtain the second clock signal.

[0051] Further, it is used to perform phase adjustment on the first clock signal to obtain the second clock signal. The phase adjustment unit may include j outputs, wherein j is an integer greater than or equal to 1, and j is greater than or equal to the number of output paths of the entire phase-locked loop device.

[0052] The phase adjustment unit includes two phase adjustment modes. The first mode is to adjust the phase of the first clock signal through a selector, and the second mode is to adjust the phase through a selector and a phase conversion module (phase shift).

[0053] For the first phase adjustment method, see Figure 4 The phase adjustment unit includes a selector, a first input end of the selector is connected to the output end of the voltage-controlled oscillator, and a second input end of the selector is connected to the static configuration bit SDX<2:0> (taking four-way output as an example, X is A / B / C / D). The phase adjustment unit is used to obtain a first phase, and adjust the phase of the first clock signal according to the first phase to obtain a second clock signal. The first phase adjustment method belongs to a static configuration.

[0054] The first phase is a configuration bit set by the user according to the needs, that is, the phase size of the clock signal output by the phase-locked loop. The selector selects the phase size to be output according to the needs of the configuration bit. For example, if the phase size required by the configuration bit is 45, the selector will force the first clock signal output by the VCO to be adjusted to the second clock signal with a phase of 45 for output. The common phase-locked loop used in FPGA can usually adjust this phase relationship in steps of 45 degrees.

[0055] For example, see Figure 5 In this embodiment, the output channels of the phase-locked loop device are 4 channels, the selector is an 8-to-1 selector (8mux1), the selectable phases of the 8-to-1 selector are 0, 45, 90, 135, 180, 225, 270, 315, and i=8, j=4 are used as an example for explanation, wherein SDA<2:0>, SDB<2:0>, SDC<2:0>, and SDD<2:0> are configuration bits corresponding to the 4 output channels respectively. If the phase of a certain output channel is determined, the selector directly selects the required output phase according to the configuration bit. For example, SDA<2:0> corresponds to the configuration bit of the first output channel, and the first output channel requires the 8-to-1 selector to select the fourth phase (i.e., 135), then the configuration bit of SDA<2:0> can be set to 011, and the adjusted phase is: SDA<2:0> / 8*360.

[0056] For the second phase adjustment method, see Figure 5 The phase adjustment unit also includes a phase conversion module, the output end of the phase conversion module is connected to the third input end of the selector, the phase conversion module is used to obtain the second phase and transmit the second phase to the selector to adjust the phase of the first clock signal through the first phase and the second phase to obtain the second clock signal.

[0057] The input end of the phase conversion module is connected to the first output end of the phase control module, wherein the phase control module can receive a signal that needs to be phase adjusted during system operation, and control the corresponding part to perform dynamic phase adjustment through the signal. For example, when the first clock signal needs to be dynamically adjusted, the phase control module controls the phase conversion module to output the phase size that needs to be dynamically adjusted, that is, the phase conversion module obtains the second phase that needs to be dynamically adjusted according to the phase control module, and the phase conversion module transmits the second phase to the selector. The selector adds the phase size corresponding to the second phase to the initial first phase, which is the phase of the second clock signal. For example, the phase size corresponding to the first phase SDA<2:0> is 135, that is, SDA<2:0> is 011, and the phase size corresponding to the second phase PHA<2:0> is 135, that is, PHA<2:0> is 011, then the phase of the second clock signal is 270, and the phase adjustment step size is: (SDA<2:0>+PHA<2:0>) / 8*360.

[0058] It should be known that the dynamic control bit signal (DYNMAICCONTROL) for controlling the phase control module may come from an internal programmable logic module or an external dynamic control interface.

[0059] In order to balance the locking time, output jitter, and stability of the phase-locked loop device in different application situations, the embodiment of the present invention can dynamically or statically configure the bandwidth of the low-pass filter, the current of the charge pump, and the gain of the voltage-controlled oscillator of the phase-locked loop device through the configuration bits of the FPGA, wherein the configuration bits are the numerical values ​​required for each part, such as the bandwidth of the low-pass filter.

[0060] The phase-locked loop analog core circuit of the embodiment of the present invention adds a phase adjustment unit, which can be dynamically or statically configured according to different application environments of the FPGA chip to meet the application requirements of output clocks with different frequencies and different phases.

[0061] The phase-locked loop analog core circuit of the embodiment of the present invention realizes a dual-loop phase-locked loop structure by nesting low-pass filters without adding additional charge pumps and filters. It not only meets the requirements of locking time and operating frequency range, but also can significantly reduce output clock jitter, while saving power consumption and chip area.

[0062] An embodiment of the present invention further provides a phase-locked loop, which is configured with the above-mentioned phase-locked loop analog core circuit.

[0063] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A dual-loop phase-locked loop analog core circuit applied to FPGA, characterized in that: include: A low-pass filter is used to integrate and filter the current signal to obtain a voltage signal, wherein the voltage signal includes a fine-tuning voltage signal and a coarse-tuning voltage signal; Wherein, the low-pass filter comprises: The resistor and capacitor module is used to integrate and filter the current signal to obtain a fine-tuning voltage signal and a feedback voltage signal; A transconductance capacitor module, used for receiving a reference voltage signal and the feedback voltage signal, and obtaining the coarse adjustment voltage signal according to the feedback voltage signal and the reference voltage signal; The low-pass filter is also used to send the feedback voltage signal to the charge pump to eliminate the charge shunting phenomenon in the charge pump; A voltage-controlled oscillator, wherein the low-pass filter is connected to the voltage-controlled oscillator via a fine-tuning loop and a coarse-tuning loop, and is used to adjust the gain of the voltage-controlled oscillator, and to perform frequency modulation processing on the fine-tuning voltage signal and the coarse-tuning voltage signal to obtain a first clock signal.

2. The analog core circuit according to claim 1, characterized in that: The resistor and capacitor module includes a capacitor C1, a capacitor C2 and a resistor R, wherein one end of the capacitor C1 is connected to the fine-tuning loop, the other end of the capacitor C1 is connected to the ground, and the capacitor C2 and the resistor R are connected in series between the fine-tuning loop and the ground.

3. The analog core circuit according to claim 2, characterized in that: The transconductance capacitor module includes a transconductance operational amplifier and a capacitor C3, wherein a first input terminal of the transconductance operational amplifier is connected between the resistor R and the capacitor C2, a second input terminal of the transconductance operational amplifier is connected to a reference voltage signal terminal, an output terminal of the transconductance operational amplifier is connected to the coarse adjustment loop, one end of the capacitor C3 is connected to the output terminal of the transconductance operational amplifier, and the other end of the capacitor C3 is connected to the ground terminal.

4. The analog core circuit according to claim 1, characterized in that: Also includes: A phase adjustment unit is connected to the voltage-controlled oscillator and is used to perform phase adjustment on the first clock signal to obtain a second clock signal.

5. The analog core circuit according to claim 4, characterized in that: The phase adjustment unit includes a selector connected to the voltage-controlled oscillator, configured to obtain a first phase, and perform phase adjustment on the first clock signal according to the first phase to obtain a second clock signal.

6. The analog core circuit according to claim 5, characterized in that: The phase adjustment unit also includes a phase conversion module connected to the selector, used to obtain a second phase, and transmit the second phase to the selector, so as to perform phase adjustment on the first clock signal through the first phase and the second phase to obtain a second clock signal.

7. The analog core circuit according to claim 1, characterized in that: Also includes: A charge pump is connected to the low-pass filter and is used to obtain the signal difference and convert the signal difference into a current signal.

8. The analog core circuit according to claim 7, characterized in that: Also includes: The phase frequency detector is connected to the charge pump and is used to obtain a reference clock signal and a feedback clock signal and detect a signal difference between the reference clock signal and the feedback clock signal.

9. A phase-locked loop, characterized in that: The invention comprises a dual-loop phase-locked loop analog core circuit as described in any one of claims 1 to 8.

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