A manufacturing method for an epitaxial wafer of a superlattice space GaInP / InGaAs / Ge cell

Abstract

The present invention discloses a manufacturing method of a superlattice space GaInP / InGaAs / Ge cell epitaxial wafer. Currently, in the GaInP / InGaAs / Ge triple-junction cell, the bandgap width of the Ge material is relatively small, and the absorbed spectral range is relatively wide, resulting in its current density being much larger than that of the InGaAs cell and the GaInP top cell layer, causing a loss in the utilization rate of sunlight. The present invention discloses a manufacturing method of a superlattice space GaInP / InGaAs / Ge cell epitaxial wafer, which introduces a superlattice structure into the base regions of the middle cell and the top cell respectively, that is: the present invention introduces GaAsP / GaInAs and GaInP / AlGaInP superlattices into the p-GaInAs base region layer of the middle cell and the p-GaInP base region layer of the top cell respectively, thereby improving the current matching in the cell, enhancing the anti-irradiation performance of the cell, simultaneously increasing the collection efficiency of minority photo-generated carriers, reducing the radiative recombination of photo-generated carriers, and thus improving the photoelectric conversion efficiency of the space GaInP / InGaAs / Ge cell epitaxial wafer and further enhancing the cell performance.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a battery epitaxial wafer, and more particularly to a method for manufacturing a superlattice space GaInP / InGaAs / Ge battery epitaxial wafer. Background Art

[0002] GaAs solar cells are currently the main power source for space satellites. Compared with other photovoltaic cells, they have the characteristics of high photoelectric conversion efficiency and good anti-irradiation performance. Currently, GaAs solar cells have various structures and types, among which the lattice-matched GaInP / InGaAs / Ge triple-junction solar cell is the most commonly used structure. In this structure, the lattice parameters of the three materials GaInP, InGaAs, and Ge are matched, and the bandgap widths are fixed. Each junction cell is responsible for absorbing the spectrum within a certain wavelength range. In the GaInP / InGaAs / Ge triple-junction cell, the Ge material has a relatively small bandgap width and a relatively wide absorption spectrum range, resulting in its current density being much larger than that of the InGaAs middle cell and the GaInP top cell layer, causing a loss in the utilization rate of sunlight.

[0003] In order to improve the current mismatch of the conventional GaInP / InGaAs / Ge triple-junction solar cell, one method is to insert quantum well structures in the GaInP top cell and the InGaAs middle cell respectively. Although the quantum well structure can broaden the absorption spectrum widths of the middle cell and the top cell, improve the anti-irradiation performance of the cell, and increase the overall current density of the cell, the potential barrier formed by the barrier layer in the quantum well structure restricts the photo-generated carriers, weakening the photon collection ability, and having a negative impact on the short-circuit current and open-circuit voltage of the cell, resulting in no obvious improvement in the performance of the cell due to the introduction of the quantum well structure. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for manufacturing a superlattice space GaInP / InGaAs / Ge battery epitaxial wafer that can improve the photon carrier collection efficiency of the space quantum well structure GaInP / InGaAs / Ge battery and increase the photoelectric conversion efficiency.

[0005] The purpose of the present invention is achieved as follows:

[0006] A manufacturing method of a superlattice space GaInP / InGaAs / Ge cell epitaxial wafer, characterized in that: GaAsP / GaInAs and GaInP / AlGaInP superlattice layers are respectively introduced into the middle cell composed of a GaInAs base region layer, an emitter region layer, an AlGaAs back surface field layer, and an AlInP window layer, and the top cell composed of a GaInP base region layer, an emitter region layer, an AlGaInP back surface field layer, and an AlInP window layer. The deposition thickness of the superlattice GaAsP layer in the middle cell is controlled at 10 - 20 nm, and the deposition thickness of the superlattice AlGaInP layer in the top cell is controlled at 10 - 20 nm. Two and one superlattice structures are respectively inserted into the middle cell and the top cell. The specific steps are as follows:

[0007] Using a Metal Organic Chemical Vapor Deposition (MOCVD) equipment, an n-AlGaInP nucleation layer, an n-GaAs / n-GaInAs buffer layer, an n++-GaAs / p++-GaAs tunneling junction layer, a p-AlGaAs / p-AlGaInAs (DBR) reflection layer, a p-AlGaAs back surface field layer, a p-GaInAs base region layer are sequentially deposited on a p-Ge substrate. Two independent GaAsP / GaInAs superlattice structures are deposited in the p-GaInAs base region layer, then an n-GaInAs emitter region layer, an n-AlInP window layer, an n++-GaInP / p++-AlGaAs tunneling junction layer, a p-AlGaInP back surface field layer, a p-GaInP base region layer are deposited. One independent GaAsP / GaInAs superlattice structure is deposited in the p-GaInP base region layer, and then an n-GaInP emitter region layer, an n-AlInP window layer and an n+-GaAs ohmic contact layer are deposited.

[0008] The substrate material is p-Ge with a thickness of 130 - 150 μm, doped Ga source, doping concentration of 0.2E18 - 3E18 cm -3 , 9° cut angle;

[0009] The deposition thickness of the n-AlGaInP nucleation layer is 0.01 μm, and the doping concentration is 1 - 2×10 18 cm -3 。

[0010] The deposition thickness of the n-GaAs / n-GaInAs buffer layer is 0.5 μm, and the doping concentration is ≥1×10 18 cm -3 。

[0011] For the n++-GaAs / p++-GaAs tunneling junction layer, the deposition thickness of the n++-GaAs layer is 0.01 - 0.03 μm, and the doping concentration is ≥5×1018 cm -3 The deposition thickness of the p++-GaAs layer is 0.01 - 0.03 μm, and the doping concentration is ≥1×10 19 cm -3 。

[0012] The deposition thickness of the p-AlGaAs / p-AlGaInAs (DBR) reflection layer is 1.8 μm, and the doping concentration is 5×10 17 cm -3 。

[0013] The deposition thickness of the p-AlGaAs backfield layer is 0.1 μm, and the doping concentration is 1 - 2×10 18 cm -3 。

[0014] The total deposition thickness of the p-GaInAs base region layer is 0.3 μm, which is divided into three layers, each layer being 0.1 μm. Two groups of superlattice structures are inserted between the three layers, and the doping concentration of all is 2 - 8×10 16 cm -3 。

[0015] There are 2 groups of the same structure in the GaAsP / GaInAs superlattice structure, and the thickness of each group of structures is 0.615 μm. In the superlattice structure, the thickness of the GaAsP layer is 0.015 μm, and the deposition thicknesses of the GaInAs layers are 0.12 μm, 0.105 μm, 0.09 μm, 0.075 μm, 0.06 μm, 0.045 μm, and 0.03 μm respectively.

[0016] The deposition thickness of the n-GaInAs emitter region layer is 0.1 μm, and the doping concentration is 1×10 18 cm -3 。

[0017] The deposition thickness of the n-AlInP window layer is 0.1 μm, and the doping concentration is 1×10 18 cm -3 。

[0018] The n++-GaInP / p++-AlGaAs tunneling junction layer, where the deposition thickness of the n++-GaInP layer is 0.01 - 0.03 μm, and the doping concentration is ≥5×10 18 cm -3 ,and the deposition thickness of the p++-AlGaAs layer is 0.01 - 0.03 μm, and the doping concentration is ≥5×10 19 cm -3 。

[0019] The deposition thickness of the p-AlGaInP backfield layer is 0.1 μm, and the doping concentration is 1 - 2×10 18 cm -3 。

[0020] The deposition thickness of the p-GaInP base region layer is 0.2 μm, which is divided into two layers, each layer being 0.1 μm. A superlattice structure is inserted between the two layers, and the doping concentration is 1 - 8×10 16 cm -3 。

[0021] The deposition thickness of the GaInP / AlGaInP superlattice structure is 0.615 μm. In the structure, the deposition thickness of AlGaInP is 0.015 μm, and the deposition thicknesses of GaInP are 0.12 μm, 0.105 μm, 0.09 μm, 0.075 μm, 0.06 μm, 0.045 μm, and 0.03 μm respectively.

[0022] The deposition thickness of the n-GaInP emitter region layer is 0.1 μm, and the doping concentration is 1×10 18 cm -3 。

[0023] The deposition thickness of the n-AlInP window layer is 0.1 μm, and the doping concentration is 1×10 18 cm -3 。

[0024] The deposition thickness of the n+-GaAs ohmic contact layer is 0.5 μm, and the doping concentration is greater than 5×10 18 cm -3 。

[0025] Since the barrier layer in the superlattice structure is thinned, the energy bands in adjacent well structures change from isolated to hybridized, resulting in a continuous energy band distribution between adjacent wells of the entire superlattice. Through the design of gradually decreasing well width, photon carriers form resonant tunneling under the action of the built-in electric field, reducing the recombination of photo-generated carriers, overcoming the drawbacks of the barrier layer limitation in the quantum well structure, and thus improving the battery performance.

[0026] Compared with the conventional structure, in the present invention, a superlattice structure is inserted between the base region layers of the middle cell and the top cell respectively, that is: in the present invention, GaAsP / GaInAs superlattice and GaInP / AlGaInP superlattice structures are respectively introduced into the p-GaInAs base region layer of the middle cell and the p-GaInP base region layer of the top cell. Therefore, it can broaden the absorption spectrum width of the battery, improve the anti-irradiation performance of the battery, enhance the collection efficiency of photo-generated carriers, thereby improving the photoelectric conversion efficiency of the space GaInP / InGaAs / Ge cell epitaxial wafer and further improving the battery performance. Description of the Drawings

[0027] Figure 1 is a schematic diagram of the epitaxial layer structure related to the present invention.

[0028] Figure 2 It is a schematic diagram of the superlattice structure of the middle battery and the top battery involved in the present invention; the superlattice structure is composed of alternating well layers and barrier layers.

[0029] Reference numerals:

[0030] 100: P-type Ge substrate;

[0031] 101: n-AlGaInP nucleation layer;

[0032] 102: n-GaAs / GaInAs buffer layer;

[0033] 103: n++-GaAs / p++-GaAs tunneling junction layer;

[0034] 104: p-AlGaAs / p-AlGaInAs (DBR) reflection layer;

[0035] 105: p-AlGaAs back surface field layer;

[0036] 106: p-GaInAs base region layer and GaAsP / GaInAs superlattice layer;

[0037] 107: n-GaInAs emitter region layer;

[0038] 108: n-AlInP window layer;

[0039] 109: n++-GaInP / p++-AlGaAs tunneling junction layer;

[0040] 110: p-AlGaInP back surface field layer;

[0041] 111: p-GaInP base region layer and GaInP / AlGaInP superlattice layer;

[0042] 112: n-GaInP emitter region layer;

[0043] 113: n-AlInP window layer;

[0044] 114: n+-GaAs ohmic contact layer. Detailed implementation manners

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] The present invention will be further described in detail below with reference to examples and the accompanying drawings.

[0047] A method for manufacturing an epitaxial wafer of a superlattice space GaInP / InGaAs / Ge cell, using equipment of type 2600G3 MOCVD (Metal Organic Chemical Vapor Deposition) produced by German company AXITRON. The substrate is a p-type Ge substrate, with a doped Ga source and a doping concentration of 0.2E18 - 3E18 cm -3 , a thickness of 130 - 150 μm, and a 9° cut angle. The MO sources used are TMGa, TMAl, and TMIn, the doping sources used are CCl4, DEZn, and SiH4, and the special gases used are AsH3 and PH3;

[0048] The specific steps are as follows:

[0049] A. Heat the MOCVD reaction chamber to 400 °C and introduce PH3, then heat the reaction chamber to 690 °C and set the pressure to 230 mbar. Form an N-type doped Ge sub-cell with a doping of about 1×10 18 cm -3 on the surface of the p-Ge substrate through P diffusion. Lower the temperature of the reaction chamber to 620 °C, introduce the sources of TMAl, TMGa, TMIn, and the special gas PH3, and deposit an n-AlGaInP nucleation layer. The deposition thickness of the AlGaInP nucleation layer is 0.01 μm, with a doping source of SiH4 and a doping concentration of 1 - 2×10 18 cm -3 ;

[0050] B. Heat the reaction chamber to 650 °C and control the pressure at 450 mbar, and deposit an n-GaAs / n-GaInAs buffer layer on the n-AlGaInP nucleation layer. The deposition thickness of the n-GaAs / n-GaInAs buffer layer is 0.5 μm, with a doping source of SiH4 and a doping concentration of ≥1×10 18 cm -3 ;

[0051] C. Lower the temperature of the reaction chamber to 630 °C and control the pressure at 50 mbar, and deposit an n++-GaAs layer on the GaAs / GaInAs buffer layer. The deposition thickness of the n++-GaAs layer is 0.01 - 0.03 μm, with a doping source of SiH4 and a doping concentration of ≥5×10 18 cm -3 , then lower the reaction temperature to 620 °C, and deposit a p++-GaAs layer on the n++-GaAs layer. The deposition thickness of the p++-GaAs layer is 0.01 - 0.03 μm, with a doping source of CCl4 and a doping concentration of ≥1×10 19 cm-3 ;

[0052] D. The reaction chamber temperature is raised to 650 °C, and a p-AlGaAs / p-AlGaInAs (DBR) reflective layer is deposited on the p++-GaAs layer. The deposition thickness of the p-AlGaAs / p-AlGaInAs reflective layer is 1.8 μm, and the DEZn source is doped with a doping concentration of 5×10 17 cm -3 ;

[0053] E. A p-AlGaAs backfield layer is deposited on the AlGaAs / AlGaInAs reflective layer at a temperature of 650 °C. The deposition thickness of the p-AlGaAs backfield layer is 0.1 μm, and the DEZn source is doped with a doping concentration of 1 - 2×10 18 cm -3 ;

[0054] F. A p-GaInAs base region layer of 0.1 μm is deposited on the AlGaAs backfield layer at a temperature of 650 °C. The DEZn source is doped with a doping concentration of 2 - 8×10 16 cm -3 , and then a superlattice structure is deposited. The GaAsP / GaInAs layers grow alternately. The deposition thickness of the GaAsP layer is 0.015 μm, and the deposition thicknesses of the GaInAs layers are 0.12 μm, 0.105 μm, 0.09 μm, 0.075 μm, 0.06 μm, 0.045 μm, and 0.03 μm respectively. The DEZn source is doped with a doping concentration of 2 - 8×10 16 cm -3 . Then, a p-GaInAs base region layer of 0.1 μm and another group of GaAsP / GaInAs superlattices are deposited under the same conditions, and then a p-GaInAs base region layer of 0.1 μm is deposited again under the same conditions;

[0055] G. An n-GaInAs emitter region layer is deposited on the p-GaInAs base region layer at a temperature of 650 °C. The deposition thickness of the n-GaInAs emitter region layer is 0.1 μm, and the SiH4 source is doped with a doping concentration of 1×10 18 cm -3 ;

[0056] H. An n-AlInP window layer is deposited on the GaInAs emitter region layer at a temperature of 650 °C. The deposition thickness of the n-AlInP window layer is 0.1 μm, and the SiH4 source is doped with a doping concentration of 1×10 18 cm -3 ;

[0057] I. Deposit an n++-GaInP / p++-AlGaAs tunneling junction layer on the AlInP window layer at a temperature of 620 °C, where: the deposition thickness of the n++-GaInP layer is 0.01 - 0.03 μm, doped with SiH4 source, doping concentration ≥ 5×10 18 cm -3 , the deposition thickness of the p++-AlGaAs layer is 0.01 - 0.03 μm, doped with CCl4 source, doping concentration ≥ 5×10 19 cm -3 ;

[0058] J. Deposit a p-AlGaInP backfield layer on the GaInP / AlGaAs tunneling junction layer at a temperature of 620 °C, the deposition thickness of the p-AlGaInP backfield layer is 0.1 μm, doped with DEZn source, doping concentration 1 - 2×10 18 -3 cm;

[0059] K. Raise the temperature of the reaction chamber to 630 °C, deposit a p-GaInP base region layer on the AlGaInP backfield layer, deposition thickness 0.1 μm, doped with DEZn source, doping concentration 1 - 8×10 16 cm -3 . Then deposit a superlattice structure, with alternating growth of GaInP / AlGaInP layers. The deposition thickness of the AlGaInP layer is 0.015 μm, and the deposition thicknesses of the GaInP layers are 0.12 μm, 0.105 μm, 0.09 μm, 0.075 μm, 0.06 μm, 0.045 μm, 0.03 μm respectively, doped with DEZn source, doping concentration 1 - 8×10 16 cm -3 . Then deposit a p-GaInP base region layer of 0.1 μm under the same conditions;

[0060] L. Deposit an n-GaInP emitter region layer on the GaInP base region layer at a temperature of 630 °C, the deposition thickness of the n-GaInP emitter region layer is 0.1 μm, doped with SiH4 source, doping concentration 1×10 18 cm -3 ;

[0061] M. Deposit an n-AlInP window layer on the GaInP emitter region layer at a temperature of 630 °C, the deposition thickness of the n-AlInP window layer is 0.1 μm, doped with SiH4 source, doping concentration 1×10 18 cm -3 ;

[0062] N. Deposit an n+-GaAs ohmic contact layer on the AlInP window layer at a temperature of 630 °C, the deposition thickness of the n+-GaAs ohmic contact layer is 0.5 μm, doped with SiH4 source, doping concentration greater than 5×10 18 cm-3 。

[0063] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0064] Although embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A manufacturing method of a superlattice space GaInP / InGaAs / Ge cell epitaxial wafer, characterized in that: The GaAsP / GaInAs and GaInP / AlGaInP superlattice layers are introduced into the middle cell and the top cell respectively, and the specific steps are as follows: Using a Metal Organic Chemical Vapor Deposition (MOCVD) equipment, successively deposit an n-AlGaInP nucleation layer, an n-GaAs / n-GaInAs buffer layer, an n++-GaAs / p++-GaAs tunneling junction layer, a p-AlGaAs / p-AlGaInAs (DBR) reflector layer, a p-AlGaAs back surface field layer, a p-GaInAs base region layer, a GaAsP / GaInAs superlattice layer, an n-GaInAs emitter region layer, an n-AlInP window layer, an n++-GaInP / p++-AlGaAs tunneling junction layer, a p-AlGaInP back surface field layer, a p-GaInP base region layer, a GaInP / AlGaInP superlattice layer, an n-GaInP emitter region layer, an n-AlInP window layer, and an n+-GaAs ohmic contact layer on a p-Ge substrate; The substrate material is a p-type Ge substrate, doped with a Ga source, with a doping concentration of 0.2E18 - 3E18 cm -3 , a thickness of 130 - 150 μm, and a 9° cut angle; The deposition thickness of the n-AlGaInP nucleation layer is 0.01 μm, doped with SiH4 source, and the doping concentration is 1 - 2×10 18 cm -3 ; The deposition thickness of the n-GaAs / n-GaInAs buffer layer is 0.5 μm, doped with SiH4 source, and the doping concentration is ≥1×10 18 cm -3 ; n++-GaAs / p++-GaAs tunneling junction layer, where the deposition thickness of the n++-GaAs layer is 0.01 - 0.03 μm, doped with SiH4 source, doping concentration ≥ 5×10 18 cm -3 , the deposition thickness of the p++-GaAs layer is 0.01 - 0.03 μm, doped with CCl4 source, doping concentration ≥ 1×10 19 cm -3 ; The deposition thickness of the p-AlGaAs / p-AlGaInAs reflective layer is 1.8 μm, doped with a DEZn source and a doping concentration of 5×10 17 cm -3 ; The deposition thickness of the p-AlGaAs backfield layer is 0.1 μm, doped with a DEZn source and a doping concentration of 1 - 2×10 18 cm -3 ; The total thickness of the p-GaInAs base region layer is 0.3 μm, which is divided into three layers, each layer being 0.1 μm. Two sets of superlattice structures are inserted between the three layers, and the doping DEZn source and the doping concentration are both 2 - 8×10 16 cm -3 ; The superlattice material is GaAsP / GaInAs, and the well layer thickness gradually decreases; The deposition thickness of the n-GaInAs emitter layer is 0.1 μm, doped with SiH4 source and the doping concentration is 1×10 18 cm -3 ; The deposition thickness of the n-AlInP window layer is 0.1 μm, doped with SiH4 source and the doping concentration is 1×10 18 cm -3 ; n++-GaInP / p++-AlGaAs tunneling junction layer, where the deposition thickness of the n++-GaInP layer is 0.01 - 0.03 μm, doped with SiH4 source and the doping concentration is ≥5×10 18 cm -3 ; the deposition thickness of the p++-AlGaAs layer is 0.01 - 0.03 μm, doped with CCl4 source and the doping concentration is ≥5×10 19 cm -3 ; The deposition thickness of the p-AlGaInP backfield layer is 0.1 μm, doped with a DEZn source and a doping concentration of 1-2×10 18 cm -3 ; The thickness of the p-GaInP base region layer is 0.2 μm, which is divided into two layers, each layer being 0.1 μm. A superlattice structure is inserted between the two layers, and the DEZn source is doped with a doping concentration of 1-8×10 16 cm -3 ; The superlattice material is GaInP / AlGaInP, and the well layer thickness gradually decreases; The deposition thickness of the n-GaInP emitter layer is 0.1 μm, doped with SiH4 source and the doping concentration is 1×10 18 cm -3 ; The deposition thickness of the n-AlInP window layer is 0.1 μm, doped with SiH4 source and the doping concentration is 1×10 18 cm -3 ; The deposition thickness of the n+-GaAs ohmic contact layer is 0.5 μm, doped with SiH4 source and the doping concentration is greater than 5×10 18 cm -3 ; In the GaAsP / GaInAs superlattice, the well layer material is Ga 0.94 In 0.06 As, and the barrier layer material is GaAs 0.5 P 0.5 ; The deposition thicknesses of the GaInAs layers are 0.12 μm, 0.105 μm, 0.09 μm, 0.075 μm, 0.06 μm, 0.045 μm, and 0.03 μm respectively; In the GaInP / AlGaInP superlattice, the well layer material is Ga 0.45 In 0.55 P, and the barrier layer material is (Al 0.1 Ga 0.9 ) 0.5 In 0.5 P; the deposition thicknesses of the GaInP layers are 0.12 μm, 0.105 μm, 0.09 μm, 0.075 μm, 0.06 μm, 0.045 μm, and 0.03 μm, respectively.

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