Semiconductor device structure

Abstract

A semiconductor device structure includes a semiconductor substrate having a well pickup region and an active region. The well pickup region and the active region each include a first well region and a second well region having different conductivity types. A well region boundary is between the first well region and the second well region. A first fin structure is located within the first well region of the well pickup region, and a plurality of second fin structures are located within the first well region of the active region. A minimum distance between the well region boundary and the first fin structure is greater than a minimum distance between the well region boundary and a one of the plurality of second fin structures closest to the well region boundary.

Description

Technical Field

[0001] The present embodiment relates to a semiconductor technology, and more particularly to a semiconductor device structure having a fin structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in multiple generations of ICs. Each generation of ICs features smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processes and IC manufacturing. In response to these advances, IC manufacturing and processes have required similar evolutions. Throughout the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased.

[0003] As the semiconductor industry advances to nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges in both manufacturing and design have led to the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated using a thin, vertical "fin" (or fin structure) extending from a substrate. The channel region of a FinFET is located within this vertical fin. The gate is located above the fin. Advantages of FinFETs include reduced short-channel effects and higher current capability.

[0004] While current fin field-effect transistors (FinFETs) and their fabrication methods are generally suitable for their intended purposes, they are not fully satisfactory in all respects. For example, as fin dimensions (e.g., fin width) and inter-fin spacing (e.g., the distance between adjacent fins) decrease, cross-diffusion between well pickup regions of different conductivity types increases the resistance of the well pickup region, leading to a decrease in the electrical performance of the semiconductor device. Therefore, manufacturing reliable semiconductor devices becomes a challenge as the size requirements continue to shrink. Summary of the Invention

[0005] A semiconductor device structure includes: a semiconductor substrate having a well pickup region and an active region, wherein the well pickup region and the active region each include a first well region having a first conductivity type and a second well region having a second conductivity type opposite to the first conductivity type, adjacent to the first well region, such that a well region boundary is located between the first well region and the second well region; a first fin structure located in the first well region of the well pickup region; and a plurality of second fin structures located in the first well region of the active region. The first fin structure is separated from the well region boundary by a first distance. One of the second fin structures closest to the well region boundary is separated from the well region boundary by a second distance. The first distance is greater than the second distance.

[0006] A semiconductor device structure includes: a well pickup region formed in a semiconductor substrate; an active region formed in the semiconductor substrate and adjacent to the well pickup region; a first fin structure formed in a first region of the well pickup region; a second fin structure formed in a first region of the active region, wherein the first region of the well pickup region and the first region of the active region are doped with a first type of impurity; a third fin structure formed in a second region of the pickup region; and a fourth fin structure formed in a second region of the active region, wherein the second region of the well pickup region and the second region of the active region are doped with a second type of impurity. The distance between a first sidewall of the first fin structure and a third sidewall of the third fin structure is greater than the distance between a second sidewall of the second fin structure and a fourth sidewall of the fourth fin structure.

[0007] A semiconductor device structure includes: a semiconductor substrate having a well pickup region and an active region adjacent to the well pickup region; two first fin structures formed adjacent to each other in the well pickup region and separated by a first distance; and two second fin structures formed adjacent to each other in the active region and separated by a second distance. The two first fin structures have different conductivity types, and the two second fin structures have different conductivity types. The first distance is greater than the second distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic plan view of a semiconductor device having a fin structure according to some embodiments is shown.

[0009] Figures 2A to 2F Schematic plan views illustrating different stages of a method for fabricating a semiconductor device having a fin structure according to some embodiments.

[0010] Figures 3A to 3F along Figures 2A to 2F Line AA′ shows cross-sectional views at different stages of a method for manufacturing a semiconductor device with a fin structure according to some embodiments.

[0011] Figures 4A to 4F along Figures 2A to 2FLine BB' shows cross-sectional views at different stages of a method for manufacturing a semiconductor device with a fin structure according to some embodiments.

[0012] Figure 5 A schematic plan view of a semiconductor device having a fin structure according to some embodiments is shown.

[0013] Figure 6 A schematic plan view of a semiconductor device having a fin structure according to some embodiments is shown.

[0014] Figure 7 A schematic plan view of a semiconductor device having a fin structure according to some embodiments is shown.

[0015] Description of reference numerals:

[0016] 10: Well pickup area

[0017] 20: Vacant area

[0018] 30: Active Zone

[0019] 40: First well region

[0020] 50: Second well region

[0021] 60: Third well region

[0022] 100: Semiconductor substrate

[0023] 100a: First fin structure

[0024] 100b: Second fin structure

[0025] 100c: Third fin structure

[0026] 100d: Fourth fin structure

[0027] 100e: Fifth fin structure

[0028] 100f: Sixth fin structure

[0029] 102: First mask layer

[0030] 104: Second mask layer

[0031] 106: Third mask layer

[0032] 110: Groove

[0033] 120: Isolate feature components

[0034] 130: Gate structure

[0035] 200, 300, 400, 500: Semiconductor devices

[0036] B1: first well region boundary

[0037] B2: Second well region boundary

[0038] D1: First distance

[0039] D2: Second distance

[0040] D3: The third distance

[0041] D4: The fourth distance

[0042] L1: length of the first fin

[0043] L2: Length of the second fin

[0044] W1: first fin width

[0045] W2: Second fin width

[0046] W3: third fin width

[0047] W4: fourth fin width DETAILED DESCRIPTION

[0048] The following disclosure provides many different embodiments or examples for implementing the different characteristic components of the present invention. The following disclosure describes specific examples of each component and its arrangement in order to simplify the present disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, if the following disclosure describes forming a first characteristic component on or above a second characteristic component, it means that it includes an embodiment in which the formed first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which additional characteristic components can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. The present disclosure will repeat the figure marks and / or text in each different example. The repetition is for the purpose of simplicity and clarity, rather than to specify the relationship between the different embodiments and / or configurations discussed.

[0049] Furthermore, spatially relative terms such as "below," "beneath," "below," "above," and "upper" are used herein to facilitate the relationship of elements or features shown in the figures of this specification to other elements or features. These spatially relative terms encompass not only the orientations shown in the figures, but also different orientations of the device during use or operation. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative symbols used herein should be interpreted accordingly.

[0050] The following describes some embodiments of the present disclosure. Additional operations may be performed before, during, or after the operational stages described in these embodiments. In different embodiments, some of the operational stages described above may be replaced or eliminated. Additional features may be incorporated into the semiconductor device structure. In different embodiments, some of the features described below may be replaced or eliminated. Although the operational steps of some embodiments are described as being performed in a particular order, these operational steps may be performed in other reasonable orders.

[0051] The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography with self-alignment processes, which can form patterns with finer pitches than can be achieved using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed on the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are used to pattern the fins.

[0052] The following embodiments provide a semiconductor device structure and a method for manufacturing the semiconductor device structure. Figure 1 FIG. 2 is a schematic plan view of a semiconductor device 200 having a fin structure according to some embodiments. Figure 1As shown, semiconductor device 200 includes a semiconductor substrate 100 having a well pickup region 10, an active region 30, and a dummy region 20. In some embodiments, dummy region 20 is located between well pickup region 10 and active region 30. In some embodiments, well pickup region 10 includes a first well region 40 having a first conductivity type, a second well region 50 having a second conductivity type opposite to the first conductivity type and adjacent to first well region 40, and a third well region 60 having the first conductivity type and adjacent to second well region 50. That is, first well region 40 and third well region 60 are doped with first-type impurities. Second well region 50 is doped with second-type impurities opposite to the first-type impurities. Furthermore, dummy region 20 and active region 30 each include a first well region 40, a second well region 50 adjacent to first well region 40, and a third well region 60 adjacent to second well region 50. As such, the second well region 50 is located between the first well region 40 and the third well region 60, such that a first well region boundary B1 is defined between the first well region 40 and the second well region 50, and a second well region boundary B2 is defined between the second well region 50 and the third well region 60. In some embodiments, the first well region 40 and the third well region 60 (e.g., PMOS regions) are used to form a P-type fin field-effect transistor (FinFET) thereon, while the second well region 50 (e.g., NMOS regions) is used to form an N-type fin field-effect transistor (FinFET) thereon. In other embodiments, the first well region 40 and the third well region 60 (e.g., NMOS regions) are used to form an N-type fin field-effect transistor (FinFET) thereon, while the second well region 50 (e.g., PMOS regions) is used to form a P-type fin field-effect transistor (FinFET) thereon.

[0053] In some embodiments, the semiconductor substrate 100 includes a semiconductor material (e.g., silicon). In other embodiments, the semiconductor substrate 100 may include another elemental semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or a combination thereof. In addition, the semiconductor substrate 100 may be a semiconductor on insulator (SOI).

[0054] In some embodiments, the semiconductor device 200 further includes a first fin structure 100 a protruding from the semiconductor substrate 100 in the first well region 40 of the well pickup region 10 . Furthermore, one or more second fin structures 100 b protrude from the semiconductor substrate 100 in the first well region 40 of the active region 30 and extend into the first well region 40 of the dummy region 20 .

[0055] In some embodiments, the first fin structure 100a is separated from the first well boundary B1 by a first distance D1. Furthermore, the one of the second fin structures 100b closest to the first well boundary B1 is also separated from the first well boundary B1 by a second distance D2. The first distance D1 may be the minimum distance between the first well boundary B1 and the first fin structure 100a. For example, the first distance D1 is the distance between the sidewall of the first fin structure 100a and the first well boundary B1. Similarly, the second distance D2 may be the minimum distance between the first well boundary B1 and the second fin structure 100b closest to the first well boundary B1. For example, the second distance D2 is the distance between the sidewall of the second fin structure 100b and the first well boundary B1. In some embodiments, the ratio of the first distance D1 to the second distance D2 is approximately in the range of 2 to 3.5. In some embodiments, the first distance D1 is approximately in the range of 50 nm to 70 nm. The second distance D2 is approximately in the range of 20 nm to 25 nm. In some embodiments, the first distance D1 is greater than the second distance D2. The design with a sufficient difference between the first distance D1 and the second distance D2 prevents the inter-diffusion region (or depletion region, which is caused by doping the first well region 40 and the second well region 50 with impurities of different conductivity types) (not shown) in the first well region 40 from extending into the first fin structure 100a. In this way, the resistance value of the first fin structure 100a can be prevented from increasing. Furthermore, the semiconductor substrate 100 may have a sufficient utilization area (which is used to form the first fin structure 100a), thereby preventing the resistance value of the first fin structure 100a from increasing. In some embodiments, the first distance D1 is not less than the maximum length of the inter-diffusion region in the first well region 40.

[0056] In some embodiments, the first fin structure 100a has a first fin width W1, and each second fin structure 100b has a second fin width W2. In some embodiments, a ratio of the first fin width W1 to the second fin width W2 is approximately in a range of 2.5 to 20. In some embodiments, the first fin width W1 is approximately in a range of 25 nm to 100 nm, and the second fin width W2 is approximately in a range of 5 nm to 10 nm.

[0057] In some embodiments, the second fin width W2 is smaller than the first fin width W1. Because the interdiffusion region within the first well region 40 may extend into the first fin structure 100a, a sufficient difference between the first fin width W1 and the second fin width W2 is maintained. This design prevents a significant increase in impurity depletion regions or impurity losses (caused by the interdiffusion region) within the first fin structure 100a. This prevents an increase in the resistance of the first fin structure 100a.

[0058] In some embodiments, the semiconductor device 200 further includes a third fin structure 100 c protruding from the semiconductor substrate 100 in the second well region 50 of the well pickup region 10. Furthermore, one or more fourth fin structures 100 d protrude from the semiconductor substrate 100 in the second well region 50 of the active region 30 and extend into the second well region 50 of the dummy region 20.

[0059] In some embodiments, the third fin structure 100c is separated from the first well boundary B1 by a third distance D3. Furthermore, the one of the fourth fin structures 100d closest to the first well boundary B1 is also separated from the first well boundary B1 by a fourth distance D4. The third distance D3 may be the minimum distance between the first well boundary B1 and the third fin structure 100c. For example, the third distance D3 is the distance between the sidewall of the third fin structure 100c and the first well boundary B1. Similarly, the fourth distance D4 may be the minimum distance between the first well boundary B1 and the fourth fin structure 100d closest to the first well boundary B1. For example, the fourth distance D4 is the distance between the sidewall of the fourth fin structure 100d and the first well boundary B1. In some embodiments, the ratio of the third distance D3 to the fourth distance D4 is approximately in the range of 1 to 2. In some embodiments, the third distance D3 is approximately in the range of 30 nm to 40 nm. The fourth distance D4 is approximately in the range of 20 nm to 30 nm. In some embodiments, the third distance D3 is greater than the fourth distance D4. Similarly, there is a sufficient difference between the third distance D3 and the fourth distance D4. Such a design prevents the inter-diffusion region (which is caused by doping the first well region 40 and the second well region 50 with impurities of different conductivity types) (not shown) in the second well region 50 from extending into the third fin structure 100c. In this way, the resistance value of the third fin structure 100c can be prevented from increasing. Furthermore, the semiconductor substrate 100 may have a sufficient utilization area (which is used to form the third fin structure 100c), thereby preventing the resistance value of the third fin structure 100c from increasing. In some embodiments, the third distance D3 is not less than the maximum length of the inter-diffusion region in the second well region 50. In some embodiments, the first distance D1 is different from the third distance D3 or is substantially equal to the third distance D3. For example, the first distance D1 is greater than the third distance D3, such as Figure 1 shown.

[0060] In some embodiments, the third fin structure 100c has a third fin width W3, and each fourth fin structure 100d has a fourth fin width W4. In some embodiments, the ratio of the third fin width W3 to the fourth fin width W4 is approximately in the range of 1.5 to 10. In some embodiments, the third fin width W3 is approximately in the range of 12 nm to 50 nm. The fourth fin width W4 is approximately in the range of 5 nm to 8 nm. In some embodiments, the fourth fin width W4 is smaller than the third fin width W3. Similarly, because the interdiffusion region within the second well region 50 may extend into the third fin structure 100c, a design with a sufficient difference between the third fin width W3 and the fourth fin width W4 prevents a significant increase in impurity depletion regions or impurity losses (caused by the interdiffusion region) within the third fin structure 100c. This prevents an increase in the resistance of the third fin structure 100c. In some embodiments, the first fin width W1 is different from or substantially equal to the third fin width W3.

[0061] In some embodiments, the first fin structure 100a has a first fin length L1, and the third fin structure 100c has a second fin length L2, which is substantially equal to the first fin length L1. In this way, the two ends of the first fin structure 100a are aligned with the two corresponding ends of the third fin structure 100c, as shown in FIG. Figure 1 In some embodiments, the first fin length L1 is approximately in the range of 50 nm to 150 nm, and the second fin length L2 is approximately in the range of 50 nm to 150 nm.

[0062] In some embodiments, the semiconductor device 200 further includes a fifth fin structure 100 e protruding from the semiconductor substrate 100 in the third well region 60 of the well pickup region 10. Furthermore, one or more sixth fin structures 100 f protrude from the semiconductor substrate 100 in the third well region 60 of the active region 30 and extend into the third well region 60 of the dummy region 20.

[0063] In some embodiments, the fifth fin structure 100e is separated from the second well region boundary B2. Furthermore, the one of the sixth fin structures 100f closest to the second well region boundary B2 is also separated from the second well region boundary B2. The minimum distance between the second well region boundary B2 and the fifth fin structure 100e (referred to as the fifth distance) may be greater than the minimum distance between the second well region boundary B2 and the one of the sixth fin structures 100f closest to the second well region boundary B2 (referred to as the sixth distance). The fifth distance may be the distance between the sidewall of the fifth fin structure 100e and the second well region boundary B2. The sixth distance may be the distance between the second well region boundary B2 and the sidewall of the sixth fin structure 100f closest to the second well region boundary B2. In some embodiments, the ratio of the fifth distance to the sixth distance is the same as or similar to the ratio of the first distance D1 to the second distance D2. Furthermore, the fifth distance is the same as or similar to the first distance D1. The sixth distance is the same as or similar to the second distance D2. Similarly, the design of having a sufficient difference between the fifth distance and the sixth distance prevents the inter-diffusion region (which is caused by doping the second well region 50 and the third well region 60 with impurities of different conductivity types) (not shown) in the third well region 60 from extending into the fifth fin structure 100e. In this way, the resistance value of the fifth fin structure 100e can be prevented from increasing. Furthermore, the semiconductor substrate 100 can have a sufficient utilization area (which is used to form the fifth fin structure 100e), thereby preventing the resistance value of the fifth fin structure 100e from increasing. In some embodiments, in some embodiments, the fifth distance is not less than the maximum length of the inter-diffusion region (which is caused by doping the second well region 50 and the third well region 60 with impurities of different conductivity types) (not shown) in the third well region 60.

[0064] In some embodiments, the third fin structure 100c is separated from the second well region boundary B2 by a distance that is the same as or different from the third distance D3. Furthermore, the one of the fourth fin structures 100d closest to the second well region boundary B2 is also separated from the second well region boundary B2 by a distance that is the same as or different from the fourth distance D4. In some embodiments, the minimum distance between the second well region boundary B2 and the third fin structure 100c is no less than the maximum length of the interdiffusion region (caused by doping the second well region 50 and the third well region 60 with impurities of different conductivity types) (not shown) within the second well region 50.

[0065] Furthermore, the minimum distance between the second well region boundary B2 and the fifth fin structure 100e is different from or substantially equal to the minimum distance between the second well region boundary B2 and the third fin structure 100c. For example, the minimum distance between the second well region boundary B2 and the fifth fin structure 100e is greater than the minimum distance between the second well region boundary B2 and the third fin structure 100c. Figure 1 shown.

[0066] In some embodiments, the fifth fin structure 100e may have a fin width that is different from the fin width of each of the sixth fin structures 100f. In one example, the fin width of the fifth fin structure 100e is the same as or similar to the first fin width W1, and the fin width of the sixth fin structure 100f is the same as or similar to the second fin width W2 or the fourth fin width W4. In this case, the fin width of the sixth fin structure 100f is smaller than the fin width of the fifth fin structure 100e. In some embodiments, the fin width of the fifth fin structure 100e is different from or substantially equal to the third fin width W3 of the third fin structure 100c. Similarly, because the interdiffusion region in the third well region 60 may extend into the fifth fin structure 100e, a design with a sufficient difference between the fifth fin structure 100e and the sixth fin structure 100f prevents a significant increase in impurity depletion regions or impurity losses (caused by the interdiffusion region) within the fifth fin structure 100e. In this way, the resistance of the fifth fin structure 100 e can be prevented from increasing.

[0067] In some embodiments, the fin length of the fifth fin structure 100e is substantially equal to the first fin length L1 of the first fin structure 100a and the second fin length L2 of the third fin structure 100c. Thus, two ends of the fifth fin structure 100e are aligned with two corresponding ends of the first fin structure 100a and two corresponding ends of the third fin structure 100c, respectively.

[0068] In some embodiments, the semiconductor device 200 further includes isolation structures, which may be located on opposite sides of the fin structures (e.g., the first fin structure 100a, the second fin structure 100b, the third fin structure 100c, the fourth fin structure 100d, the fifth fin structure 100e, and the sixth fin structure 100f). In some embodiments, each isolation structure includes an isolation feature 120 and a liner structure (not shown) covering the sidewalls and bottom of the isolation feature 120. Thus, the semiconductor substrate 100 and the lower portions of the fin structures (e.g., the first fin structure 100a, the second fin structure 100b, the third fin structure 100c, the fourth fin structure 100d, the fifth fin structure 100e, and the sixth fin structure 100f) are separated from the isolation feature 120 by the liner structure.

[0069] In some embodiments, isolation features 120 are made of a dielectric material, such as silicon oxide, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. Isolation features 120 may be shallow trench isolation (STI) features. In some embodiments, the liner structure may include a single layer or a multi-layer structure and may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide (SiC), or a combination thereof.

[0070] In some embodiments, the distance between the sidewalls of the first fin structure 100a and the sidewalls of the third fin structure 100c is greater than the distance between the sidewalls of the second fin structure 100b and the sidewalls of the fourth fin structure 100d. In some embodiments, the first fin structure 100a and the third fin structure 100c are separated by one of the isolation structures. In those cases, the isolation structure may be in direct contact with the sidewalls of the first fin structure 100a and the sidewalls of the third fin structure 100c. Similarly, in some embodiments, the distance between the sidewalls of the fifth fin structure 100e and the sidewalls of the third fin structure 100c is greater than the distance between the sidewalls of the sixth fin structure 100f and the sidewalls of the fourth fin structure 100d. In some embodiments, the fifth fin structure 100e and the third fin structure 100c are separated by one of the isolation structures. In those cases, the isolation structure may be in direct contact with the sidewalls of the fifth fin structure 100e and the sidewalls of the third fin structure 100c.

[0071] In some embodiments, the semiconductor device 200 further includes gate structures 130 disposed above the semiconductor substrate 100. Some of these gate structures 130 span the first fin structure 100a, the third fin structure 100c, and the fifth fin structure 100e within the well pickup region 10. Other gate structures 130 span the second fin structure 100b, the fourth fin structure 100d, and the sixth fin structure 100f within the dummy region 50, as well as the second fin structure 100b, the fourth fin structure 100d, and the sixth fin structure 100f within the active region 60.

[0072] In some embodiments, each gate structure 130 may include a gate dielectric layer, a gate electrode layer, and / or one or more additional layers. In some embodiments, the gate structure 130 is a sacrificial gate structure or a dummy gate structure, such as used to form a metal gate structure in a replacement gate process. In some embodiments, the gate structure 130 includes a polysilicon layer (as a gate electrode layer). Furthermore, the gate dielectric layer of the gate structure 130 may include silicon dioxide or other suitable dielectric materials. In addition, the gate dielectric layer of the gate structure 130 may include a high-k dielectric layer, such as HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, or a combination thereof.

[0073] In some embodiments, the gate structure 130 may be a metal gate structure. The metal gate structure may include an interface layer, a gate dielectric layer, a work function layer, and a fill metal layer. In some embodiments, the interface layer may include a dielectric material, such as a silicon oxide layer (SiO2) or a silicon oxynitride (SiON). Furthermore, exemplary P-type work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, or combinations thereof. Exemplary N-type work function metals may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, or combinations thereof.

[0074] Figures 2A to 2F Showing the formation according to some embodiments Figure 1 Schematic plan views of a method for fabricating a semiconductor device 200 having a fin structure at different stages. Figures 3A to 3F Shown along the Figures 2A to 2F 1 is a schematic cross-sectional view of a method for forming a semiconductor device 200 at different stages along line AA′. Figures 4A to 4F Shown along the Figures 2A to 2F 1 and 2 are cross-sectional schematic diagrams of a method for forming a BB' line of a semiconductor device 200 at different stages.

[0075] Please refer to Figure 2A 、 Figure 3A and Figure 4A, receiving a semiconductor substrate 100. In some embodiments, the semiconductor substrate 100 comprises a semiconductor material (e.g., silicon). In some other embodiments, the semiconductor substrate 100 may comprise another elemental semiconductor (e.g., germanium), a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or a combination thereof. Furthermore, the semiconductor substrate 100 is a semiconductor layer on an insulator (SOI).

[0076] In some embodiments, a semiconductor substrate 100 includes a well pickup region 10, an active region 30, and a dummy region 20 located between the well pickup region 10 and the active region 30. In some embodiments, the semiconductor substrate 100 may be doped (e.g., with P-type and / or N-type impurities) or undoped. For example, the semiconductor substrate 100 is doped with P-type and N-type impurities using a well region implantation process. Each of the well pickup region 10, the dummy region 20, and the active region 30 includes a first well region 40, a second well region 50, and a third well region 60. Furthermore, the first well region 40 and the third well region 60 are doped with first-type impurities, resulting in the first well region 40 and the third well region 60 having a first conductivity type. The second well region 50 is doped with an opposite second-type impurity, resulting in the second well region 50 having a second conductivity type opposite to the adjacent first well region 40 and third well region 60. Therefore, the second well region 50 is located between the first well region 40 and the third well region 60. A first well region boundary B1 is located between the first well region 40 and the second well region 50. Furthermore, the second well region boundary B2 is located between the second well region 50 and the third well region 60. For example, the first well region 40 and the third well region 60 (e.g., PMOS regions) are used to form a P-type FinFET therein. Furthermore, the second well region 50 (e.g., NMOS region) is used to form an N-type FinFET therein.

[0077] In some embodiments, during the implantation process of the P-type well regions of the first well region 40 and the third well region 60, the implantation energy of the P-type impurities is approximately in the range of 20 KeV to 40 KeV. Furthermore, the doping concentration of the P-type impurities is approximately 1×10 13 atoms / cm 3 to about 7×10 13 atoms / cm 3 In some embodiments, the implantation energy of the N-type impurities is in the range of about 80 KeV to about 120 KeV. Furthermore, in some embodiments, the dopant concentration of the N-type impurities is about 1×10 13 atoms / cm 3 to 6×10 13atoms / cm 3 range.

[0078] In some embodiments, the semiconductor substrate 100 includes a first region 100a and a second region 100b adjacent to the first region 100a. The first region 100a may be used to form a P-type device, such as a P-type metal oxide semiconductor field effect transistor (MOSFET). In such cases, the second region 100b may be used to form an N-type device, such as an N-type MOSFET. Therefore, the first region 100a may be referred to as a PMOS region, while the second region 100b may be referred to as an NMOS region. In some other embodiments, P-type devices (or N-type devices) are formed in both the first region 100a and the second region 100b.

[0079] In some embodiments, a first photoresist (not shown) is formed on the semiconductor substrate 100 to expose the areas where the first well region 40 and the third well region 60 are to be formed. A P-type well region implantation process is then performed on the exposed areas of the semiconductor substrate 100 to form the first well region 40 and the third well region 60. Similarly, after removing the first photoresist, a second photoresist (not shown) is formed on the semiconductor substrate 100 to form a pattern to expose the areas where the second well region 50 is to be formed. An N-type well region implantation process is then performed on the exposed areas of the semiconductor substrate 100 to form the second well region 50. In some embodiments, the first well region 40 and the third well region 60 are doped with boron (B) ions to form P-type well regions. Furthermore, the second well region 50 is doped with arsenic (As) or phosphorus (P) ions to form an N-type well region.

[0080] Next, a first mask layer 102 and a second mask layer 104 located thereover are sequentially formed on the semiconductor substrate 100 to form the fin structure in subsequent processes. The first mask layer 102 may serve as a buffer layer between the semiconductor substrate 100 and the second mask layer 104. In some embodiments, the first mask layer 102 is made of silicon oxide. In some embodiments, the second mask layer 104 is made of SiN or SiON. In some embodiments, the first mask layer 102 and the second mask layer 104 located thereover are formed by separate deposition processes. For example, the deposition process used to form the first mask layer 102 may be a thermal oxidation process. Furthermore, the deposition process used to form the second mask layer 104 may be a chemical vapor deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a plasma enhanced CVD (PECVD) process, a high-density plasma CVD (HDPCVD) process, a spin coating process, a sputtering process, or other suitable processes.

[0081] The second mask layer 104 is patterned by patterning a photoresist layer (not shown) using a photolithography process, and then the unprotected second mask layer 104 is etched by an etching process (eg, a wet etching process or a dry etching process), such as Figure 2A 、 Figure 3A and Figure 4A The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard baking). In some embodiments, after the etching process, the patterned second mask layer 104 includes fin patterns corresponding to the active region 30, and those fin patterns extend from the active region 30 into the dummy region 20.

[0082] In some embodiments, as Figure 2B 、 Figure 3B and Figure 4B As shown, a third mask layer 106 is formed to cover Figure 2A 、 Figure 3A and Figure 4A In some embodiments, the third mask layer 106 is made of photoresist or other suitable mask materials. For example, the third mask layer 106 is made of photoresist and patterned by a photolithography process. In some embodiments, after the photolithography process, the patterned third mask layer 106 includes a fin pattern corresponding to the well pickup region 10. In some embodiments, Figure 2B The fin pattern of the third mask layer 106 shown has the same Figure 2A The fin patterns of the second mask layer 104 shown have different widths. Figure 2B The minimum distance between the fin patterns of the third mask layer 106 is also different from Figure 2A The minimum distance between the fin patterns of the second mask layer 104 is shown. For example, Figure 2B The fin pattern width of the third mask layer 106 is larger than Figure 2A The fin pattern width of the second mask layer 104 is shown. Figure 2B The minimum distance between the fin patterns of the third mask layer 106 is also greater than Figure 2A The minimum distance between the fin patterns of the second mask layer 104 is shown.

[0083] like Figure 2C 、 Figure 3C and Figure 4CAs shown, after patterning the third mask layer 106, an etching process (e.g., a wet etching process or a dry etching process) is performed to remove the second mask layer 104 not covered by the patterned third mask layer 106. In this way, the fin pattern of the third mask layer 106 is transferred to the second mask layer 104. After the etching process, the patterned second mask layer 104 includes fin patterns corresponding to the well pickup region 10, the dummy region 20, and the active region 30. These fin patterns have different widths and different fin-to-fin pitches (i.e., the minimum distance between fin structures).

[0084] According to some embodiments, after forming the fin pattern in the second mask layer 104 corresponding to the well pickup region 10 , the dummy area 20 , and the active region 30 , the third mask layer 106 may be removed by a suitable removal process (eg, etching or plasma ashing).

[0085] Thereafter, an etching process (e.g., a wet etching process or a dry etching process) is performed to remove the first mask layer 102 that is not covered by the patterned second mask layer 104. As a result, the fin pattern of the second mask layer 104 is transferred into the first mask layer 102. After the etching process, the patterned first mask layer 102 includes fin patterns corresponding to the well pickup region 10, the dummy region 20, and the active region 30. These fin patterns have different widths and different fin-to-fin spacings (i.e., the minimum distance between fin structures), such as Figure 2D 、 Figure 3D and Figure 4D shown.

[0086] According to some embodiments, an etching process (eg, a wet etching process or a dry etching process) is performed on the semiconductor substrate 100 exposed at the patterned first mask layer 102 and the patterned second mask layer 104 thereon. Figure 2E 、 Figure 3E and Figure 4E As shown. In this way, a first fin structure 100a, a second fin structure 100b, a third fin structure 100c, a fourth fin structure 100d, a fifth fin structure 100e, a sixth fin structure 100f and a trench 110 are formed. During the etching process, the patterned second mask layer 104 can be completely removed, as shown. Figure 2E 、 Figure 3E and Figure 4E shown.

[0087] Thereafter, according to some embodiments, the patterned first mask layer 102 may be removed by a suitable removal process (eg, etching or plasma ashing process), such as Figure 2F 、 Figure 3F and Figure 4F As shown. Figure 2F As shown, a first fin structure 100a is formed in the first well region 40 of the well pickup region 10. A second fin structure 100b is formed in the first well region 40 of the active region 30 and extends into the first well region 40. A third fin structure 100c is formed in the second well region 50 of the well pickup region 10. A fourth fin structure 100d is formed in the second well region 50 of the active region 30 and extends into the second well region 50. A fifth fin structure 100e is formed in the third well region 60 of the well pickup region 10. A sixth fin structure 100f is formed in the third well region 60 of the active region 30 and extends into the third well region 60 of the dummy region 20.

[0088] In some embodiments, the first distance D1 (i.e., the minimum distance between the first well region boundary B1 and the first fin structure 100a) is different from the second distance D2 (i.e., the minimum distance between the first well region boundary B1 and the one of the second fin structures 100b closest to the first well region boundary B1). For example, the first distance D1 is greater than the second distance D2. In some embodiments, the first distance D1 is not less than the maximum length of the interdiffusion region (which is caused by doping the first well region 40 and the second well region 50 with impurities of different conductivity types) (not shown) in the first well region 40. In some embodiments, the first fin structure 100a has a first fin width W1, and each second fin structure 100b has a second fin width W2 different from the first fin width W1. For example, the second fin width W2 is less than the first fin width W1.

[0089] In some embodiments, third distance D3 (i.e., the minimum distance between first well region boundary B1 and third fin structure 100 c ) is different from fourth distance D4 (i.e., the minimum distance between first well region boundary B1 and the one of fourth fin structure 100 d closest to first well region boundary B1 ). For example, third distance D3 is greater than fourth distance D4 . In some embodiments, third distance D3 is also greater than the maximum length of the interdiffusion region (not shown) in second well region 50 (caused by doping first well region 40 and second well region 50 with impurities of different conductivity types). In some embodiments, first distance D1 is different from or substantially equal to third distance D3 .

[0090] In some embodiments, the third fin structure 100c has a third fin width W3, and each fourth fin structure 100d has a fourth fin width W4 that is different from the third fin width W3. For example, the fourth fin width W4 is smaller than the third fin width W3. In some embodiments, the first fin width W1 is different from or substantially equal to the third fin width W3. Furthermore, the second fin width W2 is different from or substantially equal to the fourth fin width W4.

[0091] In some embodiments, the first fin structure 100a has a first fin length L1, and the third fin structure 100c has a second fin length L2, which is substantially equal to the first fin length L1. Thus, two ends of the first fin structure 100a are aligned with two corresponding ends of the third fin structure 100c.

[0092] In some embodiments, the minimum distance between the second well region boundary B2 and the fifth fin structure 100e may be different from the minimum distance between the second well region boundary B2 and the one of the sixth fin structures 100f closest to the second well region boundary B2. Boundary B2. For example, the minimum distance between the second well region boundary B2 and the fifth fin structure 100e is greater than the minimum distance between the second well region boundary B2 and the sixth fin structure 100f closest to the second well region boundary B2. In some embodiments, the minimum distance between the second well region boundary B2 and the fifth fin structure 100e is no less than the maximum length of the interdiffusion region (which is caused by doping the second well region 50 and the third well region 60 with impurities of different conductivity types) (not shown) in the third well region 60.

[0093] In some embodiments, the minimum distance between the second well boundary B2 and the third fin structure 100c is different from the minimum distance between the second well boundary B2 and the one of the fourth fin structures 100d closest to the second well boundary B2. For example, the minimum distance between the second well boundary B2 and the third fin structure 100c is greater than the minimum distance between the second well boundary B2 and the one of the fourth fin structures 100d closest to the second well boundary B2. In some embodiments, the minimum distance between the second well boundary B2 and the third fin structure 100c is no less than the maximum length of the interdiffusion region (caused by doping the second well region 50 and the third well region 60 with impurities of different conductivity types) (not shown) in the second well region 50.

[0094] Furthermore, the minimum distance between the second well region boundary B2 and the fifth fin structure 100e is different from or substantially equal to the minimum distance between the second well region boundary B2 and the third fin structure 100c. For example, the minimum distance between the second well region boundary B2 and the fifth fin structure 100e is greater than the minimum distance between the second well region boundary B2 and the third fin structure 100c.

[0095] In some embodiments, the fifth fin structure 100e has a fin width that is different from the fin width of each of the sixth fin structures 100f. For example, the fin width of the sixth fin structure 100f is smaller than the fin width of the fifth fin structure 100e. In some embodiments, the fin width of the fifth fin structure 100e is different from or substantially equal to the third fin width W3 of the third fin structure 100c.

[0096] In some embodiments, the fin length of the fifth fin structure 100e is substantially equal to the second fin length L2 of the third fin structure 100c. As a result, two ends of the fifth fin structure 100e are aligned with two corresponding ends of the third fin structure 100c.

[0097] After forming the first fin structure 100a, the second fin structure 100b, the third fin structure 100c, the fourth fin structure 100d, the fifth fin structure 100e, and the sixth fin structure 100f, a liner structure (not shown) is conformally formed on the sidewalls and bottom of each trench 110, covering the first fin structure 100a, the second fin structure 100b, the third fin structure 100c, the fourth fin structure 100d, the fifth fin structure 100e, and the sixth fin structure 100f. The liner structure may serve as a shallow trench isolation (STI) liner and a protective layer for the first fin structure 100a, the second fin structure 100b, the third fin structure 100c, the fourth fin structure 100d, the fifth fin structure 100e, and the sixth fin structure 100f. In some embodiments, the liner structure may include a single layer or multiple layers. For example, the liner structure comprises a single layer and is made of silicon oxide (SiO2), silicon carbide (SiC), silicon nitride (SiN or Si3N4), silicon oxynitride (SiON), or other suitable dielectric materials. In some embodiments, the liner structure is formed using a thermal oxidation process or a deposition process (including CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). The liner structure may be subjected to a selective rapid thermal process to improve film quality.

[0098] According to some embodiments, after forming the liner structure, an insulating layer (not shown) is formed to cover the first fin structure 100a, the second fin structure 100b, the third fin structure 100c, the fourth fin structure 100d, the fifth fin structure 100e, and the sixth fin structure 100f, and to fill the trench 110 covering the liner structure. The insulating layer may be formed of silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof, and may be formed using a flowable CVD (FCVD) process. Other insulating materials and / or other formation processes may also be used.

[0099] According to some embodiments, after forming the insulating layer, an annealing process may be performed to bake the insulating layer. The annealing process may include a wet steam annealing process followed by a dry annealing process.

[0100] Afterwards, the insulating layer and the liner structure on the upper surfaces of the first fin structure 100a, the second fin structure 100b, the third fin structure 100c, the fourth fin structure 100d, the fifth fin structure 100e, and the sixth fin structure 100f are removed by a planarization process. The planarization process may be a chemical mechanical polishing (CMP) process. Afterwards, according to some embodiments, a portion of the insulating layer and a portion of the liner structure are removed to expose the upper portions of the first fin structure 100a, the third fin structure 100c, and the sixth fin structure 100f (e.g., Figure 3F As shown), there are also upper portions of the second fin structure 100b, the fourth fin structure 100d and the sixth fin structure 100f (as shown Figure 4F As shown in FIG. 1 ). In this way, an isolation feature 120 is formed. In some embodiments, the insulating layer and the liner structure are removed by an etching process (e.g., a dry etching process or a wet etching process) to form an isolation feature 120 (e.g., a shallow trench isolation (STI) structure), as shown in FIG. Figure 2F 、 Figure 3F and Figure 4F In some embodiments, the etching process includes a dry etching process using an etching gas including ammonia (eg, NH 3 ) and hydrogen fluoride (HF).

[0101] Then, according to some embodiments, a gate structure 130 is formed over the first fin structure 100a, the second fin structure 100b, the third fin structure 100c, the fourth fin structure 100d, the fifth fin structure 100e, and the sixth fin structure 100f to form a semiconductor device 200, such as Figure 1 In some embodiments, some of the gate structures 130 span the first fin structure 100 a , the third fin structure 100 c , and the fifth fin structure 100 e located in the well pickup region 10 , while other gate structures 130 span the second fin structure 100 b , the fourth fin structure 100 d , and the sixth fin structure 100 f located in the dummy region 50 and the second fin structure 100 b , the fourth fin structure 100 d , and the sixth fin structure 100 f located in the active region 60 .

[0102] In some embodiments, each gate structure 130 may include a gate dielectric layer, a gate electrode layer, and / or one or more additional layers. In some embodiments, the gate structure 130 is a dummy gate structure. In those cases, the gate structure 130 includes a polysilicon layer (serving as a dummy gate electrode layer). Furthermore, the dummy gate dielectric layer of the gate structure 130 may include silicon dioxide or other suitable dielectric materials. In addition, the dummy gate dielectric layer of the gate structure 130 may include a high-k dielectric layer, such as HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, or a combination thereof. The dummy gate dielectric layer may be formed by a deposition process, such as CVD, PVD, ALD, HDPCVD, metal organic CVD (MOCVD), or PECVD. Furthermore, the dummy gate electrode layer may be formed by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, or PECVD.

[0103] In some embodiments, the gate structure 130 may be a metal gate structure. The metal gate structure may include an interface layer, a gate dielectric layer, a work function layer, and a fill metal layer. In some embodiments, the interface layer may include a dielectric material, such as silicon oxide (SiO2) or silicon oxynitride (SiON). Furthermore, exemplary P-type work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, or combinations thereof. Exemplary N-type work function metals may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, or combinations thereof.

[0104] Then, in some embodiments, a gate-last process (sometimes referred to as a replacement gate process) is performed. In the gate-last process, the dummy gate structure is removed to form recesses. Then, in some embodiments, a metal gate structure is formed in each recess.

[0105] In some embodiments, the gate dielectric layer of the metal gate structure includes silicon oxide, silicon nitride, or a high-k dielectric material (including metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof). The gate dielectric layer may be formed by CVD, ALD, PECVD, or the like.

[0106] In some embodiments, the gate electrode layer of the metal gate structure may be made of a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multilayers thereof, and may be formed by electroplating, electroless plating, or other suitable methods.

[0107] Figure 5FIG. 1 is a schematic plan view illustrating a semiconductor device 300 having a fin structure according to some embodiments. Figure 5 Same as Figure 1 The components in FIG. 3 are labeled the same and their descriptions are omitted. In some embodiments, the semiconductor device 300 is similar to Figure 1 The semiconductor device 200 shown in FIG. 1 is different in that the two ends of the first fin structure 100a are not aligned with the corresponding ends of the third fin structure 100c or the corresponding ends of the fifth fin structure 100e. In one example, the two ends of the first fin structure 100a are not aligned with the corresponding ends of the third fin structure 100c, but are still aligned with the corresponding ends of the fifth fin structure 100e. In other words, the two ends of the third fin structure 100c are not aligned with the corresponding ends of the fifth fin structure 100e. In some embodiments, the semiconductor device 300 can be Figures 2A to 2F 、 Figures 3A to 3F as well as Figures 4A to 4F The same or similar method as shown is used to manufacture.

[0108] Figure 6 FIG. 4 is a schematic plan view illustrating a semiconductor device 400 having a fin structure according to some embodiments. Figure 6 Same as Figure 1 The components in FIG. 4 are labeled the same and their descriptions are omitted. In some embodiments, the semiconductor device 400 is similar to Figure 1 The semiconductor device 200 shown in FIG. 4 is different in that at least the first fin length L1 of the semiconductor device 400 is different from the second fin length L2 of the semiconductor device 400. For example, the first fin length L1 is less than the second fin length L2. As a result, at least one end of the first fin structure 100a is not aligned with the corresponding end of the third fin structure 100c. In addition, the first fin length L1 may also be greater than the second fin length L2. In some embodiments, the semiconductor device 400 may be transparent. Figures 2A to 2F 、 Figures 3A to 3F as well as Figures 4A to 4F The same or similar method as shown is used to manufacture.

[0109] Figure 7 FIG. 1 is a schematic plan view illustrating a semiconductor device 500 having a fin structure according to some embodiments. Figure 7 Same as Figure 1 The components in FIG. 5 are labeled the same and their descriptions are omitted. In some embodiments, the semiconductor device 500 is similar to Figure 1 The semiconductor device 200 shown in FIG. is different in that one or more fin structures in the active region 30 may not extend into the dummy region. In one example, the fourth fin structure 100d formed in the active region 30 may not extend into the dummy region 20. Figure 7Another difference is that one or more fin structures extending from the active region 30 to the dummy region 20 include discontinuous structures. For example, each sixth fin structure 100f includes a discontinuous structure, such as Figure 7 In some embodiments, the semiconductor device 500 can be Figures 2A to 2F 、 Figures 3A to 3F as well as Figures 4A to 4F The same or similar method as shown is used to manufacture.

[0110] In the above embodiments, a semiconductor device structure and a method for forming the same are provided. A first fin structure, a third fin structure, and a fifth fin structure are formed in a well pickup region of a semiconductor substrate. The first fin structure corresponds to the first well region. The third fin structure corresponds to the second well region, and the fifth fin structure corresponds to the third well region. A first well region boundary is formed between the first well region and the second well region. A second well region boundary is formed between the second well region and the third well region. A second fin structure, a fourth fin structure, and a sixth fin structure are formed in an active region of a semiconductor substrate. The second fin structure corresponds to the first well region. The fourth fin structure corresponds to the second well region, and the sixth fin structure corresponds to the third well region. The width of the first fin structure is greater than the width of each second fin structure. Similarly, the width of the third fin structure is greater than the width of each fourth fin structure, and the width of the fifth fin structure is greater than the width of each sixth fin structure. The minimum distance between the first well region boundary and the first fin structure is greater than the minimum distance between the first well region boundary and the second fin structure closest to the first well region boundary. The minimum distance between the first well region boundary and the third fin structure is greater than the minimum distance between the first well region boundary and the one of the fourth fin structures closest to the first well region boundary. Similarly, the minimum distance between the second well region boundary and the third fin structure is greater than the minimum distance between the second well region boundary and the one of the fourth fin structures closest to the second well region boundary. Similarly, the minimum distance between the second well region boundary and the fifth fin structure is greater than the minimum distance between the second well region boundary and the one of the sixth fin structure closest to the second well region boundary. Within the well pickup region, the minimum distance between the first fin structure and the first well region boundary, the minimum distance between the third fin structure and the first well region boundary, the minimum distance between the third fin structure and the second well region boundary, and the minimum distance between the fifth fin structure and the second well region boundary are not less than the maximum length of the interdiffusion region / depletion region caused by the formation of the first well region, the second well region, and the third well region.

[0111] Furthermore, the fin width of the first fin structure is greater than the fin width of each second fin structure. Similarly, the fin width of the third fin structure is greater than the fin width of each fourth fin structure, and the fin width of the fifth fin structure is greater than the fin width of each sixth fin structure.

[0112] In some embodiments, within a well pickup region of a semiconductor device, a minimum distance between a first fin structure and a first well region boundary, a minimum distance between a third fin structure and a first well region boundary, a minimum distance between a third fin structure and a second well region boundary, and a minimum distance between a fifth fin structure and a second well region boundary are designed to be no less than a maximum length of an interdiffusion region / depletion region resulting from the formation of the first well region, the second well region, and the third well region. Consequently, the resistance of the first fin structure, the third fin structure, and the fifth fin structure in the well pickup region can be reduced, while simultaneously reducing the fin-to-fin spacing in the active region, thereby maintaining or improving the electrical performance of the semiconductor device.

[0113] In some embodiments, the widths of the first, third, and fifth fin structures within the well pickup region of the semiconductor device are respectively greater than the widths of the second, fourth, and sixth fin structures within the active region of the semiconductor device. Consequently, impurity depletion or impurity loss (caused by the well region implantation process) within the first, third, and fifth fin structures within the well pickup region of the semiconductor device can be reduced or eliminated. This prevents further increase in the resistance of the first, third, and fifth fin structures within the well pickup region, while reducing the size (e.g., width) of the fin structures in the active region. Furthermore, as the widths of the first, third, and fifth fin structures within the well pickup region of the semiconductor device increase, the contact area between those fin structures and corresponding contact structures (e.g., contact vias) can be increased, thereby reducing contact resistance. This reduces or eliminates the voltage drop at the interface between the fin structures within the well pickup region and the corresponding contact structures.

[0114] In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a well pickup region and an active region. The well pickup region and the active region each include a first well region having a first conductivity type and a second well region having an opposite second conductivity type adjacent to the first well region, such that a well region boundary is located between the first well region and the second well region. The semiconductor device structure also includes a first fin structure located in the first well region of the well pickup region and a plurality of second fin structures located in the first well region of the active region. The first fin structure is separated from the well region boundary by a first distance. One of the second fin structures closest to the well region boundary is separated from the well region boundary by a second distance. The first distance is greater than the second distance.

[0115] In the above embodiment, the ratio of the first distance to the second distance is approximately in the range of 2 to 3.5.

[0116] In the above embodiment, the first distance is approximately in the range of 50 nm to 70 nm.

[0117] In the above embodiment, the first fin structure has a first fin width, and each second fin structure has a second fin width smaller than the first fin width. A ratio of the first fin width to the second fin width is approximately in the range of 2.5 to 20.

[0118] In the above embodiment, the semiconductor device structure further includes a plurality of gate structures located above the semiconductor substrate, wherein the gate structures span the first fin structure and the second fin structure.

[0119] In the above embodiment, the semiconductor device structure further includes a third fin structure located in the second well region of the well pickup region and a plurality of fourth fin structures located in the second well region of the active region, wherein the third fin structure is separated from the well region boundary by a third distance, and one of the fourth fin structures closest to the well region boundary is separated from the well region boundary by a fourth distance, and the third distance is greater than the fourth distance. A ratio of the third distance to the fourth distance is approximately in a range of 1 to 2. The third fin structure has a third fin width, and each of the fourth fin structures has a fourth fin width that is less than the third fin width.

[0120] In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a well pickup region formed in a semiconductor substrate. An active region is formed in the semiconductor substrate and adjacent to the well pickup region. A first fin structure is formed in a first region of the well pickup region. A second fin structure is formed in a first region of the active region. The first region of the well pickup region and the first region of the active region are doped with a first type of impurity. A third fin structure is formed in a second region of the pickup region. A fourth fin structure is formed in a second region of the active region. The second region of the well pickup region and the second region of the active region are doped with a second type of impurity. The distance between a first sidewall of the first fin structure and a third sidewall of the third fin structure is greater than the distance between a second sidewall of the second fin structure and a fourth sidewall of the fourth fin structure.

[0121] In the above embodiment, the first fin structure and the third fin structure are separated by an isolation structure, and the first sidewall of the first fin structure and the third sidewall of the third fin structure are both in direct contact with the isolation structure.

[0122] In the above embodiment, the first fin structure has a first fin width, the second fin structure has a second fin width smaller than the first fin width, and the third fin structure has a third fin width smaller than the first fin width and larger than the second fin width.

[0123] In the above embodiment, the semiconductor device structure further includes: a dummy region formed in the semiconductor substrate and located between the well pickup region and the active region, wherein the two fin structures extend into a first region of the dummy region.

[0124] In the above embodiment, the semiconductor device structure further includes a plurality of gate structures located on the semiconductor substrate, wherein the gate structures respectively span the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure.

[0125] In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a well pickup region and an active region adjacent to the well pickup region. Two first fin structures are formed adjacent to each other in the well pickup region and separated by a first distance. Two second fin structures are formed adjacent to each other in the active region and separated by a second distance. The two first fin structures have different conductivity types, and the two second fin structures have different conductivity types. The first distance is greater than the second distance.

[0126] In the above embodiment, the first fin structure has a first fin width, and the second fin structure has a second fin width smaller than the first fin width.

[0127] In the above embodiment, the first fin structures have different lengths, and at least one of the two second fin structures includes a discontinuous structure.

[0128] In the above embodiment, the semiconductor device structure further includes a third fin structure formed in the well pickup region and adjacent to one of the two first fin structures. The third fin structure is separated from the first fin structure by a first distance, and the third fin structure has a different conductivity type from the adjacent first fin structure.

[0129] The above briefly describes the features of several embodiments of the present invention, making the solutions of the present disclosure more easily understood by those skilled in the art. Anyone skilled in the art should understand that the present disclosure can be easily used as a basis for modification or design of other processes or structures to achieve the same purposes and / or obtain the same advantages as the embodiments described herein. Anyone skilled in the art should also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced, and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure comprising: A semiconductor substrate having a well pickup region and an active region, wherein the well pickup region and the active region each include a first well region having a first conductivity type and a second well region having a second conductivity type opposite to the first conductivity type, adjacent to the first well region, with a well region boundary located between the first well region and the second well region; a first fin structure located in the first well region of the well pickup region; and A plurality of second fin structures are located in the first well region of the active region; The first fin structure is separated from the well region boundary by a first distance, and one of the second fin structures closest to the well region boundary is separated from the well region boundary by a second distance, and the first distance is greater than the second distance. 2 . The semiconductor device structure of claim 1 , wherein a ratio of the first distance to the second distance is in a range of 2 to 3.

5. The semiconductor device structure of claim 1 , wherein the first distance is in a range of 50 nm to 70 nm. 4 . The semiconductor device structure of claim 1 , wherein the first fin structure has a first fin width, and each of the plurality of second fin structures has a second fin width smaller than the first fin width. The semiconductor device structure of claim 1 , wherein a ratio of the first fin width to the second fin width is in a range of 2.5 to 20.

6. The semiconductor device structure of claim 1 , further comprising: A plurality of gate structures are located above the semiconductor substrate, wherein the plurality of gate structures span the first fin structure and the plurality of second fin structures.

7. The semiconductor device structure of claim 1 , further comprising: a third fin structure located in the second well region of the well pickup region; as well as A plurality of fourth fin structures are located in the second well region of the active region, The third fin structure is separated from the well region boundary by a third distance, one of the fourth fin structures closest to the well region boundary is separated from the well region boundary by a fourth distance, and the third distance is greater than the fourth distance. 8 . The semiconductor device structure of claim 7 , wherein a ratio of the third distance to the fourth distance is in a range of 1 to 2.

9. A semiconductor device structure comprising: a well pickup region formed in a semiconductor substrate; an active region formed in the semiconductor substrate and adjacent to the well pickup region; a first fin structure formed in a first region of the well pickup region; a second fin structure formed in a first region of the active region, wherein the first region of the well pickup region and the first region of the active region are doped with a first type of dopant; a third fin structure formed in a second region of the well pickup region; and a fourth fin structure formed in a second region of the active region, wherein the second region of the well pickup region and the second region of the active region are doped with a second type of dopant, A distance between a first sidewall of the first fin structure and a third sidewall of the third fin structure is greater than a distance between a second sidewall of the second fin structure and a fourth sidewall of the fourth fin structure. 10 . The semiconductor device structure of claim 9 , wherein the first fin structure and the third fin structure are separated by an isolation structure. 11 . The semiconductor device structure of claim 10 , wherein the first sidewall of the first fin structure and the third sidewall of the third fin structure are both in direct contact with the isolation structure. 12 . The semiconductor device structure of claim 9 , wherein the first fin structure has a first fin width, and the second fin structure has a second fin width smaller than the first fin width. 13 . The semiconductor device structure of claim 12 , wherein the third fin structure has a third fin width that is smaller than the first fin width and larger than the second fin width.

14. The semiconductor device structure of claim 9, further comprising: A dummy region is formed in the semiconductor substrate and is located between the well pickup region and the active region, wherein the second fin structure extends into a first region of the dummy region.

15. A semiconductor device structure comprising: A semiconductor substrate having a well pickup region and an active region adjacent to the well pickup region; Two first fin structures are formed adjacent to each other in the well pickup region and separated by a first distance; Two second fin structures are formed adjacent to each other in the active region and separated by a second distance; wherein the first fin structure has a different conductivity type, and the second fin structure has a different conductivity type; and The first distance is greater than the second distance. 16 . The semiconductor device structure of claim 15 , wherein the first fin structure has a first fin width, and the second fin structure has a second fin width smaller than the first fin width. 17 . The semiconductor device structure of claim 15 , wherein the two first fin structures have different lengths, and a length of at least one of the two second fin structures is different from a length of the other of the two second fin structures.

18. The semiconductor device structure of claim 15, further comprising: a third fin structure formed in the well pickup region and adjacent to one of the first fin structures; The third fin structure is separated from the first fin structure adjacent to the third fin structure by a first distance, and the third fin structure and the first fin structure adjacent to the third fin structure have different conductivity types.

19. A semiconductor device structure comprising: A semiconductor substrate having a well pickup region and an active region adjacent to the well pickup region; a first fin structure and a third fin structure, having a first width and a third width respectively, and formed adjacent to each other in the well pickup region; and A second fin structure and a fourth fin structure, having a second width and a fourth width respectively, and formed adjacent to each other in the active region; The second width is smaller than the first width, the fourth width is smaller than the third width, and the first width is the same as or larger than the third width, wherein the first fin structure and the third fin structure have different conductivity types, and the second fin structure and the fourth fin structure have different conductivity types. 20 . The semiconductor device structure of claim 19 , wherein the first fin structure is separated from the third fin structure by a first distance, the second fin structure is separated from the fourth fin structure by a second distance, and the first distance is greater than the second distance.

21. The semiconductor device structure of claim 20, further comprising: a fifth fin structure formed in the well pickup region and adjacent to the first fin structure or the third fin structure; wherein the fifth fin structure is separated from the adjacent first fin structure or the third fin structure by the first distance; and The fifth fin structure has a different conductivity type from the adjacent first fin structure or the third fin structure. 22 . The semiconductor device structure of claim 19 , wherein the first fin structure and the third fin structure have different lengths, and wherein the second fin structure and the fourth fin structure have the same length. 23 . The semiconductor device structure of claim 19 , wherein the first fin structure and the third fin structure have the same length, and wherein the second fin structure and the fourth fin structure have the same length. 24 . The semiconductor device structure of claim 19 , wherein the first fin structure and the third fin structure have the same length, and wherein the second fin structure and the fourth fin structure have different lengths.

25. A semiconductor device structure comprising: A semiconductor substrate having a well pickup region and an active region, wherein each of the well pickup region and the active region includes a first well region having a first conductivity type, wherein each of the well pickup region and the active region further includes a second well region having a second conductivity type opposite to the first conductivity type and corresponding to an edge of the first well region adjacent to the well pickup region and the active region; a first fin structure located in the first well region of the well pickup region; A plurality of second fin structures are located in the first well region of the active region; wherein the first fin structure has a first width, and each of the plurality of second fin structures has a second width smaller than the first width; as well as A plurality of gate structures are located above the semiconductor substrate, wherein the plurality of gate structures span the first fin structure and the plurality of second fin structures.

26. A semiconductor device structure as described in claim 25, wherein the first fin structure has an edge that is separated from the edge of the first well region of the well pickup region by a first distance, and one of the multiple second fin structures that is closest to an edge of the first well region of the active region is separated from the edge of the first well region of the active region by a second distance, and the first distance is greater than the second distance.

27. The semiconductor device structure of claim 25, further comprising: a third fin structure located in the second well region of the well pickup region; as well as A plurality of fourth fin structures are located in the second well region of the active region, The third fin structure has a third width, and each of the fourth fin structures has a fourth width smaller than the third width.

28. A semiconductor device structure as described in claim 27, wherein the third fin structure is separated from the edge of the first well region of the well pickup region by a third distance, and one of the multiple fourth fin structures closest to the edge of the first well region of the active region is separated from the edge of the first well region of the active region by a fourth distance, and the third distance is greater than the fourth distance.

29. A semiconductor device structure comprising: a well pickup region formed in a semiconductor substrate; an active region formed in the semiconductor substrate and adjacent to the well pickup region; a first fin structure formed in a first region of the well pickup region; a second fin structure formed in a first region of the active region, wherein the first region of the well pickup region and the first region of the active region are doped with a first type dopant; a third fin structure formed in a second region of the well pickup region; and a fourth fin structure formed in a second region of the active region, wherein the second region of the well pickup region and the second region of the active region are doped with second type dopants; wherein the first fin structure has a first length and a first width, the second fin structure has a second length and a second width, the third fin structure has a third length and a third width, the fourth fin structure has a fourth length and a fourth width, and The first width is greater than the second width, and the third width is greater than the fourth width. 30 . The semiconductor device structure of claim 29 , wherein the first length is the same as the third length, and the second length is the same as the fourth length, and wherein the first length is different from the second length. 31 . The semiconductor device structure of claim 29 , wherein the first length is different from the third length, and the second length is the same as the fourth length, and wherein the first length and the third length are different from the second length.

32. The semiconductor device structure of claim 29, wherein the first length is the same as the third length, and the second length is different from the fourth length, and wherein the first length is different from the second length. 33 . The semiconductor device structure of claim 29 , wherein two ends of the first fin structure are not aligned with corresponding two ends of the third fin structure.

34. The semiconductor device structure of claim 29, further comprising: A dummy region is formed in the semiconductor substrate and is located between the well pickup region and the active region. The second fin structure extends into a first region of the dummy region.

35. The semiconductor device structure of claim 29, further comprising: A plurality of gate structures are located above the semiconductor substrate, wherein the plurality of gate structures respectively cross the first fin structure, the second fin structure, the third fin structure and the fourth fin structure.

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