Apparatus and method for performing double signed and unsigned multiplication of packed data elements

Abstract

An apparatus and method for performing dual concurrent multiplication of packed data elements. For example, one embodiment of a processor includes: a decoder for decoding a first instruction to generate a decoded instruction; a first source register for storing a first plurality of packed doubleword data elements; a second source register for storing a second plurality of packed doubleword data elements; and execution circuitry for executing the decoded instruction, the execution circuitry including: a multiplier circuit for multiplying a first doubleword data element from the first source register with a second doubleword data element from the second source register to generate a first quadword product and simultaneously multiplying a third doubleword data element from the first source register with a fourth doubleword data element from the second source register to generate a second quadword product; and a destination register for storing the first quadword product and the second quadword product as first and second packed quadword data elements.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of computer processors. More particularly, embodiments relate to apparatus and methods for performing double signed and unsigned multiplication of packed data elements. Background Art

[0002] An instruction set or instruction set architecture (ISA) is the part of a computer's architecture that is relevant to programming and includes native data types, instructions, register structure, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" herein generally refers to macroinstructions (which are instructions provided to a processor for execution)—as opposed to microinstructions or micro-operations (which are the result of a processor's decoder decoding a macroinstruction). Microinstructions or micro-operations can be configured to instruct the execution units on the processor to perform operations to implement the logic associated with the macroinstructions.

[0003] ISA is different from microarchitecture, which is a set of processor design technologies used to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, Intel® Pentium 4 processor, Intel® Core ™ The processors, from Advanced Micro Devices, Inc. of Sunnyvale, California, implement nearly identical versions of the x86 instruction set (with some extensions incorporated into a newer version), but have different internal designs. For example, the same register architecture of the ISA can be implemented differently in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a retirement register file). Unless otherwise specified, the phrases register architecture, register file, and register are used herein to refer to what is visible to the software / programmer and the manner in which instructions specify registers. Where a distinction is required, the adjectives "logical," "architectural," or "software-visible" will be used to refer to registers / files in the register architecture, while different adjectives will be used to designate registers in a given microarchitecture (e.g., physical registers, reorder buffer, retirement registers, register pool).

[0004] Multiply-accumulate is a common digital signal processing operation that computes the product of two numbers and adds the product to an accumulated value. Existing single-instruction, multiple-data (SIMD) microarchitectures implement multiply-accumulate operations by executing a series of instructions. For example, a multiply-accumulate can be performed with a multiply instruction, followed by a 4-way add, and then an accumulate with a destination quadword to generate two 64-bit saturated results. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the accompanying drawings, in which:

[0006] Figure 1A and 1B is a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention;

[0007] Figure 2A -C is a block diagram illustrating an exemplary VEX instruction format according to an embodiment of the present invention;

[0008] Figure 3 is a block diagram of a register architecture according to one embodiment of the present invention; and

[0009] Figure 4A is a block diagram illustrating both an exemplary in-order fetch, decode, and retirement pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention;

[0010] Figure 4B is a block diagram illustrating both an exemplary embodiment of an in-order fetch, decode, retirement core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to an embodiment of the present invention;

[0011] Figure 5A is a block diagram of a single processor core and its connection to the on-die interconnect network;

[0012] Figure 5B FIG. 1 shows an embodiment of the present invention. Figure 5A An expanded view of a portion of a processor core;

[0013] Figure 6 is a block diagram of a single-core processor and a multi-core processor with integrated memory controller and graphics according to an embodiment of the present invention;

[0014] Figure 7 A block diagram of a system according to one embodiment of the present invention is illustrated;

[0015] Figure 8 illustrates a block diagram of a second system according to an embodiment of the present invention;

[0016] Figure 9 illustrates a block diagram of a third system according to an embodiment of the present invention;

[0017] Figure 10 illustrates a block diagram of a system on chip (SoC) according to an embodiment of the present invention;

[0018] Figure 11 illustrates a block diagram of converting binary instructions in a source instruction set into binary instructions in a target instruction set, as opposed to the use of a software instruction converter, in accordance with an embodiment of the present invention;

[0019] Figure 12 shows a processor architecture on which embodiments of the present invention may be implemented;

[0020] Figure 13 shows a plurality of packed data elements containing real and complex values ​​according to one embodiment;

[0021] Figure 14A -B shows an embodiment of a packaged data processing architecture;

[0022] Figure 15 Shows a method according to one embodiment of the present invention;

[0023] Figure 16 Shown is a method according to another embodiment of the present invention;

[0024] Figure 17 An embodiment for right shifting multiple data elements based on an immediate value and writing the specified portion to a destination is shown;

[0025] Figure 18 An embodiment for right shifting multiple data elements based on a source value and writing a specified portion to a destination is shown;

[0026] Figure 19 An embodiment of shifting multiple data elements left based on an immediate value and writing the specified portion to a destination is shown;

[0027] Figure 20 An embodiment of shifting multiple data elements left based on a source value and writing a specified portion to a destination is shown;

[0028] Figure 21 A method according to an embodiment of the present invention is shown; and

[0029] Figure 22 A method according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0030] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention described below. However, those skilled in the art will appreciate that the embodiments of the present invention may be practiced without some of these specific details. In other instances, known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the present invention.

[0031] Exemplary Processor Architectures, Instruction Formats, and Data Types

[0032] An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify, among other things, the operation to be performed (opcode) and the operands (on which the operation is to be performed). Some instruction formats are further broken down through the definition of instruction templates (or subformats). For example, instruction templates for a given instruction format can be defined to have different subsets of the fields of the instruction format (the included fields typically adopt the same order, but at least some have different bit positions because fewer fields are included) and / or defined to have given fields interpreted differently. Therefore, each instruction in an ISA is represented using a given instruction format (and, if defined, using a given one of the instruction templates for that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has a specific opcode and instruction format, which includes an opcode field for specifying that opcode and an operand field (source 1 / destination and source 2) for selecting operands; and each occurrence of that ADD instruction in an instruction stream will have specific content in the operand field that selects a specific operand.

[0033] The embodiments of the instructions described herein may be implemented in different formats. In addition, exemplary systems, architectures, and pipelines are described in detail below. The embodiments of the instructions may be executed on such systems, architectures, and pipelines, but are not limited to those described in detail.

[0034] General Vector Friendly Instruction Format

[0035] The vector-friendly instruction format is an instruction format suitable for use with vector instructions (e.g., certain fields are present that are specific to vector operations). While embodiments are described in which both vector and scalar operations are supported by the vector-friendly instruction format, alternative embodiments use only vector operations in the vector-friendly format.

[0036] Figures 1A-1B is a block diagram illustrating a general vector friendly instruction format and its instruction template according to an embodiment of the present invention. Figure 1A is a block diagram illustrating a general vector friendly instruction format and its class A instruction template according to an embodiment of the present invention; and Figure 1B1 is a block diagram illustrating a general vector friendly instruction format and its class B instruction templates according to an embodiment of the present invention. Specifically, for the general vector friendly instruction format 100, class A and class B instruction templates are defined, both of which include a no memory access 105 instruction template and a memory access 120 instruction template. The term "general" in the context of the vector friendly instruction format refers to the fact that the instruction format is not tied to any particular instruction set.

[0037] While embodiments of the present invention will be described in which the vector friendly instruction format supports the following: 64-byte vector operand lengths (or sizes) with 32-bit (4-byte) or 64-bit (8-byte) data element widths (or sizes) (and thus, a 64-byte vector consists of 16 doubleword-sized elements or, alternatively, 8 quadword-sized elements); 64-byte vector operand lengths (or sizes) with 16-bit (2-byte) or 8-bit (1-byte) data element widths (or sizes); and 64-byte vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes). byte), or 8-bit (1 byte) data element width (or size); and 16-byte vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size); although alternative embodiments may support more, fewer, and / or different vector operand sizes (e.g., 256-byte vector operands) with more, fewer, or different data element widths (e.g., 128-bit (16-byte) data element width).

[0038] Figure 1A The category A instruction templates in include: 1) within the no memory access 105 instruction templates, a no memory access, full round control type operation 110 instruction template and a no memory access, data transformation type operation 115 instruction template are shown; and 2) within the memory access 120 instruction templates, a memory access, temporary 125 instruction template and a memory access, non-temporal 130 instruction template are shown. Figure 1B The category B instruction templates include: 1) within the no memory access 105 instruction template, the no memory access, write mask control, partial rounding control type operation 112 instruction template and the no memory access, write mask control, vsize type operation 117 instruction template are shown; and 2) within the memory access 120 instruction template, the memory access, write mask control 127 instruction template is shown.

[0039] The general vector friendly instruction format 100 includes Figures 1A-1B The following fields are listed below in the order shown.

[0040] Format field 140 - A specific value in this field (the instruction format identifier value) uniquely identifies the vector friendly instruction format, and therefore identifies occurrences of instructions in the vector friendly instruction format in an instruction stream. Thus, this field is optional in the sense that it is not required for instruction sets that only have the general vector friendly instruction format.

[0041] Base Operation Field 142 - Its content identifies different base operations.

[0042] Register index field 144—its contents specify the location of the source and destination operands (either in registers or in memory) either directly or through address generation. These include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. While in one embodiment, N may be up to three sources and one destination register, alternative embodiments may support more or fewer sources and destination registers (e.g., up to two sources may be supported, one of which also serves as the destination; up to three sources may be supported, one of which also serves as the destination; up to two sources and one destination may be supported).

[0043] Modifier field 146 - Its content distinguishes between occurrences of instructions in the general vector instruction format that specify memory access and those that do not; that is, between no memory access 105 instruction templates and memory access 120 instruction templates. Memory access operations read and / or write to the memory hierarchy (in some cases using values ​​in registers to specify the source and / or destination addresses), while non-memory access operations do not (e.g., the source and destination are registers). While in one embodiment this field also selects between three different ways to perform memory address operations, alternative embodiments may support more, fewer, or different ways to perform memory address operations.

[0044] Augmentation operation field 150 - Its contents identify which of a variety of different operations to perform in addition to the base operation. This field is context-specific. In one embodiment of the present invention, this field is divided into a category field 168, an alpha field 152, and a beta field 154. The augmentation operation field 150 allows a common group of operations to be performed in a single instruction rather than two, three, or four instructions.

[0045] Scale field 160 - its content allows for memory address generation (e.g., for use with 2 缩放 * The address of the index field (index + base address) is scaled.

[0046] Displacement field 162A - its contents are used as memory address generation (e.g., for use with 2 缩放 * The index + base address + displacement part of the address generation is used.

[0047] Displacement Factor field 162B (note that the concatenation of displacement field 162A directly above displacement factor field 162B indicates that one or the other is used)—its contents are used as part of address generation; it specifies the displacement factor to be scaled by the size of the memory access (N)—where N is the number of bytes in the memory access (e.g., for use with 2 缩放 *Address generation of index + base address + scaled displacement). Redundant low-order bits are ignored, and therefore, the contents of the displacement factor field are multiplied by the total memory operand size (N) to generate the final displacement to be used in the operation effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 174 (described later herein) and the data manipulation field 154C. The displacement field 162A and the displacement factor field 162B are optional in the sense that they are not used in the no memory access 105 instruction template and / or different embodiments may implement only one or neither of the two.

[0048] Data element width field 164 - its contents distinguish which of multiple data element widths to use (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that if only one data element width is supported and / or some aspect of the opcode is used to support the data element width, then this field is not needed.

[0049] Writemask field 170—its contents control, on a per-data-element-position basis, whether that data element position in the destination vector operand reflects the results of the base and augment operations. Class A instruction templates support merge writemasking, while class B instruction templates support both merge and zero writemasking. In merge mode, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base and augment operations); in another embodiment, the old value of each element in the destination where the corresponding mask bit has a 0 is preserved. In contrast, in zero mode, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base and augment operations); in one embodiment, elements in the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from first to last); however, the modified elements do not need to be contiguous. Therefore, writemask field 170 enables some vector operations, including loads, stores, arithmetic, logical, and so on. Although embodiments of the present invention are described in which the contents of writemask field 170 select one of a plurality of writemask registers containing a writemask to be used (and thus the contents of writemask field 170 indirectly identify the masking to be performed), alternative embodiments instead or additionally allow the contents of mask write field 170 to directly specify the masking to be performed.

[0050] Immediate field 172 - its contents allow specification of an immediate value. This field is optional in the sense that it is not present in implementations that do not support the general vector friendly format for immediate values ​​and it is not present in instructions that do not use immediate values.

[0051] Category field 168 - its contents distinguish between different categories of instructions. Figure 1A -B, the contents of this field select between category A and category B instructions. Figure 1A -B, a rounded square is used to indicate a specific value to be present in the field (e.g. Figure 1A -B corresponding to category A 168A and category B 168B for category field 168).

[0052] Instruction template for category A

[0053] In the case of non-memory access 105 instruction templates of class A, the α field 152 is interpreted as the RS field 152A, whose contents identify which of the different augmentation operation types is to be performed (e.g., round 152A.1 and data transform 152A.2 are specified for the no-memory-access, round-type operation 110 and no-memory-access, data transform-type operation 115 instruction templates, respectively), while the β field 154 identifies which of the specified types of operations is to be performed. In the no-memory-access 105 instruction templates, the scale field 160, the displacement field 162A, and the displacement-scale field 162B are not present.

[0054] No memory access instruction templates—full rounding control type operations

[0055] In the no memory access full round control type operation 110 instruction template, the beta field 154 is interpreted as a round control field 154A, the contents of which provide static rounding. Although in the described embodiment of the present invention, the round control field 154A includes the suppression of all floating point exceptions (SAE) fields 156 and the round operation control field 158, alternative embodiments may support encoding both of these concepts into the same field, or having only one or the other of these concepts / fields (e.g., having only the round operation control field 158).

[0056] SAE field 156 - its content distinguishes whether exception event reporting is disabled; when the content of the SAE field 156 indicates that suppression is enabled, the given instruction does not report any kind of floating point exception flags and does not raise any floating point exception handler.

[0057] Round operation control field 158 - Its contents determine which of a set of rounding operations to perform (e.g., round up, round down, round towards zero, and round to nearest). Thus, round operation control field 158 allows for changing the rounding mode on a per-instruction basis. In one embodiment of the invention, where the processor includes a control register for specifying the rounding mode, the contents of round operation control field 158 overwrite that register value.

[0058] No memory access instruction templates—data transformation type operations

[0059] In the no memory access data transform type operation 115 instruction template, the beta field 154 is interpreted as a data transform field 154B, the contents of which distinguish which of multiple data transforms is to be performed (eg, no data transform, swizzle, broadcast).

[0060] In the case of a class A memory access 120 instruction template, the alpha field 152 is interpreted as an eviction hint field 152B, the contents of which distinguish which of the eviction hints is to be used (in Figure 1A 152B.1 and non-temporal 152B.2 are specified for the memory access, temporary 125 instruction template and the memory access, non-temporal 130 instruction template, respectively), while the beta field 154 is interpreted as a data manipulation field 154C, the contents of which distinguish which of a plurality of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; upconversion of the source; and downconversion of the destination). The memory access 120 instruction template includes a scale field 160 and optionally a displacement field 162A or a displacement scale field 162B.

[0061] Vector memory instructions perform vector loads from and stores to memory with translation support. As with conventional vector instructions, vector memory instructions transfer data to and from memory element by element, with the actual elements being transferred being dictated by the contents of the vector mask selected as the writemask.

[0062] Memory access instruction templates—temporary

[0063] Temporary data is data that is likely to be reused quickly enough to benefit from being cached. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint completely.

[0064] Memory access instruction templates—non-temporal

[0065] Non-temporal data is data that is unlikely to be reused quickly enough to benefit from caching in level 1 cache and should be given priority for eviction. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

[0066] Instruction template for category B

[0067] In the case of class B instruction templates, the alpha field 152 is interpreted as a writemask control (Z) field 152C, the content of which distinguishes whether the writemask controlled by the writemask field 170 should be merge or zero.

[0068] In the case of class B non-memory access 105 instruction templates, a portion of the β field 154 is interpreted as the RL field 157A, the contents of which distinguish which of the different augmentation operation types is to be performed (e.g., round 157A.1 and vector length (VSIZE) 157A.2 are specified for the no memory access, write mask control, partial round control type operation 112 instruction template and the no memory access, write mask control, VSIZE type operation 117 instruction template, respectively), while the remainder of the β field 154 distinguishes which of the specified types of operations is to be performed. In the no memory access 105 instruction templates, the scale field 160, displacement field 162A, and displacement scale field 162B are not present.

[0069] In the no memory access, write mask control, partial round control type operation 110 instruction template, the remainder of the beta field 154 is interpreted as the round operation field 159A, and exception event reporting is disabled (the given instruction does not report any kind of floating point exception flags and does not invoke any floating point exception handler).

[0070] Round Operation Control Field 159A - As with Round Operation Control Field 158, its contents identify which of a set of rounding operations to perform (e.g., round up, round down, round towards zero, and round to nearest). Thus, Round Operation Control Field 159A allows for changing the rounding mode on a per-instruction basis. In one embodiment of the invention where the processor includes a control register for specifying the rounding mode, the contents of Round Operation Control Field 159A overwrite that register value.

[0071] In the no memory access, write mask control, VSIZE type operation 117 instruction template, the remainder 154 of the β field is interpreted as a vector length field 159B, the contents of which distinguish which of multiple data vector lengths is to be performed (e.g., 128, 256, or 512 bytes).

[0072] In the case of class B memory access 120 instruction templates, part of the beta field 154 is interpreted as a broadcast field 157B, the contents of which distinguish whether a broadcast-type data manipulation operation is to be performed, while the remainder of the beta field 154 is interpreted as a vector length field 159B. The memory access 120 instruction templates include a scale field 160 and, optionally, a displacement field 162A or a displacement scale field 162B.

[0073] With respect to the general vector friendly instruction format 100, a full opcode field 174 is shown that includes the format field 140, the base operation field 142, and the data element width field 164. While one embodiment is shown in which the full opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 174 includes fewer than all of these fields. The full opcode field 174 provides an operation code (opcode).

[0074] The augment operation field 150, the data element width field 164, and the write mask field 170 allow these features to be specified on a per-instruction basis in the general vector friendly instruction format.

[0075] The combination of the write mask field and the data element width field creates a typed instruction because they allow masks to be applied based on different data element widths.

[0076] The various instruction templates found within categories A and B are beneficial in different contexts. In some embodiments of the present invention, different processors or different cores within a processor may support only category A, only category B, or both categories. For example, a high-performance general-purpose out-of-order core intended for general-purpose computing may support only category B, a core intended primarily for graphics and / or scientific (throughput) computing may support only category A, and a core intended for both may support both categories. (Of course, cores with some mix of templates and instructions from both categories, but not all templates and instructions from both categories, are within the scope of the present invention.) Similarly, a single processor may include multiple cores, all of which support the same category or where different cores support different categories. For example, in a processor with separate graphics and general-purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only category A, while one or more of the general-purpose cores may be a high-performance general-purpose core intended for general-purpose computing with out-of-order execution and register renaming that supports only category B. Another processor without a separate graphics core may include one more general-purpose in-order or out-of-order core that supports both categories A and B. Of course, features from one category may also be implemented in another category in different embodiments of the present invention. A program written in a high-level language will be converted (e.g., compiled just-in-time or statically) into a variety of different executable forms, including: 1) a form with only instructions of the category supported by the target processor for execution; or 2) a form with alternative routines written using different combinations of instructions from all categories and with control flow code that selects the routine to execute based on the instructions supported by the processor (which is currently running the code).

[0077] Instruction format

[0078] VEX encoding allows instructions with more than two operands and SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides a syntax for three (or more) operands. For example, previously, two-operand instructions performed operations such as A = A + B, which overwrote the source operands. The use of the VEX prefix enables non-destructive operations such as A = B + C.

[0079] Figure 2A An exemplary AVX instruction format is shown including a VEX prefix 202 , a true opcode field 230 , a Mod R / M byte 240 , a SIB byte 250 , a displacement field 262 , and an IMM8 272 . Figure 2B Shown from Figure 2A Which fields make up the full opcode field 274 and the basic operation field 241. Figure 2C Shown from Figure 2A Which fields of constitute the register index field 244.

[0080] The VEX prefix (bytes 0-2) 202 is encoded in three bytes. The first byte is the format field 290 (VEX byte 0, bits [7:0]), which contains the explicit C4 byte value (a unique value used to distinguish the C4 instruction format). The second-third bytes (VEX bytes 1-2) include multiple bit fields that provide specific capabilities. Specifically, the REX field 205 (VEX byte 1, bits [7-5]) consists of the following: a VEX.R bit field (VEX byte 1, bit [7] - R), a VEX.X bit field (VEX byte 1, bit [6] - X), and a VEX.B bit field (VEX byte 1, bit [5] - B). The other fields of the instruction encode the lower three bits of the register index (rrr, xxx, and bbb) as known in the art, such that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode map field 215 (VEX byte 1, bits [4:0] - mmmmm) includes the contents used to encode the implied leading opcode byte. The W field 264 (VEX byte 2, bit [7] - W) is represented by the symbol VEX.W and provides different functions depending on the instruction. The role of VEX.vvvv 220 (VEX byte 2, bits [6:3] - vvvv) can include the following: 1) VEX.vvvv encodes the first source register operand specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) VEX.vvvv encodes the destination register operand specified in 1s complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand and the field is reserved and should contain 1111b. If the VEX.L 268 size field (VEX byte 2, bit [2]-L) = 0, it indicates a 28-byte vector; if VEX.L = 1, it indicates a 256-byte vector. The prefix encoding field 225 (VEX byte 2, bits [1:0]-pp) provides additional bits to the base operation field 241.

[0081] The true opcode field 230 (byte 3) is also known as the opcode byte. Portions of the opcode are specified in this field.

[0082] The MOD R / M field 240 (byte 4) includes a MOD field 242 (bits [7-6]), a Reg field 244 (bits [5-3]), and an R / M field 246 (bits [2-0]). The role of the Reg field 244 may include encoding a destination register operand or a source register operand (Rrrr's rrr), or being treated as an opcode extension and not used to encode any instruction operand. The role of the R / M field 246 may include encoding an instruction operand that references a memory address, or encoding a destination register operand or a source register operand.

[0083] Scale, Index, Base (SIB)—The contents of the scale field 250 (byte 5) include SS 252 (bits [7-6]), which is used for memory address generation. The contents of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) have been previously mentioned with respect to register indexes Xxxx and Bbbb.

[0084] The displacement field 262 and the immediate field (IMM8) 272 contain data.

[0085] Exemplary register architecture

[0086] Figure 3 is a block diagram of a register architecture 300 according to one embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 310 that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower 256 bits of the lower six zmm registers are overlaid on registers ymm0-15. The lower 128 bits of the lower six zmm registers (the lower 128 bits of the ymm registers) are overlaid on registers xmm0-15.

[0087] General purpose registers 325 - In the embodiment shown, there are sixteen 64-bit general purpose registers that are used to address memory operands in conjunction with existing x86 addressing modes. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0088] Scalar floating point stack register file (x87 stack) 345, on which the MMX packed integer flat register file 350 is aliased - in the illustrated embodiment, the x87 stack is an eight-element stack used to perform scalar floating point operations on 32 / 64 / 80-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data and are also used to hold operands for some operations performed between MMX and XMM registers.

[0089] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0090] Exemplary Core Architectures, Processors, and Computer Architectures

[0091] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a specialized core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more specialized cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors result in different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as specialized logic, such as integrated graphics and / or scientific (throughput) logic, or as a specialized core); and 4) a system-on-a-chip that may include the described CPU (sometimes referred to as an application core or application processor), the coprocessor described above, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of exemplary processor and computer architectures. Detailed herein are circuits (units) including exemplary cores, processors, etc.

[0092] Exemplary Core Architecture

[0093] Figure 4A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to embodiments of the present invention. Figure 4B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the present invention. Figure 4A - The solid boxes in B show the in-order pipeline and in-order core, while the optional addition of dashed boxes shows the register renaming, out-of-order issue / execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0094] exist Figure 4A, processor pipeline 400 includes a fetch stage 402, a length decode stage 404, a decode stage 406, an allocate stage 408, a rename stage 410, a schedule (also known as dispatch or issue) stage 412, a register read / memory read stage 414, an execute stage 416, a write back / memory write stage 418, an exception handling stage 422, and a commit stage 424.

[0095] Figure 4B A processor core 490 is shown, comprising a front end unit 430 coupled to an execution engine unit 450, and both coupled to a memory unit 470. The core 490 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 490 may be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose graphics processing unit (GPGPU) core, a graphics core, and the like.

[0096] Front end unit 430 includes a branch prediction unit 432 coupled to an instruction cache unit 434, which is coupled to an instruction translation lookaside buffer (TLB) 436, which is coupled to an instruction fetch unit 438, which is coupled to a decode unit 440. Decode unit 440 (or decoder) may decode instructions and generate as output one or more micro-ops, microcode entry points, microinstructions, other instructions, or other control signals decoded from, or otherwise reflecting or derived from, the original instruction. Decode unit 440 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), and the like. In one embodiment, core 490 includes a microcode ROM or other medium (e.g., within decode unit 440 or otherwise within front end unit 430) that stores microcode for certain macroinstructions. Decode unit 440 is coupled to rename / allocator unit 452 in execution engine unit 450 .

[0097] The execution engine unit 450 includes a rename / allocator unit 452 coupled to a retirement unit 454 and a set of one or more scheduler units 456. The scheduler units 456 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. The scheduler units 456 are coupled to physical register file units 458. Each of the physical register file units 458 represents one or more physical register files, with different physical register files storing one or more different data types, such as scalar integers, scalar floating point, packed integers, packed floating point, vector integers, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one embodiment, the physical register file units 458 include a vector register unit and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file unit 458 is overlaid by the retirement unit 454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and a retirement register file; using a future file, a history buffer, and a retirement register file; using a register map and a pool of registers; etc.). The retirement unit 454 and the physical register file unit 458 are coupled to an execution cluster 460. The execution cluster 460 includes a set of one or more execution units 462 and a set of one or more memory access units 464. The execution units 462 can perform various operations (e.g., shifts, additions, subtractions, multiplications) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to specific functions or sets of functions, other embodiments may include multiple execution units or just one execution unit that all perform all functions. Scheduler unit 456, physical register file unit 458, and execution cluster 460 are shown as possibly plural because some embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each with its own scheduler unit, physical register file unit, and / or execution cluster—and in the case of a separate memory access pipeline, some embodiments are implemented where only the execution cluster of this pipeline has memory access unit 464). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remainder in-order.

[0098] A set of memory access units 464 is coupled to a memory unit 470, which includes a data TLB unit 472 coupled to a data cache unit 474, which is coupled to a level 2 (L2) cache unit 476. In one exemplary embodiment, the memory access units 464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. The instruction cache unit 434 is further coupled to a level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and ultimately to main memory.

[0099] By way of example, the exemplary register renaming, out-of-order issue / execution core architecture may implement the following pipeline 400: 1) instruction fetch 438 performs fetch and length decode stages 402 and 404; 2) decode unit 440 performs decode stage 406; 3) rename / allocator unit 452 performs allocate stage 408 and rename stage 410; 4) scheduler unit 456 performs schedule stage 412; 5) physical register file unit 458 and memory unit 470 perform register read / memory read stage 414; execution cluster 460 performs execute stage 416; 6) memory unit 470 and physical register file unit 458 perform write back / memory write stage 418; 7) various units may be involved in exception handling stage 422; and 8) retirement unit 454 and physical register file unit 458 perform commit stage 424.

[0100] Core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set from MIPS Technologies of Sunnyvale, CA; the ARM instruction set from ARM Holdings of Sunnyvale, CA (with optional additional extensions such as NEON)), including the instructions described herein. In one embodiment, core 490 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0101] It should be understood that a core can support multithreading (running two or more parallel sets of operations or threads) and can do so in a variety of ways, including time-segmented multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads, that physical core is doing simultaneous multithreading), or a combination thereof (e.g., time-segmented fetch and decode followed by simultaneous multithreading such as in Intel® Hyper-Threading Technology).

[0102] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiment of the processor also includes separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of internal caches and external caches external to the cores and / or processors. Alternatively, all caches may be external to the cores and / or processors.

[0103] Certain exemplary in-order core architectures

[0104] Figure 5A -B is a block diagram showing a more specific exemplary in-order core architecture in which a core is one of several logic blocks in a chip (including other cores of the same and / or different types). The logic block communicates with some fixed function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network) depending on the application.

[0105] Figure 5A 5 is a block diagram of a single processor core, along with its connection to the on-die interconnect network 502 and its local subset of the level 2 (L2) cache 504, according to an embodiment of the present invention. In one embodiment, the instruction decoder 500 supports the x86 instruction set with the packed data instruction set extension. The L1 cache 506 allows low-latency access to cache memory in the scalar and vector units. While in one embodiment (to simplify the design), the scalar unit 508 and the vector unit 510 use separate register sets (scalar registers 512 and vector registers 514, respectively), and data transferred between them is written to memory and then read back from the level 1 (L1) cache 506, alternative embodiments of the present invention may use different approaches (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without being written and read back).

[0106] The local subset of the L2 cache 504 is part of the global L2 cache, which is divided into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset of the L2 cache 504. Data read by a processor core is stored in its L2 cache subset 504 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and flushed from other subsets if necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data-path is 1024 bits wide in each direction.

[0107] Figure 5B According to an embodiment of the present invention Figure 5A An expanded view of a portion of a processor core. Figure 5B Includes the L1 data cache 506A portion of the L1 cache 504, as well as more details about the vector unit 510 and vector registers 514. Specifically, the vector unit 510 is a 6-wide vector processing unit (VPU) (see 16-wide ALU 528) that runs one or more of integer, single-precision float, and double-precision float instructions. The VPU supports shuffling register inputs via shuffle unit 520, value conversion via value conversion units 522A-B, and copying via copy unit 524 on memory inputs.

[0108] Processor with integrated memory controller and graphics

[0109] Figure 6 is a block diagram of a processor 600 that may have more than one core, may have an integrated memory controller, and may have integrated graphics, according to an embodiment of the present invention. Figure 6 The solid line box in the figure shows a processor 600 with a single core 602A, a system agent 610, a set of one or more bus controller units 616, while the optional addition of the dashed line box shows an alternative processor 600 with multiple cores 602A-N, a set of one or more integrated memory controller units 614 in the system agent unit 610, and dedicated logic 608.

[0110] Thus, different implementations of processor 600 may include: 1) a CPU with specialized logic 608 that is integrated graphics and / or scientific (throughput) logic (which may include one or more cores) and cores 602A-N that are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination thereof); 2) a coprocessor with cores 602A-N that are a large number of specialized cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor with cores 602A-N that are a large number of general-purpose in-order cores. Thus, processor 600 may be a general-purpose processor, a coprocessor, or a specialized processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput Many Integrated Core (MIC) coprocessor (including 30 or more cores), an embedded processor, and the like. The processor may be implemented on one or more chips. Processor 600 may be implemented on and / or be part of one or more substrates using any of a number of process technologies (such as, for example, BiCMOS, CMOS, or NMOS).

[0111] The memory hierarchy includes one or more levels of cache within cores 604A-N, a set or one or more shared cache units 606, and external memory (not shown) coupled to a set of integrated memory controller units 614. The set of shared cache units 606 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 612 interconnects the integrated graphics logic 608, the set of shared cache units 606, and the system agent unit 610 / integrated memory controller unit 614, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between the one or more cache units 606 and the cores 602A-N.

[0112] In some embodiments, one or more of cores 602A-N may be multi-threaded. System agent 610 includes components that coordinate and operate cores 602A-N. System agent unit 610 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include logic and components required to regulate the power state of integrated graphics logic 608 and cores 602A-N. The display unit is used to drive one or more externally connected displays.

[0113] Cores 602A-N may be homogeneous or heterogeneous with respect to the architectural instruction set; that is, two or more of cores 602A-N may have the capability to run the same instruction set, while other cores may have the capability to run a different instruction set or only a subset of that instruction set.

[0114] Exemplary Computer Architecture

[0115] Figure 7-10 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices that can incorporate a processor and / or other operating logic as disclosed herein are generally suitable.

[0116] Now refer to Figure 7 , shown is a block diagram of a system 700 according to one embodiment of the present invention. System 700 may include one or more processors 710, 715 coupled to a controller hub 720. In one embodiment, controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input / output hub (IOH) 750 (which may be on separate chips); GMCH 790 includes memory and graphics controllers to which memory 740 and coprocessor 745 are coupled; IOH 750 couples input / output (I / O) devices 760 to GMCH 790. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), with memory 740 and coprocessor 745 coupled directly to processor 710 and controller hub 720 in a single chip with IOH 750.

[0117] The optional nature of the additional processor 715 is Figure 7 Each processor 710 , 715 may include one or more of the processing cores described herein and may be a version of processor 600 .

[0118] The memory 740 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 720 communicates with the processors 710, 715 via a multi-drop bus such as a front side bus (FSB), a point-to-point interface, or the like 795.

[0119] In one embodiment, coprocessor 745 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, controller hub 720 may include an integrated graphics accelerator.

[0120] There can be a variety of differences between the physical resources 710, 7155 with respect to the spectrum of specifications including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

[0121] In one embodiment, processor 710 executes instructions that control general types of data processing operations. Embedded within the instructions may be coprocessor instructions. Processor 710 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 745. Accordingly, processor 710 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 745 over a coprocessor bus or other interconnect. Coprocessor 745 accepts and executes the received coprocessor instructions.

[0122] Now refer to Figure 8 , shown is a block diagram of a first more specific exemplary system 800 according to an embodiment of the present invention. Figure 8 As shown in FIG, multiprocessor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each of processors 870 and 880 may be a version of processor 600. In one embodiment of the present invention, processors 870 and 880 are processors 710 and 715, respectively, and coprocessor 838 is coprocessor 745. In another embodiment, processors 870 and 880 are processor 710 and coprocessor 745, respectively.

[0123] Processors 870 and 880 are shown to include integrated memory controller (IMC) units 872 and 882, respectively. Processor 870 also includes point-to-point (PP) interfaces 876 and 878 as part of its bus controller unit; similarly, second processor 880 includes PP interfaces 886 and 888. Using PP interface circuits 878 and 888, processors 870 and 880 can exchange information via point-to-point (PP) interface 850. Figure 8 As shown in FIG, IMCs 872 and 882 couple the processors to respective memories (namely, memory 832 and memory 834), which may be portions of main memory locally attached to the respective processors.

[0124] Using point-to-point interface circuits 876, 894, 886, 898, processors 870, 880 can each exchange information with a chipset 890 via respective PP interfaces 852, 854. Chipset 890 can optionally exchange information with a co-processor 838 via a high-performance interface 892. In one embodiment, co-processor 838 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0125] A shared cache (not shown) may be included in either processor or external to both processors, again connected to the processors via the PP interconnect, such that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0126] Chipset 890 may be coupled to first bus 816 via interface 896. In one embodiment, first bus 816 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as PCI Express or another I / O interconnect bus, although the scope of the invention is not so limited.

[0127] like Figure 8 As shown in , various I / O devices 814 may be coupled to the first bus 816, along with a bus bridge 818 that couples the first bus 816 to a second bus 820. In one embodiment, one or more additional processors 815, such as a co-processor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor, are coupled to the first bus 816. In one embodiment, the second bus 820 may be a low pin count (LPC) bus. Various devices may be coupled to the second bus 820, including, for example, a keyboard and / or mouse 822, communication devices 827, and a storage unit 828, such as a hard drive or other mass storage device, which may include instructions / code and data 830 (in one embodiment). Further, an audio I / O 824 may be coupled to the second bus 816. Note that other architectures are possible. For example, instead of Figure 8 Instead of a point-to-point architecture, the system may implement a multi-point bus or another such architecture.

[0128] Now refer to Figure 9 , shown is a block diagram of a second more specific exemplary system 900 according to an embodiment of the present invention. Figure 8 and 9 Like elements in FIG. 1 are marked with like reference numerals, and Figure 8 Some aspects of Figure 9 Omitted to avoid Figure 9 Other aspects are difficult to understand.

[0129] Figure 9 It is shown that processors 870, 880 may respectively include integrated memory and I / O control logic ("CL") 972 and 982. Thus, CL 972, 982 includes an integrated memory controller unit and includes I / O control logic. Figure 9 Not only are memories 832, 834 shown coupled to CL 872, 882, but I / O devices 914 are also shown coupled to control logic 872, 882. Legacy I / O devices 915 are coupled to chipset 890.

[0130] Now refer to Figure 10 , shown is a block diagram of a SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements in the SoC are labeled with similar reference numerals. Likewise, dashed boxes are optional features on more advanced SoCs. Figure 10 In the embodiment, the interconnect unit 1002 is coupled to: an application processor 1010, which includes a set of one or more cores 102A-N, cache units 604A-N, and a shared cache unit 606; a system agent unit 610; a bus controller unit 616; an integrated memory controller unit 614; a set or one or more co-processors 1020, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, the co-processors 1020 include special-purpose processors such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, and the like.

[0131] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the present invention may be implemented as program code or a computer program running on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0132] Such as Figure 8The program code shown in code 830 can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor (such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor).

[0133] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. If desired, the program code can also be implemented in assembly or machine language. In fact, the mechanisms described herein are not limited to the scope of any specific programming language. In any case, the language can be a compiled or interpreted language.

[0134] One or more aspects of at least one embodiment may be implemented as representative instructions stored on a machine-readable medium, which represents various logic within a processor and, when read by a machine, causes the machine to fabricate logic for performing the techniques described herein. Such representations (known as "IP cores") may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to be loaded into fabrication machines that actually make the logic or processor.

[0135] Such machine-readable storage media may include, without limitation, a non-transitory, tangible arrangement of an article made or formed by a machine or device, including storage media (such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions).

[0136] Therefore, embodiments of the present invention also include non-transitory, tangible, machine-readable media containing instructions or containing design data, such as hardware description language (HDL), which define the structures, circuits, devices, processors and / or system features described herein. Such embodiments may also be referred to as program products.

[0137] Emulation (including binary conversion, code deformation, etc.)

[0138] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may convert (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert instructions into one or more other instructions to be processed by the core. The instruction converter is implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on the processor, off the processor, or partially on the processor and partially off the processor.

[0139] Figure 11 1 is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 11 It is shown that using a first compiler 1104, a program in a high-level language 1102 can be compiled to generate a first binary code (e.g., x86) 1106 that can be natively executed by a processor 1116 with at least one first instruction set core. In some embodiments, the processor 1116 with at least one first instruction set core represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly running or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core, or (2) an object code version of an application or other software that is intended to run on an Intel processor with at least one x86 instruction set core, so as to achieve substantially the same results as an Intel processor with at least one x86 instruction set core. The first compiler 1104 represents a compiler that is operable to generate binary code 1106 (e.g., object code) of a first instruction set that can be executed on a processor 1116 with at least one first instruction set core, with or without additional linking processing. Similarly, Figure 11Using an alternative instruction set compiler 1108, a program in a high-level language 1102 can be compiled to generate alternative instruction set binary code 1110, which can be natively executed by a processor 1114 that does not have at least one first instruction set core (e.g., a processor with a core running the MIPS instruction set from MIPS Technologies of Sunnyvale, CA and / or the ARM instruction set from ARM Holdings of Sunnyvale, CA). An instruction converter 1112 is used to convert the first binary code 1106 into code that can be natively executed by the processor 1114 that does not have a first instruction set core. This converted code is unlikely to be identical to the alternative instruction set binary code 1110, as an instruction converter capable of doing so would be difficult to create; however, the converted code will perform general operations and be composed of instructions from the alternative instruction set. Thus, instruction converter 1112 represents software, firmware, hardware, or a combination thereof that allows a processor or another electronic device that does not have a first instruction set processor or core to execute the first binary code 1106 through emulation, simulation, or any other process.

[0140] Apparatus and method for digital signal processing instructions

[0141] The following describes digital signal processing (DSP) instructions. In one embodiment, the circuits and logic for performing DSP operations are integrated into Figure 4B , in the execution engine unit 450 shown in FIG, in the various cores described above (see, for example, Figure 6 and 10 within the cores 602A-N in the Figure 5A For example, the various source and destination registers may be Figure 4B SIMD registers within the physical register file unit 458 and / or Figure 3 The vector register 310 in the following multiplication circuit, adder circuit, accumulation circuit and other circuits can be integrated into the execution component of the above architecture, as an example and not limitation, the execution component includes Figure 4B However, it should be noted that the underlying principles of the present invention are not limited to these specific architectures.

[0142] One embodiment of the present invention includes circuitry and / or logic for processing digital signal processing (DSP) instructions. In particular, one embodiment includes a multiply-accumulate (MAC) architecture with eight 16×16-bit multipliers and two 64-bit accumulators. The instruction set architecture (ISA) described below can handle various multiplication and MAC operations on 128-bit packed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. In addition, certain instructions directly support efficient fast Fourier transform (FFT) and finite impulse response (FIR) filtering, as well as post-processing of accumulated data through shift, rounding, and saturation operations.

[0143] One embodiment of the new DSP instructions uses opcode encoding based on the VEX.128 prefix, and several SSE / SSE2 / AVX instructions that handle post-processing of data are used with the DSP ISA. VEX-encoded 128-bit DSP instructions with memory operands may have relaxed memory alignment requirements.

[0144] In one embodiment, the instruction also supports various integer and fixed-point data types, including:

[0145] 1) The Q31 data type is used for signals requiring analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) greater than 16 bits;

[0146] 2) Q15 data types commonly used in DSP algorithms;

[0147] 3) complex 16-bit data types; and

[0148] 4) Complex 32-bit data types.

[0149] The instruction set architecture described herein targets a wide range of standard DSP (eg, FFT, filtering, pattern matching, correlation, polynomial evaluation, etc.) and statistical operations (eg, mean, moving average, variance, etc.).

[0150] Target applications of embodiments of the present invention include sensors, audio, classification tasks for computer vision, and speech recognition. The DSP ISA described herein includes a wide range of instructions suitable for deep neural networks (DNNs), automatic speech recognition (ASR), sensor fusion with Kalman filtering, and other major DSP applications. Given a weight sequence {w1, w2, ... w k} and the input sequence {x1, x2, x3, ...x n Many image processing and machine learning tasks require computing the i =w1x i +w2x i+1 +.................+w k xi+k-1所定义的结果序列{ y1, y2, y3, ...y n+1-k}.

[0151] Figure 12 An exemplary processor 1255 is shown on which embodiments of the present invention may be implemented, including multiple cores 0-N for executing multiple instruction threads simultaneously. The illustrated embodiment includes DSP instruction decoding circuitry / logic 1231 within decoder 1230 and DSP instruction execution circuitry / logic 1341 within execution unit 1240. These pipeline components may perform the operations described herein in response to decoding and executing DSP instructions. Although Figure 12 Only details of a single core (Core 0) are shown in FIG, but it will be understood that each of the other cores of processor 1255 may include similar components.

[0152] Before describing the specific details of embodiments of the present invention, a description of the various components of an exemplary processor 1255 is provided directly below. Each of the plurality of cores 0-N may include a memory management unit 1290 for performing memory operations (e.g., such as load / store operations), a set of general purpose registers (GPRs) 1205, a set of vector registers 1206, and a set of mask registers 1207. In one embodiment, multiple vector data elements are packed into each vector register 1206. Each vector register 1206 may have a width of 512 bits for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, and so on. However, the underlying principles of the present invention are not limited to any particular size / type of vector data. In one embodiment, mask registers 1207 include eight 64-bit operand mask registers for performing bit-masking operations on values ​​stored in vector registers 1206 (e.g., implemented as mask registers k0-k7 as described herein). However, the underlying principles of the present invention are not limited to any particular mask register size / type.

[0153] Each core 0-N may include a dedicated Level 1 (L1) cache 1212 and a Level 2 (L2) cache 1211 for caching instructions and data according to a specified cache management policy. The L1 cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. Instructions and data stored in the various processor caches are managed at the granularity of a cache line, which may be a fixed size (e.g., 64, 128, or 512 bytes in length). Each core of this exemplary embodiment has an instruction fetch unit 1210 for fetching instructions from main memory 1200 and / or a shared Level 3 (L3) cache 1216. The instruction fetch unit 1210 includes various well-known components, including: a next instruction pointer 1203 for storing the address of the next instruction to be fetched from the memory 1200 (or one of the caches); an instruction translation lookaside buffer (ITLB) 1204 for storing mappings of recently used virtual to physical instruction addresses to improve the speed of address translation; a branch prediction unit 1202 for speculatively predicting instruction branch addresses; and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0154] As mentioned above, decode unit 1230 includes DSP instruction decode circuitry / logic 1231 for decoding the DSP instructions described herein into micro-operations or "uops," and execution unit 1240 includes DSP instruction execution circuitry / logic 1241 for executing DSP instructions. Writeback / retirement unit 1250 retires executed instructions and writes back results.

[0155] Embodiments for performing double signed and unsigned multiplication of packed data elements

[0156] One embodiment of the present invention includes a first instruction for performing a vector packed double unsigned multiply operation. Specifically, execution of the first instruction multiplies a first packed unsigned doubleword (32 bits) selected from a packed quadword in a first source register with a second packed signed doubleword selected from another packed quadword in a second source register. In one embodiment, the 64-bit unsigned result is written to each of the two quadwords (64 bits) of a destination register, which may be a 128-bit register. One embodiment of the first instruction is represented as VPMULUDHHQ xmm0,xmm1,xmm2 / m128, where xmm1 and xmm2 are the two source registers and xmm0 is the destination register.

[0157] One embodiment includes a second instruction for performing a vector packed double signed multiply operation. Execution of the second instruction multiplies a first packed signed doubleword (32 bits) selected from a packed quadword in a first source register with a second packed signed doubleword selected from a packed quadword in a second source register. In one implementation, the 64-bit signed result is written to each of the two quadwords (64 bits) of a destination register, which may be a 128-bit register. One embodiment of the first instruction is represented as VPMULDHHQ xmm0,xmm1,xmm2 / m128, where xmm1 and xmm2 are the two source registers and xmm0 is the destination register.

[0158] Figure 13 Exemplary data elements and bit distributions for exemplary source and / or destination registers (SRCx / DESTx) are shown. As shown, data elements can be packed into the source and / or destination registers as words (16 bits), doublewords (32 bits), and / or quadwords (64 bits). In some embodiments that process complex numbers, the real and imaginary components can be stored in adjacent data element positions. For example, a real component can be stored as data element A, and the corresponding imaginary component can be stored as data element B. However, in other embodiments described herein (such as the 32×32 packed doubleword multiply instruction), the packed data elements BA, DC, FE, and HG do not represent complex numbers.

[0159] Figure 14A An exemplary architecture for executing packed multiplication instructions is shown. As mentioned above, these instructions can use data stored in Figure 14A The two packed source data operands are in registers SRC1 1401 and SRC2 1402. In the illustrated embodiment, SRC1 1401 stores doubleword data elements BA and FE, and source register SRC2 1402 stores doubleword data elements BA and FE.

[0160] Note that in some embodiments, it is not necessary to Figure 14A Certain components shown in FIG14 , such as accumulators 1420 - 1421 and saturation circuits 1440 - 1441 , are used to perform the described operations. In this case, it is assumed that the data simply passes through these circuits without modification.

[0161] In one embodiment, multiplier 1405 performs a multiplication of two doublewords simultaneously. For example, the first and second doublewords from the upper portion of each quadword in SRC1 (e.g., SRC1[63:32] and SRC1[127:96]) are multiplied by the corresponding first and second doublewords from the upper portion of each quadword in SRC2 (e.g., SRC2[63:32] and SRC2[127:96]). The 64-bit results of the multiplications are then stored in each quadword of the 128-bit destination. For example, the result of the multiplication SRC1[63:32]*SRC2[63:32] may be stored in DEST[63:0], while the result of the multiplication SRC1[127:96]*SRC2[127:96] may be stored in DEST[127:64]. This can be represented as:

[0162] DEST[63:0]←SRC1[63:32]*SRC2[63:32];

[0163] DEST[127:64]←SRC1[127:96]*SRC2[127:96];

[0164] As mentioned above, one instruction (e.g., VPMULUDHHQ) can be executed to perform an unsigned multiplication where the source values ​​SRC1[63:32], SRC2[63:32], SRC1[127:96], and SRC2[127:96] and the result data elements DEST[63:0] and DEST[127:64] are unsigned. In one embodiment, a second instruction is executed to perform a signed multiplication where the source values ​​and the result data elements are signed (e.g., VPMULDHHQ).

[0165] In one embodiment, the shift operations described below can be performed on the four-word result stored in the destination register. For example, the result can be right-shifted or left-shifted, and the most significant portion of the shifted result can be stored in the least significant portion of the destination register. In addition, saturation and / or routing can be performed to generate the final result.

[0166] Figure 15 A method according to an embodiment of the present invention is shown in The method can be implemented within the context of the processor and system architecture described above, but is not limited to any particular system architecture.

[0167] At 1501, a first instruction is retrieved, having fields for an opcode and first and second packed data source operands and a packed data destination operand. At 1502, the first instruction is decoded to generate a first decoded instruction (e.g., into a plurality of micro-operations). At 1503, two unsigned doubleword values ​​associated with each of the first and second operands are retrieved and stored as double packed doubleword data elements in each of the first and second source registers, respectively. As mentioned above, in one embodiment, the source operands are stored in 128-bit packed data registers having packed doubleword (32-bit) data elements.

[0168] At 1504, a first decoded instruction is executed to multiply a first unsigned doubleword data element from a first source register with a second unsigned doubleword data element from a second source register to generate a first unsigned quadword product and simultaneously multiply a third unsigned doubleword data element from the first source register with a fourth unsigned doubleword data element from the second source register to produce a second unsigned quadword product.

[0169] At 1505, the shift operations described herein may be performed on the first and second quadword results. For example, the result may be right-shifted or left-shifted, and the most significant portion of the shifted result may be stored in the least significant portion of the destination register. Additionally, saturation and / or routing may be performed to generate the final result.

[0170] Figure 16 A method according to an embodiment of the present invention is shown in FIG. The method can be implemented in the context of the above-mentioned processor and system architecture, but is not limited to any particular system architecture.

[0171] At 1601, a first instruction is retrieved, having fields for an opcode and first and second packed data source operands and a packed data destination operand. At 1602, the first instruction is decoded to generate a first decoded instruction (e.g., into a plurality of micro-operations). At 1603, two signed doubleword values ​​associated with each of the first and second operands are retrieved and stored as double packed doubleword data elements in each of the first and second source registers, respectively. As mentioned above, in one embodiment, the source operands are stored in 128-bit packed data registers having packed doubleword (32-bit) data elements.

[0172] At 1604, a first decoded instruction is executed to multiply a first signed doubleword data element from a first source register with a second signed doubleword data element from a second source register to produce a first signed quadword product and simultaneously multiply a third signed doubleword data element from the first source register with a fourth signed doubleword data element from the second source register to produce a second signed quadword product.

[0173] At 1605, the shift operations described herein may be performed on the first and second quadword results. For example, the result may be right-shifted or left-shifted, and the most significant portion of the shifted result may be stored in the least significant portion of the destination register. Additionally, saturation and / or routing may be performed to generate the final result.

[0174] Moving data elements and extracting data

[0175] One embodiment of the present invention includes instructions for performing various right and left shift operations on bits in each of a plurality of aligned unsigned quadwords (e.g., such as the results of the unsigned multiplication described above). For example, in one embodiment, the quadword is right shifted in a first packed data register or memory location (e.g., xmm2 / m128), where a 6-bit count is specified in imm8[5:0]. The most significant 16 bits [63:48] of each shifted quadword are written to bits [15:0] of the corresponding quadword in a destination register (e.g., xmm1). In one embodiment, a logical right shift of the bits in each aligned unsigned quadword is performed in a first source register (e.g., xmm2), where a 6-bit count is specified in a second source register or memory location (e.g., xmm3 / m128[5:0], xmm3 / m128[69:64]). The most significant 16 bits [63:48] of each shifted quadword are written to bits [15:0] of the corresponding quadword in a destination register (e.g., xmm1). In one embodiment, during the right shift for each aligned unsigned quadword, 0 is shifted into the most significant bit.

[0176] The upper word result may be extracted from each right-shifted quadword, with the arithmetic flag unaffected. The shifted upper 16 bits from each quadword may be rounded and saturated to a word based on the rounding control. If saturation occurs, the saturation flag may be set (e.g., in the MXCSR status register).

[0177] One embodiment also includes instructions for performing a logical left shift of the bits in each unsigned quadword. For example, the bits in each aligned unsigned quadword in a source register or memory location (e.g., xmm1 / m128) are logically shifted left, where a 6-bit count is specified in imm8[5:0]. The most significant 16 bits [63:48] of each shifted quadword are written to bits [15:0] of the corresponding quadword in the destination register (e.g., xmm1). One embodiment performs a logical left shift of the bits in each aligned unsigned quadword in a first source register (e.g., xmm2), where a 6-bit count is specified in a second source register or memory location (e.g., xmm3 / m128[5:0], xmm3 / m128[69:64]). The most significant 16 bits [63:48] of each shifted quadword are written to bits [15:0] of the corresponding quadword in the destination register (e.g., xmm1).

[0178] One embodiment shifts zeros into the least significant bits (LSBs) during the left shift for each aligned unsigned quadword. This embodiment extracts the upper word result from each left-shifted quadword without affecting the arithmetic flag. The shifted upper 16 bits from each quadword are rounded and saturated to a doubleword based on the rounding control. If saturation occurs, the saturation flag can be set in a status / control register (e.g., the MXCSR status register).

[0179] The shift operations described herein can be performed in response to execution of a single instruction. These can include VPSRLRSDUQ and VPSRLVRSDUQ, which perform a logical right shift of a packed quadword by an amount based on an immediate value and a source operand, respectively. Additionally, left shift instructions include VPSLLRSDUQ and VPSLLVRSDUQ, which perform a logical left shift of a packed quadword by an amount based on an immediate value and a source operand, respectively.

[0180] Figure 17 1701 (e.g., imm8[5:0]), shift unit 1703 shifts the value in each quadword right by N bits, storing the result in a temporary register or memory location 1720. Assuming that 6 immediate digit bits are used to identify the shift amount in this embodiment, N can have a value from 0 to 64 (i.e., 2 6 =64). Figure 17In the particular example shown in , bits b64 and b63 are shown shifted by the value of N, which is between 0 and 64. In one embodiment, shift unit 1703 inserts zeros in the bit positions from which values ​​are shifted. Thus, in the example shown, the most significant bit positions occupied by b64, b63, and b62 are filled with zeros.

[0181] In one embodiment, after the shift operation, the 32 most significant bits of each shifted quadword are written to the least significant 32 bits of destination register 1460. In the example shown, bits b64 and b63 are included in the most significant bits. However, it should be noted that this will not always be the case. For example, if the value of N is 32 or greater, bit b64 will be shifted out of the range of the most significant 32 bits, which will be filled with all zeros. When this occurs, all zeros are written to the least significant bit positions in destination register 1460.

[0182] As mentioned above, in one embodiment, a 32-bit result can be extracted from each right-shifted quadword without affecting the arithmetic flag in the processor. Additionally, if desired, the shifted upper 32 bits from each quadword can be rounded and saturated to a word based on rounding control. If saturation occurs, the saturation flag 1710 (e.g., in the MXCSR status register) can be set. Round / saturation circuit 1704 can perform rounding and / or saturation operations on the value written to the least significant bit position of each quadword.

[0183] In one embodiment, the shift unit 1703 is integrated into Figure 14A The shift unit 1703 and the rounding circuit may be implemented as a saturation circuit. Figure 14A The architecture components shown in the figure are separated by circuit / logic.

[0184] Figure 18 An embodiment is shown in which a shift value (N) that specifies the amount by which the shift unit 1703 is to shift two quadwords right is specified in another source register, such as SRC3 1402. The 6-bit value may be stored in the least significant position or the most significant position of a packed data element, such as a packed byte or packed word, with bits outside the 6 being set to zero or ignored. In one embodiment, the operation of the shift unit 1703 is substantially the same as described above for Figure 17 The operations are the same as described.

[0185] Figure 191701 (e.g., imm8[5:0]), shift unit 1703 shifts the value in each quadword left by N bits, storing the result in a temporary register or memory location 1720. Assuming that 6 immediate digit bits are used to identify the shift amount in this embodiment, N can have a value from 0 to 64 (i.e., 2 6 =64). Figure 19 In the particular example shown in , bits b0, b1, and b2 are shown shifted by a value of N, which is between 0 and 64. In one embodiment, shift unit 1703 inserts zeros in the bit positions from which the quad-bit value is shifted. Thus, in the example shown, the least significant bit positions occupied by b0, b1, and b2 are filled with zeros.

[0186] In one embodiment, after the shift operation, the 32 most significant bits of each shifted quadword are written to the least significant 32 bits of the destination register 1460. In the example shown, bits b2, b1, and b0 are included in the most significant bits. However, it should be noted that this will not always be the case. For example, if the value of N is less than 32, then bit b0 will be in the lower 32 bits of the resulting quadword (i.e., it will not be included in the most significant 32 bits). Similarly, if N is 64, then the shifted quadword is filled with all zeros, and all zeros will be written to the least significant bit positions in the destination register 1460.

[0187] As mentioned above, in one embodiment, a 32-bit result can be extracted from each left-shifted quadword without affecting the arithmetic flag in the processor. Additionally, if desired, the shifted upper 32 bits from each quadword can be rounded and saturated to a word based on rounding control. If saturation occurs, the saturation flag 1710 (e.g., in the MXCSR status register) can be set. Round / saturation circuit 1704 can perform rounding and / or saturation operations on the value written to the least significant bit position of each quadword.

[0188] Figure 20 An embodiment is shown in which a shift value (N) that specifies the amount by which the shift unit 1703 is to shift two quadwords right is specified in another source register, such as SRC2 1402. The 6-bit value may be stored in the least significant position or the most significant position of a packed data element, such as a packed byte or packed word, with bits outside the 6 being set to zero or ignored. In one embodiment, the operation of the shift unit 1703 is substantially the same as described above for Figure 17 The operations are the same as described.

[0189] Vector packed multiplication signed / unsigned bytes with accumulate

[0190] One embodiment of the present invention includes a first instruction for performing a vector packed unsigned byte multiply operation followed by an accumulation with an existing doubleword value. Specifically, execution of the first instruction multiplies 16 packed unsigned bytes from a first source register with 16 corresponding packed unsigned bytes from a second source register to generate 16 unsigned products. Four sets of 16 unsigned products are accumulated to generate four temporary results. The four temporary results are then accumulated with the unsigned doubleword value from a destination register, and the results are stored back to the destination register. In one embodiment, the four temporary results are zero-extended before the accumulation is performed. One embodiment of the first instruction is represented as VPDPBUUD xmm1,xmm2,xmm3 / m128, where xmm1, xmm2, and xmm3 are source registers and xmm3 is a destination register.

[0191] One embodiment of the present invention includes a second instruction for performing a vector packed signed byte multiplication operation followed by an accumulation with an existing doubleword value. Specifically, execution of the first instruction multiplies 16 packed signed bytes from a first source register with 16 corresponding packed signed bytes from a second source register to generate 16 signed products. Four sets of 16 signed products are accumulated to generate four temporary results. The four temporary results are then accumulated with the signed doubleword value from the destination register, and the results are stored back to the destination register. In one embodiment, the four temporary results are zero-extended before the accumulation is performed. One embodiment of the first instruction is represented as VPDPBSSD xmm1,xmm2,xmm3 / m128, where xmm1, xmm2, and xmm3 are source registers and xmm3 is a destination register.

[0192] Figure 14B Shown with Figure 14AMany of the same components are used, with one difference being that the output of destination register 1460 operates as a third source register for the accumulation operation described herein, as indicated by data lines 1470-1471. In one embodiment, multiplier 1405 simultaneously performs 16 unsigned / signed byte multiplications by multiplying each byte in SRC1 1401 with the corresponding byte in SRC2 1402 to generate 16 unsigned / signed products. In one embodiment, adder network 1410-1411 then adds four sets of four unsigned / signed products to generate four temporary results, which can be stored in temporary registers or memory locations. Each of the four temporary results is then zero-extended and added to the corresponding 32-bit data element from destination register 1460 to generate the final result. The final result is then written back to the corresponding data element position in the destination register.

[0193] In one embodiment, a vector packed unsigned multiply and accumulate is represented as:

[0194] TEMP0[17:0]←((SRC2[31:24]*SRC3[31:24])+

[0195] (SRC2[23:16]*SRC3[23:16])+

[0196] (SRC2[15:8]*SRC3[15:8])+

[0197] (SRC2[7:0]*SRC3[7:0]));

[0198] TEMP1[17:0]←((SRC2[63:56]*SRC3[63:56])+

[0199] (SRC2[55:48]*SRC3[55:48])+

[0200] (SRC2[47:40]*SRC3[47:40])+

[0201] (SRC2[39:32]*SRC3[39:32]));

[0202] TEMP2[17:0]←((SRC2[95:88]*SRC3[95:88])+

[0203] (SRC2[87:80]*SRC3[87:80])+

[0204] (SRC2[79:72]*SRC3[79:72])+

[0205] (SRC2[71:64]*SRC3[71:64]));

[0206] TEMP3[17:0]←((SRC2[127:120]*SRC3[127:120])+

[0207] (SRC2[119:112]*SRC3[119:112])+

[0208] (SRC2[111:104]*SRC3[111:104])+

[0209] (SRC2[103:96]*SRC3[103:96]));

[0210] DEST[31:0]←AddToDword({14'b0, TEMP0[17:0]}, DEST[31:0]);

[0211] DEST[63:32]←AddToDword({14'b0, TEMP1[17:0]}, DEST[63:32]);

[0212] DEST[95:64]←AddToDword({14'b0, TEMP2[17:0]}, DEST[95:64]);

[0213] DEST[127:96]←AddToDword({14'b0, TEMP3[17:0]}, DEST[127:96]);

[0214] In the above code, multiplier 1405 performs the above multiplication to generate the above product. Adder network 1410 adds the products SRC2[31:24]*SRC3[31:24], SRC2[23:16]*SRC3[23:16], SRC2[15:8]*SRC3[15:8], and SRC2[7:0]*SRC3[7:0], storing the 17-bit result in TEMP0, and adds the products SRC2[63:56]*SRC3[63:56], SRC2[55:48]*SRC3

[55] :48], SRC2[47:40]*SRC3[47:40], and SRC2[39:32]*SRC3[39:32], storing the 17-bit result in TEMP1.

[0215] Similarly, adder network 1411 adds the products SRC2[95:88]*SRC3[95:88], SRC2[87:80]*SRC3[87:80], SRC2[79:72]*SRC3[79:72], SRC2[71:64]*SRC3[71:64] and stores the 17-bit result in TEMP2, and also adds SRC2[127:120]*SRC3[127:120], SRC2[119:112]*SRC3[119:112], SRC2[111:104]*SRC3[111:104], SRC2[103:96]*SRC3[103:96] and stores the 17-bit result in TEMP3.

[0216] The AddToDword operation then zero-extends each 17-bit result to 32 bits and adds each resulting 32-bit value to one of the four doublewords stored in the destination register. The final result is then stored back into the corresponding doubleword location in the destination register.

[0217] In one embodiment, vector packed signed multiply and accumulate is represented as:

[0218] TEMP0[17:0]←((SRC2[31:24]*SRC3[31:24])+

[0219] (SRC2[23:16]*SRC3[23:16])+

[0220] (SRC2[15:8]*SRC3[15:8])+

[0221] (SRC2[7:0]*SRC3[7:0]));

[0222] TEMP1[17:0]←((SRC2[63:56]*SRC3[63:56])+

[0223] (SRC2[55:48]*SRC3[55:48])+

[0224] (SRC2[47:40]*SRC3[47:40])+

[0225] (SRC2[39:32]*SRC3[39:32]));

[0226] TEMP2[17:0]←((SRC2[95:88]*SRC3[95:88])+

[0227] (SRC2[87:80]*SRC3[87:80])+

[0228] (SRC2[79:72]*SRC3[79:72])+

[0229] (SRC2[71:64]*SRC3[71:64]));

[0230] TEMP3[17:0]←((SRC2[127:120]*SRC3[127:120])+

[0231] (SRC2[119:112]*SRC3[119:112])+

[0232] (SRC2[111:104]*SRC3[111:104])+

[0233] (SRC2[103:96]*SRC3[103:96]));

[0234] DEST[31:0]←AddToDword({14{TEMP0

[17] }, TEMP0[17:0]}, DEST[31:0]);

[0235] DEST[63:32]←AddToDword({14{TEMP1

[17] }, TEMP1[17:0]}, DEST[63:32]);

[0236] DEST[95:64]←AddToDword({14{TEMP2

[17] }, TEMP2[17:0]}, DEST[95:64]);

[0237] DEST[127:96]←AddToDword({14{TEMP3

[17] }, TEMP3[17:0]}, DEST[127:96]);

[0238] In the above code, multiplier 1405 performs the above multiplication to generate the above product. Adder network 1410 adds the products SRC2[31:24]*SRC3[31:24], SRC2[23:16]*SRC3[23:16], SRC2[15:8]*SRC3[15:8], and SRC2[7:0]*SRC3[7:0], storing the 17-bit result in TEMP0, and adds the products SRC2[63:56]*SRC3[63:56], SRC2[55:48]*SRC3

[55] :48], SRC2[47:40]*SRC3[47:40], and SRC2[39:32]*SRC3[39:32], storing the 17-bit result in TEMP1.

[0239] Similarly, adder network 1411 adds the products SRC2[95:88]*SRC3[95:88], SRC2[87:80]*SRC3[87:80], SRC2[79:72]*SRC3[79:72], SRC2[71:64]*SRC3[71:64] and stores the 17-bit result in TEMP2, and adds SRC2[127:120]*SRC3[127:120], SRC2[119:112]*SRC3[119:112], SRC2[111:104]*SRC3[111:104], SRC2[103:96]*SRC3[103:96] and stores the 17-bit result in TEMP3.

[0240] The AddToDword operation then sign-extends each 17-bit result to 32 bits and adds each resulting 32-bit value to one of the four doublewords stored in the destination register. The final result is then stored back into the corresponding doubleword location in the destination register.

[0241] In one embodiment, the shift, rounding, and saturation operations described herein can be performed on a doubleword result stored in a destination register. For example, the result can be right-shifted or left-shifted, and the most significant portion of the shifted result can be stored in the least significant portion of the destination register. Additionally, saturation and / or routing can be performed to generate the final result.

[0242] exist Figure 21 A method according to an embodiment of the present invention is shown in FIG. The method can be implemented in the context of the above-mentioned processor and system architecture, but is not limited to any particular system architecture.

[0243] At 2101, a first instruction having fields for an opcode and first, second, and third packed data source operands and a packed data destination operand is retrieved. At 2102, the first instruction is decoded to generate a first decoded instruction (e.g., decoded into a plurality of micro-ops). At 2103, first and second groups of 16 unsigned bytes are retrieved for each of the first and second operands, respectively, and stored in each of the first and second source registers as packed unsigned byte data elements, respectively.

[0244] At 2104, the first decoded instruction is executed to multiply each byte from the first source register with the corresponding byte in the second source register to generate 16 unsigned products. At 2105, four of the unsigned products are added in each of the four groups to generate four temporary results.

[0245] At 2106, each of the four temporary results is zero-extended and accumulated with one of the unsigned doubleword values ​​stored in a third source register, which may be the same physical register as the destination register. For example, each of the four temporary results TEMP0, TEMP1, TEMP2, and TEMP3 may be extended to 32 bits and added to the current value in DEST 1460 at doubleword data element positions AB, CD, EF, and GH, respectively (see Figure 14A At 2107 , each final unsigned result is stored in a packed doubleword data element position in destination register DEST 1460 .

[0246] Although not in Figure 21 , but the shift operations described herein may be performed on the final unsigned result. For example, the result may be right-shifted or left-shifted, and the most significant portion of the shifted result may be stored in the least significant portion of the destination register. Additionally, saturation and / or routing may be performed to generate the final result.

[0247] exist Figure 22 A method according to an embodiment of the present invention is shown in FIG. The method can be implemented in the context of the above-mentioned processor and system architecture, but is not limited to any particular system architecture.

[0248] At 2201, a first instruction having fields for an opcode and first, second, and third packed data source operands and a packed data destination operand is retrieved. At 2202, the first instruction is decoded to generate a first decoded instruction (e.g., decoded into a plurality of micro-ops). At 2203, first and second groups of 16 signed bytes are retrieved for each of the first and second operands, respectively, and stored in each of the first and second source registers, respectively, as packed signed byte data elements.

[0249] At 2204, the first decoded instruction is executed to multiply each byte from the first source register with the corresponding byte in the second source register to generate 16 signed products. At 2205, four of the signed products are added in each of the four groups to generate four temporary results.

[0250] At 2206, each of the four temporary results is sign-extended and accumulated with one of the signed doubleword values ​​stored in a third source register, which may be the same physical register as the destination register. For example, each of the four temporary results TEMP0, TEMP1, TEMP2, and TEMP3 may be sign-extended to 32 bits and added to the current value in DEST 1460 at doubleword data element positions AB, CD, EF, and GH, respectively (see Figure 14BAt 2207 , each final signed result is stored in a packed doubleword data element position in destination register DEST 1460 .

[0251] Although not in Figure 22 , but the shift operations described herein may be performed on the final signed result. For example, the result may be right-shifted or left-shifted, and the most significant portion of the shifted result may be stored in the least significant portion of the destination register. Additionally, saturation and / or routing may be performed to generate the final result.

[0252] This application provides the following technical solutions:

[0253] Technical Solution 1. A processor comprising:

[0254] a decoder for decoding the first instruction to generate a decoded instruction;

[0255] a first source register for storing a first plurality of packed doubleword data elements;

[0256] a second source register for storing a second plurality of packed doubleword data elements; and

[0257] an execution circuit, the execution circuit being configured to execute the decoded instruction, the execution circuit comprising:

[0258] multiplier circuitry for multiplying a first doubleword data element from the first source register by a second doubleword data element from the second source register to produce a first quadword product, and for simultaneously multiplying a third doubleword data element from the first source register by a fourth doubleword data element from the second source register to produce a second quadword product; and

[0259] A destination register is provided for storing the first quadword product and the second quadword product as first and second packed quadword data elements.

[0260] Technical Solution 2. The processor according to Technical Solution 1, further comprising:

[0261] Shift circuitry is provided for shifting the first and second packed quadword data elements right or left by an amount based on the immediate data or value in the third source register to generate first and second shifted results, respectively.

[0262] Technical Solution 3. A processor as described in Technical Solution 2, wherein the shift circuit is further used to select first and second groups of most significant bits from the first and second shifted results, respectively, and to store the first and second groups of most significant bits in the first and second least significant bit positions of the packed quad-word position in the destination register.

[0263] Technical Solution 4. The processor according to Technical Solution 2, wherein the third source register and the destination register are the same physical register.

[0264] Technical Solution 5. The processor according to Technical Solution 3 further includes a rounding circuit, wherein the rounding circuit is used to round the first and second shifted results.

[0265] Technical Solution 6. The processor according to Technical Solution 5, further comprising:

[0266] A saturation circuit is provided for saturating the first and second shifted results when necessary and for setting a saturation flag in a control register.

[0267] Technical Solution 7. The processor according to Technical Solution 1, wherein the first and second groups of most significant bits include 32 most significant bits.

[0268] Technical Solution 8. The processor of Technical Solution 1, wherein the first, second, third, and fourth doubleword data elements comprise unsigned data elements.

[0269] Technical Solution 9. The processor of Technical Solution 1, wherein the first, second, third, and fourth doubleword data elements comprise signed data elements.

[0270] Technical Solution 10. A method comprising:

[0271] decoding the first instruction to generate a decoded instruction;

[0272] storing a first plurality of packed doubleword data elements in a first source register;

[0273] storing a second plurality of packed doubleword data elements in a second source register; and

[0274] multiplying a first doubleword data element from the first source register by a second doubleword data element from the second source register to produce a first quadword product, and simultaneously multiplying a third doubleword data element from the first source register by a fourth doubleword data element from the second source register to produce a second quadword product; and

[0275] The first quadword product and the second quadword product are stored as first and second packed quadword data elements in a destination register.

[0276] Technical Solution 11. The method according to Technical Solution 10, further comprising:

[0277] The first and second packed quadword data elements are shifted right or left by an amount based on the immediate data or value in the third source register to generate first and second shifted results, respectively.

[0278] Technical Solution 12. A method as described in Technical Solution 11, wherein the shift circuit is also used to select first and second groups of most significant bits from the first and second shifted results, respectively, and to store the first and second groups of most significant bits in the first and second least significant bit positions of the packed quad-word position in the destination register.

[0279] Technical Solution 13. The method as described in Technical Solution 11, wherein the third source register and the destination register are the same physical register.

[0280] Technical Solution 14. The method according to Technical Solution 12 further includes a rounding circuit for rounding the first and second shifted results.

[0281] Technical Solution 15. The method according to Technical Solution 14 further includes:

[0282] The first and second shifted results are saturated when necessary and a saturation flag is set in a control register.

[0283] Technical Solution 16. The method as described in Technical Solution 10, wherein the first and second groups of most significant bits include 32 most significant bits.

[0284] Technical Solution 17. The method of Technical Solution 10, wherein the first, second, third, and fourth doubleword data elements comprise unsigned data elements.

[0285] Technical Solution 18. The method of Technical Solution 10, wherein the first, second, third, and fourth doubleword data elements comprise signed data elements.

[0286] Technical Solution 19. A machine-readable medium having program code stored thereon, wherein when the program code is executed by a machine, the machine performs the following operations:

[0287] decoding the first instruction to generate a decoded instruction;

[0288] storing a first plurality of packed doubleword data elements in a first source register;

[0289] storing a second plurality of packed doubleword data elements in a second source register; and

[0290] multiplying a first doubleword data element from the first source register by a second doubleword data element from the second source register to produce a first quadword product, and simultaneously multiplying a third doubleword data element from the first source register by a fourth doubleword data element from the second source register to produce a second quadword product; and

[0291] The first quadword product and the second quadword product are stored as first and second packed quadword data elements in a destination register.

[0292] Technical Solution 20. The machine-readable medium according to Technical Solution 19 further comprises program code, wherein the program code is configured to cause the machine to perform one of the following operations:

[0293] The first and second packed quadword data elements are shifted right or left by an amount based on the immediate data or value in the third source register to generate first and second shifted results, respectively.

[0294] Technical Solution 21. A machine-readable medium as described in Technical Solution 20, wherein the shift circuit is also used to select first and second groups of most significant bits from the first and second shifted results, respectively, and to store the first and second groups of most significant bits in the first and second least significant bit positions of the packed quad-word position in the destination register.

[0295] Technical Solution 22. The machine-readable medium according to Technical Solution 20, wherein the third source register and the destination register are the same physical register.

[0296] Technical Solution 23. The machine-readable medium as described in Technical Solution 20 further includes a rounding circuit, which is used to round the first and second shifted results.

[0297] Technical Solution 24. The machine-readable medium according to Technical Solution 23 further includes:

[0298] The first and second shifted results are saturated when necessary and a saturation flag is set in a control register.

[0299] Technical Solution 25. The machine-readable medium of Technical Solution 19, wherein the first and second groups of most significant bits include 32 most significant bits.

[0300] Technical Solution 26. The machine-readable medium of Technical Solution 19, wherein the first, second, third, and fourth doubleword data elements comprise unsigned data elements.

[0301] Technical Solution 27. A machine-readable medium as described in Technical Solution 19, wherein the first, second, third and fourth double word data elements include signed data elements.

[0302] In the foregoing description, embodiments of the present invention have been described with reference to specific exemplary embodiments thereof. However, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

[0303] Embodiments of the present invention may include the various steps described above. These steps may be implemented in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components containing hard-wired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

[0304] As described herein, instructions may refer to a specific configuration of hardware, such as an application-specific integrated circuit (ASIC) configured to perform certain operations or having predetermined functional or software instructions stored in memory implemented as non-transitory computer-readable media. Thus, the techniques illustrated in the figures can be implemented using code and / or data stored and executed on one or more electronic devices (e.g., end stations, network elements, etc.). Such electronic devices use computer-readable media, such as non-transitory computer-readable storage media (e.g., magnetic disks, optical disks, random access memory, read-only memory, flash memory devices, phase-change memory) and transient computer-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, digital signals, etc.), to store and communicate (internally and / or with other electronic devices over a network) code and data. Furthermore, such electronic devices generally include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touch screens, and / or displays), and network connections. The processors of the assembly are typically coupled to other components via one or more buses and bridges (also known as bus controllers). Signals carrying network traffic and storage devices represent one or more machine-readable communication media and machine-readable storage media, respectively. Thus, the storage device of a given electronic device typically stores code and / or data for execution on one or more processors of the assembly of that electronic device. Of course, one or more portions of the embodiments of the present invention may be implemented using various combinations of software, firmware, and / or hardware. Throughout this detailed description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without some of these specific details. In some instances, well-known structures and functions are not described in detail to avoid obscuring the subject matter of the present invention. Therefore, the scope and spirit of the present invention should be judged in accordance with the claims that follow.

Claims

1. A processor, comprising: a decoder for decoding the first instruction to generate a decoded instruction; a first source register for storing a first plurality of packed doubleword data elements; a second source register for storing a second plurality of packed doubleword data elements; as well as an execution circuit, the execution circuit being configured to execute the decoded instruction, the execution circuit comprising: multiplier circuitry for multiplying a first doubleword data element from the first source register with a second doubleword data element from the second source register to produce a first quadword product, and for simultaneously multiplying a third doubleword data element from the first source register with a fourth doubleword data element from the second source register to produce a second quadword product; and a destination register for storing the first quadword product and the second quadword product as first and second packed quadword data elements; The processor further includes a shift circuit configured to: shift the first and second packed quadword data elements right or left by an amount based on an immediate number or value in a third source register to generate first and second shifted results, respectively; select first and second groups of most significant bits from the first and second shifted results, respectively, and store the first and second groups of most significant bits in first and second least significant bit positions of a packed quadword location in the destination register.

2. The processor of claim 1, wherein the third source register and the destination register are the same physical register.

3. The processor of claim 1 further comprising rounding circuitry to round the first and second shifted results.

4. The processor of claim 1 or 3, further comprising: A saturation circuit is provided for saturating the first and second shifted results when necessary and for setting a saturation flag in a control register.

5. A processor as claimed in claim 1 or 3, wherein the first and second groups of most significant bits include 32 most significant bits.

6. A processor as claimed in claim 1 or 3, wherein the first, second, third and fourth doubleword data elements comprise unsigned data elements.

7. A processor as claimed in claim 1 or 3, wherein the first, second, third and fourth doubleword data elements comprise signed data elements.

8. A method for a processor, comprising: decoding the first instruction to generate a decoded instruction; storing a first plurality of packed doubleword data elements in a first source register; storing a second plurality of packed doubleword data elements in a second source register; as well as multiplying a first doubleword data element from the first source register by a second doubleword data element from the second source register to produce a first quadword product, and simultaneously multiplying a third doubleword data element from the first source register by a fourth doubleword data element from the second source register to produce a second quadword product; as well as storing the first quadword product and the second quadword product as first and second packed quadword data elements in a destination register; The method further includes: shifting the first and second packed quadword data elements right or left by an amount based on the immediate value or value in the third source register to generate first and second shifted results, respectively; and selecting first and second groups of most significant bits from the first and second shifted results, respectively, and storing the first and second groups of most significant bits in first and second least significant bit positions of the packed quadword location in the destination register.

9. The method of claim 8, wherein the third source register and the destination register are the same physical register.

10. The method of claim 8, further comprising rounding circuitry for rounding the first and second shifted results.

11. The method according to claim 8 or 10, further comprising: The first and second shifted results are saturated when necessary and a saturation flag is set in a control register.

12. The method of claim 8 or 10, wherein the first and second groups of most significant bits comprise 32 most significant bits.

13. The method of claim 8 or 10, wherein the first, second, third, and fourth doubleword data elements comprise unsigned data elements.

14. The method of claim 8 or 10, wherein the first, second, third, and fourth doubleword data elements comprise signed data elements.

15. A machine-readable medium having stored thereon program code that, when executed by a machine, causes the machine to perform one of the following operations: decoding the first instruction to generate a decoded instruction; storing a first plurality of packed doubleword data elements in a first source register; storing a second plurality of packed doubleword data elements in a second source register; as well as multiplying a first doubleword data element from the first source register by a second doubleword data element from the second source register to produce a first quadword product, and simultaneously multiplying a third doubleword data element from the first source register by a fourth doubleword data element from the second source register to produce a second quadword product; as well as storing the first quadword product and the second quadword product as first and second packed quadword data elements in a destination register; wherein the machine-readable medium further comprises program code for causing the machine to perform one of: shifting the first and second packed quadword data elements right or left by an amount based on an immediate number or value in a third source register to generate first and second shifted results, respectively; First and second groups of most significant bits are selected from the first and second shifted results, respectively, and used to store the first and second groups of most significant bits in first and second least significant bit positions of a packed quadword location in the destination register.

16. The machine-readable medium of claim 15, wherein the third source register and the destination register are the same physical register.

17. The machine-readable medium of claim 15, further comprising rounding circuitry to round the first and second shifted results.

18. The machine-readable medium of claim 15 or 17, further comprising: The first and second shifted results are saturated when necessary and a saturation flag is set in a control register.

19. The machine-readable medium of claim 15 or 17, wherein the first and second groups of most significant bits comprise 32 most significant bits.

20. A device for a processor, comprising: means for decoding a first instruction to generate a decoded instruction; means for storing a first plurality of packed doubleword data elements in a first source register; means for storing a second plurality of packed doubleword data elements in a second source register; as well as means for multiplying a first doubleword data element from the first source register by a second doubleword data element from the second source register to produce a first quadword product, and simultaneously multiplying a third doubleword data element from the first source register by a fourth doubleword data element from the second source register to produce a second quadword product; as well as means for storing the first quadword product and the second quadword product as first and second packed quadword data elements in a destination register; The apparatus further comprises: means for shifting the first and second packed quadword data elements right or left by an amount based on an immediate number or value in a third source register to generate first and second shifted results, respectively; and means for selecting first and second groups of most significant bits from the first and second shifted results, respectively, and storing the first and second groups of most significant bits in first and second least significant bit positions of a packed quadword location in the destination register.

21. The apparatus of claim 20, wherein the third source register and the destination register are the same physical register.

22. The apparatus of claim 20, further comprising rounding circuitry to round the first and second shifted results.

23. The apparatus of claim 20 or 22, further comprising: Means for saturating the first and second shifted results when needed and setting a saturation flag in a control register.

24. The apparatus of claim 20 or 22, wherein the first and second groups of most significant bits comprise 32 most significant bits.

25. Apparatus as claimed in claim 20 or 22, wherein the first, second, third and fourth doubleword data elements comprise unsigned data elements.

26. Apparatus as claimed in claim 20 or 22, wherein the first, second, third and fourth doubleword data elements comprise signed data elements.

27. A machine-readable medium having stored thereon instructions which, when executed, cause a machine to perform the method according to any one of claims 8 to 14.

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