Oxide peeling stopper

Abstract

The invention discloses an oxide peeling stopper. A power semiconductor die (100) comprises: a semiconductor body (10); an insulating layer (11) on the semiconductor body (10); a passivation structure (13), the passivation structure (13) being arranged above the insulating layer (11) and exposing a first insulating layer subsection (1111), the first insulating layer subsection (1111) extending to an edge (105) of the power semiconductor die (100); and an interruption structure (12) in the first insulating layer subsection (1111).

Description

Technical Field

[0001] The present specification relates to embodiments of power semiconductor dies, to embodiments of semiconductor wafers, and to embodiments of methods of processing semiconductor wafers. In particular, the present specification relates to embodiments of power semiconductor dies including means for preventing oxide-peeling that may occur during a wafer dicing process step. Background Art

[0002] Modern devices in automotive, consumer and industrial applications rely on power semiconductor devices for many functions, such as converting electrical energy and driving electric motors or motors.

[0003] For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used in a variety of applications including, but not limited to, switches in power supplies and power converters.

[0004] A power semiconductor device typically comprises a power semiconductor die configured to conduct a load current along a load current path between two load terminals of the die. Further, the load current path may be controlled by means of an insulated electrode, which is sometimes referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode may set the power semiconductor device in one of a conducting state and a blocking state.

[0005] With regard to the manufacturing process, multiple power semiconductor dies are typically processed simultaneously within a single wafer; that is, after having been processed, the semiconductor wafer may include multiple power semiconductor dies.

[0006] The wafer is then subjected to a separation process step, such as a dicing step, and the wafer is divided into a plurality of separate dies. After a quality inspection, the dies may then be enclosed in a package and thereafter delivered to a customer.

[0007] The quality check may include checking whether the die has been damaged during the separation process step. For example, during sawing, an insulating layer that is exposed to sawing (eg laser sawing) may become damaged.

[0008] For example, if it is considered damaged, or correspondingly, if it cannot be reliably ensured that the die has not been damaged, the die is not packaged but is discarded. Summary of the invention

[0009] Certain aspects of the present description relate to visually arranged interruption structures configured, for example, to prevent peeling of an insulating layer.

[0010] According to an embodiment, a power semiconductor die has: a semiconductor body; an insulating layer on the semiconductor body; a passivation structure, which is arranged above the insulating layer and so as to expose a first insulating layer sub-section, the first insulating layer sub-section extending to the edge of the power semiconductor die; and an interruption structure in the first insulating layer sub-section.

[0011] According to another embodiment, a semiconductor wafer includes: a semiconductor body; an insulating layer on the semiconductor body; a die region having a power semiconductor die; a cutting region arranged adjacent to the die region; a passivation structure arranged above the insulating layer and so as to expose a segment of the insulating layer, wherein a first sub-segment of the exposed insulating layer segment extends into the die region, and wherein a second sub-segment of the exposed insulating layer segment extends into the cutting region; and an interruption structure in the first insulating layer sub-segment.

[0012] According to yet another embodiment, a method includes providing a semiconductor wafer. The provided semiconductor wafer has a semiconductor body, an insulating layer on the semiconductor body, a die region having a power semiconductor die, a dicing region arranged adjacent to the die region, a passivation structure arranged above the insulating layer and such that a segment of the insulating layer is exposed, wherein a first sub-segment of the exposed insulating layer segment extends into the die region, and wherein a second sub-segment of the exposed insulating layer segment extends into the dicing region, and an interruption structure in the first insulating layer sub-segment. The method also includes dicing the semiconductor wafer along the dicing region while at least partially maintaining the interruption structure.

[0013] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The parts in the drawings are not necessarily to scale, instead emphasis is placed on illustrating the principles of the present invention. In addition, in the drawings, the same reference numerals may designate corresponding parts. In the drawings:

[0015] Figure 1 schematically and exemplarily illustrates a section of a vertical cross-section of a semiconductor wafer according to some embodiments;

[0016] Figure 2 schematically and exemplarily illustrates a section of a horizontal projection of a semiconductor wafer according to some embodiments;

[0017] Figure 3A schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor die according to some embodiments;

[0018] Figure 3Bschematically and exemplarily illustrates a section of a horizontal projection of a power semiconductor die according to some embodiments;

[0019] Figure 4 schematically and exemplarily illustrates a section of a horizontal projection of a semiconductor wafer according to some embodiments;

[0020] Figure 5-6 each schematically and exemplarily illustrates a segment of a vertical cross-section of a semiconductor wafer according to some embodiments;

[0021] Figure 7 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor die according to some embodiments; and

[0022] Figure 8 A flow chart of a method of processing a semiconductor wafer according to some embodiments is schematically and exemplarily illustrated. DETAILED DESCRIPTION

[0023] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0024] In this regard, directional terms, such as "top", "bottom", "below", "front", "rear", "back", "leading", "trailing", "above", etc., may be used with reference to the orientation of the figure being described. Because the various parts of the embodiments can be positioned in many different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0025] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation and is not meant to be a limitation of the invention. For example, features illustrated or described as part of one embodiment may be used on other embodiments or used in conjunction with other embodiments to produce yet other embodiments. It is intended that the invention includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, if not otherwise stated, the same elements or manufacturing steps have been designated by the same reference numerals in different drawings.

[0026] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, the surface of a semiconductor wafer or die. For example, both the (first) lateral direction X and the (second) lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0027] The term "vertical" as used in this specification is intended to describe an orientation that is generally arranged perpendicular to a horizontal surface, i.e. parallel to a normal direction of a surface of a semiconductor wafer / chip / die. For example, the vertical direction Z mentioned below may be an extending direction perpendicular to both the first lateral direction X and the second lateral direction Y.

[0028] In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection", and "electrically connected" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, areas, parts, or components of a device described herein. Further, in the context of this specification, the term "in contact" is intended to describe the presence of a direct physical connection between two elements of a respective semiconductor device; for example, a transition between two elements in contact with each other may not include additional intermediate elements or the like.

[0029] Additionally, in the context of this specification, if not stated otherwise, the term "electrically insulated" is used in its generally reasonably understood context, and is thus intended to describe two or more components that are located separately from each other and there is no ohmic connection connecting those components. However, components that are electrically insulated from each other may nevertheless be coupled to each other, such as mechanically and / or capacitively and / or inductively. To give an example, two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, such as by means of an insulating portion (e.g., a dielectric).

[0030] Specific embodiments described in this specification relate to power semiconductor dies (e.g., power semiconductor dies) that can be used in a power converter or power supply, but are not limited thereto. Thus, in an embodiment, such a die can be configured to carry a load current that will be fed to a load and / or provided by a power source accordingly. For example, the die can include one or more active power semiconductor units, such as a monolithically integrated diode unit, and / or a monolithically integrated transistor unit, and / or a monolithically integrated IGBT unit, and / or a monolithically integrated RC-IGBT unit, and / or a monolithically integrated MOS gate-controlled diode (MGD) unit, and / or a monolithically integrated MOSFET unit and / or its derivatives. Multiple such diode units and / or such transistor units can be integrated in the die.

[0031] The term "power semiconductor die" as used in this specification is intended to describe a single die having high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor die is intended for high currents, typically in the ampere range, such as up to 5 or 100 amperes, and / or for voltages typically above 15V, more typically up to 40V and above, such as up to at least 500V or more than 500V, such as at least 600V or at least several kV, such as in the case of high power IGBTs.

[0032] For example, the power semiconductor die described below may be a die configured to be employed as a power component in low, medium and / or high voltage applications. For example, the term "power semiconductor die" as used in this specification does not refer to a logic semiconductor device used, for example, to store data, compute data, and / or other types of semiconductor-based data processing.

[0033] Figure 1 A vertical cross section of a semiconductor wafer 200 is schematically and exemplarily illustrated, and Figure 2 Schematically and exemplarily illustrates a horizontal projection of a semiconductor wafer 200 according to one or more embodiments. Figure 1 and Figure 2 both.

[0034] The semiconductor wafer 200 has a semiconductor body 10. For example, the semiconductor body 10 is based on silicon (Si). In another embodiment, the semiconductor body 10 is based on a different material, such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs) or another wide bandgap material.

[0035] The semiconductor body 10 may have a thickness in the range of 20 μm to 1000 μm along the vertical direction Z. In an embodiment, the semiconductor body thickness 10 is below a maximum value, e.g. in order to allow separation by means of laser cutting, e.g. below 200 μm or below 100 μm. According to an embodiment, the semiconductor wafer (hereinafter also referred to as "wafer") may have a diameter, e.g. along the first lateral direction X, in the range of 1 to 20 inches, e.g. up to 14 inches.

[0036] The wafer 200 may include one or more die regions 210 , and one or more dicing regions 220 arranged adjacent to the diode region 210 (eg, laterally adjacent to the diode region 210 ).

[0037] For example, each die region 210 has at least one power semiconductor die 100 (eg, Figure 3A-B and 7 schematically and exemplarily illustrated). For example, each die area 210 integrates the at least one power semiconductor die 100. Each power semiconductor die 100 may include one or more of the following: a diode, a transistor, a MOSFET, an IGBT, an RC-IGBT, and an MGD.

[0038] For example, the processing of the semiconductor wafer 200 mainly occurs on the wafer front side 290; for example, the wafer front side 290 can be subjected to multiple processing steps, including, for example, one or more implantation processing steps, one or more epitaxy processing steps, one or more deposition processing steps, one or more photolithography processing steps, one or more etching processing steps, etc. For example, on the wafer back side 280, a homogeneously formed (i.e., unstructured) back side metallization layer 212 is provided. For example, the metallization layer 212 forms a part of the load terminal (e.g., drain terminal, collector terminal, or cathode terminal) of each power semiconductor die 100.

[0039] Processing the wafer front side 290 may include creating an insulating layer 11 on the semiconductor body 10. For example, the insulating layer 11 includes an intermediate oxide layer (German "Zwischenoxidschicht" or "ZWOX"). Further, the insulating layer 11 may include an oxide. For example, the insulating layer 11 includes silicon oxide (SiO2) and / or borophosphosilicate glass (BPSG). In an embodiment, the insulating layer 11 includes a lower oxide layer and an upper BPSG layer.

[0040] The insulating layer 11 may cover the semiconductor body 10, for example not only in the die area 210 but also at the dicing area 220. For example, the insulating layer 11 substantially covers the entire semiconductor body 10 of the wafer 200. The insulating layer 11 may be arranged in a horizontal manner, for example, such that the transition between the insulating layer 11 and the semiconductor body defines a substantially horizontal plane. For example, both the upper surface 119 and the lower surface 118 of the insulating layer 11 define a substantially horizontal plane.

[0041] In the die area 210 (eg, its corresponding active area (see Figure 3BIn the semiconductor body 10, the insulating layer 11 may be partially penetrated by contact members, such as contact strips and / or contact plugs, which are arranged and configured to contact segments of the semiconductor body 10, such as source regions and / or body regions and / or channel regions, or insulated electrodes. For example, as will become apparent from the description of the remaining figures, a plurality of trenches may extend into the semiconductor body 10 along a vertical direction Z and may include insulated trench electrodes to be contacted. For example, such trench electrodes may include control electrodes, which may need to be electrically connected to a control terminal structure, such as a gate runner. Further, such trench electrodes may include field electrodes, which may need to be electrically connected to a load terminal structure. For example, such a load terminal structure and / or such a control terminal structure can be arranged above the insulating layer 11, and the contact members penetrating the insulating layer 11 can serve as electrical connections between these terminal structures on one side and the embedded components (semiconductor regions and / or trench electrodes) on the other side, these terminal structures being arranged on top of the upper surface 119 of the insulating layer 11, and the embedded components being arranged below the lower surface 118 of the insulating layer 11.

[0042] Further, the passivation structure 13 may be arranged on the insulating layer 11, for example exclusively in the die region 210. For example, the passivation structure 13 covers the control terminal structure and the load terminal structure mentioned above, for example to provide electrical insulation between these terminal structures. In an embodiment, the passivation structure 13 may include an insulating material, for example imide. The passivation structure 13 may be configured to provide encapsulation.

[0043] For example, the passivation structure 13 does not extend into the cutting area 220. Instead, according to an embodiment, the passivation structure 13 terminates at an edge termination area of ​​a power semiconductor die included in the corresponding die area 210 (see Figure 3B within the reference numeral 190).

[0044] As illustrated, the passivation structure 13 may be arranged over the insulating layer 11 and such that a section 111 of the insulating layer 11 is exposed. Further, the passivation structure 13 may be arranged over the insulating layer so as to cover a section 112 of the insulating layer 11. For example, the covered insulating layer section 112 is exclusively arranged within the die region 210.

[0045] The exposed insulating layer section 111 may extend into each of the die area 210 and the dicing area 220. For example, a first subsection 1111 of the exposed insulating layer section 111 extends into the die area 210. A second subsection 1112 of the exposed insulating layer section 111 may be disposed within the dicing area 220.

[0046] As explained above, the cutting zone 220 may be designated to be subjected to a separation process step, wherein, for example, a laser beam may be directed onto the cutting zone 220, for example onto the surface of the second insulating layer sub-segment 1112. Additionally or alternatively, the laser beam may be directed onto a segment of the semiconductor body 10 which is arranged below the second insulating layer sub-segment 1112 and laterally overlaps the second insulating layer sub-segment 1112.

[0047] Thus, in an embodiment, once the processing of the die area 210 is completed, the wafer 200 can be subjected to a separation process step, such as a cutting (also referred to as "sawing") process step, such as a laser cutting process step. During such a separation process step, the wafer 200 can be divided into separate dies along the cutting area 220, and the separate dies can then be packaged and shipped to the customer. For example, each cutting area 220 includes a cutting (sawing) line (not shown) at the second insulating layer sub-section 1112, along which one or more laser beams are directed for performing separation.

[0048] The width of the second insulating layer subsegment 1112 along the first lateral direction X may be in the range of a few 10 μm, for example in the range of 10 μm to 150 μm. For example, the width of the second insulating layer subsegment 1112 is selected such that a laser beam having a diameter of, for example, 20 μm and a lateral deviation of, for example, + / - 20 μm can be guided along the second insulating layer subsegment 1112, for example without subjecting the first insulating layer subsegment 1111 to the laser beam.

[0049] According to an embodiment, the semiconductor wafer 200 includes an interruption structure 12 in the first insulating layer sub-section 1111. The interruption structure 12 may interrupt the insulating layer 11. For example, the interruption structure 12 divides the insulating layer 11 into separate sub-regions.

[0050] For example, the interruption structure 12 is arranged in a position that is not covered by the passivation structure 13. The interruption structure 12 may be arranged at a visible position. The interruption structure 12 may be configured to prevent a lateral peeling process of the insulation layer 11, wherein the lateral peeling process may be an uncontrolled process. For example, such an (uncontrolled) peeling process may be initiated by the separation process step, for example by means of a laser beam directed onto the second insulation layer sub-segment 1112 or (as mentioned above) by means of a laser beam directed onto the semiconductor body 10 below the second insulation layer sub-segment 1112. According to such a peeling process, the peeling may propagate laterally, for example in and towards the first lateral direction X. According to an embodiment, such a laterally propagating peeling may be prevented by means of the interruption structure 12. For example, since the interruption structure 12 may be arranged in a visible position, it may be visually checked whether the peeling process has been effectively prevented by the interruption structure 12. For example, the interruption structure is also configured to prevent the peeling process from propagating until below the passivation structure 13.

[0051] For example, the interruption structure 12 is at least partially maintained when the semiconductor wafer 200 is cut along the cutting area 220. For example, the laser beam is not directed onto all parts of the interruption structure 12, but is guided such that the interruption structure 12 is not completely destroyed.

[0052] Further optional features of the interruption structure 12 will also be explained with respect to the remaining figures.

[0053] Figure 3A schematically and exemplarily illustrates a vertical cross section of a power semiconductor die 100 , and Figure 3B Schematically and exemplarily illustrates a horizontal projection of a power semiconductor die 100 according to one or more embodiments. Figure 3A and Figure 3B both.

[0054] For example, the power semiconductor die 100 was part of a semiconductor wafer 200 and has been cut away from the semiconductor wafer 200, wherein, thereby, the die edge 105 may have been formed. As illustrated, the power semiconductor die 100 may have an active area 180 and an edge termination area 190, which surrounds the active area 180 and is terminated by the die edge 105. The passivation structure 13 may be arranged so as to cover substantially the entire active area 180 and only partially cover the edge termination area 190. Of course, the passivation structure 13 may be structured partially within the active area 180, for example in order to allow external contacts (e.g. bonding wires) to contact load terminal structures and / or control terminal structures, such as the load terminal structure 110, which are arranged on the insulating layer 11. As explained above, with regard to Figure 1 The mentioned backside metallization 212 may form a further load terminal structure of the power semiconductor die 100 , for example a load terminal structure 120 at the backside of the power semiconductor die 100 .

[0055] As further explained above, the interruption structure 12 may be at least partially maintained when the wafer 200 is separated into a plurality of power semiconductor dies 100. Figure 3A As illustrated in FIG. 1 , the interruption structure 12 is arranged within a first insulation layer subsection 1111 which is not covered by the passivation structure 13 .

[0056] According to an embodiment, the interruption structure 12 extends from an upper surface 119 of the insulating layer 11 at least to a lower surface 118 of the insulating layer 11. For example, the interruption structure 12 may even extend slightly further along the vertical direction Z than the lower surface 118, e.g. in order to contact at least one of the semiconductor body 10 and the trench electrode, as will be explained in more detail further below.

[0057] In an embodiment, the interruption structure 12 comprises a material (e.g. a gaseous material or a solid material) different from the material of the insulating layer 11. For example, the interruption structure 12 comprises one or more channels extending from the upper surface 119 to the lower surface 118. For example, these one or more channels can be left empty or respectively at least partially filled with a material different from the material of the insulating layer 11.

[0058] In another embodiment, the one or more channels of the interruption structure 12 are filled with a conductive material, such as a metal. For example, the interruption structure 12 may include a contact plug, or respectively a contact strip, for contacting the semiconductor body 10 and / or the trench electrode.

[0059] In another embodiment, the one or more channels of the interruption structure 12 are filled with an insulating material different from the material of the insulating layer 11. For example, the one or more channels are filled with imide.

[0060] For example, the one or more channels of the interruption structure 12 each exhibit a width, eg along the first lateral direction X, of at least 100 nm and not more than 200 μm, eg in order to reliably divide / cleave the insulating layer 11 .

[0061] Regardless of whether the channels of the interruption structure 12 are filled or not, the interruption structure 12 may be configured as explained above to interrupt the insulation layer 11 , for example in order to divide the insulation layer 11 into a section facing the die edge 105 and a section facing the passivation structure 13 .

[0062] For example, the interruption structure 12 may completely or at least partially surround the edge termination region 190, such as Figure 3B . Thus, the interruption structure 12 also completely or at least partially surrounds the active area 180 of the power semiconductor die 100. For example, in order to at least partially surround the edge termination area 190, the interruption structure 12 may include an arrangement of a plurality of contact strips, which are coupled to each other so as to form a substantially closed structure, which, for example, at least partially surrounds the edge termination area 190. For example, according to Figure 4 In the embodiment schematically illustrated in , four contact strips are arranged so as to form a closed rectangle around the edge termination area 190. In another embodiment, the corners do not necessarily have to be closed; instead, contact strips extending perpendicular to each other may define open corners.

[0063] Figure 4 Schematically and exemplarily, a horizontally projected section of an embodiment of a semiconductor wafer 200 is illustrated, the section comprising four adjacent die areas 210. For example, a first sawing process step has been performed in the sawing area 220 along the sawing lines 222. For example, due to such a first sawing process step, the second insulating layer sub-section 1112 (see Figure 1 ). The cross-hatched area illustrates a first insulating layer sub-section 1111, which extends laterally from the corresponding die edge 105 to the outermost termination 130 of the passivation structure 13. As explained above, the interruption structure 12 of each power semiconductor die 100, i.e. each die area 210, may include a plurality of contact strips arranged co-parallel to each other. These contact strips are not covered by the passivation structure 13, as shown. As mentioned above, Figure 4 In contrast to the schematic illustration of , the contact strips may, but do not necessarily have to, contact each other at the corners. For example, in another embodiment, contact strips extending perpendicularly to each other define an open corner.

[0064] As already explained further above, the passivation structure 13 may be structured, for example such that a terminal structure, for example the terminal structure 150 , which may be a control terminal structure and comprises, for example, a gate runner, is exposed.

[0065] Figure 5 A section of a vertical cross-section of an embodiment of a semiconductor wafer 200 with two adjacent die regions 210 is schematically and exemplarily illustrated.

[0066] Thus, a plurality of trenches 15 may extend into the semiconductor body 10 along the vertical direction Z. Each of the plurality of trenches 15 may include a trench electrode 151 and a trench insulator 152 that insulates the trench electrode 151 from the semiconductor body 10. The trenches 15 may be arranged both in the die region 210 and in the dicing region 220.

[0067] For example, a first subset of the plurality of trenches 15 may be arranged in the die region 210, wherein Figure 5-8 In each of the images, only the edge termination area (see Figure 3B The first subset may include at least one trench 15 that laterally overlaps the first insulating layer sub-segment 1111. In the illustrated embodiment, in the die region 210, four trenches 15 laterally overlap the first insulating layer sub-segment 1111.

[0068] The second subset of the plurality of trenches 15 may be arranged in the cutting region 220 , wherein each of the second subset of the plurality of trenches 15 laterally overlaps the second insulating layer sub-segment 1112 .

[0069] According to an embodiment, the first subset of the plurality of trenches 15 and the second subset of the plurality of trenches 15 have the same spatial dimensions, e.g. with respect to a total extension along the vertical direction Z and / or with respect to a trench width along the first lateral direction X. Additionally or alternatively, the first subset of the plurality of trenches 15 and the second subset of the plurality of trenches 15 are arranged according to the same trench pattern, e.g. with respect to a lateral distance (also referred to herein as “pitch”) between two adjacent trenches 15 along the first lateral direction X. In another embodiment, the trenches 15 in the dicing area 220 may be arranged according to a larger pitch than the trenches 15 in the die area 210.

[0070] For example, it may be beneficial in terms of uniformity that a trench formation process implemented to form trenches (e.g., to form control trenches, gate trenches, field plate trenches, etc.) within the active region 180 of each power semiconductor die 100 in the die region 210 is simultaneously implemented in a similar or identical manner within the dicing region 220. Thus, although such trenches 15 in the dicing region 210 are not required to control the operation of the power semiconductor die 100, they may nonetheless be formed within these regions 220 in order to provide high uniformity across the wafer 200.

[0071] According to an embodiment, the interruption structure 12 may electrically contact a trench electrode 151 of the at least one trench 15 laterally overlapping the first insulating layer sub-segment 1111. Additionally or alternatively, the interruption structure 12 may electrically contact a semiconductor region adjacent to a trench insulator 152 of the at least one trench laterally overlapping the first insulating layer sub-segment 1111, for example a doped semiconductor region 102 arranged in a mesa region between two adjacent trenches 15.

[0072] In an embodiment, a plurality of contact plugs 154 are employed for contacting the trench electrodes 151 and / or the semiconductor body 10, wherein each of the contact plugs 154 may extend from an upper surface 119 of the insulating layer 11 to a lower surface 118 of the insulating layer 11. The use of such contact plugs 154 is generally known to the skilled person. For example, depending on the design of the power semiconductor die 100, such as a pin-type trench design or a strip trench design, such contact plugs 154 may be configured as contact strips or as contact needles. They may penetrate the insulating layer 11 and extend further along the vertical direction Z than the lower surface 118 of the insulating layer 11, for example in order to contact a region of the semiconductor body 10, such as a source region, a channel region or a body region within the active region 180.

[0073] For example, Figure 7 As illustrated in , a front side metallization 110 is arranged above the insulating layer 11 and below the passivation structure 13, wherein the front side metallization 110 is electrically connected to the semiconductor body 10 in the active area 180 of the power semiconductor die 100. The front side metallization 110 may form part of a load terminal structure of the power semiconductor die 100, such as a part of a source terminal structure, an emitter terminal structure or an anode terminal structure. As already explained, the active area 180 may be laterally displaced from the first insulating layer subsection 1111. For example, in order to provide the electrical connection between the front side metallization 110 and the semiconductor body 10 and / or between the front side metallization 110 and the trench electrode 151, the contact plug 154 may be employed.

[0074] According to an embodiment, the interruption structure 12 is produced simultaneously with the contact plug 154 and in the same manner thereto or respectively in a manner similar thereto.

[0075] For example, the interruption structure 12 may include a plurality of contact plugs 154 arranged within the cutting area 220, wherein each of the contact plugs 154 of the interruption structure 12 may penetrate the insulating layer 11, i.e., within the exposed insulating layer segment 111, and, for example, within both the first insulating layer sub-segment 1111 and the second insulating layer sub-segment 1112, wherein each of the contact plugs 154 of the interruption structure 12 may contact the semiconductor body 10 (e.g., the doped semiconductor region 102) or one of the trench electrodes 151 below the lower surface 119 of the insulating layer 11.

[0076] In other words, at least one of the trenches 15 laterally overlaps with the first insulating layer subsection 1111 , wherein a trench electrode 151 electrically contacting the at least one trench 15 or a contact plug 154 of a semiconductor region adjacent to the trench insulator 152 of the at least one trench 15 may form part of the interruption structure 12 .

[0077] According to Figure 5-7 In each of the embodiments schematically and exemplarily illustrated in FIG. 1 , a further interruption structure 14 may be provided, which is covered by the passivation structure 13. For example, this first interruption structure 14 may also penetrate the insulating layer 11, for example at the covered insulating layer section 112. Figure 6 and 7 As shown in FIG. 1 , the further interruption structure 14 may include a further interruption contact plug 144, such as Figure 5 , or further interrupts the contact well 142 , wherein the contact plug 144 or respectively the contact well 142 can electrically contact the semiconductor body 10 .

[0078] The total number of trenches 15 included in the dicing area 220 may depend on the trench pattern used to form the trenches in the die area 210. For example, a power semiconductor die with a lower rated voltage may employ a trench pattern with a relatively small pitch (see FIG. Figure 6 ), while for power semiconductor dies with higher voltage ratings, trenches can be used, but with a relatively large pitch (see Figure 5 ).

[0079] Furthermore, if Figure 6, the plurality of trenches 15 may include at least two different trench types, such as trenches of the control trench type and trenches of the field plate trench type. For example, the field plate trenches are significantly larger than the control trenches, such as in terms of total vertical extension. The control trenches may include insulating control trench electrodes, wherein the field plate trenches may include larger field plate trench electrodes, which are electrically connected to the front side metallization 110 at least in the active area 180 of the corresponding power semiconductor die 100. The interruption structure 12 may include a plurality of contact plugs, which extend through the second insulating layer sub-segment 1112, such as to contact the semiconductor body 10, the control trench electrodes and / or the field plate trench electrodes.

[0080] Presented herein is also a method, an embodiment of which is Figure 8 , schematically and exemplarily illustrated in . For example, method 300 includes: providing a semiconductor wafer in step 310. The provided semiconductor wafer has: a semiconductor body; an insulating layer on the semiconductor body; a die region having a power semiconductor die; a cutting region arranged adjacent to the die region; a passivation structure, the passivation structure being arranged above the insulating layer and such that a segment of the insulating layer is exposed, wherein a first sub-segment of the exposed insulating layer segment extends into the die region, and wherein a second sub-segment of the exposed insulating layer segment extends into the cutting region; and an interruption structure in the first insulating layer sub-segment. Method 300 may also include, in step 320, cutting the semiconductor wafer along the cutting region while at least partially maintaining the interruption structure.

[0081] Features of the exemplary embodiment of the method 300 may correspond to features of the exemplary embodiment of the power semiconductor die 100 and / or to features of the exemplary embodiment of the semiconductor wafer 10 described above. And so far, reference is made to the foregoing.

[0082] For example, when carrying out the method 300, it is ensured that the interruption structure (see reference numeral 12 in other figures) is not covered, for example not only by means of a passivation structure (see reference numeral 13 and other figures), but also by another layer or the like. For example, it is ensured that the interruption structure provides a visually perceptible control element for checking whether the above-described laterally propagating spalling process has been effectively prevented by the interruption structure.

[0083] Step 320 may include performing at least one first laser cutting process step, for example in order to split the exposed insulation layer section (see reference numeral 112), for example along a cutting line (see reference numeral 222) included in the cutting area. For example, by means of the first laser cutting process step, also an upper section of the semiconductor body 10 arranged below the second insulation layer subsection 1112 (for example the upper 10 μm of the semiconductor body 10), for example including the trench 15 that has been realized in this upper section, may be removed. Thereafter, a second laser cutting process step may be performed, for example in order to cut through the semiconductor body and the backside metallization (see reference numeral 212).

[0084] Spatially relative terms such as "below," "below," "lower," "above," "upper," and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the corresponding devices in addition to those different orientations depicted in the figures. Further, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like, and are also not intended to be limiting. Throughout this description, the same terms refer to the same elements.

[0085] As used herein, the terms “having,” “containing,” “including,” “comprising,” “exhibiting,” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features.

[0086] With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A power semiconductor die, comprising: Semiconductor body; An insulating layer on a semiconductor body; a passivation structure arranged over the insulating layer such that a first insulating layer subsection of the insulating layer is exposed, the first insulating layer subsection extending to an edge of the power semiconductor die; as well as an interruption structure in the first insulating layer subsection, a plurality of trenches, wherein each of the trenches includes a trench electrode insulated from the semiconductor body by a trench insulator; as well as A plurality of contact plugs are used to contact the trench electrodes and / or the semiconductor body, wherein each of the contact plugs extends from an upper surface of the insulating layer to a lower surface of the insulating layer. 2 . The power semiconductor die of claim 1 , wherein the interruption structure extends from an upper surface of the insulating layer at least to a lower surface of the insulating layer. 3 . The power semiconductor die of claim 1 , wherein the interruption structure comprises a material different from a material of the insulating layer. 4 . The power semiconductor die of claim 1 , wherein the interruption structure comprises a contact plug for contacting one of the semiconductor body and the trench electrode. The power semiconductor die of claim 1 , wherein the interruption structure is configured to prevent a lateral spalling process of the insulating layer. 6 . The power semiconductor die of claim 1 , wherein the interruption structure is arranged in a location not covered by a passivation structure. The power semiconductor die of claim 1 , wherein the interruption structure interrupts an insulating layer. 8 . The power semiconductor die of claim 1 , wherein the interruption structure surrounds an edge termination region of the power semiconductor die.

9. The power semiconductor die of claim 1, wherein the interruption structure comprises an arrangement of a plurality of contact strips coupled to each other and forming a substantially closed structure.

10. The power semiconductor die of claim 1 , further comprising a front side metallization arranged above the insulating layer and below the passivation structure, and wherein the front side metallization is electrically connected to a semiconductor body in an active area of ​​the power semiconductor die, the active area being laterally displaced from the first insulating layer sub-section. The power semiconductor die of claim 10 , wherein at least some of the contact plugs are electrically connected to the front side metallization.

12. The power semiconductor die of claim 1 , wherein at least one of the trenches laterally overlaps with the first insulating layer subsection, and wherein one of the contact plugs electrically contacts a trench electrode of at least one trench or contacts a semiconductor region adjacent to a trench insulator of at least one trench and forms part of an interruption structure.

13. The power semiconductor die of claim 1 , further comprising a front side metallization arranged above the insulating layer and below the passivation structure, and wherein the front side metallization is electrically connected to the semiconductor body in an active area of ​​the power semiconductor die, the active area being laterally displaced from the first insulating layer sub-section.

14. The power semiconductor die of claim 1, wherein: The passivation structure comprises imide; and / or wherein the insulating layer comprises borophosphosilicate glass; and / or wherein the interruption structure comprises metal.

15. The power semiconductor die of claim 1 , further comprising: A plurality of contact plugs for contacting the semiconductor body, wherein each of the contact plugs extends from an upper surface of the insulating layer to a lower surface of the insulating layer, and wherein the contact plugs are omitted from an edge termination region of the power semiconductor die. The power semiconductor die of claim 15 , wherein the contact plug is not covered by the passivation structure.

17. A semiconductor wafer, comprising: Semiconductor body; An insulating layer on a semiconductor body; a die area having a power semiconductor die; a dicing region disposed adjacent to the die region; a passivation structure arranged over the insulating layer such that a segment of the insulating layer is exposed, wherein a first subsegment of the exposed insulating layer segment extends into the die region, and wherein a second subsegment of the exposed insulating layer segment extends into the dicing region; as well as An interruption structure in the first insulation layer subsection.

18. The semiconductor wafer according to claim 17 further includes a plurality of grooves, wherein each of the grooves includes a groove electrode, and the groove electrode is insulated from the semiconductor body by a groove insulator, wherein a first subset of the plurality of grooves is arranged in the die area and includes at least one groove that laterally overlaps with the first insulating layer sub-segment; wherein a second subset of the plurality of grooves is arranged in the cutting area, and wherein each of the second subset of the plurality of grooves laterally overlaps with the second insulating layer sub-segment.

19. The semiconductor wafer of claim 18, wherein a first subset of the plurality of grooves and a second subset of the plurality of grooves have the same spatial dimensions; and / or wherein the first subset of the plurality of grooves and the second subset of the plurality of grooves are arranged according to the same groove pattern.

20. A semiconductor wafer according to claim 18, wherein the interruption structure electrically contacts: a trench electrode of the at least one trench that laterally overlaps with the first insulating layer sub-segment; and / or a semiconductor region: the semiconductor region is adjacent to a trench insulator of the at least one trench that laterally overlaps with the first insulating layer sub-segment.

21. A method for processing a semiconductor wafer, comprising: A semiconductor wafer is provided, wherein the semiconductor wafer has: Semiconductor body; An insulating layer on a semiconductor body; a die area having a power semiconductor die; a dicing region disposed adjacent to the die region; a passivation structure arranged over the insulating layer such that a segment of the insulating layer is exposed, wherein a first subsegment of the exposed insulating layer segment extends into the die region, and wherein a second subsegment of the exposed insulating layer segment extends into the dicing region; as well as an interruption structure in the first insulating layer subsection; as well as The semiconductor wafer is diced along the dicing regions while at least partially maintaining the interruption structure.

22. The method of claim 21, wherein said cutting comprises at least one laser cutting process step.

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