Semiconductor structure

Abstract

A conductive layer is formed between a metal gate structure and a contact component, the metal gate structure including a high-k gate dielectric layer and a gate electrode. The conductive layer may be selectively deposited over an upper surface of the gate electrode, or may be non-selectively formed on the upper surfaces of the gate dielectric layer and the gate electrode by, for example, controlling the deposition time. The conductive layer has a bottom embedded in the gate electrode. The conductive layer and the contact component may be formed by different deposition techniques, but the conductive layer and the contact component may include the same composition.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure having a conductive layer, and more particularly to a semiconductor structure having a conductive layer formed between a metal gate structure and a contact component. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in successive generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (e.g., the number of interconnects per chip area) has continued to increase, while geometry (e.g., the smallest component (or wire) created by a process) has continued to decrease. This miniaturization process generally provides the benefits of increased manufacturing efficiency and reduced associated costs.

[0003] In order to achieve the above advantages, this miniaturization also increases the complexity of manufacturing ICs and processes, and the manufacturing of ICs and processes also requires corresponding development. For example, replacing polysilicon gates with metal gates to reduce the size of components and improve device performance. However, during the manufacturing of devices, forming contact components on metal gates faces challenges. For example, the high impedance between the contact components and the metal gate caused by the reduced component size is difficult to control. Therefore, improvements are needed in this area. Summary of the invention

[0004] According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes a metal gate structure, the metal gate structure includes a gate dielectric layer and a gate electrode. The semiconductor structure includes a conductive layer formed on the upper surface of the metal gate structure, and a portion of the conductive layer is embedded below the upper surface of the metal gate structure. The semiconductor structure includes a contact component, which is disposed on the upper surface of the metal gate structure, and the contact component is in direct contact with the upper surface of the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present disclosure are best understood by reading the detailed description below in conjunction with the accompanying drawings. It should be noted that the various features of the present disclosure are not drawn in accordance with industry standard operating dimensions. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced to provide clarity of description.

[0006] 1A, 4A, 5, 6A, 6C, 7A, 8A, 9A, 10A, 11A, 11C, 12A, 12B, 13A and 13B are partial cross-sectional diagrams of semiconductor structures according to some embodiments of the present invention.

[0007] FIGS. 1B, 4B, 6B, 7B, 8B, 9B, 10B and 11B are top plan views of the devices shown in FIGS. 1A, 4A, 6A, 7A, 8A, 9A, 10A and 11A (and 11C) respectively according to some embodiments of the present invention.

[0008] Figure 2 is a three-dimensional perspective view of an apparatus according to some embodiments of the present invention.

[0009] Figure 3 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0010] Reference numerals list

[0011] 100 Installations

[0012] 102 Semiconductor substrate

[0013] 106 Source / Drain Components

[0014] 108 Channel Area

[0015] 110 first interlayer dielectric layer

[0016] 120 High-k Metal Gate Structure

[0017] 122 gate dielectric layer

[0018] 124 Gate electrode

[0019] 126 Conductive layer

[0020] 128 Gate spacer

[0021] 130 Second interlayer dielectric layer

[0022] 132, 134 Contact parts

[0023] 140 Overlay

[0024] 150, 152, 154 Metal layer

[0025] 170 Part 1

[0026] 172 Part 2

[0027] Part 174, 176, 178

[0028] 200 Installations

[0029] 202 Semiconductor substrate

[0030] 204 Fins

[0031] 206 Isolation Structure

[0032] 208 Source / Drain Components

[0033] 210 first interlayer dielectric layer

[0034] 220 High-k Metal Gate Structure

[0035] 222 High-k gate dielectric layer

[0036] 224 Gate electrode

[0037] 226 Conductive layer

[0038] 228 Gate Spacer

[0039] 230 Second interlayer dielectric layer

[0040] 232 Contact parts

[0041] 300 Methods

[0042] 302, 304, 306, 308, 310, 312, 314, 316, 318, 320 Operation

[0043] 400 parts

[0044] 610 Interface layer

[0045] 612, 614, 616, 618 Type

[0046] 620 First gas precursor

[0047] 622 Second Gas Precursor

[0048] 710 Opening

[0049] D Width

[0050] H, H1 Height

[0051] H2 Depth

[0052] L Length

[0053] S deviation

[0054] T1, T2 distance

[0055] W W'W" Length DETAILED DESCRIPTION

[0056] It should be understood that the following disclosure of this specification provides many different embodiments or examples to implement different characteristic components of the present invention. The following disclosure of this specification describes specific examples of various components and their arrangement in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the present invention. For example, if the following disclosure of this specification describes forming a first characteristic component on or above a second characteristic component, it means that it includes an embodiment in which the formed first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, different examples in the description of the present invention may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplification and clarity, and are not used to limit the relationship between the various embodiments and / or the appearance structures.

[0057] Furthermore, in order to facilitate the description of the relationship between an element or feature and another (multiple) element or (multiple) feature in the drawings, spatially related terms may be used, such as "under", "below", "lower", "above", "upper" and similar terms. In addition to the orientation shown in the drawings, spatially related terms cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, the elements described as being "under" or "below" other elements or features will be positioned as being "above" the other elements or features. Therefore, the exemplary term "under" can cover both the above and below orientations. The device may also be positioned otherwise (e.g., rotated 90 degrees or positioned in other orientations), and the description of the spatially related terms used will be interpreted accordingly.

[0058] Embodiments of the present invention relate to methods for manufacturing semiconductor devices, and more particularly to methods for contacting components of metal gate structures. A metal gate structure is formed in a device, and a contact component is formed on the upper surface of the metal gate structure to continue manufacturing the device. However, as the size of the component continues to decrease, more challenges arise at this stage of manufacturing. In one example, multiple work function metal (WFM) layers included in the metal gate electrode may form a high impedance interface with the contact component, thereby limiting the execution of the overall device. In addition, the size of the component after miniaturization makes it difficult to control the electrical properties between the conductive component and the upper surface of the metal gate electrode. Therefore, the structure provided by the embodiment of the present invention helps to reduce the contact resistance between the interface of the metal gate structure and the contact component. The semiconductor device disclosed herein can be, for example, a complementary metal-oxide-semiconductor (CMOS) device, which includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device. In this structure, the device can be a two-dimensional planar metal-oxide-semiconductor field-effect transistor (MOSFET) device (FIG. 1A-1B) or a three-dimensional non-planar fin field-effect transistor (FinFET) device ( Figure 2 ). However, it should be understood that the embodiments of the present invention are not limited to a particular type of device.

[0059] Figure 1A It is along the Figure 1B 1A and 1B illustrate a cross-sectional view of a semiconductor device (or semiconductor structure) 100 along line segment AA′ of the device 100. In some embodiments, FIGS. 1A and 1B illustrate a two-dimensional planar device, such as a PMOS device, an NMOS device, or a portion of a CMOS device, and Figure 2 A three-dimensional PMOS or NMOS FinFET device is shown. Figure 3 1 is a flow chart showing a method 300 for forming semiconductor devices 100 and 200 according to an embodiment of the present invention. The method 300 is merely an example and is not intended to limit the invention beyond what is actually described in the claims. Additional operations may be provided before, during, and / or after the stages described in these embodiments. In different embodiments, these stages may be omitted or replaced.

[0060] At operation 302, method 300 provides a semiconductor substrate 102. The semiconductor substrate (or substrate) 102 includes an elemental semiconductor having a crystalline structure, such as silicon, or the substrate 102 includes other elemental semiconductors, such as germanium; the substrate 102 includes a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; the substrate 102 includes an alloy semiconductor including silicon germanium, gallium arsenic phosphide, aluminum indium phosphide, aluminum gallium arsenide, aluminum indium arsenide, gallium indium phosphide, gallium indium phosphide, and gallium indium arsenide phosphide; or a combination thereof. Alternatively, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate on the insulating layer can be made by separation by implantation of oxygen (SIMOX), wafer bonding and / or other suitable methods. The substrate 102 may also include other components such as a buried layer and / or an epitaxial semiconductor layer grown on top thereof. In some embodiments, the substrate 102 may include doped regions, such as n-type well regions, p-type well regions, depending on the type of device desired. Doping the substrate 102 can be performed by an ion implantation process, a diffusion process, an in-situ doping process, or a combination thereof.

[0061] At operation 304, method 300 forms isolation features (not shown) on substrate 102 to define an active region of device 100. The isolation features may include, for example, silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The isolation features may include structures such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures.

[0062] In operation 306, method 300 forms a dummy gate structure (not shown) on substrate 102, which will be replaced in a subsequent step. The dummy gate structure may include a dummy interface layer, which includes silicon oxide, silicon oxynitride; and a dummy gate electrode, which includes polysilicon. The dummy gate structure can be formed by a series of deposition and patterning processes. Thereafter, referring to FIGS. 1A and 4A, operation 306 forms a gate spacer 128 along the sidewall of the dummy gate structure. The gate spacer 128 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other dielectric materials, or a combination thereof, and may be formed by a deposition process and a subsequent anisotropic etching process.

[0063] Referring to FIGS. 1A and 4A , the method 300 proceeds to operation 308 to form source / drain features 106 adjacent to the dummy gate structures, thereby forming a channel region 108 below the dummy gate structures and between the source / drain features 106. The source / drain features 106 may be n-type features for forming an NMOS device, or p-type features for forming a PMOS device. In some embodiments, the source / drain features 106 may be formed by doping the source / drain regions in the substrate 102 adjacent to the dummy gate structures with one or more n-type dopants or p-type dopants as required by the device, such as by ion implantation. In another embodiment, operation 308 forms the source / drain features 106 in the source / drain regions by epitaxially growing a layer of doped semiconductor material, thereby forming raised source / drain features 106. In other embodiments, operation 308 first forms a trench by etching, recesses a portion of the source / drain region, and then epitaxially grows a semiconductor layer in the trench to form the source / drain component 106. The epitaxially grown semiconductor material may be the same as or different from the semiconductor material of the substrate 102. For example, in a p-type field effect transistor, the epitaxially grown semiconductor material is silicon germanium, and in an n-type field effect transistor, the epitaxially grown semiconductor material is silicon or silicon carbide. In some embodiments, dopants are introduced into the source / drain component 106 by in-situ doping. More specifically, the precursor used for epitaxial growth also includes a chemical substance containing dopants.

[0064] Thereafter, at operation 310, the method 300 forms a first interlayer dielectric layer 110 on the source / drain features 106 and the isolation features (FIGS. 1A and 4A). The first interlayer dielectric layer 110 may include any suitable dielectric material, such as tetraethylorthosilicate (TEOS), undoped silicon glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric material, and / or other suitable dielectric materials. The first interlayer dielectric layer 110 may include a multi-layer structure or a single-layer structure having multiple dielectric materials. For example, the first interlayer dielectric layer 110 may include a thin etch stop layer (e.g., silicon nitride) and a low-k dielectric material layer. Operation 310 may be performed by a deposition process such as spin coating, chemical vapor deposition (CVD), other suitable methods, or combinations thereof. Operation 310 may also include performing a planarization process such as chemical-mechanical polishing (CMP) to remove excess interlayer dielectric material located above the upper surface of the device 100 after depositing the first interlayer dielectric layer 110.

[0065] At operation 312, the method 300 replaces the dummy gate structure with a high-k metal gate (HK MG) structure 120 (FIGS. 1A, 4A, and 4B). Operation 312 removes a portion of the dummy gate structure to form a gate trench (not shown), and then forms the high-k metal gate structure 120 in the gate trench by a deposition process. Therefore, the formed gate material layer is U-shaped. Thereafter, a planarization process (e.g., CMP) is performed to remove excess metal gate material on the surface of the device 100.

[0066] 1A, 4A and 4B, the high-k metal gate structure 120 includes a high-k gate dielectric (or gate dielectric) layer 122, a capping layer 140 disposed between the gate dielectric layer 122 and the gate electrode 124, and a plurality of metal layers 150, 152 and 154 together form the gate electrode 124. In some embodiments, the gate electrode 124 may include an additional metal layer. In some embodiments, the high-k metal gate structure 120 may include additional material layers (not shown), such as an interface layer, a capping layer, a diffusion layer, a barrier layer, or a combination thereof. For example, the high-k metal gate structure 120 may include an interface layer between the channel region 108 and the gate dielectric layer 122. The material layers of the high-k metal gate structure 120 may be formed by one or more suitable methods, such as CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, other suitable methods, or a combination thereof. In some embodiments, one or more deposition methods are performed to form the U-shaped gate dielectric layer 122 , the capping layer 140 , the metal layers 150 , 152 and 154 of the gate electrode 124 and any other material layers disposed therebetween, such that the top surfaces of the material layers are coplanar with each other.

[0067] The high-k dielectric layer 122 may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials), such as hafnium silicon oxide (HfSiO), hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), lanthanum oxide (La2O3), titanium dioxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), or a combination thereof. The gate dielectric layer 122 may be deposited using CVD, ALD, and / or other suitable methods.

[0068] In some embodiments, the capping layer 140 includes one or more of the following materials: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO or other suitable materials. Therefore, operation 312 may further include, after forming the gate dielectric layer 122, co-sputtering the capping layer 140 on the gate dielectric layer 122 by, for example, performing a rapid thermal anneal (RTA) in nitrogen. In some embodiments, the capping layer 140 provides the high-k metal gate 120 with preferred thermal stability and limits the diffusion of metal impurities from the gate electrode 124 to the gate dielectric layer 122.

[0069] The gate electrode 124 may include one or more metal layers, such as a work function metal (WFM) layer, a conductive barrier layer, and a bulk conductive layer. The work function metal layer may be a p-type or n-type work function layer, depending on the desired device type (PMOS or NMOS). The p-type work function metal layer includes a metal with a sufficiently large equivalent work function and may include one or more of the following materials: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), other suitable metals, or combinations thereof. The n-type work function metal layer includes a metal with a sufficiently large equivalent work function and may include one or more of the following materials: tantalum (Ta), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum nitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), other suitable metals, or combinations thereof. The bulk conductive layer may include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), platinum (Pt), molybdenum (Mo), cobalt (Co), silver (Ag), manganese (Mn), zirconium (Zr), ruthenium (Ru), and / or other suitable materials. The gate electrode 124 may include multiple work function metal layers; or, include multiple work function metal layers and bulk conductive metal layers. The gate electrode 124 may be formed by one or more deposition methods, such as CVD, PVD, ALD, electroplating, and / or other suitable methods.

[0070] In the embodiments described herein, the gate electrode 124 includes a plurality of metal layers. For example, the metal layers 150, 152, and 154 may be three metal layers having the same morphology (n-type or p-type) and different work functions. Alternatively, the metal layers 150 and 152 may be two metal layers with different work functions, and the metal layer 154 may be a bulk conductive layer. In some embodiments, the gate electrode 124 may include additional work function metal layers and bulk conductive layers.

[0071] See back Figure 3 , the method 300 proceeds to operation 314, performing a surface treatment of the high-k metal gate structure 120 to form a conductive layer 126. In some embodiments, such as Figure 5As shown, the upper surface of the high-k metal gate structure 120 is bombarded with a plasma containing argon (Ar), ammonia (NH3), other suitable gas species, or a combination thereof to perform surface treatment. The plasma can be performed by applying a bias voltage in the range of about 1000 W to about 4000 W and an operating temperature in the range of about 200° C. to about 400° C. In one embodiment, the treatment period is about 1 minute. In the embodiments described herein, the surface treatment helps remove any high-resistance material located on the upper surface of the high-k metal gate structure 120 and improves the bonding between the conductive layer 126 and the upper surface of the high-k metal gate structure 120. Examples of high-resistance materials include a native oxide layer formed on one or more work function metal layers within the gate electrode 124. In some embodiments, operation 314 is optional to subsequent process steps. Advantageously, the surface treatment of operation 314 can be performed using the same machine as the subsequent steps of forming the conductive layer 126 and the contact member 132.

[0072] In some embodiments, performing the surface treatment of operation 314 forms a uniformly grown conductive layer 126 on the multiple metal layers 150, 152 and 154, which can be used to promote the bonding between the precursor material of the conductive layer 126 and the upper surface of the gate electrode 124 when removing the high-resistance material located above the upper surface of the gate electrode 124 (for example, a naturally generated oxide layer generated by the work function metal layer).

[0073] At operation 316, the method 300 forms a conductive layer 126 on the upper surface of the high-k metal gate structure 120 by a deposition process (eg, the conductive layer 126 is parallel to and in contact with the upper surface of the high-k metal gate structure 120). In this embodiment, operation 316 performs an ALD process. Fig. 6A As shown, operation 316 begins by exposing the upper surface of the high-k metal gate structure 120 to two different gas precursors in a sequential and cyclic manner, for example, exposing the upper surface of the high-k metal gate structure 120 to the first gas precursor 620 and the second gas precursor 622 alternately. In some embodiments, the deposition process performed in operation 316 is a selective deposition process, so that the conductive layer 126 is selectively formed on the upper surface of the gate electrode 124 and is self-aligned to the upper surface of the gate electrode 124.

[0074] The first gas precursor 620 may include a compound having a conductive element and a halogen, the conductive element being, for example, W, Co, Ti, Al, Cu, Au, or a combination thereof, and the halogen being, for example, chlorine (Cl) or fluorine (F). In one embodiment, the first gas precursor 620 may be tungsten chloride (WCl5), tungsten fluoride (WF6), titanium chloride (TiCl4), or other suitable materials. The second gas precursor 622 includes elements, for example, silicon (Si) and hydrogen (H). Examples of the second gas precursor 622 include hydrogen (H2) and silane (SiH4). Operation 316 performs a deposition process at a temperature ranging from about 400° C. to about 520° C. and a process pressure ranging from about 5 Torr to about 50 Torr. In some embodiments, the deposition process may be performed for about 10 minutes to about 40 minutes.

[0075] In some embodiments, the conductive layer 126 comprises a metal selected from tungsten (W), cobalt (Co), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), other suitable metals or combinations thereof. In one embodiment, the conductive layer 126 comprises W, Co or Al. When the contact features (e.g., contact features 132 or 134 of FIGS. 8A and 10A ) formed on the metal gate structure generally comprise a conductive material similar to the conductive layer 126, the contact resistance at the interface between the contact features 132 or 134 and the conductive layer 126 is generally lower than the contact resistance between the conductive layer 126 and the upper surface of the gate electrode 124 (which may include a plurality of high-resistance work function metal layers).

[0076] In some embodiments, as shown in FIGS. 6A-6B, 7A-7B, and 8A-8B, the conductive layer 126 is self-aligned to the metal layers 150, 152, and 154 of the gate electrode 124 and is not formed over the gate dielectric layer 122 or the capping layer 140. However, as shown in FIGS. 9A-9B and 12A-12B, the conductive layer 126 can be formed over the upper surface of the gate dielectric layer 122 and / or the capping layer 140 by controlling the deposition time of operation 316. In one example, the extended deposition time can allow the conductive layer 126 to extend laterally over the upper surface of the capping layer 140 and / or the gate dielectric layer 122, thereby increasing the contact area between the later-formed contact feature (e.g., the contact feature 134 of FIGS. 10A-10B) and the gate electrode 124 even if there is misalignment between the two.

[0077] In some embodiments, a portion of the conductive layer 126 may be embedded below the upper surface of the gate electrode 124, and the embedded portion may include an interfacial layer 610, which contains chemical elements contained in both the gate electrode 124 (e.g., one or more metal layers 150, 152 and 152) and the conductive layer 126. Figure 6Cis an enlarged view showing the portion where the conductive layer 126 is embedded. The interface layer 610 may include one or more of the following elements: tungsten (W), cobalt (Co), copper (Cu), gold (Au), titanium (Ti), tantalum (Ta), aluminum (Al), carbon (C), silicon (Si), nitrogen (N), and other suitable elements that are present in the gate electrode 124 and the conductive layer 126. In some embodiments, the interface layer 610 may be the bottom of the conductive layer 126, which contacts the gate electrode 124. Alternatively, the entire conductive layer 126 embedded below the upper surface of the gate electrode 124 constitutes the interface layer 610. In some embodiments, the interface layer 610 can be formed by molecular mixing between materials of the conductive layer 126 and the gate electrode 124 (for example, one or more metal layers 150, 152 and 154), so that the interface layer 610 includes chemical elements of both the conductive layer 126 and the gate electrode 124 (such as types 612, 614, 616 and 618 shown in the schematic diagram), however, the above elements may form a different composition from the metal layer of the conductive layer 126 or the gate electrode 124.

[0078] At operation 318, referring to FIGS. 7A-7B, the method 300 forms a second interlayer dielectric layer 130 over the conductive layer 126, a portion of the high-k metal gate structure 120, and the first interlayer dielectric layer 110. The second interlayer dielectric layer 130 may include the same or different material as the first interlayer dielectric layer 110, and may be, for example, TEOS, undoped silicon glass, BPSG, FSG, PSG, BSG, a low-k dielectric material, and / or other suitable dielectric substances. Operation 318 forms the second interlayer dielectric layer 130 by a deposition process, such as spin coating, CVD, other suitable methods, or a combination thereof. Operation 318 may also include performing a CMP process to remove excess ILD material located on the upper surface of the device 100.

[0079] The method 300 proceeds to operation 320 to form the contact feature 132. Operation 320 may include multiple steps, such as patterning, deposition, and CMP. First, operation 320 performs a patterning process (including a photolithography process and etching) to form (e.g., pattern) an opening 710 located in the second interlayer dielectric layer 130. From a top view ( Figure 7B ), the opening 710 corresponds to the planar shape of the contact member 132. In some embodiments, the contact member 132 is configured to be circular (eg, Figure 2The contact features 232 of the fin field effect transistor device 200 of the present invention are square, rectangular or other planar shapes. In the embodiment described herein, the opening 710 is formed directly above the upper surface of the gate electrode 124 (e.g., the metal layers 150, 152 and 154) and has a width D aligned with the gate length W. The patterning process may include forming a patterned photoresist layer (not shown) above the hard mask layer (not shown) by coating a photoresist, exposing, baking after exposure, and developing. The hard mask layer may include a material different from the interlayer dielectric layer 130, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or other suitable materials, and may be formed by a suitable method, such as thermal oxidation, CVD, PVD, ALD, other suitable methods or combinations thereof. Thereafter, the hard mask layer is etched using the patterned photoresist as an etching mask to form an opening located in the second interlayer dielectric layer 130. The etching process may include wet etching, dry etching, reactive ion etching or other suitable etching methods.

[0080] Thereafter, referring to FIGS. 8A-8B , a contact member 132 is formed in the opening 710 of the second interlayer dielectric layer 130 by deposition. In some embodiments, the contact member 132 comprises tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver (Ag), manganese (Mn), zirconium (Zr), ruthenium (Ru), other suitable conductive materials, or combinations thereof. The contact member 132 may comprise the same or different material as the conductive layer 126. For example, if the conductive layer 126 comprises metallic tungsten, then the contact member 132 may comprise metallic tungsten, metallic cobalt, and / or metallic aluminum. In some embodiments, operation 320 forms the contact member 132 by a deposition process, such as CVD, PVD, ALD, electroplating, other suitable methods, or combinations thereof. In one embodiment, the contact member 132 is formed by a CVD process different from ALD. In the embodiment described herein, the contact feature 132 is formed using a continuous deposition technique during which a single gas species is used to complete the deposition process. Advantageously, the contact resistance of the interface between the contact feature 132 and the conductive layer 126 is lower than the contact resistance of the interface between the contact feature 132 and the upper surface of the gate electrode 124 (including the metal layers 150, 152, and 154), thereby mitigating the effects of the high impedance interface between the multiple work function metal layers of the high-k metal gate structure 120 and the contact feature 132. Thereafter, one or more planarization processes, such as CMP, may be performed to remove any material located on the upper surface of the device 100.

[0081] In another embodiment, referring to FIGS. 9A-9B , instead of selectively depositing the conductive layer 126 over the upper surface of the gate electrode layer 124 in operation 316 , a portion of the conductive layer 126 is formed over the capping layer 140 and / or the gate dielectric layer 122 , such that the length W″ of the conductive layer 126 is greater than the gate length W but less than the total length L (including the gate dielectric layer 122 and the capping layer 140 ). In some embodiments, the deposition process of the conductive layer 126 is controlled such that the length W″ is at least the gate length W (as in the case of selective deposition) but does not exceed the total length L to avoid electrical shorting of the high-k metal gate 120 during device operation. In one embodiment, the difference between W″ and W is less than about 60% of the total length L. In other embodiments, (W″-W) / 2 is less than about 4 nm.

[0082] Thereafter, referring to FIGS. 10A-10B , the method 300 forms a second interlayer dielectric layer 130 (at operation 318 ), forms an opening (not shown) in the second interlayer dielectric layer 130 (at operation 318 ), and subsequently deposits a conductive material in the opening to form a contact feature 134 (at operation 320 ). The opening may be formed in a manner similar to the formation of the opening 710 described above. In the embodiments described herein, the width D of the contact feature 134 (e.g., the opening formed in the second interlayer dielectric layer 130 ) is offset from the gate length W by a distance S, which refers to a misalignment that occurs during the patterning process. In some embodiments, the offset distance S is less than about 30% of the total length L, and may be formed on either side of the upper surface of the gate electrode 124 . However, since W″ is greater than both D and W, the contact member 134 still establishes a low impedance interface with the conductive layer 126 despite the misalignment S. As described above, by increasing the deposition time of the cycle performed by the first gas species 620 (e.g., WCl5 and WF6) and / or the second gas species 622 (e.g., SiH4 and H2) in operation 316, the conductive layer 126 can be laterally extended to contact the upper surface of the cap layer 140 and / or the gate dielectric layer 122.

[0083] The following discusses various embodiments of the device 100 after forming the contact member 132 (or 134). It is understood that the conductive layer 126 may include any one or combination of the components discussed in FIGS. 11A-11C, 12A-12B, and 13A-13B below. Fig. 11C As shown, Fig. 11C yes Fig.11A11A-11C ) does not extend above the upper surface of the gate dielectric layer 122 to avoid the possibility of shorting the high-k metal gate 120. On the other hand, it is necessary to control H2 to minimize the effect of the conductive layer 126 on the work function metal layers (e.g., 150, 152, and 154). In some embodiments, H1 is in the range of about 1 nm to about 3 nm, and H2 is in the range of about 0 nm to about 8 nm. In embodiments where H2>0 nm, the ratio of H1 / H2 is in the range of about 0.1 to about 1.5. In other embodiments, the total length L is in the range of about 13 nm to about 28 nm, and the gate height H ( Fig.11A ) is in the range of about 10 nm to about 35 nm.

[0084] In some embodiments, as shown in FIGS. 11-11C and 13A-13B, the conductive layer 126 is self-aligned with the metal layers 150, 152, and 154 of the gate electrode 124 and is not formed on the gate dielectric layer 122 or the capping layer 140. In another embodiment, as shown in FIGS. 12A-12B, at least a portion of the conductive layer 126 extends to contact a side ( W ) of the gate electrode 124 (which has a length W). Fig. 12A ) or both sides ( Fig. 12B ) of the upper surface of the gate dielectric layer 122 and / or the capping layer 140. In some embodiments, the portion of the conductive layer 126 formed on the upper surface of the gate dielectric layer 122 and / or the capping layer 140 has a length W', such that W+W'( Fig. 12A ) and W+2xW'( Fig. 12B ) does not exceed the total length L to avoid short circuit of the high-k metal gate 120.

[0085] In some embodiments, as shown in FIGS. 11A-11C and 12A-12B, the conductive layer 126 is configured to have an upper surface and a lower surface that are parallel to the upper surface 120 of the metal gate structure and span the metal layers 150, 152, and 154. Alternatively, as shown in FIGS. 13A-13B, the conductive layer 126 is configured to have an upper surface and a lower surface that are inclined relative to the upper surface 120 of the metal gate structure, so that the thickness of the center of the first portion 170 of the conductive layer 126 is greater than the thickness of the outer edge.

[0086] In some embodiments, the conductive layer 126 is further configured to have a third portion 174 (eg Fig.13A), which selectively penetrates into metal layer 154 but does not penetrate into metal layers 150 or 152. Alternatively, as shown Fig. 13B As shown, the conductive layer 126 is configured to have two portions 176 and 178, which selectively penetrate into the metal layer 152 but do not penetrate into the metal layers 150 or 154. Although the figure shows a conical growth profile, the portions 174, 176 and 178 can be configured to have other geometric profiles. Thus, T1 is the distance from the highest point of the conductive layer 126 (e.g., the highest point of the portion 170) to the upper surface of the high dielectric constant metal gate 120, and T2 is the distance from the lowest point of the conductive layer 126 (e.g., the lowest point of the portions 174, 176 or 178) to the upper surface of the high dielectric constant metal gate 120. Similar to H1 and H2, the size of T1 and T2 is controlled to avoid shorting of the high dielectric constant metal gate 120 and minimize the impact of the conductive layer 126 on the work function metal layers (e.g., 150, 152 and 154). In one embodiment, the ratio of T1 / T2 is in a range of about 0.1 to about 1.5. In one embodiment, T1 is in a range of about 1 nm to about 3 nm, and T2 is in a range of about 2 nm to about 8 nm.

[0087] Embodiments of method 300 may also be performed to form three-dimensional, non-planar devices, such as Figure 2The fin field effect transistor device 200 is described. In some embodiments, a method 300 provides a semiconductor substrate 202 and a fin 204 formed by isolation structure 206. The method 300 proceeds to form a dummy gate structure (not shown) and a gate spacer 228 located above the fin 204 and the isolation feature 206. Thereafter, the method 300 forms a source / drain feature 208 on the fin 204, and then deposits a first interlayer dielectric layer 210 over the isolation feature 206 and the source / drain feature 208. The method 300 then replaces the dummy gate structure with a high-k metal gate structure 220. The components of the device 200 may include similar components to the device 100 and be manufactured using similar methods. For example, similar to the high-k metal gate structure 120, the metal gate structure 220 includes a high-k gate dielectric layer 222 and a gate electrode 224, which may further include multiple conductive material layers. The metal gate structure 220 may further include additional material layers (not shown), such as an interface layer, a capping layer, a diffusion layer, a barrier layer, or a combination thereof. The method 300 further performs forming a conductive layer 226 similar to the conductive layer 126 of the device 100 over the upper surface of the high-k metal gate structure 220. Thereafter, a second interlayer dielectric layer 230 similar to the second interlayer dielectric layer 130 of the device 100 is deposited over the conductive layer 226, a portion of the high-k metal gate structure 220, and the first interlayer dielectric layer 210, and a contact feature 232 is formed in the second interlayer dielectric layer 230 in a manner similar to the formation of the contact feature 132.

[0088] Although not limited, one or more embodiments of the present invention improve semiconductor devices and methods of forming the same. For example, an embodiment of the present invention provides a conductive layer disposed between a metal gate structure and a contact component to reduce the high impedance at the interface between the metal gate structure and the contact component caused by one or more work function metal layers present in the metal gate structure. In addition, by controlling the deposition conditions, the conductive layer can be selectively formed above the gate electrode, or non-selectively formed above both the gate electrode and the insulating material layer of the metal gate structure. The latter morphology increases the contact area between the contact component and the conductive layer, helping to mitigate the effects of misalignment that may occur when forming the contact component.

[0089] The semiconductor device 100 may be included in a microprocessor, a storage memory, and / or other integrated circuit devices. In some embodiments, the semiconductor device 100 may be a part of an IC chip, a system on chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal oxide semiconductor field effect transistors (MOSFETs), CMOS transistors, bipolar junction transistors (BJTs), laterally diffused metal oxide semiconductor (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. Additional components may be added to the semiconductor device 100 through subsequent process steps. For example, different vertical interconnect components, such as contact windows and / or vias; and / or horizontal interconnect components, such as wires, and multi-layer interconnect components, such as metal layers and interlayer dielectric layers, may be formed on the substrate 102 to connect different components of the structure of the semiconductor device 100.

[0090] Therefore, embodiments of the present invention provide any different embodiments to form a semiconductor device. In one aspect, embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes a metal gate structure, the metal gate structure includes a gate dielectric layer and a gate electrode. The semiconductor structure includes a conductive layer formed on the upper surface of the metal gate structure, and a portion of the conductive layer is embedded below the upper surface of the metal gate structure. The semiconductor structure includes a contact component, which is disposed on the upper surface of the metal gate structure, and the contact component is in direct contact with the upper surface of the conductive layer.

[0091] In some embodiments, the gate dielectric layer has an upper surface coplanar with an upper surface of the gate electrode, and the conductive layer is self-aligned with the upper surface of the gate electrode but not self-aligned with the upper surface of the gate dielectric layer.

[0092] In some embodiments, the metal gate structure further comprises a capping layer having an upper surface coplanar with an upper surface of the gate electrode, and the conductive layer is self-aligned to the upper surface of the gate electrode but not self-aligned to the upper surface of the capping layer. In some embodiments, the capping layer comprises hafnium (Hf).

[0093] In some embodiments, the upper surface of the conductive layer is located above the upper surface of the metal gate structure, so that the ratio of the distance between the highest point of the conductive layer and the upper surface of the metal gate structure to the distance between the lowest point of the conductive layer and the upper surface of the metal gate structure is between 0.1 and 1.5.

[0094] In some embodiments, the gate electrode includes two different metal layers, and the conductive layer is in direct contact with the two metal layers. In some embodiments, the conductive layer selectively penetrates into one of the two different metal layers.

[0095] In some embodiments, the conductive layer comprises metallic tungsten and the contact member comprises metallic cobalt. In some embodiments, the portion of the conductive layer embedded below the upper surface of the metal gate structure comprises an interfacial layer comprising at least one element selected from tungsten and nitrogen. In some embodiments, the interfacial layer further comprises at least one selected from titanium, aluminum, tantalum, carbon, and silicon.

[0096] In some embodiments, a contact resistance of an interface between the contact feature and the conductive layer is lower than a contact resistance of an interface between the contact feature and the metal gate structure.

[0097] In other aspects, embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes a metal gate structure, the metal gate structure includes a U-shaped gate dielectric layer and a gate electrode, the gate electrode includes at least one U-shaped metal layer, a portion of the conductive layer penetrates the gate electrode, so that the amount of the conductive layer decreases with the increase of the penetration depth, and a contact component is disposed on the upper surface of the metal gate structure, and the contact component is in direct contact with the upper surface of the conductive layer.

[0098] In some embodiments, the gate electrode includes two different metal layers, and the portion of the conductive layer that penetrates the gate electrode selectively penetrates one of the two different metal layers.

[0099] In some embodiments, the conductive layer includes a portion formed above the upper surface of the metal gate structure, such that a ratio between a distance between a highest point of the conductive layer and the upper surface of the metal gate structure and a distance between a lowest point of the conductive layer and the upper surface of the metal gate structure is between 0.1 and 1.5. In some embodiments, the gate dielectric layer has an upper surface coplanar with the gate electrode, and the portion formed above the upper surface of the metal gate structure extends laterally to contact the upper surface of the gate dielectric layer.

[0100] In other aspects, embodiments of the present invention provide methods for forming semiconductor structures. The method includes forming a metal gate structure, which includes a gate dielectric layer and a gate electrode, wherein the upper surfaces of the gate dielectric layer and the gate electrode are coplanar. The method includes selectively depositing a conductive layer on the upper surface of the gate electrode by using more than one gas species using a cyclic deposition technique. The method includes forming a contact component on the conductive layer by using a gas species using a continuous deposition technique. In some embodiments, the method further includes applying plasma to the exposed upper surface of the gate electrode before selectively depositing the conductive layer, wherein applying the charged plasma and selectively depositing the conductive layer are performed in the same machine.

[0101] In some embodiments, forming the metal gate structure further includes sputtering a capping layer between the gate dielectric layer and the gate electrode, wherein the capping layer includes hafnium (Hf).

[0102] In some embodiments, both the conductive layer and the contact member include metallic tungsten. In another embodiment, the conductive layer includes metallic tungsten and the contact member includes metallic cobalt.

[0103] In some embodiments, the gate electrode includes two different metal layers, wherein the conductive layer directly contacts the upper surfaces of the two metal layers.

[0104] In some embodiments, selectively depositing the conductive layer includes controlling the timing of the deposition such that a portion of the conductive layer laterally extends to contact the upper surface of the gate dielectric layer.

[0105] The features of many embodiments are described above so that those skilled in the art can clearly understand the concept of the present disclosure. Those skilled in the art can understand that they can use the disclosure of the present invention as a basis to design or change other processes and structures to achieve the same purpose and / or achieve the same advantages as the above embodiments. Those skilled in the art can also understand that equivalent structures that do not depart from the concept and scope of the present disclosure can be variously changed, replaced and modified without departing from the concept and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a metal gate structure comprising a gate dielectric layer and a gate electrode; a conductive layer formed on an upper surface of the metal gate structure, wherein a first portion of the conductive layer is embedded below an upper surface of the gate dielectric layer, wherein the first portion of the conductive layer penetrates the gate electrode such that the amount of the conductive layer decreases as the penetration depth increases; an interlayer dielectric layer disposed on the metal gate structure, wherein a second portion of the conductive layer is in direct contact with the interlayer dielectric layer; and A contact component extends through the interlayer dielectric layer to the conductive layer, so that the contact component directly contacts an upper surface of the conductive layer.

2. The semiconductor structure of claim 1, wherein the gate dielectric layer has an upper surface coplanar with an upper surface of the gate electrode, and wherein the conductive layer is self-aligned with the upper surface of the gate electrode but not self-aligned with the upper surface of the gate dielectric layer.

3. The semiconductor structure of claim 1 , wherein the metal gate structure further comprises a capping layer having an upper surface coplanar with the upper surface of the gate electrode, the capping layer comprising hafnium (Hf), and wherein the conductive layer is self-aligned with the upper surface of the gate electrode but not self-aligned with the upper surface of the capping layer.

4. A semiconductor structure as described in claim 1, wherein the upper surface of the conductive layer is located above the upper surface of the metal gate structure, so that the ratio of the distance between the highest point of the conductive layer and the upper surface of the metal gate structure to the distance between the lowest point of the conductive layer and the upper surface of the metal gate structure is between 0.1 and 1.

5. 5 . The semiconductor structure as claimed in claim 1 , wherein the gate electrode comprises two different metal layers, and the conductive layer is in direct contact with the two different metal layers. The semiconductor structure as claimed in claim 5 , wherein the conductive layer selectively penetrates into one of the two different metal layers.

7. The semiconductor structure of claim 1, wherein the conductive layer comprises metallic tungsten, and wherein the contact feature comprises metallic cobalt.

8. The semiconductor structure of claim 7, wherein the first portion of the conductive layer is embedded below the upper surface of the metal gate structure, and the first portion of the conductive layer includes an interface layer, and the interface layer includes at least one element selected from tungsten and nitrogen.

9. The semiconductor structure of claim 8, wherein the interface layer further comprises at least one element selected from titanium, aluminum, tantalum, carbon and silicon. 10 . The semiconductor structure of claim 1 , wherein a contact resistance at an interface between the contact feature and the conductive layer is lower than a contact resistance at an interface between the contact feature and the metal gate structure.

11. A semiconductor structure comprising: A metal gate structure, comprising a U-shaped gate dielectric layer and a gate electrode, wherein the gate electrode comprises at least one U-shaped metal layer; a conductive layer formed on an upper surface of the metal gate structure, wherein a portion of the conductive layer penetrates the gate electrode such that an amount of the conductive layer decreases as the penetration depth increases; and A contact component is disposed on the upper surface of the metal gate structure, wherein the contact component directly contacts an upper surface of the conductive layer. 12 . The semiconductor structure as claimed in claim 11 , wherein the gate electrode comprises two different metal layers, and a portion of the conductive layer penetrating the gate electrode selectively penetrates one of the two different metal layers.

13. A semiconductor structure as described in claim 11, wherein the conductive layer includes a portion formed above the upper surface of the metal gate structure, so that the ratio between the distance between the highest point of the conductive layer and the upper surface of the metal gate structure and the distance between the lowest point of the conductive layer and the upper surface of the metal gate structure is between 0.1 and 1.

5.

14. The semiconductor structure of claim 13, wherein the U-shaped gate dielectric layer has an upper surface coplanar with an upper surface of the gate electrode, and the portion formed above the upper surface of the metal gate structure extends laterally to contact the upper surface of the U-shaped gate dielectric layer.

15. A method for forming a semiconductor structure, comprising: forming a metal gate structure, wherein the metal gate structure comprises a gate dielectric layer and a gate electrode, and wherein an upper surface of the gate dielectric layer is coplanar with an upper surface of the gate electrode; selectively depositing a conductive layer on the upper surface of the gate electrode by a cyclic deposition technique using two gas precursors, wherein a first portion of the conductive layer penetrates the gate electrode such that the amount of the conductive layer decreases with increasing penetration depth; and A contact feature is formed on the conductive layer by using a continuous deposition technique of a single gas precursor. 16 . The method of claim 15 , wherein forming the metal gate structure comprises sputtering a capping layer between the gate dielectric layer and the gate electrode, wherein the capping layer comprises hafnium (Hf). 17 . The method of claim 15 , wherein both the conductive layer and the contact member comprise metallic tungsten. 18 . The method of claim 15 , wherein the conductive layer comprises metallic tungsten, and the contact member comprises metallic cobalt. 19 . The forming method according to claim 15 , further comprising applying plasma to the upper surface of the metal gate structure before selectively depositing the conductive layer, wherein applying plasma and selectively depositing the conductive layer are performed in the same machine. 20 . The method of claim 15 , wherein selectively depositing the conductive layer comprises controlling a deposition time such that a portion of the conductive layer laterally extends to contact the upper surface of the gate dielectric layer.

21. A semiconductor structure comprising: a gate stack including a metal gate electrode disposed on a gate dielectric layer; a metal layer disposed on the gate stack, wherein an upper portion of the metal layer spans a width of the metal gate electrode and a bottom portion of the metal layer penetrates the metal gate electrode such that an amount of the metal layer decreases as penetration depth increases; an interlayer dielectric layer disposed on the gate stack; and A gate contact is disposed in the interlayer dielectric layer and on the upper portion of the metal layer. 22 . The semiconductor structure of claim 21 , wherein the gate stack further comprises a capping layer disposed between the gate dielectric layer and the metal gate electrode.

23. The semiconductor structure of claim 21, wherein the bottom portion of the metal layer is laterally defined by a first width, the top portion of the metal layer is laterally defined by a second width, and the second width is greater than the first width.

24. The semiconductor structure as described in claim 21 further includes an interface layer, which is arranged between the metal layer and an upper surface of the gate stack, wherein the interface layer includes one or more chemical elements, and the one or more chemical elements are included in the metal layer, the metal gate electrode or a combination thereof.

25. A semiconductor structure comprising: A high-k metal gate stack includes a gate dielectric layer, a first metal layer, and a second metal layer different from the first metal layer; a conductive layer disposed on an upper surface of the high-k metal gate stack, wherein a first portion of the conductive layer that penetrates the first metal layer is below a second portion of the conductive layer that penetrates the second metal layer, wherein an amount of the conductive layer decreases as a penetration depth in the first metal layer increases; as well as A gate contact is disposed on the high dielectric constant metal gate stack and contacts an upper portion of the conductive layer. 26 . The semiconductor structure of claim 25 , wherein the first metal layer is a work function metal layer disposed on the gate dielectric layer, and the second metal layer is a bulk conductive layer disposed on the work function metal layer.

27. The semiconductor structure of claim 25, wherein the first metal layer is a bulk conductive layer disposed on the second metal layer, and the second metal layer is a work function metal layer disposed on the gate dielectric layer.

28. The semiconductor structure as described in claim 25 further includes an interface layer, which is disposed between the conductive layer and the upper surface of the high-k metal gate stack, and the composition of the interface layer is different from the composition of the conductive layer, the first metal layer or the second metal layer.

29. The semiconductor structure of claim 25, wherein a contact resistance at an interface between the gate contact and the conductive layer is lower than a contact resistance at an interface between the conductive layer and the high-k metal gate stack.

30. A method for forming a semiconductor structure, comprising: forming a metal gate stack, wherein the metal gate stack comprises a gate dielectric layer and a gate electrode disposed on the gate dielectric layer; performing a plasma treatment on an upper surface of the metal gate stack; forming a metal layer on the metal gate stack, such that an upper portion of the metal layer contacts the processed upper surface of the metal gate stack, and a bottom portion of the metal layer penetrates the gate electrode, such that the amount of the metal layer decreases with increasing penetration depth; forming an interlayer dielectric layer on the metal layer so that the upper portion of the metal layer is embedded in the interlayer dielectric layer; forming a contact opening in the interlayer dielectric layer to expose the upper portion of the metal layer; as well as A conductive component is formed in the contact opening to contact the upper portion of the metal layer.

31. The method of claim 30, wherein performing the plasma treatment comprises treating the metal gate stack with argon, ammonia, or a combination thereof.

32. The forming method of claim 30, wherein the plasma treatment is performed to remove a native oxide formed on a portion of the gate electrode. 33 . The method of claim 30 , wherein forming the metal layer comprises selectively depositing the upper portion of the metal layer on the gate electrode.

34. A semiconductor structure comprising: A metal gate structure including a gate dielectric layer and a gate electrode; a conductive layer disposed on the metal gate structure, the conductive layer comprising a bottom portion disposed below an upper surface of the metal gate structure and an upper portion disposed on the upper surface of the metal gate structure, and the upper portion laterally extends beyond a side wall of the bottom portion, wherein the bottom portion of the conductive layer penetrates the gate electrode, so that the amount of the conductive layer decreases with increasing penetration depth; and A contact member directly contacts the upper portion of the conductive layer.

35. The semiconductor structure of claim 34, wherein the sidewall of the bottom portion of the conductive layer is defined by the gate electrode. 36 . The semiconductor structure of claim 34 , further comprising a capping layer disposed between the gate dielectric layer and the gate electrode.

37. The semiconductor structure of claim 34, further comprising an interlayer dielectric layer disposed on the metal gate structure and surrounding the contact feature, wherein a sidewall of the upper portion of the conductive layer is defined by the interlayer dielectric layer.

38. The semiconductor structure of claim 34, wherein the upper portion of the conductive layer is embedded in the contact feature.

39. The semiconductor structure as described in claim 34 further includes an interface layer, which is arranged between the conductive layer and the upper surface of the metal gate structure, and the interface layer includes one or more chemical elements, and the one or more chemical elements are included in the conductive layer, the gate electrode or a combination thereof.

40. A semiconductor structure comprising: A gate stack includes a high-k gate dielectric layer and a metal gate electrode disposed on the high-k gate dielectric layer; a metal layer disposed on the gate stack, wherein the metal layer includes a first portion disposed on a second portion, wherein the second portion of the metal layer penetrates the metal gate electrode such that an amount of the metal layer decreases with increasing penetration depth; as well as A gate contact is in direct contact with the first portion of the metal layer, wherein a side wall of the first portion of the metal layer is defined by the gate contact, and a side wall of the second portion of the metal layer is defined by the metal gate electrode. 41 . The semiconductor structure of claim 40 , wherein a width of the second portion of the metal layer decreases with distance away from an upper surface of the gate stack.

42. A semiconductor structure as described in claim 40, wherein the metal gate electrode includes a first layer and a second layer on the first layer, and the first layer and the second layer have different compositions, and the sidewall of the second portion of the metal layer is defined by the first layer rather than the second layer.

43. A semiconductor structure as described in claim 40, wherein the metal gate electrode includes a first layer and a second layer on the first layer, and the first layer and the second layer have different compositions, and the sidewall of the second portion of the metal layer is defined by the second layer rather than the first layer.

44. The semiconductor structure of claim 40, further comprising an interface layer disposed between the metal layer and an upper surface of the gate stack, and the composition of the interface layer is different from the composition of the metal layer and the composition of the metal gate electrode.

45. The semiconductor structure of claim 40, wherein a contact resistance at an interface between the gate contact and the metal layer is lower than a contact resistance at an interface between the metal layer and the gate stack.

46. ​​A semiconductor structure comprising: A gate stack includes a high-k gate dielectric layer and a metal gate electrode disposed on the high-k gate dielectric layer; a conductive layer disposed on the gate stack, wherein the conductive layer includes an upper portion disposed on a bottom portion, wherein the upper portion laterally spans a first distance, the bottom portion penetrates the gate stack and laterally spans a second distance, and the second distance is less than the first distance, wherein the bottom portion of the conductive layer penetrates the metal gate electrode such that the amount of the conductive layer decreases as the penetration depth increases; and A gate contact is in direct contact with the upper portion of the conductive layer.

47. The semiconductor structure of claim 46, wherein the bottom of the conductive layer is embedded in the metal gate electrode.

48. The semiconductor structure of claim 46, wherein the gate stack further comprises a capping layer disposed between the high-k gate dielectric layer and the metal gate electrode.

49. A semiconductor structure as described in claim 46, wherein the metal gate electrode includes a first metal layer and a second metal layer disposed on the first metal layer, the first metal layer and the second metal layer have different compositions, and the bottom of the conductive layer selectively penetrates the first metal layer compared to the second metal layer.

50. A semiconductor structure as described in claim 46, wherein the metal gate electrode includes a first metal layer and a second metal layer disposed on the first metal layer, the first metal layer and the second metal layer have different compositions, and the bottom of the conductive layer selectively penetrates the second metal layer compared to the first metal layer.

51. The semiconductor structure of claim 46, further comprising an interface layer, the interface layer being disposed between the conductive layer and an upper surface of the metal gate electrode, and the composition of the interface layer being different from the composition of both the conductive layer and the metal gate electrode.

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