Replacement Gate Structure for Fabricating Advanced Integrated Circuit Structures

Abstract

Embodiments of the present disclosure pertain to the field of manufacturing advanced integrated circuit structures, and more particularly to the field of manufacturing integrated circuit structures at the 10-nanometer node and smaller and the resulting structures. In an example, an integrated circuit structure includes fins. An isolation structure surrounds the lower fin portions, the isolation structure including an insulating material having a top surface and semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fins. A gate dielectric layer is over the top of the upper fin portions and laterally adjacent to sidewalls of the upper fin portions, the gate dielectric layer further being over the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 593,149, entitled "ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION", filed on Nov. 30, 2017, the entire content of which is incorporated herein by reference. Field of the Invention

[0003] Embodiments of the present disclosure are in the field of advanced integrated circuit structure fabrication, and more particularly, in the field of fabricating integrated circuit structures at the 10 - nanometer node and smaller, and the resulting structures. Background Art

[0004] For the past several decades, the scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller features enables an increase in the density of functional units on the limited footprint of a semiconductor chip. For example, shrinking the size of transistors allows for the incorporation of a greater number of memory or logic devices on a chip, resulting in the fabrication of products with greater capacity. However, the drive for ever - greater capacity is not without problems. The need to optimize the performance of each device becomes increasingly important.

[0005] Variability in conventional and currently known manufacturing processes may limit the possibility of further scaling them into the 10 - nanometer node or sub - 10 - nanometer node range. Therefore, the fabrication of functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies in current manufacturing processes, or the replacement of current manufacturing processes with them. Brief Description of the Drawings

[0006] Figure 1A A cross - sectional view of a starting structure is shown after deposition of a hard mask material layer formed on an interlayer dielectric (ILD) layer, but before its patterning.

[0007] Figure 1B A cross - sectional view of the structure is shown after patterning the hard mask layer by pitch - halving Figure 1A of the structure.

[0008] Figure 2A is a schematic diagram of a pitch - quartering method for fabricating semiconductor fins according to an embodiment of the present disclosure.

[0009] Figure 2B A cross - sectional view of semiconductor fins fabricated using the pitch - quartering method according to an embodiment of the present disclosure is shown.

[0010] Figure 3ASchematic diagram of the fusion fin pitch quartering method for manufacturing semiconductor fins according to an embodiment of the present disclosure.

[0011] Figure 3B Cross-sectional view of semiconductor fins manufactured using the fusion fin pitch quartering method according to an embodiment of the present disclosure.

[0012] Figures 4A - 4C Cross-sectional view showing various operations in a method of manufacturing multiple semiconductor fins according to an embodiment of the present disclosure.

[0013] Figure 5A Cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure according to an embodiment of the present disclosure.

[0014] Figure 5B Cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure according to another embodiment of the present disclosure.

[0015] Figures 6A - 6D Cross-sectional view showing various operations during the manufacture of a three-layer trench isolation structure according to an embodiment of the present disclosure.

[0016] Figures 7A - 7E Oblique three-dimensional cross-sectional view showing various operations in a method of manufacturing an integrated circuit structure according to an embodiment of the present disclosure.

[0017] Figures 8A - 8F Shows, according to an embodiment of the present disclosure, for various operations in a method of manufacturing an integrated circuit structure, along Figure 7E Slightly projected cross-sectional view taken along the a-a' axis.

[0018] Figure 9A Shows, according to an embodiment of the present disclosure, for an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region, along Figure 7E Slightly projected cross-sectional view taken along the a-a' axis.

[0019] Figure 9B Shows, according to an embodiment of the present disclosure, for an integrated circuit structure including an epitaxial source or drain region and a three-layer trench isolation structure, along Figure 7E Cross-sectional view taken along the b-b' axis.

[0020] Figure 10 Cross-sectional view of an integrated circuit structure taken at the source or drain position according to an embodiment of the present disclosure.

[0021] Figure 11 Cross-sectional view of another integrated circuit structure taken at the source or drain position according to an embodiment of the present disclosure.

[0022] Figures 12A - 12D A cross-sectional view is shown that depicts various operations in a method of fabricating an integrated circuit structure, taken at a source or drain location and in accordance with an embodiment of the present disclosure.

[0023] Figure 13A and Figure 13B A plan view is shown that depicts various operations in a method of patterning a fin having a multi-gate pitch for forming a local isolation structure, in accordance with an embodiment of the present disclosure.

[0024] Figures 14A - 14D A plan view is shown that depicts various operations in a method of patterning a fin having a single-gate pitch for forming a local isolation structure, in accordance with another embodiment of the present disclosure.

[0025] Figure 15 A cross-sectional view is shown of an integrated circuit structure having a fin with a multi-gate pitch for local isolation, in accordance with an embodiment of the present disclosure.

[0026] Figure 16A A cross-sectional view is shown of an integrated circuit structure having a fin with a single-gate pitch for local isolation, in accordance with another embodiment of the present disclosure.

[0027] Figure 16B A cross-sectional view is shown that depicts a location where a fin isolation structure can be formed to replace a gate electrode, in accordance with an embodiment of the present disclosure.

[0028] Figures 17A - 17C A cross-sectional view is shown that depicts various depth possibilities for a fin incision fabricated using a fin trimming isolation approach, in accordance with an embodiment of the present disclosure.

[0029] Figure 18 A plan view and a corresponding cross-sectional view taken along the a-a' axis are shown that depict possible options comparing the depth at a local location of a fin incision within a fin to the depth at a wider location, in accordance with an embodiment of the present disclosure.

[0030] Figure 19A and Figure 19B A cross-sectional view is shown that depicts various operations in a method of selecting a fin end stress source location at an end of a fin having a wide incision, in accordance with an embodiment of the present disclosure.

[0031] Figure 20A and Figure 20B A cross-sectional view is shown that depicts various operations in a method of selecting a fin end stress source location at an end of a fin having a local incision, in accordance with an embodiment of the present disclosure.

[0032] Figures 21A - 21MA cross-sectional view showing various operations in a method of manufacturing an integrated circuit structure with a differentiated fin end dielectric plug according to an embodiment of the present disclosure.

[0033] Figures 22A - 22D A cross-sectional view showing an exemplary structure of a PMOS fin end stress source dielectric plug according to an embodiment of the present disclosure.

[0034] Figure 23A A cross-sectional view showing another semiconductor structure with fin end stress-induced features according to another embodiment of the present disclosure.

[0035] Figure 23B A cross-sectional view showing another semiconductor structure with fin end stress-induced features according to another embodiment of the present disclosure.

[0036] Figure 24A An inclined view showing a fin with uniaxial tensile stress according to an embodiment of the present disclosure.

[0037] Figure 24B An inclined view showing a fin with uniaxial compressive stress according to an embodiment of the present disclosure.

[0038] Figure 25A and Figure 25B A plan view showing various operations in a method of patterning a fin with a single gate pitch for forming a local isolation structure at a selected gate line cut location according to an embodiment of the present disclosure.

[0039] Figures 26A - 26C Shows according to an embodiment of the present disclosure for Figure 25B A cross-sectional view of various possibilities of dielectric plugs for multi-cut and fin trim isolation (FTI) local fin cut locations and only multi-cut locations for respective regions of the structure.

[0040] Figure 27A A plan view and a corresponding cross-sectional view of an integrated circuit structure with a gate line cut having a dielectric plug extending into a dielectric spacer of the gate line according to an embodiment of the present disclosure.

[0041] Figure 27B A plan view and a corresponding cross-sectional view of an integrated circuit structure with a gate line cut having a dielectric plug extending outside a dielectric spacer of the gate line according to another embodiment of the present disclosure.

[0042] Figures 28A - 28FA cross-sectional view shows various operations in a method of manufacturing an integrated circuit structure having a gate line cut with a dielectric plug, the dielectric plug having an upper portion extending beyond a dielectric spacer of the gate line and a lower portion extending into the gate line dielectric spacer, in accordance with another embodiment of the present disclosure.

[0043] Figures 29A - 29C A plan view and a corresponding cross-sectional view of an integrated circuit structure having residual dummy gate material at a portion at the bottom of a permanent gate stack are shown, in accordance with an embodiment of the present disclosure.

[0044] Figures 30A - 30D A cross-sectional view shows various operations in a method of manufacturing an integrated circuit structure having residual dummy gate material at a portion at the bottom of a permanent gate stack, in accordance with another embodiment of the present disclosure.

[0045] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure is shown, in accordance with an embodiment of the present disclosure.

[0046] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure is shown, in accordance with another embodiment of the present disclosure.

[0047] Figure 32A A plan view of a plurality of gate lines over a pair of semiconductor fins is shown, in accordance with an embodiment of the present disclosure.

[0048] Figure 32B A cross-sectional view taken along the Figure 32A a-a' axis is shown, in accordance with an embodiment of the present disclosure.

[0049] Figure 33A A cross-sectional view of a pair of NMOS devices and a pair of PMOS devices is shown, the pair of NMOS devices having a differential voltage threshold based on modulated doping and the pair of PMOS devices having a differential voltage threshold based on modulated doping, in accordance with an embodiment of the present disclosure.

[0050] Figure 33B A cross-sectional view of a pair of NMOS devices and a pair of PMOS devices is shown, the pair of NMOS devices having a differential voltage threshold based on a differential gate electrode structure and the pair of PMOS devices having a differential voltage threshold based on a differential gate electrode structure, in accordance with another embodiment of the present disclosure.

[0051] Figure 34AA cross-sectional view of three NMOS devices and three PMOS devices according to an embodiment of the present disclosure is shown. The three NMOS devices have different voltage thresholds based on a differentiated gate electrode structure and a modulated doping, and the three PMOS devices have different voltage thresholds based on a differentiated gate electrode structure and a modulated doping.

[0052] Figure 34B A cross-sectional view of three NMOS devices and three PMOS devices according to another embodiment of the present disclosure is shown. The three NMOS devices have different voltage thresholds based on a differentiated gate electrode structure and a modulated doping, and the three PMOS devices have different voltage thresholds based on a differentiated gate electrode structure and a modulated doping.

[0053] Figures 35A - 35D A cross-sectional view of various operations in a method of manufacturing an NMOS device having a different voltage threshold based on a differentiated gate electrode structure according to an embodiment of the present disclosure is shown.

[0054] Figures 36A - 36D A cross-sectional view of various operations in a method of manufacturing a PMOS device having a different voltage threshold based on a differentiated gate electrode structure according to an embodiment of the present disclosure is shown.

[0055] Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is shown.

[0056] Figures 38A - 38H A cross-sectional view of various operations in a method of manufacturing an integrated circuit structure using a dual-metal gate replacement gate process flow according to an embodiment of the present disclosure is shown.

[0057] Figures 39A - 39H A cross-sectional view of various operations representing a method of manufacturing a dual-silicide-based integrated circuit according to an embodiment of the present disclosure is shown.

[0058] Figure 40A A cross-sectional view of an integrated circuit structure having a trench contact portion for an NMOS device according to an embodiment of the present disclosure is shown.

[0059] Figure 40B A cross-sectional view of an integrated circuit structure having a trench contact portion for a PMOS device according to another embodiment of the present disclosure is shown.

[0060] Figure 41A A cross-sectional view of a semiconductor device having a conductive contact portion on a source or drain region according to an embodiment of the present disclosure is shown.

[0061] Figure 41BA cross-sectional view of another semiconductor device having a conductive contact on an elevated source or drain region, according to an embodiment of the present disclosure.

[0062] Figure 42 A plan view of a plurality of gate lines over a pair of semiconductor fins, according to an embodiment of the present disclosure.

[0063] Figures 43A - 43C A cross-sectional view taken along the Figure 42 a-a' axis of various operations in a method for fabricating an integrated circuit structure, according to an embodiment of the present disclosure.

[0064] Figure 44 A cross-sectional view of an integrated circuit structure taken along the Figure 42 b-b' axis, according to an embodiment of the present disclosure.

[0065] Figure 45A and Figure 45B A plan view and a corresponding cross-sectional view of an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to an embodiment of the present disclosure.

[0066] Figures 46A - 46D A cross-sectional view representing various operations in a method for fabricating an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to an embodiment of the present disclosure.

[0067] Figure 47A A plan view of a semiconductor device having a gate contact over a non-active portion of a gate electrode. Figure 47B A cross-sectional view of a non-planar semiconductor device having a gate contact over a non-active portion of a gate electrode.

[0068] Figure 48A A plan view of a semiconductor device having a gate contact via over an active portion of a gate electrode, according to an embodiment of the present disclosure. Figure 48B A cross-sectional view of a non-planar semiconductor device having a gate contact via over an active portion of a gate electrode, according to an embodiment of the present disclosure.

[0069] Figures 49A - 49D A cross-sectional view representing various operations in a method for fabricating a semiconductor structure having a gate contact structure over an active portion of a gate, according to an embodiment of the present disclosure.

[0070] Figure 50 A plan view and a corresponding cross-sectional view of an integrated circuit structure having a trench contact portion including an overlying insulating capping layer, according to an embodiment of the present disclosure.

[0071] Figures 51A - 51F Shows cross-sectional views of various integrated circuit structures in accordance with embodiments of the present disclosure, each integrated circuit structure having a trench contact portion including an overlying insulating capping layer and having a gate stack including an overlying insulating capping layer.

[0072] Figure 52A Shows a plan view of another semiconductor device having a gate contact via disposed over an active portion of a gate in accordance with another embodiment of the present disclosure.

[0073] Figure 52B Shows a plan view of another semiconductor device having a trench contact via coupling trench contact pairs in accordance with another embodiment of the present disclosure.

[0074] Figures 53A - 53E Shows cross-sectional views representing various operations in a method of manufacturing an integrated circuit structure having a gate stack including an overlying insulating capping layer in accordance with embodiments of the present disclosure.

[0075] Figure 54 Is a schematic diagram of a quartering method of pitch for trenches for manufacturing an interconnect structure in accordance with embodiments of the present disclosure.

[0076] Figure 55A Shows a cross-sectional view of a metallization layer manufactured using a quartering pitch scheme in accordance with embodiments of the present disclosure.

[0077] Figure 55B Shows a cross-sectional view of a metallization layer manufactured using a halving pitch scheme over a metallization layer manufactured using a quartering pitch scheme in accordance with embodiments of the present disclosure.

[0078] Figure 56A Shows a cross-sectional view of an integrated circuit structure in accordance with embodiments of the present disclosure in which a metallization layer having one metal line component is over a metallization layer having a different metal line component.

[0079] Figure 56B Shows a cross-sectional view of an integrated circuit structure in accordance with embodiments of the present disclosure in which a metallization layer having one metal line component is coupled to a metallization layer having a different metal line component.

[0080] Figures 57A - 57C Shows a cross-sectional view of an individual interconnect having various liner and conductive capping structure arrangements in accordance with embodiments of the present disclosure.

[0081] Figure 58 Shows a cross-sectional view of an integrated circuit structure in accordance with embodiments of the present disclosure in which four metallization layers having one metal line component and pitch are over two metallization layers having different metal line components and a smaller pitch.

[0082] Figures 59A - 59D A cross-sectional view showing various interconnect and via arrangements with a bottom conductive layer according to an embodiment of the present disclosure.

[0083] Figures 60A - 60D A cross-sectional view showing a structural arrangement of a recessed line profile for a BEOL metallization layer according to an embodiment of the present disclosure.

[0084] Figures 61A - 61D A cross-sectional view showing a structural arrangement of a stepped line profile for a BEOL metallization layer according to an embodiment of the present disclosure.

[0085] Figure 62A A plan view and a corresponding cross-sectional view taken along the a-a' axis of the plan view of a metallization layer according to an embodiment of the present disclosure are shown.

[0086] Figure 62B A cross-sectional view showing a line end or a plug according to an embodiment of the present disclosure.

[0087] Figure 62C Another cross-sectional view showing a line end or a plug according to an embodiment of the present disclosure.

[0088] Figures 63A - 63F A plan view and a corresponding cross-sectional view showing various operations in a plug final processing scheme according to an embodiment of the present disclosure are shown.

[0089] Figure 64A A cross-sectional view showing a conductive line plug with a seam therein according to an embodiment of the present disclosure.

[0090] Figure 64B A cross-sectional view showing a stack of metallization layers including a conductive line plug at a lower metal line position according to an embodiment of the present disclosure.

[0091] Figure 65 A first view of a cell layout for a memory cell is shown.

[0092] Figure 66 A first view of a cell layout for a memory cell having an internal node jumper according to an embodiment of the present disclosure is shown.

[0093] Figure 67 A second view of a cell layout for a memory cell is shown.

[0094] Figure 68 A second view of a cell layout for a memory cell having an internal node jumper according to an embodiment of the present disclosure is shown.

[0095] Figure 69 A third view of a cell layout for a memory cell is shown.

[0096] Figure 70 Shows a third view of a cell layout for a memory cell with an internal node jumper, according to an embodiment of the present disclosure.

[0097] Figure 71A And Figure 71B Show a bit cell layout and a schematic diagram for a six-transistor (6T) static random access memory (SRAM), respectively, according to an embodiment of the present disclosure.

[0098] Figure 72 Shows a cross-sectional view of two different layouts for the same standard cell, according to an embodiment of the present disclosure.

[0099] Figure 73 Shows a plan view of four different cell arrangements indicating even (E) or odd (O) designations, according to an embodiment of the present disclosure.

[0100] Figure 74 Shows a plan view of a block-level multi-grid, according to an embodiment of the present disclosure.

[0101] Figure 75 Shows an exemplary acceptable (pass) layout based on standard cells with different versions, according to an embodiment of the present disclosure.

[0102] Figure 76 Shows an exemplary unacceptable (fail) layout based on standard cells with different versions, according to an embodiment of the present disclosure.

[0103] Figure 77 Shows another exemplary acceptable (pass) layout based on standard cells with different versions, according to an embodiment of the present disclosure.

[0104] Figure 78 Shows a partial cut plan view and a corresponding cross-sectional view of a fin-based thin film resistor structure, according to an embodiment of the present disclosure, where the cross-sectional view is taken along the a-a' axis of the partial cut plan view.

[0105] Figures 79 - 83 Shows a plan view and a corresponding cross-sectional view representing various operations in a method of manufacturing a fin-based thin film resistor structure, according to an embodiment of the present disclosure.

[0106] Figure 84 Shows a plan view of a fin-based thin film resistor structure with multiple exemplary positions for anode or cathode electrode contacts, according to an embodiment of the present disclosure.

[0107] Figures 85A - 85DPlan views of various fin geometries for fabricating fin-based precision resistors according to embodiments of the present disclosure are shown.

[0108] Figure 86 A cross-sectional view of a photolithography mask structure according to an embodiment of the present disclosure is shown.

[0109] Figure 87 A computing device according to one embodiment of the present disclosure is shown.

[0110] Figure 88 An interposer including one or more embodiments of the present disclosure is shown.

[0111] Figure 89 is an isometric view of a mobile computing platform according to an embodiment of the present disclosure, the mobile computing platform employing an IC manufactured according to one or more processes described herein or including one or more features described herein.

[0112] Figure 90 A cross-sectional view of a flip-chip mounted die is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0113] Advanced integrated circuit structure manufacturing is described. In the following description, many specific details are set forth, such as specific integration and material systems, in order to provide a deeper understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be recognized that the various embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale.

[0114] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the term "exemplary" means "used as an example, instance, or illustration". Any embodiment described herein as exemplary is not necessarily understood to be preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory presented in the aforementioned technical field, background technology, summary of the invention, or the following detailed description.

[0115] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0116] Terms. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0117] "Comprising". This term is open-ended. As used in the appended claims, this term does not exclude additional structure or acts.

[0118] "Configured to". Various units or components may be described or claimed as "configured to" perform one or more tasks. In this context, "configured to" is used to imply structure by indicating that the unit or component includes the structure that performs one or more of those tasks during operation. Thus, even when the specified unit or component is not currently operating (e.g., not turned on or active), the unit or component can be said to be configured to perform the task. Reciting that a unit or circuit or component "is configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, paragraph 6, for that unit or component.

[0119] "First", "second", etc. As used herein, these terms serve as labels for the nouns that follow and do not imply any type of order (e.g., spatial, temporal, logical, etc.).

[0120] "Coupled" - The following description refers to elements or nodes or features that are "coupled" together. As used herein, unless otherwise expressly specified, "coupled" means that an element or node or feature is directly or indirectly connected to another element or node or feature (or directly or indirectly communicates with it), and is not necessarily in a mechanical manner.

[0121] In addition, certain terms are also used for reference purposes only in the following description, and thus these terms are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to the directions provided for reference in the drawings. Terms such as "front", "back", "rear", "side", "outer", and "inner" describe the orientation or position or both of parts of a component within a consistent but arbitrary reference system, which can be clearly understood by referring to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0122] "Suppress" - As used in this application, suppress is used to describe reducing an effect or minimizing it. When a component or feature is described as suppressing an action, movement, or condition, it may completely prevent an outcome or consequence or a future state. Additionally, "suppress" can also refer to reducing or lowering a consequence, manifestation, or effect that might otherwise occur. Thus, when a component, element, or feature is said to suppress an outcome or state, it does not necessarily completely prevent or eliminate the said outcome or state.

[0123] The embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses everything up to (but not including) the deposition of the metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wiring).

[0124] The embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring such as one or more metallization layers on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage, contacts (pads), interconnect lines, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in BEOL.

[0125] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such an approach may also be applicable to BEOL processing. Similarly, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such an approach may also be applicable to FEOL processing.

[0126] Pitch division processing and patterning schemes may be implemented to achieve the embodiments described herein, or may be included as part of the embodiments described herein. Pitch division patterning typically refers to pitch halving, pitch quartering, etc. Pitch division schemes may be applicable to FEOL processing, BEOL processing, or both FEOL (devices) and BEOL (metallization) processing. According to one or more embodiments described herein, lithography is first performed to print unidirectional lines (e.g., strictly unidirectional or predominantly unidirectional) with a predefined pitch. Then pitch division processing is performed as a technique to increase line density.

[0127] In an embodiment, the term "grid structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a close-pitch grid structure. In one such embodiment, the close pitch cannot be achieved directly by selected lithography. For example, a pattern based on selected lithography can be formed first, but the pitch can be halved using spacer mask patterning, as is known in the art. Further, the initial pitch can be quartered by a second round of spacer mask patterning. Therefore, the grid-like pattern described herein can have metal lines, ILD lines, or hard mask lines spaced at substantially uniform spacings and having substantially uniform widths. For example, in some embodiments, the spacing variation will be within ten percent, the width variation will be within ten percent, and in some embodiments, the spacing variation will be within five percent, and the width variation will be within five percent. The pattern can be manufactured by halving the spacing or quartering the spacing, or other spacing division methods. In an embodiment, the grid is not necessarily a single spacing.

[0128] In a first example, pitch halving may be implemented to double the line density of the fabricated grid structure. Figure 1A A cross-sectional view of the starting structure is shown after deposition of a hard mask material layer formed on an inter-layer dielectric (ILD) layer, but before patterning thereof. Figure 1B shows the hard mask layer after patterning by halving the pitch Figure 1A A cross-sectional view of the structure.

[0129] refer to Figure 1A , a starting structure 100 has a hard mask material layer 104 formed on an inter-layer dielectric (ILD) layer 102. A patterned mask 106 is disposed over the hard mask material layer 104. The patterned mask 106 has spacers 108 formed on the hard mask material layer 104 along the sidewalls of the features (lines) thereof.

[0130] refer to Figure 1B , the hard mask material layer 104 is patterned in a pitch-halving manner. Specifically, the patterned mask 106 is first removed. The resulting pattern of the spacer 108 has doubled the density of the mask 106, or halved the pitch or features of the mask 106. For example, the pattern of the spacer 108 is transferred to the hard mask material layer 104 by an etching process to form a patterned hard mask 110, as shown in FIG. 1B . In one such embodiment, the patterned hard mask 110 is formed to have a grid pattern having unidirectional lines. The grid pattern of the patterned hard mask 110 can be a closely spaced grid pattern. For example, a closely spaced pitch may not be directly achievable by a selected photolithography technique. Further, although not shown, the initial pitch may be quartered by a second round of spacer mask patterning. Thus, Figure 1BThe grid-like pattern of the patterned hard mask 110 may have hard mask lines spaced apart from each other at a constant pitch and having a constant width. The dimensions achieved can be much smaller than the critical dimensions of the lithography technology employed.

[0131] Accordingly, for front-end-of-line (FEOL) or back-end-of-line (BEOL) or both, a homogeneous film can be patterned using lithography and etching processes, which can involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering. It should be appreciated that other pitch division methods can also be implemented. In any case, in an embodiment, the grid layout can be fabricated by a selected lithography method (e.g., 193nm immersion lithography (193i)). Pitch division can be implemented to increase the density of the lines in the grid layout by a factor of n. The grid layout formed using 193i lithography plus "n" times pitch division can be designated as 193i+P / n pitch division. In one such embodiment, 193nm immersion scaling can be continued for many generations using cost-effective pitch division.

[0132] In the fabrication of integrated circuit devices, as device dimensions continue to shrink, multi-gate transistors such as tri-gate transistors have become more prevalent. Tri-gate transistors are typically fabricated on a bulk silicon substrate or a silicon-on-insulator substrate. In some instances, a bulk silicon substrate is preferred because it is less costly and compatible with existing high-yield bulk silicon substrate infrastructure.

[0133] However, scaling multi-gate transistors is not without consequences. As the dimensions of these building blocks of microelectronic circuits decrease and as the absolute number of building blocks fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

[0134] According to one or more embodiments of the present disclosure, a pitch quartering method is implemented for patterning a semiconductor layer to form semiconductor fins. In one or more embodiments, a fused fin pitch quartering method is implemented.

[0135] Figure 2A is a schematic diagram of a pitch quartering method 200 for fabricating semiconductor fins according to an embodiment of the present disclosure. Figure 2B A cross-sectional view of semiconductor fins fabricated using the pitch quartering method according to an embodiment of the present disclosure is shown.

[0136] Reference Figure 2A, in operation (a), the photoresist layer (PR) is patterned to form photoresist features 202. Standard lithography processing techniques such as 193 immersion lithography can be used to pattern the photoresist features 202. In operation (b), a material layer such as an insulating layer or a dielectric hard mask layer is patterned using the photoresist features 202 to form a first backbone (BB1) feature 204. Then a first spacer (SP1) feature 206 adjacent to the sidewalls of the first backbone feature 204 is formed. In operation (c), the first backbone feature 204 is removed to leave only the first spacer feature 206. Before or during the removal of the first backbone feature 204, the first spacer feature 206 can be thinned to form a thinned first spacer feature 206', as shown in Figure 2A . Depending on the spacing and size required for the BB2 features (208, described below), this thinning can be performed (as shown) before or after the removal of BB1 (feature 204). In operation (d), the first spacer feature 206 or the thinned first spacer feature 206' is used to pattern a material layer such as an insulating layer or a dielectric hard mask layer to form a second backbone (BB2) feature 208. Then a second spacer (SP2) feature 210 adjacent to the sidewalls of the second backbone feature 208 is formed. In operation (e), the second backbone feature 208 is removed to leave only the second spacer feature 210. Then the remaining second spacer feature 210 can be used to pattern a semiconductor layer to provide a plurality of semiconductor fins having a size that is one-quarter the pitch relative to the initial patterned photoresist features 202. As an example, referring to Figure 2B , the second spacer feature 210 is used as a mask for patterning (e.g., dry or plasma etch patterning) to form a plurality of semiconductor fins 250, such as silicon fins formed from a bulk silicon layer. In the example of Figure 2B , all of the plurality of semiconductor fins 250 have substantially the same pitch and spacing.

[0137] It should be recognized that the spacing between the initial patterned photoresist features can be modified to change the structural results of the pitch quartering process. In the example, Figure 3A is a schematic diagram of a fused fin pitch quartering method 300 for manufacturing semiconductor fins according to an embodiment of the present disclosure. Figure 3B shows a cross-sectional view of semiconductor fins manufactured using the fused fin pitch quartering method according to an embodiment of the present disclosure.

[0138] Referring to Figure 3A, in operation (a), the photoresist layer (PR) is patterned to form photoresist features 302. Standard lithography processing techniques such as 193 immersion lithography can be used, but with spacings (e.g., spacings known as sub-design rule pitches) that may ultimately conflict with the design rules required to produce uniformly spaced multiple patterns, to pattern the photoresist features 302. In operation (b), the photoresist features 302 are used to pattern a material layer such as an insulating layer or a dielectric hard mask layer to form first backbone (BB1) features 304. Then first spacer (SP1) features 306 are formed adjacent to the sidewalls of the first backbone features 304. However, in contrast to the scheme shown in Figure 2A , due to the closer photoresist features 302, some of the adjacent first spacer features 306 are fused spacer features. In operation (c), the first backbone features 304 are removed to leave only the first spacer features 306. Before or after removing the first backbone features 304, some of the first spacer features 306 can be thinned to form thinned first spacer features 306’, as shown in Figure 3A . In operation (d), the first spacer features 306 and the thinned first spacer features 306’ are used to pattern a material layer such as an insulating layer or a dielectric hard mask layer to form second backbone (BB2) features 308. Then second spacer (SP2) features 310 are formed adjacent to the sidewalls of the second backbone features 308. However, at positions where the BB2 features 308 are fused features, such as at the center BB2 feature 308 in Figure 3A , no second spacer is formed. In operation (e), the second backbone features 308 are removed to leave only the second spacer features 310. Then the remaining second spacer features 310 can be used to pattern a semiconductor layer to provide multiple semiconductor fins having a quarter-pitch size relative to the initial patterned photoresist features 302.

[0139] As an example, referring to Figure 3B , the second spacer features 310 are used as a mask for patterning (e.g., dry or plasma etch patterning) to form multiple semiconductor fins 350, such as silicon fins formed from a bulk silicon layer. However, in the example of Figure 3B , the multiple semiconductor fins 350 have varying pitches and spacings. Such a fused fin spacer patterning approach can be implemented to substantially eliminate the presence of fins at certain positions in the pattern of the multiple fins. Thus, fusing the first spacer features 306 in certain positions allows for the fabrication of six or four fins based on two first backbone features 304, which would typically produce eight fins based on two first backbone features 304, as combined with Figure 2A and Figure 2BAs described. In one example, in a slab, the fins have a pitch that is closer than what is typically allowed by creating fins at a uniform pitch and then cutting away the unwanted fins, although the latter approach can still be implemented in accordance with the embodiments described herein.

[0140] In an exemplary embodiment, referring to Figure 3B , an integrated circuit structure, a first plurality of semiconductor fins 352 have a longest dimension along a first direction (y, into the page). Adjacent individual semiconductor fins 353 of the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount (S1) in a second direction (x) orthogonal to the first direction. A second plurality of semiconductor fins 354 have a longest dimension along the first direction y. Adjacent individual semiconductor fins 355 of the second plurality of semiconductor fins 354 are spaced apart from each other by the first amount (S1) in the second direction. The closest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are spaced apart from each other by a second amount (S2) in the second direction x. In an embodiment, the second amount S2 is greater than the first amount S1 but less than twice the first amount S1. In another embodiment, the second amount S2 exceeds twice the first amount S1.

[0141] In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are continuous with the underlying single-crystalline silicon substrate. In one embodiment, the individual fins of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 have sidewalls that taper outwardly from the top to the bottom of the individual fins of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 in the second direction x. In one embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0142] In another exemplary embodiment, referring to Figure 3A and Figure 3B, A method of manufacturing an integrated circuit structure includes forming a first primary backbone structure 304 (left BB1) and a second primary backbone structure 304 (right BB1). Forming a primary spacer structure 306 adjacent to the sidewalls of the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). Fusing the primary spacer structure 306 between the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). Removing the first primary backbone structure (left BB1) and the second primary backbone structure (right BB1), and providing first, second, third, and fourth secondary backbone structures 308. Fusing the second and third secondary backbone structures (e.g., the middle pair of the secondary backbone structures 308). Forming a secondary spacer structure 310 adjacent to the sidewalls of the first, second, third, and fourth secondary backbone structures 308. Then removing the first, second, third, and fourth secondary backbone structures 308. Then patterning a semiconductor material using the secondary spacer structure 310 to form semiconductor fins 350 in the semiconductor material.

[0143] In one embodiment, the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) are patterned using a sub-design rule spacing between them. In one embodiment, the semiconductor material includes silicon. In one embodiment, the individual semiconductor fins in the semiconductor fins 350 have sidewalls that taper outwardly from the top to the bottom of the individual semiconductor fins in the second direction x. In one embodiment, the semiconductor fins 350 are continuous with the underlying single-crystalline silicon substrate. In one embodiment, patterning the semiconductor material using the secondary spacer structure 310 includes forming a first plurality of semiconductor fins 352 having a longest dimension along a first direction y, wherein adjacent individual semiconductor fins in the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount S1 in a second direction x orthogonal to the first direction y. Forming a second plurality of semiconductor fins 354 having a longest dimension along the first direction y, wherein adjacent individual semiconductor fins in the second plurality of semiconductor fins 354 are spaced apart from each other by the first amount S1 in the second direction x. The nearest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are spaced apart from each other by a second amount S2 in the second direction x. In an embodiment, the second amount S2 is greater than the first amount S1. In one such embodiment, the second amount S2 is less than twice the first amount S1. In another such embodiment, the second amount S2 is greater than twice the first amount S1 but less than three times the first amount S1. In an embodiment, as Figure 3BAs shown, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0144] In another aspect, it should be recognized that a fin trimming process, where fin removal is performed as an alternative to the fin fusion approach, can trim (remove) fins during hard mask patterning or by physically removing fins. As an example of the latter approach, Figures 4A - 4C FIG. shows a cross-sectional view representing various operations in a method of fabricating a plurality of semiconductor fins according to an embodiment of the present disclosure.

[0145] Referring to Figure 4A , a patterned hard mask layer 402 is formed over a semiconductor layer 404 such as a bulk single-crystalline silicon layer. Referring to Figure 4B , fins 406 are then formed in the semiconductor layer 404 by, for example, a dry or plasma etching process. Referring to Figure 4C , for example, selected fins 406 are removed using a masking and etching process. In the illustrated example, one of the fins 406 is removed and a residual fin stub 408 may be left. In such a "fin trimming last" approach, the hard mask 402 is patterned as a whole to provide a grid structure without removing or modifying individual features. The total number of fins is not modified until after the fins are fabricated.

[0146] In another aspect, a multi-layer trench isolation region can be implemented between semiconductor fins, which can be referred to as a shallow trench isolation (STI) structure. In an embodiment, a multi-layer STI structure is formed between silicon fins formed in a bulk silicon substrate to define sub-fin regions of the silicon fins.

[0147] It may be desirable to use bulk silicon for fin-based or tri-gate transistors. However, a concern is that the region (sub-fin) below the active silicon fin portion of the device (e.g., the gate control region, or HSi) is eliminated or not under gate control. As such, if the source or drain region is at or below the HSi point, there may be a leakage path through the sub-fin region. It is possible that the leakage path in the sub-fin region should be controlled for the device to operate properly.

[0148] One way to address the above issues involves using a well injection operation, where the sub-fin region is heavily doped (e.g., much greater than 2E18 / cm 3 ), which cuts off sub-fin leakage but also results in significant doping in the fins. Adding halo implants further increases fin doping such that the ends of the line fins are doped at a high level (e.g., greater than about 1E18 / cm 3 ).

[0149] Another approach involves doping provided by sub - fin doping without having to deliver the same level of doping to the HSi portion of the fin. The process can involve selectively doping the sub - fin region of a triple - gate or FinFET transistor fabricated on a bulk silicon wafer, for example, by out - diffusion of a triple - gate doped glass sub - fin. For example, selectively doping the sub - fin region of a triple - gate or FinFET transistor can mitigate sub - fin leakage while keeping the fin doping very low. Incorporating solid - state doping sources (e.g., p - type and n - type doped oxides, nitrides, or carbides) into the transistor process flow (after recessing from the fin sidewalls) delivers well doping to the sub - fins while keeping the fin body relatively undoped.

[0150] Thus, the process scheme can include using a solid - state source doping layer (e.g., boron - doped oxide) deposited on the fin after fin etching. Later, after trench filling and polishing, the doping layer is recessed with the trench - filling material to define the fin height (HSi) for the device. This operation removes the doping layer from the fin sidewalls above the HSi. Thus, the doping layer exists only along the fin sidewalls in the sub - fin region, ensuring precise control of doping placement. After drive - in annealing, the high doping is confined to the sub - fin region, rapidly transitioning to low doping in the adjacent region of the fin above the HSi (thus forming the channel region of the transistor). Typically, borosilicate glass (BSG) is implemented for NMOS fin doping, while phosphosilicate (PSG) or arsenosilicate glass (AsSG) layers are implemented for PMOS fin doping. In one example, such a p - type solid - state dopant source layer is a BSG layer with a boron concentration in the range of approximately 0.1 - 10 wt%. In another example, such an n - type solid - state dopant source layer is a PSG layer or an AsSG layer with a phosphorus or arsenic concentration, respectively, in the range of approximately 0.1 - 10 wt%. A silicon nitride capping layer can be included on the doping layer, and then a silicon dioxide or silicon oxide fill material can be included on the silicon nitride capping layer.

[0151] According to another embodiment of the present disclosure, for relatively thin fins (e.g., fins with a width less than approximately 20 nanometers), the sub - fin leakage is sufficiently low, where an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide fill material is included on the silicon nitride capping layer. It should be recognized that doping of the sub - fin region, such as halo doping, can also be implemented using such a structure.

[0152] Figure 5A A cross - sectional view of a pair of semiconductor fins separated by a three - layer trench isolation structure is shown in accordance with an embodiment of the present disclosure.

[0153] Reference Figure 5A , the integrated circuit structure includes fins 502, such as silicon fins. The fin 502 has a lower fin portion (sub-fin) 502A and an upper fin portion 502B (H Si ). The first insulating layer 504 is directly on the sidewalls of the lower fin portion 502A of the fin 502. The second insulating layer 506 is directly on the first insulating layer 504, and the first insulating layer 504 is directly on the sidewalls of the lower fin portion 502A of the fin 502. The dielectric fill material 508 is directly adjacent to the second insulating layer 506 directly on the first insulating layer 504 in the lateral direction, and the first insulating layer 504 is directly on the sidewalls of the lower fin portion 502A of the fin 502.

[0154] In an embodiment, the first insulating layer 504 is an undoped insulating layer including silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, the first insulating layer 504 includes silicon and oxygen and has no atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter. In an embodiment, the first insulating layer 504 has a thickness in the range of 0.5 - 2 nanometers.

[0155] In an embodiment, the second insulating layer 506 includes silicon and nitrogen, such as stoichiometric Si 3 N 4 silicon nitride insulating layer, silicon-rich silicon nitride insulating layer, or silicon-poor silicon nitride insulating layer. In an embodiment, the second insulating layer 506 has a thickness in the range of 2 - 5 nanometers.

[0156] In an embodiment, the dielectric fill material 508 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, the gate electrode is finally formed on and laterally adjacent to the top of the sidewalls of the upper fin portion 502B of the fin 502.

[0157] It should be recognized that during processing, the upper fin portion of the semiconductor fin may be etched or consumed. Also, the trench isolation structure between the fins may be etched to have a non-planar topography, or may be formed with a non-planar topography during fabrication. As an example, Figure 5B shows a cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure according to another embodiment of the present disclosure.

[0158] Reference Figure 5B, the integrated circuit structure includes a first fin 552, such as a silicon fin. The first fin 552 has a lower fin portion 552A and an upper fin portion 552B, and a shoulder feature 554 at a region between the lower fin portion 552A and the upper fin portion 552B. A second fin 562, such as a second silicon fin, has a lower fin portion 562A and an upper fin portion 562B, and a shoulder feature 564 at a region between the lower fin portion 562A and the upper fin portion 562B. A first insulating layer 574 is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562. The first insulating layer 574 has a first end portion 574A that is substantially coplanar with the shoulder feature 554 of the first fin 552, and the first insulating layer 574 also has a second end portion 574B that is substantially coplanar with the shoulder feature 564 of the second fin 562. A second insulating layer 576 is directly on the first insulating layer 574, and the first insulating layer 574 is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562.

[0159] A dielectric fill material 578 is laterally adjacent to the second insulating layer 576 that is directly on the first insulating layer 574, and the first insulating layer 574 is directly on the sidewalls of the lower fin portion 552A of the first fin 552 and directly on the sidewalls of the lower fin portion 562A of the second fin 562. In an embodiment, the dielectric fill material 578 has an upper surface 578A, wherein a portion of the upper surface 578A of the dielectric fill material 578 is below at least one of the shoulder features 554 of the first fin 552 and below at least one of the shoulder features 564 of the second fin 562, as Figure 5B shown.

[0160] In an embodiment, the first insulating layer 574 is an undoped insulating layer including silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In an embodiment, the first insulating layer 574 includes silicon and oxygen and has no other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter. In an embodiment, the first insulating layer 574 has a thickness in the range of 0.5 - 2 nanometers.

[0161] In an embodiment, the second insulating layer 576 includes silicon and nitrogen, such as a stoichiometric Si 3 N 4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In an embodiment, the second insulating layer 576 has a thickness in the range of 2 - 5 nanometers.

[0162] In an embodiment, the dielectric fill material 578 includes silicon and oxygen, such as a silicon oxide or silica insulating layer. In an embodiment, the gate electrode is finally formed over the top of and laterally adjacent to the sidewall of the upper fin portion 552B of the first fin 552, and over the top of and laterally adjacent to the sidewall of the upper fin portion 562B of the second fin 562. The gate electrode is also over the dielectric fill material 578 between the first fin 552 and the second fin 562.

[0163] Figures 6A - 6D A cross-sectional view showing various operations in manufacturing a three-layer trench isolation structure according to an embodiment of the present disclosure.

[0164] Reference Figure 6A , a method of manufacturing an integrated circuit structure includes forming fins 602, such as silicon fins. A first insulating layer 604 is directly formed on the fins 602 and conformal with the fins 602, as Figure 6B shown. In an embodiment, the first insulating layer 604 includes silicon and oxygen and does not have other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter.

[0165] Reference Figure 6C , a second insulating layer 606 is directly formed on the first insulating layer 604 and conformal with the first insulating layer 604. In an embodiment, the second insulating layer 606 includes silicon and nitrogen. A dielectric fill material 608 is directly formed on the second insulating layer 606, as Figure 6D shown.

[0166] In an embodiment, the method further involves recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 to provide fins 602 having exposed upper fin portions 602A (e.g., the upper fin portions 502B, 552B, or 562B of FIGS. 5A and Figure 5B ). The resulting structure may be as described in connection with Figure 5A or Figure 5B . In one embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a wet etching process. In another embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a plasma etching or dry etching process.

[0167] In an embodiment, a first insulating layer 604 is formed using a chemical vapor deposition process. In an embodiment, the term chemical vapor deposition process forms a second insulating layer 606. In an embodiment, a dielectric fill material 608 is formed using a spin coating process. In one such embodiment, the dielectric fill material 608 is a spin-on material and is exposed to a vapor treatment, for example, before or after a recess etching process, to provide a cured material including silicon and oxygen. In an embodiment, a gate electrode is finally formed over the top of the sidewall of the upper fin portion of the fin 602 and is laterally adjacent to the sidewall of the upper fin portion of the fin 602.

[0168] In another aspect, the gate sidewall spacer material may be retained over a particular trench isolation region as protection against corrosion of the trench isolation region during subsequent processing operations. For example, Figure 7A - FIG. 7E shows an angled three-dimensional cross-sectional view of various operations in a method of manufacturing an integrated circuit structure in accordance with an embodiment of the present disclosure.

[0169] Referring Figure 7A , a method of manufacturing an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is formed to be directly adjacent to the sidewall of the lower fin portion 702A of the fin 702. A gate structure 706 is formed over the upper fin portion 702B and over the insulating structure 704. In an embodiment, the gate structure is a dummy or placeholder gate structure including a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C. A dielectric material 708 is formed to be conformal with the upper fin portion 702B of the fin 702, conformal with the gate structure 706, and conformal with the insulating structure 704.

[0170] Referring Figure 7B , a hard mask material 710 is formed over the dielectric material 708. In an embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin coating process.

[0171] Referring Figure 7C , the hard mask material 710 is recessed to form a recessed hard mask material 712 and to expose a portion of the dielectric material 708 that is conformal with the upper fin portion 702B of the fin 702 and conformal with the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708 that is conformal with the insulating structure 704. In an embodiment, the hard mask material 710 is recessed using a wet etching process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0172] Referring Figure 7D, the dielectric material 708 is anisotropically etched to form a patterned dielectric material 714 along the sidewalls of the gate structure 706 (as dielectric spacers 714A), along portions of the sidewalls of the upper fin portions 702B of the fins 702, and over the insulating structure 704.

[0173] Reference Figure 7E , from Figure 7D , the recessed hard mask material 712 is removed from the structure. In an embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and a gate electrode stack. In an embodiment, further processing includes forming embedded source or drain structures on opposite sides of the gate structure 706, as described in more detail below.

[0174] Again reference Figure 7E , in an embodiment, the integrated circuit structure 700 includes a first fin (left 702), such as a first silicon fin, the first fin having a lower fin portion 702A and an upper fin portion 702B. The integrated circuit structure also includes a second fin (right 702), such as a second silicon fin, the second fin having a lower fin portion 702A and an upper fin portion 702B. The insulating structure 704 is directly adjacent to the sidewalls of the lower fin portions 702A of the first fin and is directly adjacent to the sidewalls of the lower fin portions 702A of the second fin. The gate electrode 706 is over the upper fin portion 702B of the first fin (left 702), over the upper fin portion 702B of the second fin (right 702), and over a first portion 704A of the insulating structure 704. A first dielectric spacer 714A is along the sidewall of the upper fin portion 702B of the first fin (left 702), and a second dielectric spacer 702C is along the sidewall of the upper fin portion 702B of the second fin (right 702). The second dielectric spacer 714C is continuous with the first dielectric spacer 714B over a second portion 704B of the insulating structure 704 that is between the first fin (left 702) and the second fin (right 702).

[0175] In an embodiment, the first and second dielectric spacers 714B and 714C include silicon and nitrogen, such as stoichiometric Si 3 N 4 silicon nitride material, silicon-rich silicon nitride material, or silicon-poor silicon nitride material.

[0176] In an embodiment, the integrated circuit structure 700 further includes an embedded source or drain structure on opposite sides of the gate electrode 706, the embedded source or drain structure having a bottom surface below the top surfaces of first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, and the source or drain structure having a top surface above the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702, as described below in connection with Figure 9B described. In an embodiment, the insulating structure 704 includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric fill material laterally directly on the second insulating layer, also as described below in connection with Figure 9B described.

[0177] Figures 8A - 8F A slightly projected cross-sectional view taken along the Figure 7E a-a' axis is shown of various operations in a method for fabricating an integrated circuit structure according to an embodiment of the present disclosure.

[0178] Referring to Figure 8A , a method of fabricating an integrated circuit structure includes forming fins 702, such as silicon fins. The fins 702 have a lower fin portion ( Figure 8A not visible in Figures 8A - 8F ) and an upper fin portion 702B. An insulating structure 704 is formed to be directly adjacent to the sidewalls of the lower fin portion 702A of the fins 702. A pair of gate structures 706 are formed over the upper fin portion 702B and over the insulating structure 704. It should be appreciated that the perspective view shown in

[0179] is slightly projected to show the gate structures 706 and portions of the insulating structure in front of (off the page) the upper fin portion 702B, where the upper fin portion slightly enters the page. In an embodiment, the gate structure 706 is a dummy or placeholder gate structure including a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

[0179] Referring to Figure 8B , which corresponds to the process operation described in connection with Figure 7A , a dielectric material 708 is formed to be conformal with the upper fin portion 702B of the fins 702, conformal with the gate structures 706, and conformal with the exposed portions of the insulating structure 704.

[0180] Referring to Figure 8C , which corresponds to the process operation described in connection with Figure 7B , a hard mask material 710 is formed over the dielectric material 708. In an embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-on process.

[0181] Reference Figure 8D , which corresponds to the process operation in conjunction with Figure 7C described above, to recess the hard mask material 710 to form a recessed hard mask material 712 and expose a portion of the dielectric material 708 that is conformal with the upper fin portion 702B of the fin 702 and conformal with the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708 that is conformal with the insulating structure 704. In an embodiment, the hard mask material 710 is recessed using a wet etching process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0182] Reference Figure 8E , which corresponds to the process operation in conjunction with Figure 7D described above, anisotropically etch the dielectric material 708 to form a patterned dielectric material 714 along the sidewalls of the gate structure 706 (as portion 714A), along a portion of the sidewalls of the upper fin portion 702B of the fin 702, and over the insulating structure 704.

[0183] Reference Figure 8F , which corresponds to the process operation in conjunction with Figure 7E described, remove the recessed hard mask material 712 from the Figure 8E structure. In an embodiment, the gate structure 706 is a dummy gate structure, and the process includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In an embodiment, further processing includes forming an embedded source or drain structure on opposite sides of the gate structure 706, as described in more detail below.

[0184] Referring again to Figure 8F , in an embodiment, the integrated circuit structure 700 includes fins 702, such as silicon fins, the fins 702 having a lower fin portion ( Figure 8F(not visible in the figure) and an upper fin portion 702B. The insulating structure 704 is directly adjacent to the sidewalls of the lower fin portion of the fin 702. The first gate electrode (left 706) is above the upper fin portion 702B and above the first portion 704A of the insulating structure 704. The second gate electrode (right 706) is above the upper fin portion 702B and above the second portion 704A' of the insulating structure 704. The first dielectric spacer (right 714A of the left 706) is along the sidewall of the first gate electrode (left 706), and the second dielectric spacer (left 714A of the right 706) is along the sidewall of the second gate electrode (right 706). The second dielectric spacer is continuous with the first dielectric spacer above the third portion 704A" of the insulating structure 704 between the first gate electrode (left 706) and the second gate electrode (right 706).

[0185] Figure 9A A slightly projected cross-sectional view taken along the Figure 7E a-a' axis of an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region according to an embodiment of the present disclosure is shown. Figure 9B A cross-sectional view taken along the Figure 7E b-b' axis of an integrated circuit structure including an epitaxial source or drain region and a multi-layer trench isolation structure according to an embodiment of the present disclosure is shown.

[0186] Referring to Figure 9A and Figure 9B , in an embodiment, the integrated circuit structure includes embedded source or drain structures 910 on opposite sides of the gate electrode 706. The embedded source or drain structure 910 has a bottom surface 910A below the top surface 990 of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portion 702B of the first and second fins 702. The embedded source or drain structure 910 has a top surface 910B above the top surface of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portion 702B of the first and second fins 702.

[0187] In an embodiment, the gate stack 706 is a permanent gate stack 920. In one such embodiment, the permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924 such as a work function gate layer, and a gate fill material 926, as Figure 9A shown. In an embodiment where the permanent gate structure 920 is above the insulating structure 704, the permanent gate structure 920 is formed on a residual polysilicon portion 930, which may be a residue of a replacement gate process involving a sacrificial polysilicon gate electrode.

[0188] In an embodiment, the insulating structure 704 includes a first insulating layer 902, a second insulating layer 904 directly on the first insulating layer 902, and a dielectric fill material 906 directly on the second insulating layer 904 in a lateral direction. In one embodiment, the first insulating layer 902 is an undoped insulating layer including silicon and oxygen. In one embodiment, the second insulating layer 904 includes silicon and nitrogen. In one embodiment, the dielectric fill material 906 includes silicon and oxygen.

[0189] In another aspect, an epitaxial embedded source or drain region is implemented as a source or drain structure for a semiconductor fin. As an example, Figure 10 A cross-sectional view of an integrated circuit structure taken at a source or drain location in accordance with an embodiment of the present disclosure is shown.

[0190] Referring Figure 10 , the integrated circuit structure 1000 includes P-type devices, such as P-type metal oxide semiconductor (PMOS) devices. The integrated circuit structure 1000 also includes N-type devices, such as N-type metal oxide semiconductor (NMOS) devices.

[0191] Figure 10 The PMOS devices of include a first plurality of semiconductor fins 1002, such as silicon fins formed from a bulk silicon substrate 1001. At a source or drain location, an upper portion of the fin 1002 has been removed and the same or a different semiconductor material has been grown to form a source or drain structure 1004. It should be appreciated that at a cross-sectional view taken on either side of the gate electrode, the source or drain structure 1004 will look the same, e.g., they will look substantially the same on the source side as on the drain side. In an embodiment, as described, the source or drain structure 1004 has a portion below and a portion above the upper surface of the insulating structure 1006. In an embodiment, as shown, the source or drain structure 1004 has a strong facet. In an embodiment, a conductive contact 1008 is formed over the source or drain structure 1004. However, in one such embodiment, the strong facet and the relatively wide growth of the source or drain structure 1004 at least somewhat inhibit good coverage of the conductive contact 1008.

[0192] Figure 10The NMOS device includes a second plurality of semiconductor fins 1052, such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain location, the upper portion of the fin 1052 has been removed and the same or a different semiconductor material has been grown to form the source or drain structure 1054. It should be appreciated that at a cross-sectional view taken on either side of the gate electrode, the source or drain structure 1054 will look the same, e.g., they will look substantially the same on the source side as on the drain side. In an embodiment, as described above, the source or drain structure 1054 has a portion below and a portion above the upper surface of the insulating structure 1006. In an embodiment, as shown, the source or drain structure 1054 has a weaker facet relative to the source or drain structure 1004. In an embodiment, the conductive contact 1058 is formed over the source or drain structure 1054. In one such embodiment, the weaker facet and the resulting narrower growth of the source or drain structure 1054 (compared to the source or drain structure 1004) enhance the good coverage of the conductive contact 1058.

[0193] The shape of the source or drain structure of the PMOS device can be changed to improve the contact area with the overlying contact. For example, Figure 11 FIG. shows a cross-sectional view of another integrated circuit structure taken at the source or drain location in accordance with an embodiment of the present disclosure.

[0194] Referring to Figure 11 , the integrated circuit structure 1100 includes a P-type semiconductor (e.g., PMOS) device. The PMOS device includes a first fin 1102, such as a silicon fin. The first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not shown, the first epitaxial source or drain structure 1104 is on a first side of a first gate electrode (which may be formed over an upper fin portion of a channel portion such as fin 1102), and a second epitaxial source or drain structure is embedded in the first fin 1102 at a second side of such first gate electrode opposite the first side. In an embodiment, the first epitaxial source or drain structure 1104 and the second epitaxial source or drain structure include silicon and germanium and have a profile 1105. In one embodiment, the profile is a matchstick profile as shown in FIG. 11. The first conductive electrode 1108 is over the first epitaxial source or drain structure 1104.

[0195] Referring again to Figure 11, in an embodiment, the integrated circuit structure 1100 further includes an N-type semiconductor (e.g., NMOS) device. The NMOS device includes a second fin 1152 such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. In one embodiment, although not shown, the third epitaxial source or drain structure 1154 is on a first side of the second gate electrode (which may be formed over an upper fin portion of a channel portion such as fin 1152), and a fourth epitaxial source or drain structure is embedded in the second fin 1152 at a second side of such second gate electrode opposite the first side. In an embodiment, the third epitaxial source or drain structure 1154 and the fourth epitaxial source or drain structure include silicon and have a profile generally the same as the profile 1105 of the first and second epitaxial source or drain structures 1004. A second conductive electrode 1158 is over the third epitaxial source or drain structure 1154.

[0196] In an embodiment, the first epitaxial source or drain structure 1104 has a weaker faceting. In an embodiment, the first epitaxial source or drain structure 1104 has a height of approximately 50 nanometers and has a width in the range of 30 - 35 nanometers. In one such embodiment, the third epitaxial source or drain structure 1154 has a height of approximately 50 nanometers and has a width in the range of 30 - 35 nanometers.

[0197] In an embodiment, the first epitaxial source or drain structure 1104 varies in germanium concentration from approximately 20% at the bottom 1104A of the first epitaxial source or drain structure 1104 to approximately 45% at the top 1104B of the first epitaxial source or drain structure 1104. In an embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In one such embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus atoms or arsenic atoms.

[0198] Figures 12A - 12D A cross-sectional view is shown in accordance with an embodiment of the present disclosure taken at a source or drain location and depicting various operations during the fabrication of an integrated circuit structure.

[0199] Reference Figure 12A , a method of fabricating an integrated circuit structure includes forming fins, such as silicon fins formed from a silicon substrate 1201. The fin 1202 has a lower fin portion 1202A and an upper fin portion 1202B. In an embodiment, although not shown, at a location into the page, a gate electrode is formed over a portion of the upper fin portion 1202B of the fin 1202. Such a gate electrode has a first side opposite a second side and defines source or drain locations on the first and second sides. For example, for illustrative purposes, Figures 12A - 12DThe cross-sectional position of the view is taken at one of the source or drain positions at one of the sides of the gate electrode.

[0200] Reference Figure 12B , the source or drain position of the fin 1202 is recessed to form a recessed fin portion 1206. The recessed source or drain position of the fin 1202 can be on one side of the gate electrode and on the second side of the gate electrode. Reference Figure 12A and Figure 12B both. In an embodiment, the dielectric spacer 1204 is formed along the sidewall of a portion of the fin 1202, for example, formed on one side of the gate structure. In one such embodiment, recessing the fin 1202 involves recessing the fin 1202 below the top surface 1204A of the dielectric spacer 1204.

[0201] Reference Figure 12C , an epitaxial source or drain structure 1208 is formed on the recessed fin 1206, for example, so that it can be formed on one side of the gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed fin 1206 that is on the second side of such a gate electrode. In an embodiment, the epitaxial source or drain structure 1208 includes silicon and germanium and has a matchstick profile, as Figure 12C shown. In an embodiment, the dielectric spacer 1204 is included and along the lower portion 1208A of the sidewall of the epitaxial source or drain structure 1208, as shown.

[0202] Reference Figure 12D , a conductive electrode 1210 is formed on the epitaxial source or drain structure 1208. In an embodiment, the conductive electrode 1210 includes a conduction barrier layer 1210A and a conductive fill material 1201B. In one embodiment, the conductive electrode 1210 follows the profile of the epitaxial source or drain structure 1208, as shown. In other embodiments, the upper portion of the epitaxial source or drain structure 1208 is etched during the manufacture of the conductive electrode 1210.

[0203] In another aspect, fin trim isolation (FTI) and single gate spacer for isolated fins are described. Non-planar transistors utilizing fins of semiconductor material protruding from a substrate surface employ gate electrodes that wrap two, three, or even all sides of the fin (i.e., dual-gate, triple-gate, nanowire transistors). Typically, source and drain regions are then formed in the fin on either side of the gate electrode, or formed as regrown portions of the fin. To isolate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor, a gap or space can be formed between two adjacent fins. Such isolation gaps typically require some masking etch. Once isolated, the gate stack is then typically patterned over the individual fins again using some masking etch (e.g., line etch or opening etch, depending on the particular implementation).

[0204] One potential problem with the fin isolation techniques described above is that the gate is not self-aligned to the ends of the fins, and the alignment of the gate stack pattern to the semiconductor fin pattern relies on the overlap of these two patterns. As such, lithographic overlap tolerances are added to the sizing of the semiconductor fins and the isolation gaps, where the fins require greater length and the isolation gaps are larger than the isolation gaps for a given level of transistor functionality. Thus, device architectures and manufacturing techniques that reduce such over-sizing provide highly advantageous improvements in transistor density.

[0205] Another potential problem with the fin isolation techniques described above is that the stress in the semiconductor fins required to improve carrier mobility can be lost from the channel region of the transistor, where too much unconstrained fin surface is left during manufacturing, allowing the fin strain to relax. Thus, device architectures and manufacturing techniques that maintain a higher level of the desired fin stress provide advantageous improvements in non-planar transistor performance.

[0206] According to embodiments of the present disclosure, through-gate fin isolation architectures and techniques are described herein. In the illustrated exemplary embodiments, non-planar transistors in a microelectronic device such as an integrated circuit (IC) are isolated from each other in a manner that is self-aligned to the gate electrodes of the transistors. Although embodiments of the present disclosure are applicable to almost any IC employing non-planar transistors, exemplary ICs include, but are not limited to: microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., wireless ICs including digital baseband and analog front-end modules), and power ICs.

[0207] In an embodiment, isolation regions electrically isolate two ends of adjacent semiconductor fins from each other, and only one patterning mask level is utilized to position the isolation regions relative to gate electrodes. In an embodiment, a plurality of sacrificial placeholder strips of a fixed pitch are formed using a single mask, with a first subset of the placeholder strips defining the location or dimensions of the isolation regions and a second subset of the placeholder strips defining the location or dimensions of the gate electrodes. In certain embodiments, the first subset of the placeholder strips is removed, and isolation cuts are fabricated into the semiconductor fins in the openings obtained by removing the first subset, while ultimately replacing the second subset of the placeholder strips with a non-sacrificial gate electrode stack. Since the subset of the placeholder used for gate electrode replacement is used to form the isolation regions, the method and resulting architecture are referred to herein as "through-gate" isolation. For example, one or more through-gate isolation embodiments described herein can achieve higher transistor density and a higher level of favorable transistor channel stress.

[0208] Greater transistor density can be achieved by utilizing isolation defined after placement or definition of the gate electrodes, because the fins can be perfectly sized and placed for isolation on the fly using the gate electrodes such that the gate electrodes and the isolation regions are integer multiples of the minimum feature pitch of a single masking level. In other embodiments where the semiconductor fins have a lattice mismatch with the substrate on which the fins are disposed, a greater degree of strain is maintained by defining isolation after placement or definition of the gate electrodes. For such embodiments, other features of the transistor (e.g., gate electrodes and additional source or drain material) formed prior to defining the ends of the fins contribute to mechanically maintaining the fin strain after isolation cuts are fabricated into the fins.

[0209] To provide further context, transistor scaling can benefit from more dense packing of the cells within a chip. Currently, most cells are separated from their adjacent cells by two or more dummy gates that have buried fins. The cells are isolated by etching the fins under these two or more dummy gates, and the dummy gates connect one cell to another. Scaling could be significantly beneficial if the number of dummy gates separating adjacent cells could be reduced from two or more to one. As described above, one scheme requires two or more dummy gates. The fins under two or more dummy gates are etched during fin patterning. A potential problem with this approach is that the dummy gates consume space on the chip that could be used for the cells. In an embodiment, the approach described herein enables separating adjacent cells using only a single dummy gate.

[0210] In an embodiment, the fin trimming isolation approach is implemented as a self-aligned patterning scheme. Here, the fins under a single gate are etched away. Thus, adjacent cells can be separated by a single dummy gate. Advantages of this approach can include saving space on the chip and allowing for greater computing power per given area. This approach can also allow for fin trimming to be performed at sub-fin pitch distances.

[0211] Figure 13A and Figure 13B FIG. shows a plan view representing various operations in a method of patterning fins having a multi-gate spacing for forming a local isolation structure according to an embodiment of the present disclosure.

[0212] Referring Figure 13A to, a plurality of fins 1302 are shown as having a length along a first direction 1304. A grid 1306 is shown along a second direction 1308 orthogonal to the first direction 1304, with a spacing 1307 between the grids, defining positions for ultimately forming a plurality of gate lines.

[0213] Referring Figure 13B to, a portion of the plurality of fins 1302 is cut (e.g., removed by an etching process) to leave fins 1310 having a notch 1312 therein. Thus, the isolation structure ultimately formed in the notch 1312 has a size that exceeds a single gate line, e.g., the size of three gate lines 1306. Thus, a gate structure is formed ultimately along the positions of the gate lines 1306 above the isolation structure formed at least partially in the notch 1312. Thus, the notch 1312 is a relatively wide fin notch.

[0214] Figures 14A - 14D FIG. shows a plan view representing various operations in a method of patterning fins having a single gate spacing for forming a local isolation structure according to another embodiment of the present disclosure.

[0215] Referring Figure 14A to, a method of fabricating an integrated circuit structure includes forming a plurality of fins 1402, with individual fins among the plurality of fins 1402 having a longest dimension along a first direction 1404. A plurality of gate structures 1406 are above the plurality of fins 1402, with individual gate structures among the gate structures 1406 having a longest dimension along a second direction 1408 orthogonal to the first direction 1404. In an embodiment, the gate structures 1406 are sacrificial or dummy gate lines made of, for example, polysilicon. In one embodiment, the plurality of fins 1402 are silicon fins and are continuous with a portion of a underlying silicon substrate.

[0216] Referring Figure 14B, a dielectric material structure 1410 is formed between adjacent gate structures among a plurality of gate structures 1406.

[0217] Reference Figure 14C , a portion 1412 of one of the plurality of gate structures 1406 is removed to expose a portion 1414 of each of the plurality of fins 1402. In an embodiment, removing the portion 1412 of one of the plurality of gate structures 1406 involves using a lithography window 1416 that is wider than the width 1418 of the portion 1412 of one of the plurality of gate structures 1406.

[0218] Reference Figure 14D , the exposed portion 1414 of each of the plurality of fins 1402 is removed to form a notch region 1420. In an embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed using a dry or plasma etching process. In an embodiment, removing the exposed portion 1414 of each of the plurality of fins 1402 involves etching to a depth less than the height of the plurality of fins 1402. In one such embodiment, the depth is greater than the depth of the source or drain region in the plurality of fins 1402. In an embodiment, the depth is deeper than the depth of the active portion of the plurality of fins 1402 to provide an isolation margin. In an embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without etching or substantially without etching the source or drain region (e.g., epitaxial source or drain region) of the plurality of fins 1402. In one such embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without laterally etching or substantially without laterally etching the source or drain region (e.g., epitaxial source or drain region) of the plurality of fins 1402.

[0219] In an embodiment, the notch region 1420 is ultimately filled, for example, with an insulating layer at the location of the removed portion 1414 of each of the plurality of fins 1402. Exemplary insulating layer or "multi-notch" or "plug" structures are described below. However, in other embodiments, the notch region 1420 is only partially filled with an insulating layer, and then a conductive structure is formed therein. The conductive structure can be used as a local interconnect. In an embodiment, before filling the notch region 1420 with an insulating layer or with an insulating layer that houses a local interconnect structure, a solid source dopant layer can inject or deliver dopant through the notch region 1420 into the local notch portions of one or more fins.

[0220] Figure 15 A cross-sectional view of an integrated circuit structure having fins with multi-gate spacings for local isolation according to an embodiment of the present disclosure is shown.

[0221] Reference Figure 15, the silicon fin 1502 has a first fin portion 1504 that is laterally adjacent to a second fin portion 1506. The first fin portion 1504 is separated from the second fin portion 1506 by a wide notch 1508, such as as described in connection with Figure 13A and Figure 13B The wide notch 1508 has a width X. A dielectric fill material 1510 is formed in the wide notch 1508 and electrically isolates the first fin portion 1504 from the second fin portion 1506. A plurality of gate lines 1512 are over the silicon fin 1502, where each of the gate lines may include a gate dielectric and a gate electrode stack 1514, a dielectric capping layer 1516, and sidewall spacers 1518. Two gate lines (the left two gate lines 1512) occupy the wide notch 1508, such that the first fin portion 1504 is effectively separated from the second fin portion 1506 by two dummy gates or passive gates.

[0222] In contrast, the fin portions may be separated by a single gate pitch. As an example, Figure 16A FIG. shows a cross-sectional view of an integrated circuit structure having fins with a single gate spacing for local isolation in accordance with another embodiment of the present disclosure.

[0223] Referring to Figure 16A , the silicon fin 1602 has a first fin portion 1604 that is laterally adjacent to a second fin portion 1606. The first fin portion 1604 is separated from the second fin portion 1606 by a narrow notch 1608, such as as described in connection with Figures 14A - 14D The narrow notch 1608 has a width Y, where Y is less than Figure 15 X. A dielectric fill material 1610 is formed in the narrow notch 1608 and electrically isolates the first fin portion 1604 from the second fin portion 1606. A plurality of gate lines 1612 are over the silicon fin 1602, where each of the gate lines may include a gate dielectric and a gate electrode stack 1614, a dielectric capping layer 1616, and sidewall spacers 1618. The dielectric fill material 1610 occupies the position previously occupied by a single gate line, such that the first fin portion 1604 is separated from the second fin portion 1606 by a single "plugged" gate line. In one embodiment, a residual spacer material 1620 remains on the sidewalls at the position of the removed portion of the gate line, as shown. It should be appreciated that other regions of the fin 1602 may be isolated from each other by two or more passive gate lines (region 1622 having three passive gate lines) fabricated by an earlier, wider fin notch process, as described below.

[0224] Referring again to Figure 16A, the integrated circuit structure 1600 includes fins 1602, such as silicon fins. The fins 1602 have the longest dimension along a first direction 1650. An isolation structure 1610 separates a first upper portion 1604 of the fin 1602 from a second upper portion 1606 of the fin 1602 along the first direction 1650. The isolation structure 1610 has a center 1611 along the first direction 1650.

[0225] A first gate structure 1612A is over the first upper portion 1604 of the fin 1602. The first gate structure 1612A has the longest dimension along a second direction 1652 (e.g., into the page) that is orthogonal to the first direction 1650. A center 1613A of the first gate structure 1612A is spaced apart from the center 1611 of the isolation structure 1610 by a spacing along the first direction 1650. A second gate structure 1612B is over the first upper portion 1604 of the fin 1602. The second gate structure 1612B has the longest dimension along the second direction 1652. A center 1613B of the second gate structure 1612B is spaced apart from the center 1613A of the first gate structure 1612A by a spacing along the first direction 1650. A third gate structure 1612C is over the second upper portion 1606 of the fin 1602. The third gate structure 1612C has the longest dimension along the second direction 1652. A center 1613C of the third gate structure 1612C is spaced apart from the center 1611 of the isolation structure 1610 by a spacing along the first direction 1650. In an embodiment, the isolation structure 1610 has a top that is substantially coplanar with the tops of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C, as shown.

[0226] In an embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C includes a gate electrode 1660 on and between sidewalls of a high-k gate dielectric layer 1662, as shown for an exemplary third gate structure 1612C. In one such embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C further includes an insulating cap 1616 on the gate electrode 1660 and on the sidewalls of the high-k gate dielectric layer 1662.

[0227] In an embodiment, the integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on a first upper portion 1604 of a fin 1602 between a first gate structure 1612A and an isolation structure 1610. A second epitaxial semiconductor region 1664B is on the first upper portion 1604 of the fin 1602 between the first gate structure 1612A and a second gate structure 1612B. A third epitaxial semiconductor region 1664C is on a second upper portion 1606 of the fin 1602 between a third gate structure 1612C and the isolation structure 1610. In one embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions include silicon and germanium. In another embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions include silicon.

[0228] In an embodiment, the isolation structure 1610 induces stress on a first upper portion 1604 of the fin 1602 and on a second upper portion 1606 of the fin 1602. In one embodiment, the stress is compressive stress. In one embodiment, the stress is tensile stress. In other embodiments, the isolation structure 1610 is a partially filled insulating layer in which a conductive structure is then formed. The conductive structure can be used as a local interconnect. In an embodiment, before forming the isolation structure 1610 using an insulating layer or an insulating layer that houses a local interconnect structure, dopants are implanted or delivered into local cut portions of one or more fins by a solid source dopant layer.

[0229] In another aspect, it is to be appreciated that instead of an active gate electrode at a local location of a fin cut or at a wider location of a fin cut, an isolation structure, such as the isolation structure 1610 described above, can be formed. Additionally, the depth of such a local or wider location of a fin cut can be formed to vary relative to each other within the fin. In a first example, Figure 16B A cross-sectional view is shown that illustrates a fin isolation structure that can be formed to replace the location of a gate electrode, according to an embodiment of the present disclosure.

[0230] Reference Figure 16B, a fin 1680, such as a silicon fin, is formed over a substrate 1682 and may be continuous with the substrate 1682. The fin 1680 has a fin end or a wide fin notch 1684, for example, the notch 1684 may be formed during fin patterning in the last fin trimming manner as described above. The fin 1680 also has a local notch 1686, where, for example, a portion of the fin 1680 is removed using a fin trimming isolation method in which dummy gates are replaced with dielectric plugs, as described above. An active gate electrode 1688 is formed over the fin and, for illustrative purposes, is shown slightly in front of the fin 1680, with the fin 1680 in the background, where the dashed lines represent the covered area in the front view. Dielectric plugs 1690 may be formed at the fin end or the wide fin notch 1684 to replace the use of an active gate at such a position. Additionally, or as an alternative, dielectric plugs 1692 may be formed at the local notch 1686 to replace the use of an active gate at such a position. It should be appreciated that an epitaxial source or drain region 1694 is also shown at the position of the fin 1680 between the active gate electrode 1688 and the plug 1690 or 1692. Additionally, in an embodiment, the surface roughness of the end of the fin at the local notch 1686 is rougher than the end of the fin at the wide notch position, as Figure 16B shown.

[0231] Figures 17A - 17C Shows various depth possibilities of fin notches fabricated using a fin trimming isolation method according to an embodiment of the present disclosure.

[0232] Refer to Figure 17A , a semiconductor fin 1700, such as a silicon fin, is formed over a lower substrate 1702 and may be continuous with the lower substrate 1702. The fin 1700 has a lower fin portion 1700A and an upper fin portion 1700B, as defined by the height of the insulating structure 1704 relative to the fin 1700. A local fin isolation notch 1706A separates the fin 1700 into a first fin portion 1710 and a second fin portion 1712. In Figure 17A the example, as shown along the a-a' axis, the depth of the local fin isolation notch 1706A is the entire depth of the fin 1700 to the substrate 1702.

[0233] Refer to Figure 17B , in a second example, as shown along the a-a' axis, the depth of the local fin isolation notch 1706B is deeper than the entire depth of the fin 1700 to the substrate 1702. That is, the notch 1706B extends into the lower substrate 1702.

[0234] Refer to Figure 17C, in the third example, as shown along the a-a' axis, the depth of the local fin isolation cut 1706C is less than the entire depth of the fin 1700 but deeper than the upper surface of the isolation structure 1704. Referring again to Figure 17C , in the fourth example, as shown along the a-a' axis, the depth of the local fin isolation cut 1706D is less than the entire depth of the fin 1700 and is at a level substantially coplanar with the upper surface of the isolation structure 1704.

[0235] Figure 18 A plan view showing possible options for comparing the depth of a local position of a fin cut within a display fin with the depth of a wider position and a corresponding cross-sectional view taken along the a-a' axis are shown.

[0236] Refer to Figure 18 , first and second semiconductor fins 1800 and 1802, such as silicon fins, have upper fin portions 1800B and 1802B that extend above the insulating structure 1804. Both fins 1800 and 1802 have fin ends or wide fin cuts 1806, for example, the cut 1806 can be formed during fin patterning in the last fin trimming manner described above. Both fins 1800 and 1802 also have local cuts 1808, where, for example, a portion of fin 1800 or 1802 is removed using a fin trimming isolation method in which dummy gates are replaced with dielectric plugs, as described above. In an embodiment, the surface roughness of the ends of fins 1800 and 1802 at the local cut 1808 is rougher than the ends of the fins at the position of 1806, as Figure 18 shown.

[0237] Refer to Figure 18 In the cross-sectional view, lower fin portions 1800A and 1802A can be seen below the height of the insulating structure 1804. Moreover, what is seen in the cross-sectional view is the remaining portion 1810 of the fin removed at the last fin trimming process before forming the insulating structure 1804, as described above. Although shown protruding above the substrate, the remaining portion 1810 can also be at the level of the substrate or enter the substrate, as shown by the additional exemplary wide cut depth 1820. It should be recognized that the wide cuts 1806 of fins 1800 and 1802 can also be at the level described for the cut depth 1820, showing an example thereof. The local cut 1808 can have an exemplary depth corresponding to that described for Figures 17A - 17C , as shown.

[0238] Referring jointly to Figure 16A , Figure 16B , Figures 17A - 17C and Figure 18, according to an embodiment of the present disclosure, an integrated circuit structure includes a fin, the fin includes silicon, the fin has a top and sidewalls, wherein the top has a longest dimension in a first direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin in the first direction. The first isolation structure has a width in the first direction. The first end of the first portion of the fin has a surface roughness. The gate structure includes a gate electrode that is above a region of the first portion of the fin and laterally adjacent to the sidewalls of the region. The gate structure has a width in the first direction, and the center of the gate structure is spaced apart from the center of the first isolation structure by a spacing in the first direction. A second isolation structure is above a second end of the first portion of the fin, the second end being opposite to the first end. The second isolation structure has a width in the first direction, and the second end of the first portion of the fin has a surface roughness that is less than the surface roughness of the first end of the first portion of the fin. The center of the second isolation structure is spaced apart from the center of the gate structure by a spacing in the first direction.

[0239] In one embodiment, the first end of the first portion of the fin has a fan-shaped morphology, as shown in FIG. 16B. In one embodiment, a first epitaxial semiconductor region is on the first portion of the fin between the gate structure and the first isolation structure. A second epitaxial semiconductor region is on the first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have a width in a second direction orthogonal to the first direction, and the width in the second direction is wider than the width of the first portion of the fin under the gate structure in the second direction. For example, as combined with Figure 11 and Figure 12D shown epitaxial features, which, for example, have a wider width than the fin portion where the epitaxial features are grown in the perspective views shown in Figure 11 and Figure 12D . In one embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the first portion of the fin and along the sidewalls of the gate electrode.

[0240] With common reference to Figure 16A 、 Figure 16B 、 Figures 17A - 17C and Figure 18, according to another embodiment of the present disclosure, an integrated circuit structure includes a fin, the fin includes silicon, the fin has a top and sidewalls, wherein the top has a longest dimension in a direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin in the direction. The first end of the first portion of the fin has a depth. A gate structure includes a gate electrode over the top of the region of the first portion of the fin and laterally adjacent to the sidewalls of the region. A second isolation structure is over a second end of the first portion of the fin, the second end being opposite to the first end. The second end of the first portion of the fin has a depth different from the depth of the first end of the first portion of the fin.

[0241] In one embodiment, the depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width in the direction, and the gate structure has a width in the direction. The second isolation structure has a width in the direction. In one embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by a pitch in the direction, and the center of the second isolation structure is spaced apart from the center of the gate structure by the pitch in the direction.

[0242] Common reference Figure 16A , Figure 16B , Figures 17A - 17C and Figure 18 , according to another embodiment of the present disclosure, an integrated circuit structure includes a first fin, the first fin includes silicon, the first fin has a top and sidewalls, wherein the top has a longest dimension in a direction, and a discontinuity separates a first end of a first portion of the first fin from a first end of a second portion of the fin in the direction. The first portion of the first fin has a second end opposite to the first end, and the first end of the first portion of the fin has a depth. The integrated circuit structure further includes a second fin, the second fin includes silicon, the second fin has a top and sidewalls, wherein the top has a longest dimension in the direction. The integrated circuit structure further includes a remaining or residual fin portion between the first fin and the second fin. The residual fin portion has a top and sidewalls, wherein the top has a longest dimension in the direction, and the top is non-coplanar with the depth of the first end of the first portion of the fin.

[0243] In one embodiment, the depth of the first end of the first portion of the fin is lower than the top of the remaining or residual fin portion. In one embodiment, the depth of the second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the first end of the first portion of the fin is higher than the top of the remaining or residual fin portion. In one embodiment, the depth of the second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin has a depth coplanar with the top of the residual fin portion. In one embodiment, the depth of the second end of the first portion of the fin has a depth lower than the top of the residual fin portion. In one embodiment, the depth of the second end of the first portion of the fin has a depth higher than the top of the residual fin portion.

[0244] In another aspect, the dielectric plugs formed in the position of the local fin cuts or wide fin cuts can be adjusted to provide specific stress to the fin or fin portion. In such an embodiment, the dielectric plugs can be referred to as fin end stress sources.

[0245] One or more embodiments relate to the fabrication of fin-based semiconductor devices. Performance improvements to such devices can be made by inducing channel stress from a multi-plug fill process. Embodiments can include inducing mechanical stress in a metal oxide semiconductor field effect transistor (MOSFET) channel using the material properties in the multi-plug fill process. As a result, the induced stress can enhance the mobility and drive current of the transistor. In addition, the plug fill methods described herein can allow for the elimination of any seam or void formation during deposition.

[0246] To provide context, the unique material properties of the plug fill that manipulates the adjacent fins can induce stress in the channel. According to one or more embodiments, by adjusting the composition, deposition, and post-treatment conditions of the plug fill material, the stress in the channel is modulated to benefit both NMOS and PMOS transistors. Additionally, such plugs can be deeper in the fin substrate compared to other common stress source techniques such as epitaxial source or drain. The property of the plug fill that achieves this effect also eliminates seams or voids during deposition and mitigates certain defect patterns during the process.

[0247] To provide more context, currently, there is no artificial stress engineering for gate (multi)-plugs. The stress enhancement from traditional stress sources such as epitaxial source or drain, dummy multi-gate removal, stress liner, etc. unfortunately tends to decrease as the device pitch shrinks. To address one or more of the above problems, according to one or more embodiments of the present disclosure, an additional stress source is incorporated into the transistor structure. Another possible benefit of such a process can be the elimination of seams or voids within the plug, which are common for other chemical vapor deposition methods.

[0248] Figure 19A and Figure 19B A cross-sectional view shows various operations in a method of selecting a fin end stress source location at an end of a fin having a wide notch as part of, for example, the fin trim final process as described above according to an embodiment of the present disclosure.

[0249] Reference Figure 19A , a fin 1900, such as a silicon fin, is formed over a substrate 1902 and can be continuous with the substrate 1902. The fin 1900 has a fin end or a wide fin notch 1904, for example, the notch 1904 can be formed during fin patterning in the fin trim final manner described above. Active gate electrode positions 1908 and dummy gate electrode positions 1908 are formed over the fin 1900 and are shown, for illustrative purposes, to be slightly in front of the fin 1900, and the fin 1900 is in the background, where the dashed lines represent the covered area in the front view. It should be appreciated that an epitaxial source or drain region 1910 is also shown at the position of the fin 1900 between the gate positions 1906 and 1908. Additionally, an interlayer dielectric material 1912 is included at the position of the fin 1900 between the gate positions 1906 and 1908.

[0250] Reference Figure 19B, the gate dummy structure or dummy gate location 1908 is removed to expose the fin ends and the wide fin cuts 1904. This removal creates an opening 1920 in which a dielectric plug, such as a fin end stress source dielectric plug, can ultimately be formed.

[0251] Figure 20A and Figure 20B FIG. shows a cross-sectional view of various operations in a method of selecting a fin end stress location at a fin end having a local cut as part of, for example, the fin trim isolation process as described above, in accordance with an embodiment of the present disclosure.

[0252] Reference Figure 20A , fins 2000, such as silicon fins, are formed over a substrate 2002 and may be continuous with the substrate 2002. The fins 2000 have local cuts 2004, where portions of the fins 2000 are removed, for example, using a fin trim isolation approach in which the dummy gate is removed and the fins are etched in local locations, as described above. Active gate electrode locations 2006 and dummy gate electrode locations 2008 are formed over the fins 2000 and are shown, for illustrative purposes, slightly in front of the fins 2000, and the fins 2000 are in the background, where the dashed lines represent the covered areas in a front view. It should be appreciated that epitaxial source or drain regions 2010 are also shown at the location of the fins 2000 between the gate locations 2006 and 2008. Additionally, an interlayer dielectric material 2012 is included at the location of the fins 2000 between the gate locations 2006 and 2008.

[0253] Reference Figure 20B , the gate dummy structure or dummy gate electrode location 2008 is removed to expose the fin ends having local cuts 2004. This removal creates an opening 2020 in which a dielectric plug, such as a fin end stress source dielectric plug, can ultimately be formed.

[0254] Figures 21A - 21M FIG. shows a cross-sectional view of various operations in a method of fabricating an integrated circuit structure having a differentiated fin end dielectric plug, in accordance with an embodiment of the present disclosure.

[0255] Reference Figure 21A, the starting structure 2100 includes an NMOS region and a PMOS region. The NMOS region of the starting structure 2100 includes a first fin 2102, such as a first silicon fin, which is formed above the substrate 2104 and may be continuous with the substrate 2104. The first fin 2102 has a fin end 2106, which may be formed by a local or wide fin cut. A first active gate electrode position 2108 and a first dummy gate electrode position 2110 are formed on the first fin 2102 and, for illustrative purposes, are shown slightly in front of the first fin 2102, with the first fin 2102 in the background, where the dashed line represents the covered area in the front view. An epitaxial N-type source or drain region 2112, such as an epitaxial silicon source or drain structure, is also shown at the position of the first fin 2102 between the gate positions 2108 and 2110. In addition, an interlayer dielectric material 2114 is included at the position of the first fin 2102 between the gate positions 2108 and 2110.

[0256] The PMOS region of the starting structure 2100 includes a second fin 2122, such as a second silicon fin, which is formed above the substrate 2104 and may be continuous with the substrate 2104. The second fin 2122 has a fin end 2126, which may be formed by a local or wide fin cut. A second active gate electrode position 2128 and a second dummy gate electrode position 2130 are formed on the second fin 2122 and, for illustrative purposes, are shown slightly in front of the second fin 2122, with the second fin 2122 in the background, where the dashed line represents the covered area in the front view. An epitaxial P-type source or drain region 2132, such as an epitaxial silicon germanium source or drain structure, is also shown at the position of the second fin 2122 between the gate positions 2128 and 2130. In addition, an interlayer dielectric material 2134 is included at the position of the second fin 2122 between the gate positions 2128 and 2130.

[0257] Reference Figure 21B , the first and second dummy gate electrodes at positions 2110 and 2130 are removed respectively. Upon removal, the fin ends 2106 of the first fin 2102 and the fin ends 2126 of the second fin 2122 are exposed. This removal also creates openings 2116 and 2136 respectively, in which dielectric plugs, such as fin end stress source dielectric plugs, can ultimately be formed.

[0258] Reference Figure 21C , a material liner 2140 is conformally formed with the Figure 21B structure. In an embodiment, the material liner includes silicon and nitrogen, such as a silicon nitride material liner.

[0259] ReferenceFigure 21D A protective capping layer 2142, such as a metal nitride layer, is formed on Figure 21C the structure of.

[0260] Refer to Figure 21E A hard mask material 2144, such as a carbon-based hard mask material, is formed on Figure 21D the structure of. A photolithography mask or mask stack 2146 is formed on the hard mask material 2144.

[0261] Refer to Figure 21F From Figure 21E the structure of, a portion of the hard mask material 2144 and a portion of the protective capping layer 2142 in the PMOS region are removed. The photolithography mask or mask stack 2146 is also removed.

[0262] Refer to Figure 21G A second material liner 2148 is conformally formed with Figure 21F the structure of. In an embodiment, the second material liner includes silicon and nitrogen, such as a second silicon nitride material liner. In an embodiment, the second material liner 2148 has a different stress state to adjust the stress in the exposed plugs.

[0263] Refer to Figure 21H A second hard mask material 2150, such as a second carbon-based hard mask material, is formed on Figure 21G the structure of and then recessed into the opening 2136 of the PMOS region of the structure.

[0264] Refer to Figure 21I From Figure 21H the structure of, the second material liner 2148 is etched away to remove the second material liner 2148 from the NMOS region and recess the second material liner 2148 in the PMOS region of the structure.

[0265] Refer to Figure 21J From Figure 21I the structure of, the hard mask material 2144, the protective capping layer 2142, and the second hard mask material 2150 are removed. The removal leaves two different fill structures for the opening 2116, respectively, compared to the opening 2136.

[0266] Refer to Figure 21K An insulating fill material 2152 is formed in and planarized in the openings 2116 and 2136 of Figure 21J the structure of. In an embodiment, the insulating fill material 2152 is a flowable oxide material, such as a flowable silicon oxide or silicon dioxide material.

[0267] Refer to Figure 21L The insulating fill material 2152 is recessed into Figure 21KWithin the openings 2116 and 2136 of the structure to form a recessed insulating fill material 2154. In an embodiment, a steam oxidation process is performed as part of the recess process, or a steam oxidation process is performed after the recess process to cure the recessed insulating fill material 2154. In one such embodiment, the recessed insulating fill material 2154 shrinks, thereby inducing tensile stress on the fins 2102 and 2122. However, there is less tensile stress inducing material in the PMOS region than in the NMOS region.

[0268] Reference Figure 21M , a third material layer 2156 is on Figure 21L the structure. In an embodiment, the third material layer 2156 includes silicon and nitrogen, such as a third silicon nitride material layer. In an embodiment, the third material layer 2156 prevents the recessed insulating fill material 2154 from being etched away during subsequent source or drain contact etching.

[0269] Figures 22A - 22D A cross-sectional view showing an exemplary structure of a PMOS fin end stress source dielectric plug according to an embodiment of the present disclosure.

[0270] Reference Figure 22A , the opening 2136 on the PMOS region of the structure 2100 includes a material layer 2140 along the sidewalls of the opening 2136. The second material layer 2148 is conformal with the lower portion of the material layer 2140 but is recessed relative to the upper portion of the material layer 2140. The recessed insulating fill material 2154 is within the second material layer 2148 and has an upper surface coplanar with the upper surface of the second material layer 2148. The third material layer 2156 is within the upper portion of the material layer 2140 and on the upper surface of the insulating fill material 2154 and on the upper surface of the second material layer 2148. The third material layer 2156 has a seam 2157, for example, as an artifact of the deposition process for forming the third material layer 2156.

[0271] Reference Figure 22B , the opening 2136 on the PMOS region of the structure 2100 includes a material layer 2140 along the sidewalls of the opening 2136. The second material layer 2148 is conformal with the lower portion of the material layer 2140 but is recessed relative to the upper portion of the material layer 2140. The recessed insulating fill material 2154 is within the second material layer 2148 and has an upper surface coplanar with the upper surface of the second material layer 2148. The third material layer 2156 is within the upper portion of the material layer 2140 and on the upper surface of the insulating fill material 2154 and on the upper surface of the second material layer 2148. The third material layer 2156 has no seam.

[0272] Reference Figure 22C , the opening 2136 in the PMOS region of the structure 2100 includes a material liner 2140 along the sidewalls of the opening 2136. The second material liner 2148 is conformal with the lower portion of the material liner 2140, but is recessed relative to the upper portion of the material liner 2140. The recessed insulating fill material 2154 is within and over the second material liner 2148 and has an upper surface above the upper surface of the second material liner 2148. The third material liner 2156 is within the upper portion of the material liner 2140 and on the upper surface of the insulating fill material 2154. The third material liner 2156 is shown without seams, but in other embodiments, the third material liner 2156 has seams.

[0273] Reference Figure 22D , the opening 2136 in the PMOS region of the structure 2100 includes a material liner 2140 along the sidewalls of the opening 2136. The second material liner 2148 is conformal with the lower portion of the material liner 2140, but is recessed relative to the upper portion of the material liner 2140. The recessed insulating fill material 2154 is within the second material liner 2148 and has an upper surface recessed below the upper surface of the second material liner 2148. The third material liner 2156 is within the upper portion of the material liner 2140 and on the upper surface of the insulating fill material 2154 and on the upper surface of the second material liner 2148. The third material liner 2156 is shown without seams, but in other embodiments, the third material liner 2156 has seams.

[0274] Common reference Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figures 21A - 21M and Figure 22A - Figure 22D, according to an embodiment of the present disclosure, an integrated circuit structure includes fins, such as silicon, the fins having a top and sidewalls. The top has a longest dimension in one direction. A first isolation structure is above a first end of the fin. A gate structure includes a gate electrode above the top of a region of the fin and laterally adjacent to the sidewalls of the region. The gate structure is spaced apart from the first isolation structure in this direction. A second isolation structure is above a second end of the fin, the second end being opposite to the first end. The second isolation structure is spaced apart from the gate structure in this direction. Both the first isolation structure and the second isolation structure include a first dielectric material (e.g., material liner 2140) that laterally surrounds a recessed second dielectric material (e.g., second material liner 2148) different from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material (e.g., recessed insulating fill material 2154) different from the first and second dielectric materials.

[0275] In one embodiment, both the first isolation structure and the second isolation structure further include a fourth dielectric material (e.g., third material liner 2156) laterally surrounded by an upper portion of the first dielectric material, the fourth dielectric material being on the upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is further on the upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a generally vertical center seam. In another such embodiment, the fourth dielectric material has no seam.

[0276] In one embodiment, the third dielectric material has an upper surface coplanar with the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface below the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface above the upper surface of the second dielectric material, and the third dielectric material is further above the upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In one such embodiment, the gate electrode is a P-type gate electrode.

[0277] In one embodiment, the first isolation structure has a width in this direction, the gate structure has a width in this direction, and the second isolation structure has a width in this direction. In one such embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by a spacing in this direction, and the center of the second isolation structure is spaced apart from the center of the gate structure by the spacing in this direction. In one embodiment, both the first and second isolation structures are in corresponding trenches in an interlayer dielectric layer.

[0278] In one such embodiment, a first source or drain region is between the gate structure and a first isolation structure. A second source or drain region is between the gate structure and a second isolation structure. In one such embodiment, the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium. In one such embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the fin and along sidewalls of the gate electrode.

[0279] In another aspect, the depth of an individual dielectric plug can vary within the semiconductor structure or within an architecture formed on a common substrate. As an example, Figure 23A A cross-sectional view of another semiconductor structure having fin-end stress-induced features in accordance with another embodiment of the present disclosure is shown. Referring to Figure 23A , including a shallow dielectric plug 2308A and a pair of deep dielectric plugs 2308B and 2308C. In one such embodiment, as shown, the shallow dielectric plug 2308C is at a depth approximately equal to the depth of the semiconductor fin 2302 within the substrate 2304, while the pair of deep dielectric plugs 2308B and 2308C are at a depth below the depth of the semiconductor fin 2302 within the substrate 2304.

[0280] Referring again to Figure 23A , such an arrangement can achieve stress amplification on a fin trim isolation (FTI) device in a trench etched deeper into the substrate 2304 to provide isolation between adjacent fins 2302. Such a manner can be implemented to increase the density of transistors on a chip. In an embodiment, the stress effect induced from plug filling on the transistor is amplified in an FTI transistor because stress transfer occurs in both the fin and the substrate or right under the transistor.

[0281] In another aspect, the width or amount of a tensile stress-induced oxide layer included in the dielectric plug can be changed within the semiconductor structure or within an architecture formed on a common substrate, e.g., depending on whether the device is a PMOS device or an NMOS device. As an example, Figure 23B A cross-sectional view of another semiconductor structure having fin-end stress-induced features in accordance with another embodiment of the present disclosure is shown. Referring to Figure 23B , in a particular embodiment, the NMOS device includes a relatively greater amount of tensile stress-induced oxide layers 2350 than the corresponding PMOS device.

[0282] Referring again to Figure 23B, in an embodiment, differential plug filling is implemented to induce appropriate stress in NMOS and PMOS. For example, the NMOS plugs 2308D and 2308E have a larger volume and a wider width of the tensile stress inducing oxide layer 2350 than the PMOS plugs 2308F and 2308G. The plug filling can be patterned to induce different stresses in NMOS and PMOS devices. For example, lithographic patterning can be used to open the PMOS device (e.g., widen the dielectric plug trench for the PMOS device), at which time different filling options can be executed to distinguish the plug filling in the NMOS device from the plug filling in the PMOS device. In an exemplary embodiment, reducing the volume of the flowable oxide in the plugs on the PMOS device can reduce the induced tensile stress. In one such embodiment, the compressive stress may mainly come from, for example, the compressive stress source and drain regions. In other embodiments, using different plug liners or different filling materials provides adjustable stress control.

[0283] As described above, it should be recognized that the multi-plug stress effect can be beneficial to NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress). According to an embodiment of the present disclosure, the semiconductor fin is a uniaxially stressed semiconductor fin. The uniaxially stressed semiconductor fin can be stressed uniaxially using tensile stress or using compressive stress. For example, according to one or more embodiments of the present disclosure, Figure 24A shows an inclined view of a fin having a tensile uniaxial stress, while Figure 24B shows an inclined view of a fin having a compressive uniaxial stress.

[0284] Refer to Figure 24A , the semiconductor fin 2400 has a discrete channel region (C) disposed therein. The source region (S) and the drain region (D) are disposed in the semiconductor fin 2400, on either side of the channel region (C). The discrete channel region of the semiconductor fin 2400 has a current flow direction from the source region (S) to the drain region (D) along the direction of the uniaxial tensile stress (arrows pointing away from each other and towards the ends 2402 and 2404).

[0285] Refer to Figure 24B, the semiconductor fin 2450 has a discrete channel region (C) disposed therein. Source regions (S) and drain regions (D) are disposed in the semiconductor fin 2450, on either side of the channel region (C). The discrete channel region of the semiconductor fin 2450 has a current flow direction from the source region (S) to the drain region (D) along the direction of uniaxial compressive stress (the arrows pointing towards each other and from ends 2452 and 2454). Accordingly, the embodiments described herein can be implemented to improve transistor mobility and drive current, thereby allowing circuits and chips to be executed faster.

[0286] In another aspect, there may be a relationship between the location of fabricating a gate line cut (multi-cut) and the location of fabricating a fin trim isolation (FTI) local fin cut. In an embodiment, the FTI local cut is fabricated only in the location of fabricating the multi-cut. However, in one such embodiment, the FTI cut is not necessarily fabricated at every location where the multi-cut is fabricated.

[0287] Figure 25A and Figure 25B A plan view shows various operations in a method of patterning a fin having a single gate pitch for forming a local isolation structure in a selected gate line cut location, according to an embodiment of the present disclosure.

[0288] Referring Figure 25A , a method of fabricating an integrated circuit structure includes forming a plurality of fins 2502, where an individual fin among the plurality of fins 2502 has a longest dimension along a first direction 2504. A plurality of gate structures 2506 are over the plurality of fins 2502, where an individual fin among the gate structures 2506 has a longest dimension along a second direction 2508 orthogonal to the first direction 2504. In an embodiment, the gate structures 2506 are sacrificial or dummy gate lines made of, for example, polysilicon. In one embodiment, the plurality of fins 2502 are silicon fins and are continuous with a portion of the underlying silicon substrate.

[0289] Referring again Figure 25A, a dielectric material structure 2510 is formed between adjacent gate structures among a plurality of gate structures 2506. Portions 2512 and 2513 of two gate structures among the plurality of gate structures 2506 are removed to expose portions of each of the plurality of fins 2502. In an embodiment, removing portions 2512 and 2513 of two gate structures among the gate structures 2506 involves using a lithography window wider than the width of each of portions 2512 and 2513 of the gate structures 2506. The exposed portions of each of the plurality of fins 2502 at location 2512 are removed to form a notch region 2520. In an embodiment, the exposed portions of each of the plurality of fins 2502 are removed using a dry or plasma etching process. However, the exposed portions of each of the plurality of fins 2502 at location 2513 are masked from being removed. In an embodiment, region 2512 / 2520 represents both multi-notch and FTI local fin notch. However, location 2513 represents only multi-notch.

[0290] Reference Figure 25B , an insulating structure 2530 such as a dielectric plug is used to fill location 2512 / 2520 of the multi-notch and FTI local fin notch and location 2513 of the multi-notch. Exemplary insulating structures or “multi-notch” or “plug” structures are described below.

[0291] Figures 26A - 26C A cross-sectional view shows various possibilities of dielectric plugs for respective regions of a structure for Figure 25B multi-notch and FTI local fin notch locations and only multi-notch locations according to an embodiment of the present disclosure.

[0292] Reference Figure 26A , along Figure 25B axis a-a’ of the structure, a cross-sectional view of portion 2600A of dielectric plug 2530 at location 2513 is shown. Portion 2600A of dielectric plug 2530 is shown on uncut fins 2502 and between dielectric material structures 2510.

[0293] Reference Figure 26B , along Figure 25B axis b-b’ of the structure, a cross-sectional view of portion 2600B of dielectric plug 2530 at location 2512 is shown. Portion 2600B of dielectric plug 2530 is shown on cut fin location 2520 and between dielectric material structures 2510.

[0294] Reference Figure 26C , along Figure 25BA cross-sectional view of a portion 2600C of the dielectric plug 2530 at position 2512 is shown along the c-c' axis of the structure. The portion 2600C of the dielectric plug 2530 is shown on the trench isolation structure 2602 between the fins 2502 and between the dielectric material structures 2510. In the embodiment described above by way of example, the trench isolation structure 2602 includes a first insulating layer 2602A, a second insulating layer 2602B, and an insulating fill material 2602C on the second insulating layer 2602B.

[0295] Collective reference Figure 25A 、 Figure 25B and Figures 26A - 26C According to an embodiment of the present disclosure, a method of manufacturing an integrated circuit structure includes forming a plurality of fins, with individual fins among the plurality of fins extending along a first direction. A plurality of gate structures are formed over the plurality of fins, with individual gate structures among the gate structures extending along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent gate structures among the plurality of gate structures. A portion of a first gate structure among the plurality of gate structures is removed to expose a first portion of each of the plurality of fins. A portion of a second gate structure among the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed. A first insulating structure is formed in the positions of the removed first portions of the plurality of fins. A second insulating structure is formed in the positions of the removed portions of the second one among the plurality of gate structures.

[0296] In one embodiment, removing portions of the first and second gate structures among the plurality of gate structures involves using a lithography window wider than the width of each of the portions of the first and second gate structures among the plurality of gate structures. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth less than the height of the plurality of fins. In one such embodiment, the depth is greater than the depth of the source or drain regions in the plurality of fins. In one embodiment, the plurality of fins include silicon fins and are continuous with a portion of the underlying silicon substrate.

[0297] Collective reference Figure 16A 、 Figure 25A 、 Figure 25B and Figures 26A - 26C, According to another embodiment of the present disclosure, an integrated circuit structure includes a fin that includes silicon and has a longest dimension in a first direction. An isolation structure is over an upper portion of the fin, and the isolation structure has a center in the first direction. A first gate structure is over the upper portion of the fin, and the first gate structure has a longest dimension in a second direction orthogonal to the first direction. A center of the first gate structure is spaced apart from a center of the isolation structure by a spacing in the first direction. A second gate structure is over the upper portion of the fin, and the second gate structure has a longest dimension in the second direction. A center of the second gate structure is spaced apart from a center of the first gate structure by the spacing in the first direction. A third gate structure is over an upper portion of the fin on a side of the isolation structure opposite the first and second gate structures, and the third gate structure has a longest dimension in the second direction. A center of the third gate structure is spaced apart from a center of the isolation structure by the spacing in the first direction.

[0298] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between sidewalls of a high-k gate dielectric layer. In one such embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on sidewalls of the high-k gate dielectric layer.

[0299] In one embodiment, a first epitaxial semiconductor region is on an upper portion of the fin between the first gate structure and the isolation structure. A second epitaxial semiconductor region is on an upper portion of the fin between the first gate structure and the second gate structure. A third epitaxial semiconductor region is on an upper portion of the fin between the third gate structure and the isolation structure. In one such embodiment, the first, second, and third epitaxial semiconductor regions include silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions include silicon.

[0300] Common reference Figure 16A , Figure 25A , Figure 25B and Figures 26A - 26C, According to another embodiment of the present disclosure, an integrated circuit structure includes a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure having a longest dimension along a first direction. An isolation structure is on the STI structure, the isolation structure having a center along the first direction. A first gate structure is on the STI structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a spacing along the first direction. A second gate structure is on the STI structure, the second gate structure having a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by the spacing along the first direction. A third gate structure is on the STI structure, on a side of the isolation structure opposite to the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by the spacing along the first direction.

[0301] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between sidewalls of a high-k gate dielectric layer. In one such embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on sidewalls of the high-k gate dielectric layer. In one embodiment, the pair of semiconductor fins is a pair of silicon fins.

[0302] In another aspect, whether multi-cut and FTI local fin cuts together or only multi-cut, an insulating structure or dielectric plug for filling the cut position can laterally extend into the dielectric spacer of the corresponding cut gate line, even beyond the dielectric spacer of the corresponding cut gate line.

[0303] In a first example where the trench contact shape is not affected by the multi-cut dielectric plug, Figure 27A A plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cut with a dielectric plug extending into the dielectric spacer of the gate line according to an embodiment of the present disclosure are shown.

[0304] Reference Figure 27A, the integrated circuit structure 2700A includes a first silicon fin 2702 having a longest dimension along a first direction 2703. A second silicon fin 2704 has a longest dimension along the first direction 2703. An insulator material 2706 is between the first silicon fin 2702 and the second silicon fin 2704. A gate line 2708 is above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709, the second direction 2709 being orthogonal to the first direction 2703. The gate line 2708 has a first side 2708A and a second side 2708B, and has a first end 2708C and a second end 2708D. The gate line 2708 has a discontinuity 2710 above the insulator material 2706 between the first end 2708C and the second end 2708D of the gate line 2708. The discontinuity 2710 is filled with a dielectric plug 2712.

[0305] A trench contact 2714 is above the first silicon fin 2702 and above the second silicon fin 2704 along the second direction 2709 at the first side 2708A of the gate line 2708. The trench contact 2714 is continuous above the insulator material 2706 at a position 2715 that is laterally adjacent to the dielectric plug 2712. A dielectric spacer 2716 is laterally between the trench contact 2714 and the first side 2708A of the gate line 2708. The dielectric spacer 2716 is continuous along the first side 2708A of the gate line 2708 and the dielectric plug 2712. The dielectric spacer 2716 has a width (W2) that is thinner than a width (W1) that is laterally adjacent to the first side 2708A of the gate line 2708 and that is laterally adjacent to the dielectric plug 2712.

[0306] In one embodiment, a second trench contact 2718 is above the first silicon fin 2702 and above the second silicon fin 2704 along the second direction 2709 at the second side 2708B of the gate line 2708. The second trench contact 2718 is continuous above the insulator material 2706 at a position 2719 that is laterally adjacent to the dielectric plug 2712. In one such embodiment, a second dielectric spacer 2720 is laterally between the second trench contact 2718 and the second side 2708B of the gate line 2708. The second dielectric spacer 2720 is continuous along the second side 2708B of the gate line 2708 and the dielectric plug 2712. The second dielectric spacer has a width that is thinner than a width that is laterally adjacent to the second side 2708B of the gate line 2708 and that is laterally adjacent to the dielectric plug 2712.

[0307] In one embodiment, the gate line 2708 includes a high-k gate dielectric layer 2722, a gate electrode 2724, and a dielectric capping layer 2726. In one embodiment, the dielectric plug 2712 includes the same material as the dielectric spacer 2714 but is discrete from the dielectric spacer 2714. In one embodiment, the dielectric plug 2712 includes a material different from that of the dielectric spacer 2714.

[0308] In a second example where the trench contact shape is affected by the multi-notch dielectric plug, Figure 27B A plan view and a corresponding cross-sectional view of an integrated circuit structure with a gate line notch having a dielectric plug extending beyond a dielectric spacer to a gate line are shown in accordance with another embodiment of the present disclosure.

[0309] Refer to Figure 27B , the integrated circuit structure 2700B includes a first silicon fin 2752 having a longest dimension along a first direction 2753. A second silicon fin 2754 has a longest dimension along the first direction 2753. An insulator material 2756 is between the first silicon fin 2752 and the second silicon fin 2754. A gate line 2758 is over the first silicon fin 2752 and over the second silicon fin 2754 along a second direction 2759, the second direction 2759 being orthogonal to the first direction 2753. The gate line 2758 has a first side 2758A and a second side 2758B, and has a first end 2758C and a second end 2758D. The gate line 2758 has a discontinuity 2760 above the insulator material 2756 between the first end 2758C and the second end 2758D of the gate line 2758. The discontinuity 2760 is filled with a dielectric plug 2762.

[0310] A trench contact 2764 is over the first silicon fin 2752 and over the second silicon fin 2754 along the second direction 2759 at the first side 2758A of the gate line 2758. The trench contact 2764 is continuous above the insulator material 2756 at a position 2765 that is laterally adjacent to the dielectric plug 2762. A dielectric spacer 2766 is laterally between the trench contact 2764 and the first side 2758A of the gate line 2758. The dielectric spacer 2766 is along the first side 2758A of the gate line 2758 but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2766. The trench contact 2764 has a width (W1) that is thinner when laterally adjacent to the dielectric plug 2762 than a width (W2) when laterally adjacent to the dielectric spacer 2766.

[0311] In one embodiment, the second trench contact 2768 is over the first silicon fin 2752 and over the second silicon fin 2754 along a second direction 2759 at a second side 2758B of the gate line 2758. The second trench contact 2768 is continuous over the insulator material 2756 at a location 2769 that is laterally adjacent to the dielectric plug 2762. In one such embodiment, a second dielectric spacer 2770 is laterally between the second trench contact 2768 and the second side 2758B of the gate line 2758. The second dielectric spacer 2770 is along the second side 2758B of the gate line 2758 but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2770. The second trench contact 2768 has a width that is thinner when laterally adjacent to the dielectric plug 2762 than when laterally adjacent to the second dielectric spacer 2770.

[0312] In one embodiment, the gate line 2758 includes a high-k dielectric layer 2772, a gate electrode 2774, and a dielectric capping layer 2776. In one embodiment, the dielectric plug 2762 includes the same material as the dielectric spacer 2764 but is discrete from the dielectric spacer 2764. In one embodiment, the dielectric plug 2762 includes a material different from the dielectric spacer 2764.

[0313] In a third example where the dielectric plug for the multi-notch location tapers from the top of the plug to the bottom of the plug, Figures 28A - 28F A cross-sectional view shows various operations in a method of manufacturing an integrated circuit structure having a gate line notch with a dielectric plug, the dielectric plug having an upper portion that extends beyond a dielectric spacer of the gate line and a lower portion that extends into the gate line dielectric spacer, according to another embodiment of the present disclosure.

[0314] Reference Figure 28A , a plurality of gate lines 2802 are formed over a structure 2804, such as over a trench isolation structure between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line, e.g., having a dummy gate electrode 2806 and a dielectric cap 2808. Portions of such sacrificial or dummy gate lines may be replaced later in a replacement gate process, e.g., after the formation of the dielectric plugs described below. Dielectric spacers 2810 are along the sidewalls of the gate lines 2802. A dielectric material 2812, such as an inter-dielectric layer, is between the gate lines 2802. A mask 2814 is formed and lithographically patterned to expose a portion of one of the gate lines 2802.

[0315] Reference Figure 28B, with the mask 2814 in place, the central gate line 2802 is removed using an etching process. Then the mask 2814 is removed. In an embodiment, the etching process etches a portion of the dielectric spacer 2810 of the removed gate line 2802, thereby forming a reduced dielectric spacer 2816. Additionally, an upper portion of the dielectric material 2812 exposed by the mask 2814 is etched in the etching process, thereby forming an etched dielectric material portion 2818. In a particular embodiment, a residual dummy gate material 2820, such as residual polysilicon, remains in the structure as an artifact of an incomplete etching process.

[0316] Reference Figure 28C , a hard mask 2822 is formed over Figure 28B the structure. The hard mask 2822 can be conformal with Figure 28B an upper portion of the structure, particularly conformal with the etched dielectric material portion 2818.

[0317] Reference Figure 28D , for example, the residual dummy gate material 2820 is removed using an etching process, which can be chemically similar to the etching process used to remove the central gate line in the gate line 2802. In an embodiment, the hard mask 2822 protects the etched dielectric material portion 2818 from further etching during the removal of the residual dummy gate material 2820.

[0318] Reference Figure 28E , the hard mask 2822 is removed. In one embodiment, the hard mask 2822 is removed without or with substantially no further etching of the etched dielectric material portion 2818.

[0319] Reference Figure 28F , a dielectric plug 2830 is formed in an opening of Figure 28E the structure. An upper portion of the dielectric plug 2830 is over the etched dielectric material portion 2818, for example, effectively exceeding the initial spacer 2810. A lower portion of the dielectric plug 2830 is adjacent to the reduced dielectric spacer 2816, for example, effectively entering but not exceeding the initial spacer 2810. As a result, the dielectric plug 2830 has a tapered profile, as shown in Figure 28F . It should be appreciated that the dielectric plug 2830 can be fabricated from the materials and processes described above for other multi-notch or FTI plugs or fin tip stressors.

[0320] In another aspect, a portion of a dummy gate structure or placeholder gate structure can be maintained over a trench isolation region below a permanent gate structure as a protective structure during a replacement gate process to prevent the trench isolation region from being etched. For example, Figures 29A - 29CA plan view and a corresponding cross-sectional view of an integrated circuit structure having residual dummy gate material at a portion at the bottom of a permanent gate stack according to an embodiment of the present disclosure are shown.

[0321] Referring Figures 29A - 29C , the integrated circuit structure includes fins 2902 protruding from a semiconductor substrate 2904, such as silicon fins. The fins 2902 have a lower fin portion 2902B and an upper fin portion 2902A. The upper fin portion 2902A has a top 2902C and sidewalls 2902D. An isolation structure 2906 surrounds the lower fin portion 2902B. The isolation structure 2906 includes an insulating material 2906C having a top surface 2907. A semiconductor material 2908 is on a portion of the top surface 2907 of the insulating material 2906C. The semiconductor material 2908 is separated from the fins 2902.

[0322] A gate dielectric layer 2910 is over the top 2902C of the upper fin portion 2902A and is laterally adjacent to the sidewalls 2902D of the upper fin portion 2902A. The gate dielectric layer 2910 is further over the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C. An intervening additional gate dielectric layer 2911, such as an oxidized portion of the fin 2902, can be between the gate dielectric layer 2910 over the top 2902C of the upper fin portion 2902A and the sidewalls 2902D of the upper fin portion 2902A and is laterally adjacent to the sidewalls 2902D. A gate electrode 2912 is over the gate dielectric layer 2910 over the top 2902C of the upper fin portion 2902A and is laterally adjacent to the sidewalls 2902D of the upper fin portion 2902A. The gate electrode 2912 is further over the gate dielectric layer 2910 over the semiconductor material 2908 on the portion of the top surface 2907 of the insulating material 2906C. A first source or drain region 2916 is adjacent to a first side of the gate electrode 2912, and a second source or drain region 2918 is adjacent to a second side of the gate electrode 2912, the second side being opposite the first side. In the embodiment described above by way of example, the isolation structure 2906 includes a first insulating layer 2906A, a second insulating layer 2906B, and an insulating material 2606C.

[0323] In one embodiment, the semiconductor material 2908 on a portion of the top surface 2907 of the insulating material 2906C is or includes polysilicon. In one embodiment, the top surface 2907 of the insulating material 2906C has a concave depression, and as shown, the semiconductor material 2908 is in the concave depression. In one embodiment, the isolation structure 2906 includes a second insulating material (2906A or 2906B or both 2906A / 2906B) along the bottom and sidewalls of the insulating material 2906C. In one such embodiment, the portion of the second insulating material (2906A or 2906B or both 2906A / 2906B) along the sidewall of the insulating material 2906C has a top surface that is above the uppermost surface of the insulating material 2906, as shown. In one embodiment, the top surface of the second insulating material (2906A or 2906B or both 2906A / 2906B) is higher than or coplanar with the uppermost surface of the semiconductor material 2908.

[0324] In one embodiment, the semiconductor material 2908 on a portion of the top surface 2907 of the insulating material 2906C does not extend beyond the gate dielectric layer 2910. That is, in terms of a plan view, the position of the semiconductor material 2908 is limited to the area covered by the gate stack 2912 / 2910. In one embodiment, the first dielectric spacer 2920 is along a first side of the gate electrode 2912. The second dielectric spacer 2922 is along a second side of the gate electrode 2912. In one such embodiment, the gate dielectric layer 2910 also extends along the sidewalls of the first dielectric spacer 2920 and the second dielectric spacer 2922, as Figure 29B shown.

[0325] In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (e.g., a work function layer). In one such embodiment, the work function layer 2912A includes titanium and nitrogen. In another embodiment, the work function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 further includes a conductive fill metal layer 2912B over the work function layer 2912A. In one such embodiment, the conductive fill metal layer 2912B includes tungsten. In a particular embodiment, the conductive fill metal layer 2912B includes 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the insulating cap 2924 is on the gate electrode 2912 and may extend over the gate dielectric layer 2910, as Figure 29B shown.

[0326] Figures 30A - 30DA cross-sectional view showing various operations in a method of manufacturing an integrated circuit structure having residual dummy gate material at a portion at the bottom of a permanent gate stack according to another embodiment of the present disclosure. The perspective view is along the Figure 29C portion of the structure along the a-a' axis.

[0327] Referring Figure 30A , a method of manufacturing an integrated circuit structure includes forming fins 3000 from a semiconductor substrate 3002. The fins 3000 have a lower fin portion 3000A and an upper fin portion 3000B. The upper fin portion 3000B has a top 3000C and sidewalls 3000D. An isolation structure 3004 surrounds the lower fin portion 3000A. The isolation structure 3004 includes an insulating material 3004C having a top surface 3005. A dummy gate electrode 3006 is over the top 3000C of the upper fin portion 3000B and is laterally adjacent to the sidewalls 3000D of the upper fin portion 3000B. The dummy gate electrode 3006 includes a semiconductor material.

[0328] Although not shown from the Figure 30A perspective (but the location therefor is shown in Figure 29C ), a first source or drain region may be formed adjacent to a first side of the dummy gate electrode 3006, and a second source or drain region may be formed adjacent to a second side of the dummy gate electrode 3006, the second side being opposite the first side. Additionally, a gate dielectric spacer may be formed along the sidewalls of the dummy gate electrode 3006, and an interlayer dielectric (ILD) layer may be formed laterally adjacent to the dummy gate electrode 3006.

[0329] In one embodiment, the dummy gate electrode 3006 is or includes polysilicon. In one embodiment, the top surface 3005 of the insulating material 3004C of the isolation structure 3004 has a concave depression, as shown. A portion of the dummy gate electrode 3006 is within the concave depression. In one embodiment, the isolation structure 3004 includes a second insulating material (3004A or 3004B or both 3004A / 3004B) along the bottom and sidewalls of the insulating material 3004C, as shown. In one such embodiment, the portion of the second insulating material (3004A or 3004B or both 3004A / 3004B) along the sidewalls of the insulating material 3004C has a top surface above at least a portion of the top surface 3005 of the insulating material 3004C. In one embodiment, the top surface of the second insulating material (3004A or 3004B or both 3004A / 3004B) is above the lowest surface of a portion of the dummy gate electrode 3006.

[0330] Referring Figure 30B, for example, along Figure 30A the direction 3008, the dummy gate electrode 3006 is etched from the top 3000C and the sidewall 3000D of the upper fin portion 3000B. The etching process can be referred to as a replacement gate process. In an embodiment, the etching or replacement gate process is not completed, and a portion 3012 of the dummy gate electrode 3006 is left on at least a part of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0331] Refer to Figure 30A and Figure 30B , in an embodiment, the oxidized portion 3010 of the upper fin portion 3000B formed before the dummy gate electrode 3006 is formed is retained during the etching process, as shown. However, in another embodiment, a dummy gate dielectric layer is formed before the dummy gate electrode 3006 is formed, and the dummy gate dielectric layer is removed after the dummy gate electrode is etched.

[0332] Refer to Figure 30C , the gate dielectric layer 3014 is formed over the top 3000C of the upper fin portion 3000B and is laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In one embodiment, the gate dielectric layer 3014 is formed on the oxidized portion 3010 of the upper fin portion 3000B over the top 3000C of the upper fin portion 3000B and is laterally adjacent to the sidewall 3000D of the upper fin portion 3000B, as shown. In another embodiment, in the case where the oxidized portion 3010 of the upper fin portion 3000B is removed after the dummy gate electrode is etched, the gate dielectric layer 3014 is directly formed on the upper fin portion 3000B, over the top 3000C of the upper fin portion 3000B, and is laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In either case, in an embodiment, the gate dielectric layer 3014 is further formed on the portion 3012 of the dummy gate electrode 3006 on a part of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0333] Refer to Figure 30D , the permanent gate electrode 3016 is formed over the gate dielectric layer 3014 over the top 3000C of the upper fin portion 3000B and is laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. The permanent gate electrode 3016 is further over the gate dielectric layer 3014 on the portion 3012 of the dummy gate electrode 3006 on a part of the top surface 3005 of the insulating material 3004C.

[0334] In one embodiment, forming the permanent gate electrode 3016 includes forming a work function layer 3016A. In one such embodiment, the work function layer 3016A includes titanium and nitrogen. In another such embodiment, the work function layer 3016A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, forming the permanent gate electrode 3016 further includes forming a conductive fill metal layer 3016B formed over the work function layer 3016A. In one such embodiment, forming the conductive fill metal layer 3016B includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF 6 ) precursor. In an embodiment, an insulating gate cap layer 3018 is formed over the permanent gate electrode 3016.

[0335] In another aspect, some embodiments of the present disclosure include an amorphous high-k layer for a gate electrode in a gate dielectric structure. In other embodiments, a partially or fully crystalline high-k layer for a gate electrode is included in the gate dielectric structure. In one embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0336] In an embodiment, ways of increasing charge in a device channel and improving subthreshold behavior by employing a ferroelectric or antiferroelectric gate oxide are described herein. Ferroelectric and antiferroelectric gate oxides are capable of increasing channel charge to achieve higher current, and are also capable of making a steeper turn-on behavior.

[0337] To provide context, ferroelectric and antiferroelectric (FE or AFE) materials based on hafnium or zirconium (Hf or Zr) are typically much thinner than ferroelectric materials such as lead zirconate titanate (PZT), such that they can be compatible with highly scaled logic technologies. The FE or AFE materials have two characteristics that can improve the performance of logic transistors: (1) higher charge in the channel achieved through FE or AFE polarization, and (2) a steeper turn-on behavior due to a sharp FE or AFE transition. Such properties can improve transistor performance by increasing current and reducing the subthreshold swing (SS).

[0338] Figure 31A A cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure in accordance with an embodiment of the present disclosure is shown.

[0339] Reference Figure 31A, the integrated circuit structure 3100 includes a gate structure 3102 over a substrate 3104. In one embodiment, the gate structure 3102 is over or above a semiconductor channel structure 3106 including a single crystal material such as single crystal silicon. The gate structure 3102 includes a gate dielectric over the semiconductor channel structure 3106 and a gate electrode over the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3102A. The gate electrode has a conductive layer 3102B on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. The conductive layer 3102B includes a metal and may be a barrier layer, a work function layer, or a template layer that enhances the crystallinity of the FE or AFE layer. One or more gate fill layers 3102C are on or over the conductive layer 3102B. Source regions 3108 and drain regions 3110 are on opposite sides of the gate structure 3102. Source or drain contacts 3112 are electrically connected to the source regions 3108 and drain regions 3110 at locations 3149 and are spaced apart from the gate structure 3102 by an interlayer dielectric layer 3114 or a gate dielectric spacer 3116. In Figure 31A the example, the source regions 3108 and drain regions 3110 are regions of the substrate 3104. In an embodiment, the source or drain contacts 3112 include a barrier layer 3112A and a conductive trench fill material 3112B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3102A extends along the dielectric spacer 3116, as Figure 31A shown.

[0340] In an embodiment, and as applicable throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide including Zr and Hf, having a Zr:Hf ratio of 50:50 or having more Zr. The ferroelectric effect can increase as the orthorhombic crystallinity increases. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

[0341] In an embodiment, and as applicable throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide including Zr and Hf, having a Zr:Hf ratio of 80:20 or having more Zr, even up to 100% Zr, ZrO 2 . In one embodiment, the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystallinity.

[0342] In an embodiment, and as applicable throughout the disclosure, the gate dielectric of the gate stack 3102 further includes an amorphous dielectric layer 3103 between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106, such as a native silicon oxide layer, a high-k dielectric (HfOx, Al 2 O 3 etc.) or a combination of an oxide and a high-k. In an embodiment, and as applicable throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness in the range of 1 nanometer to 8 nanometers. In an embodiment, and as applicable throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a grain size generally in the range of 20 nanometers or greater.

[0343] In an embodiment, after depositing the ferroelectric or antiferroelectric polycrystalline material layer 3102A, for example, by atomic layer deposition (ALD), a layer including a metal (e.g., layer 3102B, such as titanium nitride or tantalum nitride or tungsten of 5 - 10 nanometers) is formed on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. Then annealing is performed. In one embodiment, annealing is performed for a period of time in the range of 1 millisecond - 30 minutes. In one embodiment, annealing is performed at a temperature in the range of 500 - 1100 degrees Celsius.

[0344] Figure 31B A cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure is shown.

[0345] Reference Figure 31B, the integrated circuit structure 3150 includes a gate structure 3152 over a substrate 3154. In one embodiment, the gate structure 3152 is over or above a semiconductor channel structure 3156 including a single crystal material such as single crystal silicon. The gate structure 3152 includes a gate dielectric over the semiconductor channel structure 3156 and a gate electrode over the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3152A and may also include an amorphous oxide layer 3153. The gate electrode has a conductive layer 3152B on the ferroelectric or antiferroelectric polycrystalline material layer 3152A. The conductive layer 3152B includes a metal and may be a barrier layer or a work function layer. One or more gate fill layers 3152C are on or over the conductive layer 3152B. Raised source regions 3158 and raised drain regions 3160 (e.g., regions of semiconductor material different from the semiconductor channel structure 3156) are on opposite sides of the gate structure 3152. Source or drain contacts 3162 are electrically connected to the source region 3158 and the drain region 3160 at location 3199 and are spaced apart from the gate structure 3152 by one or both of an interlayer dielectric layer 3164 or a gate dielectric spacer 3166. In an embodiment, the source or drain contact 3162 includes a barrier layer 3162A and a conductive trench fill material 3162B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3152A extends along the dielectric spacer 3166, as Figure 31B shown.

[0346] Figure 32A A plan view of multiple gate lines over semiconductor fins according to another embodiment of the present disclosure is shown.

[0347] Reference Figure 32A , multiple active gate lines 3204 are formed over multiple semiconductor fins 3200. dummy gate lines 3206 are at the ends of the multiple semiconductor fins 3200. The spacing 3208 between the gate lines 3204 / 3206 is a location where trench contacts can be positioned to provide conductive contacts to source or drain regions (e.g., source or drain regions 3251, 3252, 3253, and 3254). In an embodiment, the pattern of the multiple gate lines 3204 / 3206 or the pattern of the multiple semiconductor fins 3200 is described as a grid structure. In one embodiment, the grid-like pattern includes multiple gate lines 3204 / 3206 spaced apart at a constant pitch and having a constant width, or the pattern of the multiple semiconductor fins 3200, or both.

[0348] Figure 32B A cross-sectional view taken along the Figure 32A a-a' axis according to an embodiment of the present disclosure is shown.

[0349] ReferenceFigure 32B , multiple active gate lines 3264 are formed over semiconductor fins 3262 formed over a substrate 3260. dummy gate lines 3266 are at the ends of the semiconductor fins 3262. a dielectric layer 3270 is outside the dummy gate lines 3266. trench contact material 3297 is between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264. embedded source or drain structures 3268 are in the semiconductor fins 3262, between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264.

[0350] The active gate lines 3264 include a gate dielectric structure 3272, a work function gate electrode portion 3274, a fill gate electrode portion 3276, and a dielectric capping layer 3278. dielectric spacers 3280 are arranged along the sidewalls of the active gate lines 3264 and the dummy gate lines 3266. in an embodiment, the gate dielectric structure 3272 includes a ferroelectric or antiferroelectric polycrystalline material layer 3298. in one embodiment, the gate dielectric structure 3272 further includes an amorphous oxide layer 3299.

[0351] In another aspect, devices of the same conductivity type (e.g., n-type or p-type) can have differentiated gate electrode stacks for the same conductivity type. however, for comparison purposes, devices of the same conductivity type can have differentiated voltage thresholds (VTs) based on modulated doping.

[0352] Figure 33A Cross-sectional views of an NMOS device pair and a PMOS device pair according to embodiments of the present disclosure are shown, the NMOS device pair having differentiated voltage thresholds based on modulated doping and the PMOS device pair having differentiated voltage thresholds based on modulated doping.

[0353] Reference Figure 33A, a first NMOS device 3302 is adjacent to a second NMOS device 3304 over a semiconductor active region 3300 (e.g., over a silicon fin or a substrate). Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first gate electrode conductive layer 3308 (e.g., a work function layer), and a gate electrode conductive fill 3310. In an embodiment, the first gate electrode conductive layers 3308 of the first NMOS device 3302 and the second NMOS device 3304 have the same material and the same thickness, and thus have the same work function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304. In one such embodiment, the first NMOS device 3302 is referred to as a "standard VT" device, and the second NMOS device 3304 is referred to as a "high VT" device. In an embodiment, the differential VT is achieved by using modulated doping or differential implant doping at regions 3312 of the first NMOS device 3302 and the second NMOS device 3304.

[0354] Referring again to Figure 33A , a first PMOS device 3322 is adjacent to a second PMOS device 3324 over a semiconductor active region 3320 (e.g., over a silicon fin or a substrate). Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326, a first gate electrode conductive layer 3328 (e.g., a work function layer), and a gate electrode conductive fill 3330. In an embodiment, the first gate electrode conductive layers 3328 of the first PMOS device 3322 and the second PMOS device 3324 have the same material and the same thickness, and thus have the same work function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324. In one such embodiment, the first PMOS device 3322 is referred to as a "standard VT" device, and the second PMOS device 3324 is referred to as a "low VT" device. In an embodiment, the differential VT is achieved by using modulated doping or differential implant doping at regions 3332 of the first PMOS device 3322 and the second PMOS device 3324.

[0355] Compared with Figure 33A Figure 33B FIG. shows a cross-sectional view of an NMOS device pair and a PMOS device pair according to another embodiment of the present disclosure, where the NMOS device pair has a differential voltage threshold based on a differential gate electrode structure, and the PMOS device pair has a differential voltage threshold based on a differential gate electrode structure.

[0356] Referring to Figure 33B, a first NMOS device 3352 is adjacent to a second NMOS device 3354 over a semiconductor active region 3350 (e.g., over a silicon fin or a substrate). Both the first NMOS device 3352 and the second NMOS device 3354 include a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. Specifically, the first NMOS device 3322 includes a first gate electrode conductive layer 3358 such as a first work function layer, and a gate electrode conductive fill 3360. The second NMOS device 3354 includes a second gate electrode conductive layer 3359 such as a second work function layer, the first gate electrode conductive layer 3358, and a gate electrode conductive fill 3360. The first NMOS device 3352 has a lower VT than the second NMOS device 3354. In one such embodiment, the first NMOS device 3352 is referred to as a "standard VT" device, and the second NMOS device 3354 is referred to as a "high VT" device. In an embodiment, the differential VT is achieved by using differential gate stacks for devices of the same conduction type.

[0357] Referring again to Figure 33B , a first PMOS device 3372 is adjacent to a second PMOS device 3374 over a semiconductor active region 3370 (e.g., over a silicon fin or a substrate). Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. Specifically, the first PMOS device 3372 includes a gate electrode conductive layer 3378A (e.g., a work function layer) having a first thickness, and a gate electrode conductive fill 3380. The second PMOS device 3374 includes a gate electrode conductive layer 3378B having a second thickness, and a gate electrode conductive fill 3380. In one embodiment, the gate electrode conductive layer 3378A and the gate electrode conductive layer 3378B have the same composition, but the thickness of the gate electrode conductive layer 3378B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3378A (the first thickness). The first PMOS device 3372 has a higher VT than the second PMOS device 3374. In one such embodiment, the first PMOS device 3372 is referred to as a "standard VT" device, and the second PMOS device 3374 is referred to as a "low VT" device. In an embodiment, the differential VT is achieved by using differential gate stacks for devices of the same conduction type.

[0358] Referring again to Figure 33B, according to an embodiment of the present disclosure, an integrated circuit structure includes fins (e.g., silicon fins, such as 3350). It should be recognized that the fins have a top (as shown) and sidewalls (into the page and out of the page). A gate dielectric layer 3356 is above the top of the fin and is laterally adjacent to the sidewalls of the fin. The N-type gate electrode of device 3354 is above the gate dielectric layer 3356 above the top of the fin and is laterally adjacent to the sidewalls of the fin. The N-type gate electrode includes a P-type metal layer 3359 on the gate dielectric layer 3356 and an N-type metal layer 3358 on the P-type metal layer 3359. It will be recognized that a first N-type source or drain region may be adjacent to a first side of the gate electrode (e.g., into the page), and a second N-type source or drain region may be adjacent to a second side of the gate electrode (e.g., out of the page), the second side being opposite the first side.

[0359] In one embodiment, the P-type metal layer 3359 includes titanium and nitrogen, and the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer 3359 has a thickness in the range of 2 - 12 angstroms, and in a specific embodiment, the P-type metal layer 3359 has a thickness in the range of 2 - 4 angstroms. In one embodiment, the N-type gate electrode further includes a conductive fill metal layer 3360 on the N-type metal layer 3358. In one such embodiment, the conductive fill metal layer 3360 includes tungsten. In a particular embodiment, the conductive fill metal layer 3360 includes 95 or more atomic percent tungsten and 0.1 to 2 atomic percent fluorine.

[0360] Referring again to Figure 33B , according to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), the first N-type device 3352 having a first gate dielectric layer 3356, and a first N-type metal layer 3358 on the first gate dielectric layer 3356. Moreover, it further includes a second N-type device 3354 having a voltage threshold (VT), the second N-type device 3354 having a second gate dielectric layer 3356, a P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the P-type metal layer 3359.

[0361] In one embodiment, the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same composition. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same thickness. In one embodiment, the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen, and the P-type metal layer 3359 includes titanium and nitrogen.

[0362] Referring again to Figure 33B , according to another embodiment of the present disclosure, an integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT), the first P-type device 3372 having a first gate dielectric layer 3376, and a first P-type metal layer 3378A on the first gate dielectric layer 3376. The first P-type metal layer 3378A has a thickness. A second P-type device 3378 is also included and has a voltage threshold (VT). The second P-type device 3374 has a second gate dielectric layer 3376 and a second P-type metal layer 3378B on the second gate dielectric layer 3376. The second P-type metal layer 3378B has a thickness greater than the thickness of the first P-type metal layer 3378A.

[0363] In one embodiment, the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same composition. In one embodiment, both the first P-type metal layer 3378A and the second P-type metal layer 3378B include titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is less than the work function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not shown, the second P-type metal layer 3378B includes a first metal film (e.g., from a second deposition) on a second metal film (e.g., from a first deposition), and the seam is between the first metal film and the second metal film.

[0364] Referring again to Figure 33B , according to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a first gate dielectric layer 3356, and a first N-type metal layer 3358 on the first gate dielectric layer 3356. A second N-type device 3354 has a second gate dielectric layer 3356, a first P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the first P-type metal layer 3359. The first P-type device 3372 has a third gate dielectric layer 3376 and a second P-type metal layer 3378A on the third gate dielectric layer 3376. The second P-type metal layer 3378A has a thickness. The second P-type device 3374 has a fourth gate dielectric layer 3376 and a third P-type metal layer 3378B on the fourth gate dielectric layer 3376. The third P-type metal layer 3378B has a thickness greater than the thickness of the second P-type metal layer 3378A.

[0365] In one embodiment, the first N-type device 3352 has a voltage threshold (VT), the second N-type device 3354 has a voltage threshold (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352. In one embodiment, the first P-type device 3372 has a voltage threshold (VT), the second P-type device 3374 has a voltage threshold (VT), and the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the third P-type metal layer 3378B includes a first metal film on a second metal film, and a seam is between the first metal film and the second metal film.

[0366] It should be recognized that more than two types of VT devices of the same conduction type can be included in the same structure (e.g., on the same die). In a first example, Figure 34A A cross-sectional view of three NMOS devices and three PMOS devices according to an embodiment of the present disclosure is shown, the three NMOS devices having different voltage thresholds based on a differentiated gate electrode structure and a modulated doping, and the three PMOS devices having different voltage thresholds based on a differentiated gate electrode structure and a modulated doping.

[0367] Refer to Figure 34A, a first NMOS device 3402 is adjacent to a second NMOS device 3404 and a third NMOS device 3403 over a semiconductor active region 3400 (e.g., over a silicon fin or substrate). The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 include a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have structurally identical or similar gate electrode stacks. However, the second NMOS device 3404 has a gate electrode stack that is structurally different from that of the first NMOS device 3402 and the third NMOS device 3403. Specifically, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408 (e.g., a first work function layer) and a gate electrode conductive fill 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409 (e.g., a second work function layer), the first gate electrode conductive layer 3408, and a gate electrode conductive fill 3410. The first NMOS device 3402 has a lower VT than the second NMOS device 3404. In one such embodiment, the first NMOS device 3402 is referred to as a "standard VT" device, and the second NMOS device 3404 is referred to as a "high VT" device. In an embodiment, the differential VT is achieved by using a differentiated gate stack for devices of the same conduction type. In an embodiment, the third NMOS device 3403 has a VT different from that of the first NMOS device 3402 and the second NMOS device 3404, even though the gate electrode structure of the third NMOS device 3403 is the same as that of the first NMOS device 3402. In one embodiment, the VT of the third NMOS device is between the VT of the first NMOS device 3402 and the VT of the second NMOS device 3404. In an embodiment, the differential VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using a modulated doping or a differential implant doping at a region 3412 of the third NMOS device 3403. In one such embodiment, the third N-type device 3403 has a channel region with a dopant concentration different from that of the channel region of the first N-type device 3402.

[0368] Refer again to Figure 34A, the first PMOS device 3422 is adjacent to the second PMOS device 3424 and the third PMOS device 3423 above the semiconductor active region 3420 (e.g., above a silicon fin or substrate). The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 include a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have structurally identical or similar gate electrode stacks. However, the second PMOS device 3424 has a gate electrode stack that is structurally different from that of the first PMOS device 3422 and the third PMOS device 3423. Specifically, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conductive layer 3408A (e.g., a work function layer) having a first thickness, and a gate electrode conductive fill 3430. The second PMOS device 3424 includes a gate electrode conductive layer 3428B having a second thickness, and a gate electrode conductive fill 3430. In one embodiment, the gate electrode conductive layer 3428A and the gate electrode conductive layer 3428B have the same composition, but the thickness of the gate electrode conductive layer 3428B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3428A (the first thickness). In an embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424. In one such embodiment, the first PMOS device 3422 is referred to as a "standard VT" device, and the second PMOS device 3424 is referred to as a "low VT" device. In an embodiment, the differential VT is achieved by using a differentiated gate stack for devices of the same conduction type. In an embodiment, the third PMOS device 3423 has a VT different from the VT of the first PMOS device 3422 and the VT of the second PMOS device 3424, even though the gate electrode structure of the third PMOS device 3423 is the same as that of the first PMOS device 3422. In one embodiment, the VT of the third PMOS device 3423 is between the VT of the first PMOS device 3422 and the VT of the second PMOS device 3424. In an embodiment, the differential VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved by using a modulated doping or a differentiated implanted doping at the region 3432 of the third PMOS device 3423. In one such embodiment, the third P-type device 3423 has a channel region having a dopant concentration different from that of the channel region of the first P-type device 3422.

[0369] In a second example, Figure 34BA cross-sectional view of three NMOS devices and three PMOS devices according to another embodiment of the present disclosure is shown. The three NMOS devices have different voltage thresholds based on a differentiated gate electrode structure and a modulated doping, and the three PMOS devices have different voltage thresholds based on a differentiated gate electrode structure and a modulated doping.

[0370] Referring Figure 34B , a first NMOS device 3452 is adjacent to a second NMOS device 3454 and a third NMOS device 3453 over a semiconductor active region 3450 (e.g., over a silicon fin or a substrate). The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 include a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have structurally identical or similar gate electrode stacks. However, the first NMOS device 3452 has a gate electrode stack that is structurally different from that of the second NMOS device 3454 and the third NMOS device 3453. Specifically, the first NMOS device 3452 includes a first gate electrode conductive layer 3458 (e.g., a first work function layer) and a gate electrode conductive fill 3460. The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459 (e.g., a second work function layer), the first gate electrode conductive layer 3458, and the gate electrode conductive fill 3460. The first NMOS device 3452 has a lower VT than the second NMOS device 3454. In one such embodiment, the first NMOS device 3452 is referred to as a "standard VT" device, and the second NMOS device 3454 is referred to as a "high VT" device. In an embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conduction type. In an embodiment, the third NMOS device 3453 has a VT that is different from the VT of the first NMOS device 3452 and the VT of the second NMOS device 3454, even though the gate electrode structure of the third NMOS device 3453 is the same as that of the second NMOS device 3454. In one embodiment, the VT of the third NMOS device 3453 is between the VT of the first NMOS device 3452 and the VT of the second NMOS device 3454. In an embodiment, the differentiated VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by using a modulated doping or a differentiated implanted doping at a region 3462 of the third NMOS device 3453. In one such embodiment, the third N-type device 3453 has a channel region with a dopant concentration different from that of the channel region of the second N-type device 3454.

[0371] Referring againFigure 34B , a first PMOS device 3472 is adjacent to a second PMOS device 3474 and a third PMOS device 3473 over a semiconductor active region 3470 (e.g., over a silicon fin or a substrate). The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 include a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have structurally identical or similar gate electrode stacks. However, the first PMOS device 3472 has a gate electrode stack that is structurally different from the second PMOS device 3474 and the third PMOS device 3473. Specifically, the first PMOS device 3472 includes a gate electrode conductive layer 3478A (e.g., a work function layer) having a first thickness, and a gate electrode conductive fill 3480. The second PMOS device 3474 and the third PMOS device 3473 include a gate electrode conductive layer 3478B having a second thickness, and a gate electrode conductive fill 3480. In one embodiment, the gate electrode conductive layer 3478A and the gate electrode conductive layer 3478B have the same composition, but the thickness of the gate electrode conductive layer 3478B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3478A (the first thickness). In an embodiment, the first PMOS device 3472 has a higher VT than the second PMOS device 3474. In one such embodiment, the first PMOS device 3472 is referred to as a "standard VT" device, and the second PMOS device 3474 is referred to as a "low VT" device. In an embodiment, the differential VT is achieved by using a differentiated gate stack for devices of the same conduction type. In an embodiment, the third PMOS device 3473 has a VT different from the VT of the first PMOS device 3472 and the VT of the second PMOS device 3474, even though the gate electrode structure of the third PMOS device 3473 is the same as the gate electrode structure of the second PMOS device 3474. In one embodiment, the VT of the third PMOS device 3473 is between the VT of the first PMOS device 3472 and the VT of the second PMOS device 3474. In an embodiment, the differential VT between the third PMOS device 3473 and the first PMOS device 3472 is achieved by using a modulated doping or a differentiated implanted doping at a region 3482 of the third PMOS device 3473. In one such embodiment, the channel region of the third P-type device 3473 has a dopant concentration different from the dopant concentration of the channel region of the second P-type device 3474.

[0372] Figures 35A - 35D A cross-sectional view shows various operations in a method of manufacturing an NMOS device having a differential voltage threshold based on a differential gate electrode structure according to an embodiment of the present disclosure.

[0373] Reference Figure 35A , wherein a "standard VT NMOS" region (STD VT NMOS) and a "high VT NMOS" region (HIGH VT NMOS) are shown to bifurcate on a common substrate, and a method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3506 over a first semiconductor fin 3502 and over a second semiconductor fin 3504 (e.g., over first and second silicon fins). A P-type metal layer 3508 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and over the second semiconductor fin 3504.

[0374] Reference Figure 35B , a portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 over the first semiconductor fin 3502, but a portion 3509 of the P-type metal layer 3508 remains on the gate dielectric layer 3506 over the second semiconductor fin 3504.

[0375] Reference Figure 35C , an N-type metal layer 3510 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and on the portion 3509 of the P-type metal layer on the gate dielectric layer 3506 over the second semiconductor fin 3504. In an embodiment, subsequent processing includes forming a first N-type device having a voltage threshold (VT) over the first semiconductor fin 3502 and forming a second N-type device having a voltage threshold (VT) over the second semiconductor fin 3504, wherein the VT of the second N-type device is higher than the VT of the first N-type device.

[0376] Reference Figure 35D , in an embodiment, a conductive fill metal layer 3512 is formed on the N-type metal layer 3510. In one such embodiment, forming the conductive fill metal layer 3512 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF 6 ) precursor.

[0377] Figures 36A - 36D Cross-sectional views illustrate various operations in a method of fabricating a PMOS device having different voltage thresholds based on a differentiated gate electrode structure, according to embodiments of the present disclosure.

[0378] Reference Figure 36A, where the "standard VT PMOS" region (STD VT PMOS) and the "low VT PMOS" region (LOW VT PMOS) are shown as bifurcating on a common substrate, and a method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3606 over a first semiconductor fin 3602 and over a second semiconductor fin 3604 (e.g., over first and second silicon fins). A first P-type metal layer 3608 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 and over the second semiconductor fin 3604.

[0379] Reference Figure 36B , removing a portion of the first P-type metal layer 3608 from the gate dielectric layer 3606 over the first semiconductor fin 3602, but a portion 3609 of the first P-type metal layer 3608 remains on the gate dielectric layer 3606 over the second semiconductor fin 3604.

[0380] Reference Figure 36C , a second P-type metal layer 3610 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 and on the portion 3609 of the first P-type metal layer on the gate dielectric layer 3606 over the second semiconductor fin 3604. In an embodiment, subsequent processing includes forming a first P-type device having a voltage threshold (VT) over the first semiconductor fin 3602 and forming a second P-type device having a voltage threshold (VT) over the second semiconductor fin 3604, where the VT of the second P-type device is lower than the VT of the first P-type device.

[0381] In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same composition. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness and the same composition. In one embodiment, a seam 3611 is between the first P-type metal layer 3608 and the second P-type metal layer 3610, as shown.

[0382] Reference Figure 36D , in an embodiment, a conductive fill metal layer 3612 is formed over the P-type metal layer 3610. In one such embodiment, forming the conductive fill metal layer 3612 includes using tungsten hexafluoride (WF 6)The precursor is used to form a tungsten-containing film by atomic layer deposition (ALD). In one embodiment, an N-type metal layer 3614 is formed on the P-type metal layer 3610 before forming the conductive filling metal layer 3612, as shown. In one such embodiment, the N-type metal layer 3614 is an artifact of a dual-metal gate replacement solution.

[0383] In another aspect, a metal gate structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. In an example, Figure 37 A cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure is shown.

[0384] Reference Figure 37 , the integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 and a P-well region 3708. The N-well region 3704 has a first semiconductor fin 3706 protruding therefrom, and the P-well region 3708 has a second semiconductor fin 3710 protruding therefrom. The first semiconductor fin 3706 is spaced apart from the second semiconductor fin 3710. The N-well region 3704 and the P-well region 3708 are directly adjacent in the semiconductor substrate 3702. A trench isolation structure 3712 is on the semiconductor substrate 3702, outside and between the first semiconductor fin 3706 and the second semiconductor fin 3710. The first 3706 and second 3710 semiconductor fins extend above the trench isolation structure 3712.

[0385] A gate dielectric layer 3714 is on the first 3706 and second 3710 semiconductor fins and on the trench isolation structure 3712. The gate dielectric layer 3714 is continuous between the first 3706 and second 3710 semiconductor fins. A conductive layer 3716 is above the gate dielectric layer 3714 above the first semiconductor fin 3706, but not above the gate dielectric layer 3714 above the second semiconductor fin 3710. In one embodiment, the conductive layer 3716 includes titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is above the conductive layer 3716 above the first semiconductor fin 3706, but not above the conductive layer 3716 above the second semiconductor fin 3710. The p-type metal gate layer 3718 is further on a part (but not all) of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710. An N-type metal gate layer 3720 is above the second semiconductor fin 3710, above the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and above the p-type metal gate layer 3718.

[0386] In one embodiment, an interlayer dielectric (ILD) layer 3722 is over a trench isolation structure 3712 that is external to a first semiconductor fin 3706 and a second semiconductor fin 3710. The ILD layer 3722 has an opening 3724 that exposes the first 3706 and second 3710 semiconductor fins. In one such embodiment, a conductive layer 3716, a p-type metal gate layer 3718, and an n-type metal gate layer 3720 are further formed along sidewalls 3726 of the opening 3724, as shown. In a particular embodiment, the conductive layer 3716 has a top surface 3717 that is below a top surface 3719 of the p-type metal gate layer 3718 and below a top surface 3721 of the n-type metal gate layer 3720 along the sidewalls 3726 of the opening 3724, as shown.

[0387] In one embodiment, the p-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, the n-type metal gate layer 3720 includes titanium and aluminum. In one embodiment, a conductive fill metal layer 3730 is over the n-type metal layer 3720, as shown. In one such embodiment, the conductive fill metal layer 3730 includes tungsten. In a particular embodiment, the conductive fill metal layer 3730 includes 95 or more atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 has a layer including hafnium and oxygen. In one embodiment, a thermal or chemical oxide layer 3732 is between upper portions of the first 3706 and second 3710 semiconductor fins, as shown. In one embodiment, the semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0388] Now referring only to Figure 37 the right side of, according to embodiments of the present disclosure, an integrated circuit structure includes a semiconductor substrate 3702 that includes an N-well region 3704 having semiconductor fins 3706 protruding therefrom. A trench isolation structure 3712 is on the semiconductor substrate 3702 and around the semiconductor fins 3706. The semiconductor fins 3706 extend above the trench isolation structure 3712. A gate dielectric layer 3714 is over the semiconductor fins 3706. A conductive layer 3716 is over the gate dielectric layer 3714 that is over the semiconductor fins 3706. In one embodiment, the conductive layer 3716 includes titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is over the conductive layer 3716 that is over the semiconductor fins 3706.

[0389] In one embodiment, an interlayer dielectric (ILD) layer 3722 is above the trench isolation structure 3712. The ILD layer has an opening that exposes the semiconductor fins 3706. A conductive layer 3716 and a P-type metal gate layer 3718 are further formed along the sidewalls of the opening. In one such embodiment, the conductive layer 3716 has a top surface along the sidewalls of the opening, and the top surface is lower than the top surface of the P-type metal gate layer 3718 along the sidewalls of the opening. In one embodiment, the P-type metal gate layer 3718 is above the conductive layer 3716. In one embodiment, the P-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, a conductive fill metal layer 3730 is above the P-type metal gate layer 3718. In one such embodiment, the conductive fill metal layer 3730 includes tungsten. In a particular such embodiment, the conductive fill metal layer 3730 consists of 95 or more atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 includes a layer having hafnium and oxygen.

[0390] Figures 38A - 38H A cross-sectional view shows various operations in a method of manufacturing an integrated circuit structure using a dual-metal gate replacement gate process flow in accordance with an embodiment of the present disclosure.

[0391] Reference Figure 38A , which shows an NMOS (N-type) region and a PMOS (P-type) region, a method of manufacturing an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 3802 above first 3804 and second 3806 semiconductor fins above a substrate 3800. An opening 3808 is formed in the ILD layer 3802, and the opening 3808 exposes the first 3804 and second 3806 semiconductor fins. In one embodiment, the opening 3808 is formed by removing a gate dummy or dummy gate structure initially in a position above the first 3804 and second 3806 semiconductor fins.

[0392] A gate dielectric layer 3810 is formed in the opening 3808 and on the first 3804 and second 3806 semiconductor fins and on a portion of a trench isolation structure 3812 between the first 3804 and second 3806 semiconductor fins. In one embodiment, the gate dielectric layer 3810 is formed on a thermal or chemical oxide layer 3811 such as a silicon oxide or silicon dioxide layer formed on the first 3804 and second 3806 semiconductor fins, as shown. In another embodiment, the gate dielectric layer 3810 is directly formed on the first 3804 and second 3806 semiconductor fins.

[0393] The conductive layer 3814 is formed over the gate dielectric layer 3810 formed over the first 3804 and second 3806 semiconductor fins. In one embodiment, the conductive layer 3814 includes titanium, nitrogen, and oxygen. The p-type metal gate layer 3816 is formed over the conductive layer 3814 formed over the first semiconductor fin 3804 and over the second semiconductor fin 3806.

[0394] Reference Figure 38B , a dielectric etch stop layer 3818 is formed over the p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 includes a first silicon oxide (e.g., SiO 2 ) layer, an aluminum oxide layer over the first silicon oxide layer (e.g., Al 2 O 3 ), and a second silicon oxide (e.g., SiO 2 ) layer over the aluminum oxide layer.

[0395] Reference Figure 38C , a mask 3820 is formed over the Figure 38B structure. The mask 3820 covers the PMOS region and exposes the NMOS region.

[0396] Reference Figure 38D , the dielectric etch stop layer 3818, the p-type metal gate layer 3816, and the conductive layer 3814 are patterned to provide a patterned dielectric etch stop layer 3819, a patterned p-type metal gate layer 3817 over the patterned conductive layer 3815 over the first semiconductor fin 3804 but not over the second semiconductor fin 3806. In an embodiment, the conductive layer 3814 protects the second semiconductor fin 3806 during patterning.

[0397] Reference Figure 38E , the mask 3820 is removed from the Figure 38D structure. Reference Figure 38F , the patterned dielectric etch stop layer 3819 is removed from the Figure 38E structure.

[0398] Reference Figure 38G, an n-type metal gate layer 3822 is formed over the second semiconductor fin 3806, over a portion of the trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806, and over the patterned p-type metal gate layer 3817. In an embodiment, a patterned conductive layer 3815, a patterned p-type metal gate layer 3817, and an n-type metal gate layer 3822 are further formed along the sidewall 3824 of the opening 3808. In one such embodiment, the patterned conductive layer 3815 has a top surface that is below the top surface of the patterned p-type metal gate layer 3817 along the sidewall 3824 of the opening 3808 and below the top surface of the n-type metal gate layer 3822 along the sidewall 3824 of the opening 3808.

[0399] Reference Figure 38H , a conductive fill metal layer 3826 is formed over the n-type metal layer 3822. In one embodiment, the conductive fill metal layer 3826 is formed by depositing a tungsten-containing film using tungsten hexafluoride (WF 6 ) precursor by atomic layer deposition (ALD).

[0400] In another aspect, a dual silicide structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. As an exemplary process flow, Figures 39A - 39H a cross-sectional view is shown that depicts various operations in a method of manufacturing a dual-silicide-based integrated circuit according to an embodiment of the present disclosure.

[0401] Reference Figure 39A , where an NMOS region and a PMOS region are shown as diverging on a common substrate, a method of manufacturing an integrated circuit structure includes forming a first gate structure 3902 that may include a dielectric sidewall spacer 3903 over a first fin 3904 such as a first silicon fin. A second gate structure 3952 that may include a dielectric sidewall spacer 3953 is formed over a second fin 3954 such as a second silicon fin. An insulating material 3906 is formed adjacent to the first gate structure 3902 over the first fin 3904 and adjacent to the second gate structure 3952 over the second fin 3954. In one embodiment, the insulating material 3906 is a sacrificial material and is used as a mask during the dual silicide process.

[0402] Reference Figure 39B, a first portion of the insulating material 3906 is removed above the first fin 3904 but not above the second fin 3954 to expose a first 3908 and a second 3910 source or drain region of the first fin 3904 adjacent to the first gate structure 3902. In an embodiment, the first 3908 and second 3910 source or drain regions are epitaxial regions formed within recessed portions of the first fin 3904, as shown. In one such embodiment, the first 3908 and second 3910 source or drain regions include silicon and germanium.

[0403] Reference Figure 39C , a first metal silicide layer 3912 is formed over the first 3908 and second 3910 source or drain regions of the first fin 3904. In one embodiment, the first metal silicide layer 3912 is formed by depositing a layer including nickel and platinum over a Figure 39B structure, annealing the layer including nickel and platinum, and removing unreacted portions of the layer including nickel and platinum.

[0404] Reference Figure 39D , after forming the first metal silicide layer 3912, a second portion of the insulating material 3906 is removed above the second fin 3954 to expose a third 3958 and a fourth 3960 source or drain region of the second fin 3954 adjacent to the second gate structure 3952. In an embodiment, the second 3958 and third 3960 source or drain regions are formed within the second fin 3954, such as within a second silicon fin, as shown. However, in another embodiment, the third 3958 and fourth 3960 source or drain regions are epitaxial regions formed within recessed portions of the second fin 3954. In one such embodiment, the third 3958 and fourth 3960 source or drain regions include silicon.

[0405] Reference Figure 39E , a first metal layer 3914 is formed over Figure 39D the structure, i.e., over the first 3908, second 3910, third 3958, and fourth 3960 source or drain regions. A second metal silicide layer 3962 is then formed over the third 3958 and fourth 3960 source or drain regions of the second fin 3954. For example, the second metal silicide layer 3962 is formed from the first metal layer 3914 using an annealing process. In an embodiment, the composition of the second metal silicide layer 3962 is different from the composition of the first metal silicide layer 3912. In one embodiment, the first metal layer 3914 is or includes a titanium layer. In one embodiment, the first metal layer 3914 is formed as a conformal metal layer, e.g., conformal to Figure 39D open trenches, as shown.

[0406] Reference Figure 39F, in an embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer 3916 above each of the first 3908, second 3910, third 3958, and fourth 3960 source or drain regions.

[0407] Reference Figure 39G , in an embodiment, the second metal layer 3918 is formed on Figure 39F the U-shaped metal layer 3916 of the structure. In an embodiment, the composition of the second metal layer 3918 is different from that of the U-shaped metal layer 3916.

[0408] Reference Figure 39H , in an embodiment, the third metal layer 3920 is formed on Figure 39G the second metal layer 3918 of the structure. In an embodiment, the third metal layer 3920 has the same composition as the U-shaped metal layer 3916.

[0409] Refer again to Figure 39H , according to an embodiment of the present disclosure, the integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) above a substrate. The P-type semiconductor device includes a first fin 3904, such as a first silicon fin. It should be appreciated that the first fin has a top (shown as 3904A) and sidewalls (into and out of the page). The first gate electrode 3902 includes a first gate dielectric layer above the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904, and includes a first gate electrode above the first gate dielectric layer above the top 3904A of the first fin 3904 and laterally adjacent to the sidewalls of the first fin 3904. The first gate electrode 3902 has a first side 3902A and a second side 3902B opposite the first side 3902A.

[0410] The first 3908 and second 3910 semiconductor source or drain regions are adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902, respectively. The first 3930 and second 3932 trench contact structures are above the first 3908 and second 3910 semiconductor source or drain regions adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902, respectively. The first metal silicide layer 3912 is directly between the first 3930 and second 3932 trench contact structures and the first 3908 and second 3910 semiconductor source or drain regions, respectively.

[0411] The integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) above a substrate. The N-type semiconductor device includes a second fin 3954, such as a second silicon fin. It should be appreciated that the second fin has a top (shown as 3954A) and sidewalls (into and out of the page). The second gate electrode 3952 includes a second gate dielectric layer over the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954, and includes a second gate electrode over the second gate dielectric layer over the top 3954A of the second fin 3954 and laterally adjacent to the sidewalls of the second fin 3954. The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite the first side 3952A.

[0412] A third 3958 and a fourth 3960 semiconductor source or drain region are adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952, respectively. Third 3970 and fourth 3972 trench contact structures are over the third 3958 and fourth 3960 semiconductor source or drain regions adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952, respectively. A second metal silicide layer 3962 is directly between the third 3970 and fourth 3972 trench contact structures and the third 3958 and fourth 3960 semiconductor source or drain regions. In an embodiment, the first metal silicide layer 3912 includes at least one metal species not included in the second metal silicide layer 3962.

[0413] In one embodiment, the second metal silicide layer 3962 includes titanium and silicon. The first metal silicide layer 3912 includes nickel, platinum, and silicon. In one embodiment, the first metal silicide layer 3912 further includes germanium. In one embodiment, the first metal silicide layer 3912 further includes titanium, e.g., incorporated into the first metal silicide layer 3912 during subsequent formation of the second metal silicide layer 3962 using the first metal layer 3914. In such an embodiment, the silicide layer already formed on the PMOS source or drain region is further modified by an annealing process for forming a silicide region on the NMOS source or drain region. This may result in the silicide layer on the PMOS source or drain region having a small percentage of all silicided metals. However, in other embodiments, the silicide layer already formed on the PMOS source or drain region is not changed or is substantially not changed by the annealing process for forming a silicide region on the NMOS source or drain region.

[0414] In one embodiment, the first 3908 and second 3910 semiconductor source or drain regions are first and second embedded semiconductor source or drain regions that include silicon and germanium. In one such embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are third and fourth embedded semiconductor source or drain regions that include silicon. In another embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are formed in fin 3954 and are not an embedded epitaxial region.

[0415] In an embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all include a U-shaped metal layer 3916 and a T-shaped metal layer 3918 over and on the entirety of the U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 includes titanium, and the T-shaped metal layer 3918 includes cobalt. In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all include a third metal layer 3920 over the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition. In a particular embodiment, the third metal layer 3920 and the U-shaped metal layer include titanium, and the T-shaped metal layer 3918 includes cobalt.

[0416] In another aspect, a trench contact structure for, e.g., a source or drain region is described. In an example, Figure 40A A cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device in accordance with an embodiment of the present disclosure is shown. Figure 40B A cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device in accordance with another embodiment of the present disclosure is shown.

[0417] Referring Figure 40A, the integrated circuit structure 4000 includes fins 4002, such as silicon fins. A gate dielectric layer 4004 is on the fins 4002. A gate electrode 4006 is on the gate dielectric layer 4004. In an embodiment, the gate electrode 4006 includes a conformal conductive layer 4008 and a conductive fill 4010. In an embodiment, a dielectric cap 4012 is on the gate electrode 4006 and on the gate dielectric layer 4004. The gate electrode has a first side 4006A and a second side 4006B opposite the first side 4006A. Dielectric spacers 4013 are along the sidewalls of the gate electrode 4006. In one embodiment, the gate dielectric layer 4004 is further between a first one of the dielectric spacers 4013 and the first side 4006A of the gate electrode 4006, and between a second one of the dielectric spacers 4013 and the second side 4006B of the gate electrode 4006, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fins 4002 and the gate dielectric layer 4004.

[0418] First 4014 and second 4016 semiconductor source or drain regions are adjacent to the first 4006A and second 4006B sides of the gate electrode 4006, respectively. In one embodiment, the first 4014 and second 4016 semiconductor source or drain regions are in the fins 4002, as shown. However, in another embodiment, the first 4014 and second 4016 semiconductor source or drain regions are embedded epitaxial regions formed in recesses of the fins 4002.

[0419] First 4018 and second 4020 trench contact structures are respectively on the first 4014 and second 4016 semiconductor source or drain regions adjacent to the first 4006A and second 4006B sides of the gate electrode 4006. The first 4018 and second 4020 trench contact structures both include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 on and over the entirety of the U-shaped metal layer 4022. In one embodiment, the U-shaped metal layer 4022 and the T-shaped metal layer 4024 have different compositions. In one such embodiment, the U-shaped metal layer 4022 includes titanium, and the T-shaped metal layer 4024 includes cobalt. In an embodiment, the first 4018 and second 4020 trench contact structures both include a third metal layer 4026 on the T-shaped metal layer 4024. In one such embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 have the same composition. In a particular embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 include titanium, and the T-shaped metal layer 4024 includes cobalt.

[0420] The first trench contact via 4028 is electrically connected to the first trench contact portion 4018. In a particular embodiment, the first trench contact via 4028 is on and coupled to the third metal layer 4026 of the first trench contact portion 4018. The first trench contact via 4028 further is on and in contact with a portion of one of the dielectric spacers 4013 and is on and in contact with a portion of the dielectric cap 4012. The second trench contact via 4030 is electrically connected to the second trench contact portion 4020. In a particular embodiment, the second trench contact via 4030 is on and coupled to the third metal layer 4026 of the second trench contact portion 4020. The second trench contact via 4030 further is on and in contact with a portion of another of the dielectric spacers 4013 and is on and in contact with another portion of the dielectric cap 4012.

[0421] In an embodiment, a metal silicide layer 4032 is directly between the first 4018 and second 4020 trench contact structures and the first 4014 and second 4016 semiconductor source or drain regions, respectively. In one embodiment, the metal silicide layer 4032 includes titanium and silicon. In a particular such embodiment, the first 4014 and second 4016 semiconductor source or drain regions are first and second N-type semiconductor source or drain regions.

[0422] Reference Figure 40B Referring, the integrated circuit structure 4050 includes fins 4052, such as silicon fins. A gate dielectric layer 4054 is over the fins 4052. A gate electrode 4056 is over the gate dielectric layer 4054. In an embodiment, the gate electrode 4056 includes a conformal conductive layer 4058 and a conductive fill 4060. In an embodiment, a dielectric cap 4062 is over the gate electrode 4056 and over the gate dielectric layer 4054. The gate electrode has a first side 4056A and a second side 4056B opposite the first side 4056A. Dielectric spacers 4063 are along the sidewalls of the gate electrode 4056. In one embodiment, the gate dielectric layer 4054 further is between a first one of the dielectric spacers 4063 and the first side 4056A of the gate electrode 4056 and between a second one of the dielectric spacers 4063 and the second side 4056B of the gate electrode 4056, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical oxide silicon or silicon dioxide layer, is between the fins 4052 and the gate dielectric layer 4054.

[0423] The first 4064 and second 4066 semiconductor source or drain regions are adjacent to the first 4056A and second 4056B sides of the gate electrode 4056, respectively. In one embodiment, the first 4064 and second 4066 semiconductor source or drain regions are embedded epitaxial regions formed in the recesses 4065 and 4067 of the fin 4052, as shown. However, in another embodiment, the first 4064 and second 4066 semiconductor source or drain regions are within the fin 4052.

[0424] The first 4068 and second 4070 trench contact structures are respectively over the first 4064 and second 4066 semiconductor source or drain regions adjacent to the first 4056A and second 4056B sides of the gate electrode 4056. The first 4068 and second 4070 trench contact structures each include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 over and on the entirety of the U-shaped metal layer 4072. In one embodiment, the U-shaped metal layer 4072 and the T-shaped metal layer 4074 have different compositions. In one such embodiment, the U-shaped metal layer 4072 includes titanium, and the T-shaped metal layer 4074 includes cobalt. In one embodiment, the first 4068 and second 4070 trench contact structures each further include a third metal layer 4076 over the T-shaped metal layer 4074. In one such embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 have the same composition. In a particular embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 include titanium, and the T-shaped metal layer 4074 includes cobalt.

[0425] The first trench contact via 4078 is electrically connected to the first trench contact portion 4068. In a particular embodiment, the first trench contact via 4078 is over and coupled to the third metal layer 4076 of the first trench contact portion 4068. The first trench contact via 4078 further contacts and is over a portion of one of the dielectric spacers 4063 and over and contacts a portion of the dielectric cap 4062. The second trench contact via 4080 is electrically connected to the second trench contact portion 4070. In a particular embodiment, the second trench contact via 4080 is over and coupled to the third metal layer 4076 of the second trench contact portion 4070. The second trench contact via 4080 further contacts and is over a portion of the other of the dielectric spacers 4063 and over and contacts another portion of the dielectric cap 4062.

[0426] In an embodiment, a metal silicide layer 4082 is directly between a first 4068 and a second 4070 trench contact structure and a first 4064 and a second 4066 semiconductor source or drain region, respectively. In one embodiment, the metal silicide layer 4082 includes nickel, platinum, and silicon. In a particular such embodiment, the first 4064 and second 4066 semiconductor source or drain regions are first and second P-type semiconductor source or drain regions. In one embodiment, the metal silicide layer 4082 further includes germanium. In one embodiment, the metal silicide layer 4082 further includes titanium.

[0427] One or more embodiments described herein relate to using metal chemical vapor deposition for wrap-around semiconductor contacts. Embodiments may be applicable to or include one or more of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

[0428] Particular embodiments may include using low temperature (e.g., below 500 degrees Celsius, or in the range of 400 - 500 degrees Celsius) chemical vapor deposition of a contact metal to fabricate a titanium or similar metal layer to provide a conformal source or drain contact. Implementing such a conformal source or drain contact may improve three-dimensional (3D) transistor complementary metal oxide semiconductor (CMOS) performance.

[0429] To provide context, sputtering may be used to deposit metal on a semiconductor contact layer. Sputtering is a line-of-sight process and may not be well-suited for 3D transistor fabrication. Known sputtering schemes have poor or incomplete metal-semiconductor junctions on the device contact surface, at an angle to the deposition incidence.

[0430] According to one or more embodiments of the present disclosure, a low temperature chemical vapor deposition process is implemented to fabricate a contact metal to provide conformal properties in three dimensions and to maximize the metal-semiconductor junction contact area. The resulting larger contact area may reduce the resistance of the junction. Embodiments may include depositing on a semiconductor surface having a non-flat morphology, where the morphology of a region refers to the surface shape and features themselves, and non-flat morphology includes non-flat surface shapes and features or portions of surface shapes and features, i.e., not a completely flat surface shape and features.

[0431] Embodiments described herein may include fabricating a wrap-around contact structure. In one such embodiment, the use of a pure metal conformally deposited onto a transistor source-drain contact by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. Such conformal deposition can be used to increase the available area of the metal-semiconductor contact and reduce resistance, thereby improving the performance of the transistor device. In an embodiment, the deposition temperature is low, resulting in minimizing the contact resistance per unit area.

[0432] It should be appreciated that integration schemes involving metal layer deposition processes as described herein can be used to fabricate various integrated circuit structures. According to an embodiment of the present disclosure, a method of fabricating an integrated circuit structure includes providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, the substrate having features thereon. The method further includes reacting titanium tetrachloride (TiCl 4 ) and hydrogen (H 2 ) to form a titanium (Ti) layer on the features of the substrate.

[0433] In an embodiment, the titanium layer has a total atomic composition including 98% or more titanium and 0.5 - 2% chlorine. In an alternative embodiment, a high-purity metal layer of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V) is fabricated using a similar process. In an embodiment, there is a relatively small film thickness variation. For example, in an embodiment, all coverages are greater than 50%, and the nominal value is 70% or greater (i.e., the thickness variation is 30% or less). In an embodiment, the thickness measured on silicon (Si) or silicon germanium (SiGe) is thicker than the thickness measured on other surfaces because Si or SiGe reacts during deposition and accelerates the uptake of Ti. In an embodiment, the film composition includes approximately 0.5% Cl (or less than 1%) as an impurity, and generally no other observed impurities. In an embodiment, the deposition process enables the metal to cover non-line-of-sight surfaces, such as surfaces hidden by the line-of-sight of sputter deposition. Embodiments described herein can be implemented to improve transistor device drive by reducing the external resistance of the current driven through the source and drain contacts.

[0434] According to an embodiment of the present disclosure, the features of the substrate are source or drain contact trenches exposing a semiconductor source or drain structure. The titanium layer (or other high-purity metal layer) is a conductive contact layer for the semiconductor source or drain structure. Exemplary embodiments of such implementations are described below in conjunction with Figure 41A 、 Figure 41B 、 Figure 42 、 Figures 43A - 43C and Figure 44 .

[0435] Figure 41AA cross-sectional view of a semiconductor device having a conductive contact on a source or drain region in accordance with an embodiment of the present disclosure is shown.

[0436] Referring Figure 41A , semiconductor structure 4100 includes a gate structure 4102 over a substrate 4104. The gate structure 4102 includes a gate dielectric layer 4102A, a work function layer 4102B, and a gate fill 4102C. Source region 4108 and drain region 4110 are on opposite sides of the gate structure 4102. A source or drain contact 4112 is electrically connected to the source region 4108 and the drain region 4110 and is spaced apart from the gate structure 4102 by one or both of an interlayer dielectric 4114 or a gate dielectric spacer 4116. The source region 4108 and the drain region 4110 are regions of the substrate 4104.

[0437] In an embodiment, the source or drain contact 4112 includes, for example, a high-purity metal layer 4112A as described above and a conductive trench fill material 4112B. In one embodiment, the high-purity metal layer 4112A has a total atomic composition that includes 98% or more titanium. In one such embodiment, the total atomic composition of the high-purity metal layer 4112A further includes 0.5 - 2% chlorine. In an embodiment, the high-purity metal layer 4112A has a thickness variation of 30% or less. In an embodiment, the conductive trench fill material 4112B is composed of a conductive material such as, but not limited to, Cu, Al, W, or an alloy thereof.

[0438] Figure 41B A cross-sectional view of another semiconductor device having a conductive contact on a raised source or drain region in accordance with an embodiment of the present disclosure is shown.

[0439] Referring Figure 41B , semiconductor structure 4150 includes a gate structure 4152 over a substrate 4154. The gate structure 4152 includes a gate dielectric layer 4152A, a work function layer 4152B, and a gate fill 4152C. Source region 4158 and drain region 4160 are on opposite sides of the gate structure 4152. A source or drain contact 4162 is electrically connected to the source region 4158 and the drain region 4160 and is spaced apart from the gate structure 4152 by one or both of an interlayer dielectric layer 4164 or a gate dielectric spacer 4166. The source region 4158 and the drain region 4160 are epitaxial or embedded material regions formed in an etched-away region of the substrate 4154. As shown, in an embodiment, the source region 4158 and the drain region 4160 are raised source and drain regions. In a specific such embodiment, the raised source and drain regions are raised silicon source and drain regions or raised silicon germanium source and drain regions.

[0440] In an embodiment, the source or drain contact 4162 includes, for example, a high-purity metal layer 4162A and a conductive trench fill material 4162B as described above. In one embodiment, the high-purity metal layer 4162A has a total atomic composition that includes 98% or more titanium. In one such embodiment, the total atomic composition of the high-purity metal layer 4162A further includes 0.5 - 2% chlorine. In an embodiment, the high-purity metal layer 4162A has a thickness variation of 30% or less. In an embodiment, the conductive trench fill material 4162B is composed of a conductive material such as, but not limited to, Cu, Al, W, or an alloy thereof.

[0441] Thus, in an embodiment, with reference Figure 41A and Figure 41B , the integrated circuit structure includes features having a surface (source or drain contact trenches exposing semiconductor source or drain structures). The high-purity metal layer 4112A or 4162A is on the surface of the source or drain contact trenches. It should be appreciated that the contact formation process can involve consuming the exposed silicon or germanium or silicon-germanium material of the source or drain region. Such consumption can degrade device performance. In contrast, according to embodiments of the present disclosure, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure is not corroded or consumed, or is substantially not corroded or consumed under the source or drain contact trenches. In one such embodiment, there is a lack of consumption or corrosion due to the low-temperature deposition of the high-purity metal contact layer.

[0442] Figure 42 A plan view of multiple gate lines over a semiconductor fin pair according to an embodiment of the present disclosure is shown.

[0443] With reference Figure 42 , multiple active gate lines 4204 are formed over multiple semiconductor fins 4200. The dummy gate lines 4206 are at the ends of the multiple semiconductor fins 4200. The spacing 4208 between the gate lines 4204 / 4206 is a location where a trench contact can be formed as a conductive contact to access a source or drain region (e.g., source or drain regions 4251, 4252, 4253, and 4254).

[0444] Figures 43A - 43C A cross-sectional view taken along the Figure 42 a-a' axis of various operations in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure is shown.

[0445] With reference Figure 43A, multiple active gate lines 4304 are formed over semiconductor fins 4302 formed over a substrate 4300. dummy gate lines 4306 are at the ends of the semiconductor fins 4302. a dielectric layer 4310 is between the active gate lines 4304, between the dummy gate lines 4306 and the active gate lines 4304, and outside the dummy gate lines 4306. embedded source or drain structures 4308 are in the semiconductor fins 4302 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304. the active gate lines 4304 include a gate dielectric layer 4312, a work function gate electrode portion 4314, a fill gate electrode portion 4316, and a dielectric capping layer 4318. dielectric spacers 4320 are arranged along the sidewalls of the active gate lines 4304 and the dummy gate lines 4306.

[0446] Reference Figure 43B , portions of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304 are removed to provide an opening 4330 at a location where a trench contact is to be formed. removing portions of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304 may cause corrosion of the embedded source or drain structures 4308 to provide a corroded embedded source or drain structure 4332 that may have an upper saddle-shaped profile, as Figure 43B shown.

[0447] Reference Figure 43C , trench contacts 4334 are formed in the openings 4330 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304. each of the trench contacts 4334 may include a metal contact layer 4336 and a conductive fill material 4338.

[0448] Figure 44 illustrates a cross-sectional view taken along the Figure 42 b-b' axis of an integrated circuit structure according to an embodiment of the present disclosure.

[0449] Reference Figure 44 , a fin 4402 is shown over a substrate 4404. a lower portion of the fin 4402 is surrounded by a trench isolation material 4404. an upper portion of the fin 4402 has been removed to enable growth of embedded source and drain structures 4406. trench contacts 4408 are formed in an opening in a dielectric layer 4410 that exposes the embedded source and drain structures 4406. the trench contacts include a metal contact layer 4412 and a conductive fill material 4414. it should be appreciated that, according to an embodiment, the metal contact layer 4412 extends to the top of the trench contacts 4408, asFigure 44 as shown. However, in another embodiment, the metal contact layer 4412 does not extend to the top of the trench contact 4408 and is recessed somewhat within the trench contact 4408, e.g., similar to Figure 43C the illustration of the metal contact layer 4436 in

[0450] Thus, with common reference to Figure 42 , Figures 43A - 43C and Figure 44 , in accordance with embodiments of the present disclosure, an integrated circuit structure includes semiconductor fins (4200, 4302, 4402) over a substrate (4300, 4400). The semiconductor fins (4200, 4302, 4402) have tops and sidewalls. Gate electrodes (4204, 4304) are over the tops and adjacent to sidewalls of a portion of the semiconductor fins (4200, 4302, 4402). The gate electrodes (4204, 4304) define channel regions in the semiconductor fins (4200, 4302, 4402). A first semiconductor source or drain structure (4251, 4332, 4406) is at a first end of the channel region on a first side of the gate electrodes (4204, 4304), and the first semiconductor source or drain structure (4251, 4332, 4406) has a non-flat topography. A second semiconductor source or drain structure (4252, 4332, 4406) is at a second end of the channel region on a second side of the gate electrodes (4204, 4304), the second end being opposite the first end, and the second side being opposite the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non-flat topography. Metal contact material (4336, 4412) is directly over the first semiconductor source or drain structure (4251, 4332, 4406) and directly over the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact material (4336, 4412) is conformal to the non-flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and conformal to the non-flat topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0451] In an embodiment, the metal contact material (4336, 4412) has a total atomic composition including 95% or more of a single metal species. In one such embodiment, the metal contact material (4336, 4412) has a total atomic composition including 98% or more of titanium. In a specific such embodiment, the total atomic composition of the metal contact material (4336, 4412) further includes 0.5 - 2% of chlorine. In an embodiment, the metal contact material (4336, 4412) has a thickness variation of 30% or less along the non - flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the non - flat topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0452] In an embodiment, the non - flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non - flat topography of the second semiconductor source or drain structure (4252, 4332, 4406) both include a raised central portion and a lower side portion, for example, as shown in Figure 44 In an embodiment, the non - flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non - flat topography of the second semiconductor source or drain structure (4252, 4332, 4406) both include a saddle - shaped portion, for example, as shown in Figure 43C shown in

[0453] In an embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) include silicon. In an embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) further include germanium, for example, in the form of silicon germanium.

[0454] In an embodiment, the metal contact material (4336, 4412) directly on the first semiconductor source or drain structure (4251, 4332, 4406) further extends along the sidewalls of the trenches in the dielectric layer (4320, 4410) above the first semiconductor source or drain structure (4251, 4332, 4406), and the trenches expose a portion of the first semiconductor source or drain structure (4251, 4332, 4406). In one such embodiment, the thickness of the metal contact material (4336) along the sidewalls of the trenches thins from the position of the metal contact material (4336A at 4332 of the first semiconductor source or drain structure) to a position (4336B) above the first semiconductor source or drain structure (4332). Figure 43CAn example thereof is shown. In an embodiment, the conductive filler material (4338, 4414) is on the metal contact material (4336, 4412) within the trench, as Figure 43C and Figure 44 shown.

[0455] In an embodiment, the integrated circuit structure further includes a second semiconductor fin having a top and sidewalls (e.g., Figure 42 upper fins 4200, 4302, 4402). Gate electrodes (4204, 4304) are also over the top of a portion of the second semiconductor fin and adjacent to the sidewalls of the portion, and the gate electrodes define a channel region in the second semiconductor fin. A third semiconductor source or drain structure (4253, 4332, 4406) is at a first end of the channel region of the second semiconductor fin on a first side of the gate electrodes (4204, 4304), and the third semiconductor source or drain structure has a non-planar profile. A fourth semiconductor source or drain structure (4254, 4332, 4406) is at a second end of the channel region of the second semiconductor fin on a second side of the gate electrodes (4204, 4304), the second end being opposite the first end, and the fourth semiconductor source or drain structure (4254, 4332, 4406) has a non-planar profile. Metal contact material (4336, 4412) is directly on the third semiconductor source or drain structure (4253, 4332, 4406) and directly on the fourth semiconductor source or drain structure (4254, 4332, 4406), and the metal contact material (4336, 4412) is conformal with the non-planar profile of the third semiconductor source or drain structure (4253, 4332, 4406) and conformal with the non-planar profile of the fourth semiconductor source or drain structure (4254, 4332, 4406). In an embodiment, the metal contact material (4336, 4412) is continuous between the first semiconductor source or drain structure (4251, 4332, left side 4406) and the third semiconductor source or drain structure (4253, 4332, right side 4406), and is continuous between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0456] In another aspect, a hard mask material can be used to preserve (prevent etching), and can be retained at a location where the conductive trench contact over the dielectric material in the trench line location is interrupted, such as at the contact plug location. For example, Figure 45A and Figure 45B respectively show a plan view and a corresponding cross-sectional view of an integrated circuit structure including a trench contact plug having a hard mask material thereon according to an embodiment of the present disclosure.

[0457] Refer toFigure 45A and Figure 45B In an embodiment, the integrated circuit structure 4500 includes fin 4502A, such as a silicon fin. A plurality of gate structures 4506 are over the fin 4502A. Individual gate structures in the gate structure 4506 are along a direction 4508 orthogonal to the fin 4502A and have a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is over the fin 4502A and directly between the dielectric sidewall spacers 4510 of a first pair 4506A / 4506B of the gate structures 4506. A contact plug 4514B is over the fin 4502A and directly between the dielectric sidewall spacers 4510 of a second pair 4506B / 4506C of the gate structures 4506. The contact plug 4514B includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0458] In an embodiment, the lower dielectric material 4516 of the contact plug 4516B includes silicon and oxygen, such as silicon oxide or silicon dioxide material. The upper hard mask material 4518 of the contact plug 4516B includes silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride material.

[0459] In an embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514B, as shown.

[0460] In an embodiment, individual gate structures in the plurality of gate structures 4506 include a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of individual gate structures in the plurality of gate structures 4506 has an upper surface coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514B, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical oxide silicon or silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526.

[0461] Referring again to Figure 45A and Figure 45B, in an embodiment, the integrated circuit structure 4500 includes a plurality of fins 4502, such as a plurality of silicon fins. Individual fins among the plurality of fins 4502 extend along a first direction 4504. A plurality of gate structures 4506 are over the plurality of fins 4502. Individual gate structures among the plurality of gate structures 4506 extend along a second direction 4508 that is orthogonal to the first direction 4504. Individual gate structures among the plurality of gate structures 4506 have a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is over a first fin 4502A among the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of a pair of gate structures 4506. A contact plug 4514A is over a second fin 4502B among the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of a pair of gate structures 4506. Similar to the cross-sectional view of contact plug 4514B, contact plug 4514A includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0462] In an embodiment, the lower dielectric material 4516 of contact plug 4516A includes silicon and oxygen, such as silicon oxide or silicon dioxide material. The upper hard mask material 4518 of contact plug 4516A includes silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride material.

[0463] In an embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of contact plug 4514A or 4514B, as shown.

[0464] In an embodiment, individual gate structures among the plurality of gate structures 4506 include a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of individual gate structures among the plurality of gate structures 4506 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of contact plug 4514A or 4514B, as shown. In an embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526.

[0465] One or more embodiments of the present disclosure relate to a gate-aligned contact process. Such a process can be implemented to form contact structures for semiconductor structure fabrication (e.g., for integrated circuit fabrication). In an embodiment, a contact pattern is formed to be aligned with an existing gate pattern. In contrast, other approaches typically involve additional lithography processes that utilize strict registration of a lithographic contact pattern with an existing gate pattern in combination with selective contact etch. For example, another process can include patterning of a multi-(gate) grid, where the contacts and contact plugs are patterned separately.

[0466] According to one or more embodiments described herein, a contact formation method involves forming a contact pattern that is substantially perfectly aligned to an existing gate pattern while eliminating the use of lithography operations with a super-strict registration budget. In one such embodiment, this approach enables the use of a wet etch that is inherently highly selective (e.g., relative to dry or plasma etch) to create contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with contact plug lithography operations. In one such embodiment, this approach enables the elimination of the need for lithography operations (such as those used in other approaches) that are otherwise critical for creating the contact pattern. In an embodiment, the trench contact grid is not patterned separately, but rather is formed between multiple (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before gate grid cutting.

[0467] Figures 46A - 46D A cross-sectional view is shown that depicts various operations in a method of manufacturing an integrated circuit structure including a trench contact plug having a hard mask material thereon, in accordance with an embodiment of the present disclosure.

[0468] Reference Figure 46A , a method of manufacturing an integrated circuit structure includes forming a plurality of fins, with individual fins 4602 among the plurality of fins extending along a first direction 4604. Individual fins 4602 among the plurality of fins can include diffusion regions 4606. A plurality of gate structures 4608 are formed over the plurality of fins. Individual gate structures among the plurality of gate structures 4508 extend along a second direction 4610 that is orthogonal to the first direction 4604 (e.g., the direction 4610 is into and out of the page). A sacrificial material structure 4612 is formed between a first pair of the gate structures 4608. A contact plug 4614 is between a second pair of the gate structures 4608. The contact plug includes a lower dielectric material 4616. A hard mask material 4618 is on the lower dielectric material 4616.

[0469] In an embodiment, the gate structure 4608 includes a sacrificial or dummy gate stack and a dielectric spacer 4609. The sacrificial or dummy gate stack may be composed of polysilicon or silicon nitride pillars or some other sacrificial material that may be referred to as dummy gate material.

[0470] Referring Figure 46B , from Figure 46A the structure, the sacrificial material structure 4612 is removed to form an opening 4620 between the first pair in the gate structure 4608.

[0471] Referring Figure 46C , a trench contact structure 4622 is formed in the opening 4620 between the first pair in the gate structure 4608. Further, in an embodiment, as part of forming the trench contact structure 4622, Figure 46A and Figure 46B the hard mask 4618 is planarized. The finally completed contact plug 4614’ includes an upper hard mask material 4616 and an upper hard mask material 4624 formed by the hard mask material 4618.

[0472] In an embodiment, the lower dielectric material 4616 of each of the contact plugs 4614’ includes silicon and oxygen, and the upper hard mask material 4624 of each of the contact plugs 4614’ includes silicon and nitrogen. In an embodiment, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface coplanar with the upper surface of the upper hard mask material 4624 of the contact plug 4614’.

[0473] Referring Figure 46D , in a replacement gate process scenario, the sacrificial or dummy gate stack of the gate structure 4608 is replaced. In such a scenario, the dummy gate material, such as polysilicon or silicon nitride pillar material, is removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, contrary to what is performed from earlier processing.

[0474] Thus, the permanent gate structure 4630 includes a permanent gate dielectric layer 4632 and a permanent gate electrode layer or stack 4634. Further, in an embodiment, for example, the top portion of the permanent gate structure 4630 is removed by an etching process and replaced with a dielectric cap 4636. In an embodiment, the dielectric cap 4636 of the individual permanent gate structures in the permanent gate structure 4630 has an upper surface coplanar with the upper surface of the upper hard mask material 4624 of the contact plug 4614’.

[0475] Referring againFigures 46A - 46D , in an embodiment, the replacement gate process is performed after forming the trench contact structure 4622, as shown. However, according to other embodiments, the replacement gate process is performed before forming the trench contact structure 4622.

[0476] In another aspect, a contact over active gate (COAG) structure and process are described. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed over an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure relate to a method of manufacturing a semiconductor structure or device having one or more gate contact structures formed over an active portion of a gate electrode of the semiconductor structure or device. The manner described herein can be used to reduce the standard cell area by enabling the formation of gate contact portions over the active gate region. In one or more embodiments, the gate contact structure fabricated to contact the gate electrode is a self-aligned via structure.

[0477] In technologies with slightly relaxed space and layout constraints compared to current-generation space and layout constraints, contacts to the gate structure can be fabricated by forming contacts to a portion of the gate electrode disposed over an isolation region. As an example, Figure 47A A plan view of a semiconductor device having a gate contact portion disposed over a non-active portion of a gate electrode is shown.

[0478] Reference Figure 47A , the semiconductor structure or device 4700A includes a diffusion or active region 4704 disposed in a substrate 4702 and within an isolation region 4706. One or more gate lines (also referred to as multi-lines), such as gate lines 4708A, 4708B, and 4708C, are disposed over the diffusion or active region 4704 and over a portion of the isolation region 4706. Source or drain contact portions (also referred to as trench contact portions), such as contact portions 4710A and 4710B, are disposed over the source and drain regions of the semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contacts to the trench contact portions 4710A and 4710B, respectively. A separate gate contact portion 4714 and an overlying gate contact via 4716 provide contact to the gate line 4708B. Compared to the source or drain trench contact portions 4710A or 4710B, from a plan view perspective, the gate contact portion 4714 is disposed over the isolation region 4706 but not over the diffusion or active region 4704. Additionally, neither the gate contact portion 4714 nor the gate contact via 4716 is disposed between the source or drain trench contact portions 4710A and 4710B.

[0479] Figure 47B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over a non-active portion of a gate electrode is shown. Referring to Figure 47B , semiconductor structure or device 4700B (e.g., a non-planar version of device 4700A of Figure 47A ) includes a non-planar diffusion or active region 4704C (e.g., a fin structure) formed from a substrate 4702 and within isolation regions 4706. A gate line 4708B is disposed over the non-planar diffusion or active region 4704B and over a portion of the isolation region 4706. As shown, gate line 4708B includes a gate electrode 4750 and a gate dielectric layer 4752, along with a dielectric capping layer 4754. Also visible from this perspective are gate contact 4714 and overlying gate contact via 4716, along with overlying metal interconnect 4760, all disposed within an inter-level dielectric stack or layer 4770. As seen from Figure 47B 's perspective, gate contact 4714 is disposed over isolation region 4706 but not over non-planar diffusion or active region 4704B.

[0480] Referring again to Figure 47A and Figure 47B , the arrangements of semiconductor structures or devices 4700A and 4700B place the gate contact over the isolation region, respectively. Such arrangements waste layout space. However, placing the gate contact over the active region would require a very strict registration budget, or the gate size would have to be increased to provide sufficient space for the gate contact to land. Additionally, historically, gate contacts over diffusion regions have been avoided because of the risk of drilling through other gate materials (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described herein solve the above problems by providing a viable way to fabricate a contact structure for making contact with a portion of a gate electrode formed over a diffusion or active region, and the resulting structure.

[0481] As an example, Figure 48A a plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode in accordance with an embodiment of the present disclosure is shown. Referring to Figure 48A, the semiconductor structure or device 4800A includes a diffusion or active region 4804 disposed in a substrate 4802 and within an isolation region 4806. One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed over the diffusion or active region 4804 and over a portion of the isolation region 4806. Source or drain contact portions, such as contact portions 4810A and 4810B, are disposed over the source and drain regions of the semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contact with the trench contact portions 4810A and 4810B, respectively. A gate contact via 4816, without an intervening separate gate contact layer, provides contact with the gate line 4808B. Compared with Figure 47A , from a top - down view, the gate contact portion 4816 is disposed over the diffusion region or active region 4804 and between the source or drain contact portions 4810A and 4810B.

[0482] Figure 48B A cross - sectional view of a non - planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an embodiment of the present disclosure, is shown. Referring to Figure 48B , the semiconductor structure or device 4800B (e.g., a non - planar version of the device 4800A of Figure 48A ) includes a non - planar diffusion or active region 4804B (e.g., a fin structure) formed from the substrate 4802 and within the isolation region 4806. A gate line 4808B is disposed over the non - planar diffusion or active region 4804B and over a portion of the isolation region 4806. As shown, the gate line 4808B includes a gate electrode 4850, a gate dielectric layer 4852, along with a dielectric capping layer 4854. Also visible from this perspective is the gate contact via 4816, along with an overlying metal interconnect 4860, both disposed within an inter - layer dielectric stack or layer 4870. Also visible from the perspective of Figure 48B is that the gate contact via 4816 is disposed over the non - planar diffusion or active region 4804B.

[0483] Thus, referring again to Figure 48A and Figure 48B , in an embodiment, the trench contact vias 4812A, 4812B, and the gate contact via 4816 are formed in the same layer and are substantially coplanar. Compared with Figure 47A and FIG. 47B, the contact to the gate line would otherwise include an additional gate contact layer, e.g., which could extend perpendicular to the corresponding gate line. However, in combination with Figure 48A and Figure 48BIn the described structure, the fabrication of structures 4800A and 4800B enables the contact portions to land directly from the metal interconnect layer on the active gate portion without shorting to adjacent source-drain regions. In an embodiment, such an arrangement provides a large area reduction in the circuit layout by eliminating the need to extend the transistor gate over the isolation region to form reliable contact portions. As used throughout this document, in an embodiment, the reference to the active portion of the gate refers to that portion of the gate line or structure that is disposed (from a planar view perspective) over the active or diffused region of the underlying substrate. In an embodiment, the reference to the passive portion of the gate refers to that portion of the gate line or structure that is disposed (from a planar view perspective) over the isolation region of the underlying substrate.

[0484] In an embodiment, the semiconductor structure or device 4800 is a non-planar device, such as but not limited to a finFET or a triple-gate device. In such an embodiment, the corresponding semiconductor channel region is constituted by or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 4808A - 4808C surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, such as in a gate-all-around device, at least the channel region is fabricated as a discrete three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 4808A - 4808C completely surrounds the channel region.

[0485] More generally, one or more embodiments relate to a manner for directly landing a gate contact via on an active transistor gate and the structure formed thereby. Such a manner can eliminate the need to extend the gate line over the isolation region for contact purposes. Such a manner can also eliminate the need for a separate gate contact (GCN) layer to conduct signals from the gate line or structure. In an embodiment, the above features are eliminated by recessing the contact metal in the trench contact (TCN) and introducing additional dielectric material (e.g., TILA) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer having etch characteristics different from the gate dielectric material cap layer that has been used for trench contact alignment in a gate alignment contact process (GAP) treatment scheme (e.g., GILA).

[0486] As an exemplary fabrication scheme, Figures 49A - 49D FIG. shows cross-sectional views of various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over the active portion of a gate, in accordance with an embodiment of the present disclosure.

[0487] Reference Figure 49A, a semiconductor structure 4900 is provided after the formation of the trench contact portion (TCN). It should be recognized that the specific arrangement of using the structure 4900 is for illustrative purposes only, and various possible layouts may benefit from the embodiments of the disclosure described herein. The semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A - 4908E disposed above the substrate 4902. The gate stack structure may include a gate dielectric layer and a gate electrode. For example, trench contacts (such as trench contacts 4910A - 4910C) leading to diffusion regions of the substrate 4902 are also included in the structure 4900 and are spaced apart from the gate stack structures 4908A - 4908E by dielectric spacers 4920. An insulating capping layer 4922 may be disposed on the gate stack structures 4908A - 4908E (e.g., GILA), as also Figure 49A shown. As also Figure 49A shown, a contact barrier region or "contact plug" (such as region 4923 made of an interlayer dielectric material) may be included in the region where contact formation is to be blocked.

[0488] In an embodiment, providing the structure 4900 involves forming a contact pattern that is substantially perfectly aligned to an existing gate pattern while eliminating the use of lithography operations with a super - strict registration budget. In one such embodiment, this approach enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching) to create contact openings. In an embodiment, the contact pattern is formed by leveraging the existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, this approach enables the elimination of the need for lithography operations (as used in other approaches) that are otherwise critical for generating the contact pattern. In an embodiment, the trench contact grid is not patterned separately but is formed between multiple (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid patterning but before the gate grid cutting.

[0489] In addition, the gate stack structures 4908A - 4908E can be fabricated through a replacement gate process. In such a scenario, dummy gate materials such as polysilicon or silicon nitride pillar materials can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, contrary to performing from earlier processing. In an embodiment, the dummy gate is removed through a dry etching or wet etching process. In one embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a dry etching process including SF 6 and in another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a water - based NH4 It is removed by a wet etching process using OH or tetraethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and removed by wet etching including aqueous phosphoric acid.

[0490] In an embodiment, one or more of the methods described herein substantially contemplate a dummy gate and replacement gate process in combination with a dummy and replacement contact process to achieve structure 4900. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature annealing of at least a portion of the permanent gate stack. For example, in a specific such embodiment, for example, after forming the gate dielectric layer, annealing of at least a portion of the permanent gate structure is performed at a temperature above about 600 degrees Celsius. The annealing is performed before forming the permanent contact.

[0491] Reference Figure 49B , the trench contacts 4910A - 4910C of structure 4900 are recessed into the spacer 4920 to provide recessed trench contacts 4911A - 4911C having a height lower than the top surfaces of the spacer 4920 and the insulating cap layer 4922. Then an insulating cap layer 4924 is formed over the recessed trench contacts 4911A - 4911C (e.g., TILA). According to an embodiment of the present disclosure, the insulating cap layer 4924 over the recessed trench contacts 4911A - 4911C is made of a material having etching characteristics different from those of the insulating cap layer 4922 over the gate stack structures 4908A - 4908E. As will be seen in subsequent processing operations, such a difference can be utilized to selectively etch one of 4922 / 4924 with respect to the other.

[0492] The trench contacts 4910A - 4910C can be recessed by a process selective to the materials of the spacer 4920 and the insulating cap layer 4922. For example, in one embodiment, the trench contacts 4910A - 4910C are recessed by an etching process such as a wet etching process or a dry etching process. The insulating cap layer 4924 can be formed by a process suitable for providing a conformal and sealing layer over the exposed portions of the trench contacts 4910A - 4910C. For example, in one embodiment, the insulating cap layer 4924 is formed as a conformal layer over the entire structure by chemical vapor deposition (CVD) process. Then, for example, the conformal layer is planarized by chemical mechanical polishing (CMP) to provide the insulating cap layer 4924 material only over the trench contacts 4910A - 4910C and to re - expose the spacer 4920 and the insulating cap layer 4922.

[0493] Regarding the appropriate material combinations for the insulating capping layers 4922 / 4924, in one embodiment, one of the 4922 / 4924 pair is composed of silicon oxide, while the other is composed of silicon nitride. In another embodiment, one of the 4922 / 4924 pair is composed of silicon oxide, while the other is composed of carbon-doped silicon nitride. In another embodiment, one of the 4922 / 4924 pair is composed of silicon oxide, while the other is composed of silicon carbide. In another embodiment, one of the 4922 / 4924 pair is composed of silicon nitride, while the other is composed of carbon-doped silicon nitride. In another embodiment, one of the 4922 / 4924 pair is composed of silicon nitride, while the other is composed of silicon carbide. In another embodiment, one of the 4922 / 4924 pair is composed of carbon-doped silicon nitride, while the other is composed of silicon carbide.

[0494] Reference Figure 49C , an interlayer dielectric (ILD) 4930 and a hard mask 4932 stack are formed and patterned to provide, for example, a metal(0) trench 4934 patterned above the structure in Figure 49B .

[0495] The interlayer dielectric (ILD) 4930 can be composed of a material suitable for electrically isolating the metal features ultimately formed therein while maintaining a robust structure between front-end and back-end processing. Additionally, in embodiments, the composition of the ILD 4930 is selected to be consistent with the via etch selectivity for the trench contact dielectric capping layer patterning, as described in more detail below in connection with Figure 49D . In one embodiment, the ILD 4930 is composed of a single or several layers of silicon oxide or a single or several layers of carbon-doped oxide (CDO) material. However, in other embodiments, the ILD 4930 has a bilayer composition, with its top composed of a material different from the bottom portion of the lower layer of the ILD 4930. The hard mask layer 4932 can be composed of a material suitable for serving as a subsequent sacrificial layer. For example, in one embodiment, the hard mask layer 4932 is substantially composed of carbon, for example, as a crosslinked organic polymer layer. In other embodiments, a silicon nitride or carbon-doped silicon nitride layer is used as the hard mask 4932. The interlayer dielectric (ILD) 4930 and the hard mask 4932 stack can be patterned by photolithography and etching processes.

[0496] Reference Figure 49D , via openings 4936 (e.g., VCT) are formed in the interlayer dielectric (ILD) 4930, extending from the metal(0) trench 4934 to one or more of the recessed trench contacts 4911A - 4911C. For example, in Figure 49DTherein, via openings are formed to expose the recessed trench contact portions 4911A and 4911C. Forming the via openings 4936 includes etching both the interlayer dielectric (ILD) 4930 and corresponding portions of the insulating capping layer 4924. In one such embodiment, a portion of the insulating capping layer 4922 (e.g., the portion of the insulating capping layer 4922 that is over the gate stack structures 4908B and 4908E) is exposed during patterning of the interlayer dielectric (ILD) 493. In this embodiment, the insulating capping layer 4924 is etched to form the via openings 4936 selectively with respect to the insulating capping layer 4922 (i.e., without significantly etching or affecting the insulating capping layer 4922).

[0497] In one embodiment, the via opening pattern is ultimately transferred to the insulating capping layer 4924 (i.e., the trench contact capping layer) by an etching process without etching the insulating capping layer 4922 (i.e., the gate insulating capping layer). The insulating capping layer 4924 (TILA) can be composed of any material or combination of materials including: silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, amorphous silicon, various metal oxides and silicides, including zirconium oxide, hafnium oxide, lanthanum oxide, or combinations thereof. Any of the following techniques can be used to deposit the layer: CVD, ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD. The corresponding plasma dry etching is developed as a combination of chemical and physical sputtering mechanisms. Uniform polymer deposition can be used to control the material removal rate, etch profile, and film selectivity. Dry etching typically utilizes a mixture of gases including: NF 3 、CHF 3 、C 4 F 8 、HBr and O 2 ,with typical pressures in the range of 30 - 100 mTorr and a plasma bias of 50 - 1000 watts. The dry etching can be designed to achieve a significant etch selectivity between the capping layers 4924 (TILA) and 4922 (GILA) to minimize the loss of 4922 (GILA) during the dry etching of 4929 (TILA), thereby forming a contact to the source / drain regions of the transistor.

[0498] Referring again to Figure 49D ,it is recognized that a similar approach can be implemented to fabricate a via opening pattern that is ultimately transferred to the insulating capping layer 4922 (i.e., the trench contact capping layer) by an etching process without etching the insulating capping layer 4924 (i.e., the gate insulating capping layer).

[0499] To further illustrate the concept of the contact over active gate (COAG) technology,Figure 50 A plan view and corresponding cross-sectional view of an integrated circuit structure having trench contacts including an overlying insulating capping layer are shown in accordance with an embodiment of the present disclosure.

[0500] Referring Figure 50 , integrated circuit structure 5000 includes a gate line 5004 over a semiconductor substrate or fin 5002 such as a silicon fin. Gate line 5004 includes a gate stack 5005 (e.g., including a gate dielectric layer or stack and a gate electrode on the gate dielectric layer or stack) and a gate insulating capping layer 5006 on gate stack 5005. Dielectric spacers 5008 are along the sidewalls of gate stack 5005 and, in an embodiment, along the sidewalls of gate insulating capping layer 5006, as shown.

[0501] Trench contacts 5010 are adjacent to the sidewalls of gate line 5004 with dielectric spacers 5008 therebetween. Individual trench contacts in trench contacts 5010 include a conductive contact structure 5011 and a trench contact insulating capping layer 5012 on conductive contact structure 5011.

[0502] Referring again Figure 50 , a gate contact via 5014 is formed in an opening in gate insulating capping layer 5006 and electrically contacts gate stack 5005. In an embodiment, gate contact via 5014 electrically contacts gate stack 5005 at a position above semiconductor substrate or fin 5002 and laterally between trench contacts 5010, as shown. In one such embodiment, trench contact insulating capping layer 5012 on conductive contact structure 5011 prevents gate contact via 5014 from shorting the gate to the source or shorting the gate to the drain.

[0503] Referring again Figure 50 , a trench contact via 5016 is formed in an opening in trench contact insulating capping layer 5012 and electrically contacts a corresponding conductive contact structure 5011. In an embodiment, trench contact via 5016 electrically contacts a corresponding conductive contact structure 5011 at a position above semiconductor substrate or fin 5002 and laterally adjacent to gate stack 5005 of gate line 5004, as shown. In one such embodiment, gate insulating capping layer 5006 on gate stack 5005 prevents trench contact via 5016 from shorting the source to the gate or shorting the drain to the gate.

[0504] It should be appreciated that different structural relationships between the insulating gate capping layer and the insulating trench contact capping layer can be fabricated. As an example, Figures 51A - 51FA cross-sectional view of various integrated circuit structures in accordance with embodiments of the present disclosure is shown, each integrated circuit structure having a trench contact including an overlying insulating capping layer and having a gate stack including an overlying insulating capping layer.

[0505] Referring Figure 51A , Figure 51B and Figure 51C , integrated circuit structures 5100A, 5100B, and 5100C each include a fin 5102, such as a silicon fin. Although shown as a cross-sectional view, it is to be appreciated that the fin 5102 has a top 5102A and sidewalls (into and out of the page of the perspective view shown). First 5104 and second 5106 gate dielectric layers are over the top 5102A of the fin 5102 and laterally adjacent to the sidewalls of the fin 5102. First 5108 and second 5110 gate electrodes are respectively over the first 5104 and second 5106 gate dielectric layers, over the top 5102A of the fin 5102 and laterally adjacent to the sidewalls of the fin 5102. The first 5108 and second 5110 gate electrodes each include a conformal conductive layer 5109A (such as a work function setting layer), and a conductive fill material 5109B over the conformal conductive layer 5109A. The first 5108 and second 5110 gate electrodes each have a first side 5112 and a second side 5114 opposite the first side 5112. The first 5108 and second 5110 gate electrodes also each have an insulating cap 5116 having a top surface 5118.

[0506] A first dielectric spacer 5120 is adjacent to the first side 5112 of the first gate electrode 5108. A second dielectric spacer 5122 is adjacent to the second side 5114 of the second gate electrode 5110. A semiconductor source or drain region 5124 is adjacent to the first 5120 and second 5122 dielectric spacers. A trench contact structure 5126 is over the semiconductor source or drain region 5124 adjacent to the first 5120 and second 5122 dielectric spacers.

[0507] The trench contact structure 5126 includes an insulating cap 5128 on a conductive structure 5130. The insulating cap 5128 of the trench contact structure 5126 has a top surface 5129 that is generally coplanar with the top surface 5118 of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes. In an embodiment, the insulating cap 5128 of the trench contact structure 5126 extends laterally into recesses 5132 in the first 5120 and second 5122 dielectric spacers. In such an embodiment, the insulating cap 5128 of the trench contact structure 5126 is suspended above the conductive structure 5130 of the trench contact structure 5126. However, in other embodiments, the insulating cap 5128 of the trench contact structure 5126 does not extend laterally into the recesses 5132 in the first 5120 and second 5122 dielectric spacers and is thus not suspended above the conductive structure 5130 of the trench contact structure 5126.

[0508] It should be appreciated that the conductive structure 5130 of the trench contact structure 5126 may not be rectangular, as Figures 51A - 51C shown. For example, the conductive structure 5130 of the trench contact structure 5126 may have a cross-sectional geometry similar to or the same as the geometry shown for the conductive structure 5130A in the projection of Figure 51A .

[0509] In an embodiment, the insulating cap 5128 of the trench contact structure 5126 has a composition different from that of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes. In one such embodiment, the insulating cap 5128 of the trench contact structure 5126 includes a carbide material, such as silicon carbide material. The insulating caps 5116 of the first 5108 and second 5110 gate electrodes include a nitride material, such as silicon nitride material.

[0510] In an embodiment, both of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes have a bottom surface 5117A that is lower than the bottom surface 5128A of the insulating cap 5128 of the trench contact structure 5126, as Figure 51A shown. In another embodiment, both of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes have a bottom surface 5117A that is generally coplanar with the bottom surface 5128B of the insulating cap 5128 of the trench contact structure 5126, as Figure 51B shown. In another embodiment, both of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes have a bottom surface 5117C that is higher than the bottom surface 5128C of the insulating cap 5128 of the trench contact structure 5126, as Figure 51C shown.

[0511] In an embodiment, the conductive structure 5130 of the trench contact structure 5128 includes a U-shaped metal layer 5134, a T-shaped metal layer 5136 over and on the entirety of the U-shaped metal layer 5134, and a third metal layer 5138 on the T-shaped metal layer 5136. The insulating cap 5128 of the trench contact structure 5126 is on the third metal layer 5138. In one such embodiment, the third metal layer 5138 and the U-shaped metal layer 5134 include titanium, and the T-shaped metal layer 5136 includes cobalt. In a particular such embodiment, the T-shaped metal layer 5136 further includes carbon.

[0512] In an embodiment, the metal silicide layer 5140 is directly between the conductive structure 5130 of the trench contact structure 5126 and the semiconductor source or drain region 5124. In one such embodiment, the metal silicide layer 5140 includes titanium and silicon. In a particular such embodiment, the semiconductor source or drain region 5124 is an N-type semiconductor source or drain region. In another embodiment, the metal silicide layer 5140 includes nickel, platinum, and silicon. In a particular such embodiment, the semiconductor source or drain region 5124 is a P-type semiconductor source or drain region. In another particular such embodiment, the metal silicide layer further includes germanium.

[0513] In an embodiment, referring to Figure 51D , the conductive via 5150 is on a portion of the first gate electrode 5108 that is above the top 5102A of the fin 5102 and is electrically connected to that portion. The conductive via 5150 is in the opening 5152 in the insulating cap 5116 of the first gate electrode 5108. In one such embodiment, the conductive via 5150 is on a portion of the insulating cap 5128 of the trench contact structure 5126 but is not electrically connected to the conductive structure 5130 of the trench contact structure 5126. In a particular such embodiment, the conductive via 5150 is in the corroded portion 5154 of the insulating cap 5128 of the trench contact structure 5126.

[0514] In an embodiment, referring to Figure 51E , the conductive via 5160 is on a portion of the trench contact structure 5126 and is electrically connected to that portion. The conductive via is in the opening 5162 in the insulating cap 5128 of the trench contact structure 5126. In one such embodiment, the conductive via 5160 is on a portion of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes but is not electrically connected to the first 5108 and second 5110 gate electrodes. In a particular such embodiment, the conductive via 5160 is in the corroded portion 5164 of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes.

[0515] Referring again to Figure 51E, in an embodiment, the conductive via 5160 is a second conductive via having the same structure as the Figure 51D conductive via 5150. In one such embodiment, such a second conductive via 5160 is isolated from the conductive via 5150. In another such embodiment, such a second conductive via 5160 is fused with the conductive via 5150 to form an electrical shorting contact 5170, as Figure 51F shown.

[0516] The methods and structures described herein can enable the formation of other structures or devices that are impossible or difficult to fabricate using other methods. In a first example, Figure 52A a plan view of another semiconductor device having a gate contact via disposed over an active portion of a gate is shown in accordance with another embodiment of the present disclosure. Referring to Figure 52A , the semiconductor structure or device 5200 includes a plurality of gate structures 5208A - 5208C that intersect with a plurality of trench contact portions 5210A and 5210B (these features are disposed above the active region of the substrate, not shown). A gate contact via 5280 is formed on the active portion of the gate structure 5208B. The gate contact via 5280 is also disposed on the active portion of the gate structure 5208C, coupling the gate structures 5208B and 5208C. It should be appreciated that an intervening trench contact portion 5210B can be isolated from the contact 5280 using a trench contact isolation capping layer (e.g., TILA). Figure 52A The contact configuration of

[0517] can provide an easier way to bundle adjacent gate lines in a layout without routing the bundled lines through an upper layer of metallization, thus enabling a smaller cell area or a less complex wiring scheme or both. Figure 52B In a second example, Figure 52B , a plan view of another semiconductor device having a trench contact via coupling a pair of trench contact portions is shown in accordance with another embodiment of the present disclosure. Referring to Figure 52BThe contact portion structure can provide an easier way to bundle adjacent trench contact portions in a layout without routing the bundle lines through the upper layer of metallization, thus enabling a smaller cell area or a circuit scheme with less complexity or both.

[0518] An insulating capping layer for a gate electrode can be fabricated using several deposition operations, and as a result, the insulating capping layer can include artifacts of multiple deposition fabrication processes. For example, Figures 53A - 53E A cross-sectional view is shown that depicts various operations in a method of fabricating an integrated circuit structure including a gate stack having an overlying insulating capping layer, in accordance with an embodiment of the present disclosure.

[0519] Reference Figure 53A , starting structure 5300 includes a gate stack 5304 over a substrate or fin 5302. Gate stack 5304 includes a gate dielectric layer 5306, a conformal conductive layer 5308, and a conductive fill material 5310. In an embodiment, gate dielectric layer 5306 is a high-k gate dielectric layer formed using an atomic layer deposition (ALD) process, and the conformal conductive layer is a work function layer formed using an ALD process. In one such embodiment, a thermal or chemical oxide layer 5312, such as thermal or chemical silicon dioxide or silicon oxide layer, is between substrate or fin 5302 and gate dielectric layer 5306. A dielectric spacer 5314, such as a silicon nitride spacer, is adjacent to the sidewalls of gate stack 5304. Dielectric gate stack 5304 and dielectric spacer 5314 are accommodated in an interlayer dielectric (ILD) layer 5316. In an embodiment, gate stack 5304 is formed using a replacement gate and replacement gate dielectric pr...

Claims

1. An integrated circuit structure, comprising: a fin protruding from a semiconductor substrate, the fin having a lower fin portion and an upper fin portion, the upper fin portion having a top and sidewalls; an isolation structure surrounding the lower fin portion, the isolation structure including an insulating material having a top surface and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin; a gate dielectric layer over the top of the upper fin portion and laterally adjacent to the sidewalls of the upper fin portion, the gate dielectric layer further over the semiconductor material on the portion of the top surface of the insulating material; a gate electrode over the gate dielectric layer that is over the top of the upper fin portion and laterally adjacent to the sidewalls of the upper fin portion, the gate electrode further over the gate dielectric layer over the semiconductor material on the portion of the top surface of the insulating material; a first source or drain region adjacent to a first side of the gate electrode; and a second source or drain region adjacent to a second side of the gate electrode, the second side being opposite the first side.

2. The integrated circuit structure according to claim 1, wherein, the semiconductor material on the portion of the top surface of the insulating material includes polysilicon.

3. The integrated circuit structure according to claim 1, wherein, the top surface of the insulating material has a concave depression, and wherein the semiconductor material is in the concave depression.

4. The integrated circuit structure according to claim 1, wherein, the isolation structure includes a second insulating material along the bottom and sidewalls of the insulating material.

5. The integrated circuit structure according to claim 4, wherein, a portion of the second insulating material along the sidewall of the insulating material has a top surface higher than the uppermost surface of the insulating material.

6. The integrated circuit structure according to claim 5, wherein, the top surface of the second insulating material is higher than the uppermost surface of the semiconductor material.

7. The integrated circuit structure according to claim 1, wherein, the semiconductor material on the portion of the top surface of the insulating material does not extend beyond the gate dielectric layer.

8. The integrated circuit structure according to claim 1, further comprising: a first dielectric spacer along the first side of the gate electrode; and a second dielectric spacer along the second side of the gate electrode.

9. The integrated circuit structure according to claim 8, wherein, the gate dielectric layer further extends along the sidewalls of the first dielectric spacer and the second dielectric spacer.

10. The integrated circuit structure according to claim 1, wherein, the gate electrode includes a work function layer.

11. The integrated circuit structure according to claim 10, wherein, the work function layer includes titanium and nitrogen.

12. The integrated circuit structure according to claim 10, wherein, the work function layer includes titanium, aluminum, carbon, and nitrogen.

13. The integrated circuit structure according to claim 10, wherein, The gate electrode further includes a conductive fill metal layer over the work function layer.

14. The integrated circuit structure according to claim 13, wherein, the conductive fill metal layer includes tungsten.

15. The integrated circuit structure according to claim 14, wherein, the conductive fill metal layer includes tungsten with an atomic percentage of 95 or greater and fluorine with an atomic percentage of 0.1 to 2.

16. A method of manufacturing an integrated circuit structure, the method comprising: forming fins from a semiconductor substrate, the fins having a lower fin portion and an upper fin portion, the upper fin portion having a top and sidewalls; forming an isolation structure around the lower fin portion, the isolation structure including an insulating material having a top surface; forming a dummy gate electrode over the top of the upper fin portion and laterally adjacent to the sidewalls of the upper fin portion, the dummy gate electrode including a semiconductor material; forming a first source or drain region adjacent to a first side of the dummy gate electrode and a second source or drain region adjacent to a second side of the dummy gate electrode, the second side being opposite the first side; forming an interlayer dielectric (ILD) layer laterally adjacent to the dummy gate electrode; etching the dummy gate electrode from the top and sidewalls of the upper fin portion, wherein the etching is not completed and a portion of the dummy gate electrode is left on a portion of the top surface of the insulating material of the isolation structure; forming a gate dielectric layer over the top of the upper fin portion and laterally adjacent to the sidewalls of the upper fin portion, the gate dielectric layer further being formed on the portion of the dummy gate electrode on the portion of the top surface of the insulating material of the isolation structure; and forming a permanent gate electrode over the gate dielectric layer that is over the top of the upper fin portion and laterally adjacent to the sidewalls of the upper fin portion, the permanent gate electrode further being over the gate dielectric layer on the portion of the dummy gate electrode on the portion of the top surface of the insulating material.

17. The method according to claim 16, further comprising: forming a dummy gate dielectric layer before forming the dummy gate electrode; and removing the dummy gate dielectric layer after etching the dummy gate electrode.

18. The method according to claim 16, wherein, the dummy gate electrode includes polysilicon.

19. The method according to claim 16, wherein, the top surface of the insulating material of the isolation structure has a concave depression, and wherein the portion of the dummy gate electrode is in the concave depression.

20. The method according to claim 16, wherein, the isolation structure includes a second insulating material along the bottom and sidewalls of the insulating material.

21. The method according to claim 20, wherein, the portion of the second insulating material along the sidewall of the insulating material has a top surface that is higher than at least a portion of the top surface of the insulating material.

22. The method according to claim 21, Among them, the top surface of the second insulating material is higher than the lowermost surface of the portion of the dummy gate electrode.

23. The method according to claim 16, wherein, the portion of the dummy gate electrode on the portion of the top surface of the insulating material does not extend beyond the gate dielectric layer.

24. The method according to claim 16, further comprising: forming a first dielectric spacer along the first side of the dummy gate electrode and a second dielectric spacer along the second side of the dummy gate electrode before forming the interlayer dielectric (ILD) layer.

25. The method according to claim 24, wherein, forming the gate dielectric layer further along the sidewalls of the first dielectric spacer and the second dielectric spacer.

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