Method and apparatus for wafer level die bridge

Abstract

Methods and apparatus for a wafer-level die bridge are disclosed. A wafer-level bridge die is attached to a redistribution layer (RDL) that has been temporarily bonded to a carrier with an adhesive layer. Electrical interconnects are formed on the RDL and on the bridge die and encapsulated in a first mold layer. A plurality of dies are coupled to the RDL and the bridge die so that the dies are electrically connected to at least one electrical interconnect of the RDL and at least one electrical interconnect of the bridge die. A second mold layer is formed on the first mold layer to encapsulate the plurality of dies. The temporary bond is then broken and the carrier is removed, thereby exposing the RDL connections.

Description

Technical Field

[0001] Embodiments of the present principles relate generally to semiconductor processing. Background Art

[0002] Integrated circuits are usually formed by different processes according to the desired functions. Multiple chips of a function are generally constructed on a single wafer and then cut to form a single die or "chip". In other examples, multiple chips may have multiple functions and include die partitioning and multiple functional die integration. The chip has input and output ("I / O"), and the I / O of the chip needs to be electrically connected to the I / O connection of other chips. For example, a processing chip may need to be connected to a memory chip to perform functions correctly. One way to electrically connect two chips is to use an active or passive device called a "bridge". The bridge provides a path from the I / O of one chip to the I / O connection of another chip. The bridge can be a silicon die with a passive connection path or an active function. However, using a bridge to provide a connection usually increases the manufacturing complexity of semiconductor devices, and therefore may also limit the manufacturers that can manufacture semiconductor devices. The bridge formed in the substrate is usually as in the aforementioned case, which may limit the process of the manufacturing plant (the manufacturer of the chip), which is contrary to the outsourced assembly and test (OSAT) facility (limited to wafer-level manufacturing). Some wafer-level processes that form a redistribution layer (RDL) after bridge and chip placement run the risk of having to discard expensive chips due to low RDL yield.

[0003] Thus, the inventors have provided an improved method and apparatus for forming wafer-level die bridges. Summary of the invention

[0004] Some embodiments of a method of forming a wafer-level bridge die include: forming a redistribution layer (RDL); and attaching a bridge die on the RDL, the bridge die having electrical connections on an exposed surface opposite the RDL.

[0005] Some embodiments of a method for forming a wafer-level bridge die further include: forming the RDL on a carrier; or attaching the bridge die to the RDL using an adhesive between the bridge die and the RDL; or forming at least one electrical interconnect on the RDL; forming at least one electrical interconnect on the bridge die; forming a first mold layer over the RDL and the bridge die; and coupling a plurality of dies to the RDL and to the bridge die so that the dies are electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die; or forming a second mold layer on the first mold layer and on the plurality of dies; or forming at least one integrated passive device on the first mold layer; and forming a second mold layer on the first mold layer, on the plurality of dies, and on the at least one integrated passive device; or forming a second mold layer on the RDL using a copper-based material. L or at least one electrical interconnect is formed on the bridge chip; or at least one electrical interconnect is formed on the RDL; at least one electrical interconnect is formed on the bridge tube core; at least one first part of at least one through-mold via (TMV) is formed on the RDL; a first mold layer is formed above the RDL and the bridge tube core; at least one second part of the at least one TMV is formed; a plurality of tube cores are coupled to the RDL and to the bridge tube core, so that the tube cores are electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge tube core; and a second mold layer is formed on the first mold layer and on the plurality of tube cores, and the at least one TMV has an electrical connection at the top surface of the second mold layer for supporting package stacking (PoP) electrical connection; or the at least one TMW is formed using an electroplating process.

[0006] Some embodiments of a method for forming a wafer-level bridge die include: temporarily bonding a redistribution layer (RDL) to a carrier; attaching a bridge die to the RDL, the bridge die having electrical connections on an exposed surface opposite the RDL; forming at least one electrical interconnect on the RDL; forming at least one electrical interconnect on the exposed surface of the bridge die; forming a first mold layer on the RDL and the bridge die; coupling a plurality of dies to the RDL and to the bridge die so that the dies are electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die; forming a second mold layer on the first mold layer and on the plurality of dies; and removing the carrier from the RDL.

[0007] Some embodiments of a method for forming a wafer-level bridge die also include: attaching a heat exchange layer to the top surface of at least one of the multiple dies; or electrically connecting the RDL to a substrate or a printed circuit board; or forming at least one integrated passive device on the first mold layer before forming the second mold layer; or forming at least one through-mold via from the RDL to the top surface of the second mold layer.

[0008] Some embodiments of an apparatus for connecting semiconductor devices include: a redistribution layer (RDL); a bridge die; and an adhesive layer interposed between the RDL and the bridge die.

[0009] Some embodiments of an apparatus for connecting semiconductor devices further include: at least one electrical interconnect on the RDL; at least one electrical interconnect on the bridge die; and a first mold layer on the RDL and the bridge die; or a plurality of dies coupled to the RDL and to the bridge die such that the die is electrically connected to at least one of the at least one electrical interconnect of the RDL and to at least one of the at least one electrical interconnect of the bridge die; and a second mold layer on the first mold layer and on the plurality of dies; or a plurality of dies coupled to the RDL and to the bridge die such that the die is electrically connected to at least one of the at least one electrical interconnect of the RDL and to at least one of the at least one electrical interconnect of the bridge die; at least one integrated passive device on the first mold layer; and a second mold layer on the first mold layer and on the plurality of dies; a second mold layer on the plurality of dies and on the at least one integrated passive device; or at least one electrical interconnect on the RDL; at least one integrated passive device on the RDL; at least one electrical interconnect on the bridge die; at least one first portion of at least one through-mold via (TMV) on the RDL; and a first mold layer on the RDL and the bridge die; or at least one second portion of the at least one TMV; a plurality of dies coupled to the RDL and to the bridge die such that the dies are electrically connected to at least one of the at least one electrical interconnects of the RDL and to at least one of the at least one electrical interconnects of the bridge die; and a second mold layer on the first mold layer and on the plurality of dies, the at least one TMV having an electrical connection at a top surface of the second mold layer for supporting a package-on-package (PoP) electrical connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present principles, briefly summarized above and discussed in more detail below, can be understood with reference to the illustrative embodiments of the present principles depicted in the accompanying drawings. However, the drawings illustrate only typical embodiments of the present principles and are therefore not to be considered limiting of the scope, as the present principles may admit to other equally effective embodiments.

[0011] Figure 1 A method of forming a wafer-level bridge die according to some embodiments of the present principles.

[0012] Figure 2

[0046] Another method of forming a wafer-level bridge die in accordance with some embodiments of the present principles.

[0013] Figures 3A to 3G Depicted are some embodiments according to the present principles. Figure 1 The method forms a device.

[0014] Figures 4A to 4F Depicted are some embodiments according to the present principles. Figure 2 The method forms a device.

[0015] To facilitate understanding, the same reference numerals have been used as much as possible to indicate the same elements common to each figure. The figures are not drawn to scale and may be simplified for clarity. The elements and features of some embodiments may be beneficially combined in other embodiments without further description. DETAILED DESCRIPTION

[0016] The wafer-level die bridge is attached to the redistribution layer (RDL). The RDL can be pre-fabricated and temporarily bonded to the carrier or formed directly on the carrier with a temporarily bonded adhesive. Generally, RDL has a low throughput (high failure rate). Fine-pitch RDL structures are even more difficult to manufacture. By first pre-fabricating the RDL and attaching the RDL to the carrier or first forming the RDL on the carrier, any defective RDL can be discarded without discarding other valuable components, thereby reducing the overall production cost. In addition, since the RDL is constructed first, the thermal budget of other semiconductor devices (such as dies) does not limit the RDL formation process. Another advantage is that extended high temperature curing of the RDL can be achieved without the risk of damaging other expensive components.

[0017] The bridge die is manufactured separately by following a back-end-of-line (BEOL) process flow (e.g., dual damascene process) or a standard RDL process flow (semi-additive process), which can achieve designs less than 1 / 1 line / space (typically, 0.8 / 0.8L / S or 0.4 / 0.4μm). Fine pitch circuits are able to meet chip-to-chip interconnect needs. In addition, since the die bridge is produced at the wafer level and no foundry work is required, the process is also highly compatible with outsourced assembly and test (OSAT) facilities. If the RDL is built after chip placement, most, if not all, OSAT facilities are likely not to have the precision alignment capabilities to correctly form the RDL, limiting foundry production and increasing manufacturing costs.

[0018] Since the RDL is formed first, the fine line spacing can be 2 / 2 or less. The RDL is formed on a carrier, which can have a very smooth surface. When the RDL is formed on other mold layers and the die, a step height is formed at the die / mold intersection. The step height produces a morphology that is not suitable for forming fine pitch RDL, greatly reducing the yield of finer pitch RDL, and then, when the RDL process fails, the cost is increased due to the loss of manufacturing time and the loss of chip cost. The RDL first wafer-level die bridge process has the advantages of better control of the RDL process (no die thermal budget issues), improved RDL quality (fine pitch control caused by flat morphology) and increased RDL yield without the risk of losing expensive dies. The wafer-level die bridge process cost is also lower than the bridge solution using an inserter. Since there is no inserter, the size can also be reduced, so the die replacement insert becomes the limiting factor of the size. The size reduction allows the wafer-level bridge die to be compatible with larger packages (a breakthrough in 2X mask size).

[0019] Figure 1 A method 100 for forming a first wafer-level bridge die at an RDL according to some embodiments of the present principles is shown. The method 100 involves Figures 3A to 3G In block 102, as shown in FIG. Figure 3A The structure 300A shown includes an RDL 306, wherein at least one electrical interconnect 314 is formed on the RDL 306, the RDL 306 is temporarily bonded to the carrier 302 using the bonding layer 304 or the RDL 306, and at least one electrical connector 314 is formed on the bonding layer 304 on the carrier 302. The carrier 302 can be made of a material such as glass, GaN, silicon, or a polypropylene (prepreg) substrate. In block 104, as shown in FIG. Figure 3BThe structure 300B shown includes a bridge die 310 attached to the RDL 306 with an adhesive 308. The adhesive 308 helps to position and hold the bridge die during further processing, thereby allowing the method 100 to be performed. The adhesive 308 can be an organic or inorganic substance or compound commonly used in wire bonding technology. In frame 106, the structure 300B also includes at least one electrical interconnect 312 formed on an exposed surface 330 of the bridge chip 310 opposite to the RDL 306. The electrical interconnects 312, 314 allow connection with the RDL 306 and the bridge die 310 after forming subsequent layers (discussed below). The electrical interconnects 312, 314 are sometimes referred to as pillars and can be formed of conductive materials, such as metals including, for example, copper-based materials, tungsten-based materials, and silver-based materials, and / or, for example, conductive polymer-based materials. The electrical interconnects 312, 314 are typically formed using an electroplating process. An optional integrated passive device (IPD) 322 may also be placed on the top surface 394 of the RDL 306. The inclusion of an IPD is another advantage of the method 100 over other techniques.

[0020] In block 108, Figure 3C The illustrated structure 300C includes a first mold layer 316 formed on the RDL 306 and the bridge die 310. The first mold layer 316 may be formed of a material such as, for example, polyimide, benzocyclobutene, polybenzoxazole, epoxy molding compound (EMC) (with or without filler), etc. After forming the first mold layer 316, a planarization process such as chemical mechanical polishing (CMP) may be used to planarize the top surface 360 ​​of the first mold layer 316 to further expose the electrical interconnects 312, 314. In block 110, as shown in FIG. Figure 3D The illustrated structure 300D includes a plurality of dies 318, 320 disposed on a first mold layer 316 and coupled to the RDL 306 and the bridge die 310 via electrical interconnects 312, 314. Another optional integrated passive device (IPD) 322 may also be disposed on the top surface 360 ​​of the first mold layer 316.

[0021] In block 112, as Figure 3E The illustrated structure 300E includes a second mold layer 324 formed on the first mold layer 316 and on the plurality of dies 318, 320 (and optionally on the IPD). The second mold layer 324 may be formed of a material such as, for example, polyimide, benzocyclobutene, polybenzoxazole, epoxy molding compound (EMC) (with or without filler), etc. A planarization process such as CMP may be employed after forming the second mold layer 324 to planarize a top surface 370 of the second mold layer 324 to further expose top surfaces 380 of the plurality of dies 318, 320. Planarization may allow for better contact between the top surfaces 380 of the plurality of dies and a heat exchange layer, etc. (discussed below). In block 114, as shown in FIG. Figure 3FThe structure 300F shown has the carrier 302 removed (debonded) from the RDL 306. For example, ball bonding can be used to form optional balls 326 to connect the lower surface 390 of the RDL 306 to other circuits. Figure 3G The illustrated structure 300G includes an optional substrate or printed circuit board 354 and an optional heat exchange layer 350 in contact with the top surface 380 of the plurality of dies 318, 320 to remove heat during operation of the plurality of dies 318, 320. The substrate or printed circuit board 354 may contain additional circuitry connected via optional balls 326 formed on the lower surface 390 of the RDL 306.

[0022] Figure 2 is another method 200 for forming an RDL first wafer-level bridge die according to some embodiments of the present principles. The method 200 involves Figures 4A to 4F , which will be referred to accordingly. Similar reference numerals are used to simplify the description where appropriate. In block 202, as Figure 4A The illustrated structure 400A includes an RDL 306 that is temporarily bonded to a carrier 302 with a bonding layer 304 or formed on a bonding layer 304 on the carrier 302. The carrier 302 may be made of a material such as a glass, GaN, silicon, or polypropylene (prepreg) substrate. In block 204, the structure 400A further includes a bridge die 310 attached to the RDL 306 with an adhesive 308. The adhesive 308 helps position and hold the bridge die during further processing, thereby allowing the method 200 to be performed. The adhesive 308 may be an organic or inorganic substance commonly used in wire bonding techniques.

[0023] In block 206, structure 400A further includes at least one electrical interconnect 312 formed on an exposed surface 330 of bridge die 310 opposite RDL 306. Electrical interconnects 312, 314 allow for connection to RDL 306 and bridge die 310 after subsequent layers (discussed below) are formed. Electrical interconnects 312, 314 are sometimes referred to as pillars and may be formed of a conductive material such as, for example, a metal including copper-based materials, tungsten-based materials, and silver-based materials and / or, for example, a conductive polymer-based material. An electroplating process is typically used to form electrical interconnects 312, 314. In block 208, structure 400A further includes at least one through-mold via (TMV) (TMV) extending through RDL 306. Figure 4C-4EAt least one first portion 402 of at least one TMV 406 can be formed of similar materials (metal, conductive polymer, etc.) and using similar processes (including electroplating processes, etc.) as electrical interconnects 312, 314. Although not shown, at least one TMV 406 can be electrically connected to RDL 306. Including TMVs is another advantage of method 200 over other technologies.

[0024] In block 210, Figure 4B The illustrated structure 400B includes a first mold layer 316 formed on the RDL 306 and the bridge die 310. After forming the first mold layer 316, a planarization process such as CMP may be used to planarize the top surface 360 ​​of the first mold layer 316 to further expose the electrical interconnects 312, 314 and at least one first portion 402 of the at least one TMV 406. In block 212, as shown in FIG. Figure 4C The illustrated structure 400C includes at least one second portion 404 of at least one TMV 406. The at least one second portion 404 of at least one TMV 406 may be formed, for example, using an electroplating process or the like to form the at least one second portion 404 on the at least one first portion 402 of the at least one TMV 406.

[0025] In block 214, Figure 4D The illustrated structure 400D includes a plurality of dies 318, 320 disposed on the first mold layer 316 and coupled to the RDL 306 and the bridge die 310 via electrical interconnects 312, 314. An optional integrated passive device (IPD) 322 (not shown) may also be disposed on the top surface 360 ​​of the first mold layer 316 along with at least one TMV 406 having a top surface 420. In block 216, the structure 400D further includes a second mold layer 324 formed on the first mold layer 316 and on the plurality of dies 318, 320 (and on the optional IPD). A planarization process such as CMP may be employed after forming the second mold layer 324 to planarize the top surface 370 of the second mold layer 324 to further expose the top surfaces 380 of the plurality of dies 318, 320. Planarization may allow for better contact between the top surfaces 380 of the plurality of dies and heat exchange layers, etc. (discussed above).

[0026] In block 218, Figure 4E The structure 400E shown has the carrier 302 removed (debonded) from the RDL 306. For example, ball bonding can be used to form optional balls 326 to connect the lower surface 390 of the RDL 306 to other circuits. Figure 4FThe illustrated structure 400F includes an optional semiconductor package 408 connected to at least one TMV 406 via optional balls 410 formed by ball bonding of a top surface 420 of at least one TMV 406. At least one TMV 406 advantageously allows for support of package-on-package (PoP) electrical connections.

[0027] The above method has the advantage of higher die and bridge die placement accuracy and tighter tolerances of the RDL relative to substrate-based processes. This method also has the advantage of being compatible with high temperature dielectrics because the RDL is constructed first (not limited by the die thermal budget). This method also has the advantage of enabling OSATs to form the process in-house without the assistance of a foundry.

[0028] While the foregoing is directed to embodiments of the present principles, other and further embodiments of the present principles may be devised without departing from the basic scope thereof.

[0029] Component Symbol List

[0030] 100 Methods

[0031] 102 Frame

[0032] 104 Frame

[0033] 106 Frame

[0034] 108 Frame

[0035] 110 Frame

[0036] 112 Frame

[0037] 114 Frame

[0038] 200 Methods

[0039] 202 Frame

[0040] 204 Frame

[0041] 206 Frame

[0042] 208 Frame

[0043] 210 Frame

[0044] 212 Frame

[0045] 214 Frame

[0046] 218 Box

[0047] 300a-g Structure

[0048] 302 Carrier

[0049] 304 Bonding layer

[0050] 306 RDL

[0051] 308 Adhesive

[0052] 310 Bridge Die

[0053] 312 Electrical interconnects

[0054] 314 Electrical interconnects

[0055] 316 First mold layer

[0056] 318 Multiple Dies

[0057] More than 320 dies

[0058] 322 Integrated Passive Devices

[0059] 324 Second mold layer

[0060] 326 Optional Ball

[0061] 330 Exposed Surface

[0062] 350 Optional heat exchange layer

[0063] 354 Printed Circuit Board

[0064] 360 top surface

[0065] 370 Top surface

[0066] 380 Exposed top surface

[0067] 390 Lower surface

[0068] 394 Top surface

[0069] 400a-f Structure

[0070] 402 Part 1

[0071] 404 A Part II

[0072] 406 TMV

[0073] 408 Optional semiconductor package

[0074] 410 Optional Ball

Claims

1. A method for forming a wafer-level bridge die, comprising: forming a redistribution layer (RDL); attaching a bridge die to the RDL, the bridge die having electrical connections on an exposed surface opposite the RDL; forming at least one electrical interconnect on the RDL; forming at least one electrical interconnect on the bridge die; forming at least one first portion of at least one through-mold via (TMV) on the RDL; forming a first mold layer on the RDL and the bridge die; forming at least one second portion of the at least one TMV on the at least one first portion of the at least one TMV; coupling a plurality of dies to the RDL and to the bridge die such that the dies are electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die; and A second mold layer is formed on the first mold layer and on the plurality of dies, the at least one TMV having electrical connections at a top surface of the second mold layer for supporting package-on-package (PoP) electrical connections.

2. The method of claim 1, further comprising: The RDL is formed on a carrier.

3. The method of claim 1, further comprising: The bridge die is attached to the RDL using an adhesive between the bridge die and the RDL.

4. The method of claim 1, further comprising: A first mold layer is formed over the RDL and the bridge die.

5. The method of claim 4, further comprising: A second mold layer is formed on the first mold layer and on the plurality of dies.

6. The method of claim 4, further comprising: forming at least one integrated passive device on the first mold layer; and A second mold layer is formed on the first mold layer, on the plurality of dies, and on the at least one integrated passive device.

7. The method of claim 4, further comprising: At least one electrical interconnect is formed on the RDL or at least one electrical interconnect is formed on the bridge die using a copper-based material.

8. A method of forming a wafer-level bridge die, comprising: temporarily bonding a redistribution layer (RDL) to a carrier; attaching a bridge die to the RDL, the bridge die having electrical connections on an exposed surface opposite the RDL; forming at least one electrical interconnect on the RDL; forming at least one electrical interconnect on the exposed surface of the bridge die; forming at least one first portion of at least one through-mold via (TMV) on the RDL; forming a first mold layer on the RDL and the bridge die; forming at least one second portion of the at least one TMV on the at least one first portion of the at least one TMV; coupling a plurality of dies to the RDL and to the bridge die such that the dies are electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die; forming a second mold layer on the first mold layer and on the plurality of dies, the at least one TMV having electrical connections at a top surface of the second mold layer for supporting package-on-package (PoP) electrical connections; and The carrier is removed from the RDL.

9. An apparatus for connecting a semiconductor device, comprising: Redistribution layer (RDL); Bridge die; an adhesive layer interposed between the RDL and the bridge die; at least one electrical interconnect formed on the RDL; at least one electrical interconnect formed on the bridge die; a first mold layer on the RDL and the bridge die; a plurality of dies coupled to the RDL and to the bridge die such that the dies are electrically connected to at least one of the at least one electrical interconnect of the RDL and to at least one of the at least one electrical interconnect of the bridge die; at least one integrated passive device on the RDL; at least one first portion of at least one through-mold via (TMV) on the RDL; at least one second portion of said at least one TMV on said at least one first portion of said at least one TMV; and A second mold layer on the first mold layer and on the plurality of dies, the at least one TMV having electrical connections at a top surface of the second mold layer for supporting package-on-package (PoP) electrical connections.

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